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target/arm: Add isar_feature tests for PAN + ATS1E1 target/arm: Add ID_AA64MMFR2_EL1 target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field target/arm: Define an aa32_pmu_8_1 isar feature test function target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks target/arm: Stop assuming DBGDIDR always exists target/arm: Move DBGDIDR into ARMISARegisters target/arm: Enable ARMv8.2-ATS1E1 in -cpu max target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks target/arm: Read debug-related ID registers from KVM target/arm/monitor: Introduce qmp_query_cpu_model_expansion target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none target/arm: convert isar regs to array target/arm: parse cpu feature related options target/arm: register CPU features for property target/arm: Allow ID registers to synchronize to KVM target/arm: introduce CPU feature dependency mechanism target/arm: introduce KVM_CAP_ARM_CPU_FEATURE target/arm: Add CPU features to query-cpu-model-expansion target/arm: Update ID fields target/arm: Add more CPU features target/arm: ignore evtstrm and cpuid CPU features target/arm: Update the ID registers of Kunpeng-920 target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest target/arm: clear EL2 and EL3 only when kvm is not enabled Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Liang Yan <lyan@suse.com> Signed-off-by: Peng Liang <liangpeng10@huawei.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>