target/arm: Update ID fields
Update definitions for ID fields, up to ARMv8.6. Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com> Signed-off-by: Peng Liang <liangpeng10@huawei.com> (cherry-picked from commit f87ed4385cdadf4af38b76385d2aa581b7ade6c9)
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target-arm-Update-ID-fields.patch
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target-arm-Update-ID-fields.patch
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From e6c94219b9f6a201853b19c8db0b02ef8ee4a9d5 Mon Sep 17 00:00:00 2001
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From: Peng Liang <liangpeng10@huawei.com>
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Date: Tue, 11 Aug 2020 10:18:57 +0800
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Subject: [PATCH] target/arm: Update ID fields
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Update definitions for ID fields, up to ARMv8.6.
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Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
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Signed-off-by: Peng Liang <liangpeng10@huawei.com>
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(cherry-picked from commit f87ed4385cdadf4af38b76385d2aa581b7ade6c9)
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---
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target/arm/cpu.h | 17 +++++++++++++++++
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1 file changed, 17 insertions(+)
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index 068c3fa2ad..eb875e112a 100644
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--- a/target/arm/cpu.h
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+++ b/target/arm/cpu.h
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@@ -1691,6 +1691,8 @@ FIELD(ID_ISAR6, DP, 4, 4)
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FIELD(ID_ISAR6, FHM, 8, 4)
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FIELD(ID_ISAR6, SB, 12, 4)
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FIELD(ID_ISAR6, SPECRES, 16, 4)
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+FIELD(ID_ISAR6, BF16, 20, 4)
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+FIELD(ID_ISAR6, I8MM, 24, 4)
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FIELD(ID_MMFR3, CMAINTVA, 0, 4)
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FIELD(ID_MMFR3, CMAINTSW, 4, 4)
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@@ -1736,6 +1738,9 @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
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FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
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FIELD(ID_AA64ISAR1, SB, 36, 4)
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FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
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+FIELD(ID_AA64ISAR1, BF16, 44, 4)
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+FIELD(ID_AA64ISAR1, DGH, 48, 4)
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+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
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FIELD(ID_AA64PFR0, EL0, 0, 4)
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FIELD(ID_AA64PFR0, EL1, 4, 4)
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@@ -1746,11 +1751,18 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
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FIELD(ID_AA64PFR0, GIC, 24, 4)
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FIELD(ID_AA64PFR0, RAS, 28, 4)
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FIELD(ID_AA64PFR0, SVE, 32, 4)
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+FIELD(ID_AA64PFR0, SEL2, 36, 4)
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+FIELD(ID_AA64PFR0, MPAM, 40, 4)
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+FIELD(ID_AA64PFR0, AMU, 44, 4)
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+FIELD(ID_AA64PFR0, DIT, 44, 4)
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+FIELD(ID_AA64PFR0, CSV2, 56, 4)
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+FIELD(ID_AA64PFR0, CSV3, 60, 4)
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FIELD(ID_AA64PFR1, BT, 0, 4)
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FIELD(ID_AA64PFR1, SBSS, 4, 4)
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FIELD(ID_AA64PFR1, MTE, 8, 4)
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FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
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+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
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FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
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FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
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@@ -1764,6 +1776,8 @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
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FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
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FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
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FIELD(ID_AA64MMFR0, EXS, 44, 4)
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+FIELD(ID_AA64MMFR0, FGT, 56, 4)
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+FIELD(ID_AA64MMFR0, ECV, 60, 4)
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FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
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FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
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@@ -1773,6 +1787,8 @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
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FIELD(ID_AA64MMFR1, PAN, 20, 4)
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FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
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FIELD(ID_AA64MMFR1, XNX, 28, 4)
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+FIELD(ID_AA64MMFR1, TWED, 32, 4)
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+FIELD(ID_AA64MMFR1, ETS, 36, 4)
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FIELD(ID_AA64MMFR2, CNP, 0, 4)
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FIELD(ID_AA64MMFR2, UAO, 4, 4)
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@@ -1799,6 +1815,7 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
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FIELD(ID_AA64DFR0, PMSVER, 32, 4)
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FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
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FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
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+FIELD(ID_AA64DFR0, MUPMU, 48, 4)
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FIELD(ID_DFR0, COPDBG, 0, 4)
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FIELD(ID_DFR0, COPSDBG, 4, 4)
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--
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2.23.0
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