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target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1

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Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them
where we currently have hard-coded bit values.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200214175116.9164-7-peter.maydell@linaro.org
(cherry-picked from commit ceb2744b47a1ef4184dca56a158eb3156b6eba36)
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
This commit is contained in:
Huawei Technologies Co., Ltd 2020-02-14 17:51:01 +00:00 committed by Euler Robot
parent b963c46486
commit 0aa9d98ac5
1 changed files with 77 additions and 0 deletions
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target-arm-Add-and-use-FIELD-definitions-for-ID_AA64.patch Normal file
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@ -0,0 +1,77 @@
From 21d5d53e9114c3b4d3d8c888b1c5fdec1667ecc7 Mon Sep 17 00:00:00 2001
From: Peter Maydell <peter.maydell@linaro.org>
Date: Fri, 14 Feb 2020 17:51:01 +0000
Subject: [PATCH] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them
where we currently have hard-coded bit values.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200214175116.9164-7-peter.maydell@linaro.org
(cherry-picked from commit ceb2744b47a1ef4184dca56a158eb3156b6eba36)
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
---
target/arm/cpu.c | 2 +-
target/arm/cpu.h | 10 ++++++++++
target/arm/helper.c | 6 +++---
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 811e5c6365..dbd05e0113 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1522,7 +1522,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
cpu);
#endif
} else {
- cpu->id_aa64dfr0 &= ~0xf00;
+ cpu->id_aa64dfr0 = FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
cpu->id_dfr0 &= ~(0xf << 24);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3e65bc50a4..91cc02b43f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1779,6 +1779,16 @@ FIELD(ID_AA64MMFR2, BBM, 52, 4)
FIELD(ID_AA64MMFR2, EVT, 56, 4)
FIELD(ID_AA64MMFR2, E0PD, 60, 4)
+FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
+FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
+FIELD(ID_AA64DFR0, PMUVER, 8, 4)
+FIELD(ID_AA64DFR0, BRPS, 12, 4)
+FIELD(ID_AA64DFR0, WRPS, 20, 4)
+FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
+FIELD(ID_AA64DFR0, PMSVER, 32, 4)
+FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
+FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
+
FIELD(ID_DFR0, COPDBG, 0, 4)
FIELD(ID_DFR0, COPSDBG, 4, 4)
FIELD(ID_DFR0, MMAPDBG, 8, 4)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c50b1ba1c9..419be64037 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5611,9 +5611,9 @@ static void define_debug_regs(ARMCPU *cpu)
* check that if they both exist then they agree.
*/
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
- assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
- assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) == brps);
+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) == wrps);
+ assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) == ctx_cmps);
}
define_one_arm_cp_reg(cpu, &dbgdidr);
--
2.23.0