target/arm: Move DBGDIDR into ARMISARegisters
We're going to want to read the DBGDIDR register from KVM in a subsequent commit, which means it needs to be in the ARMISARegisters sub-struct. Move it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200214175116.9164-12-peter.maydell@linaro.org (cherry-picked from commit 4426d3617d64922d97b74ed22e67e33b6fb7de0a) Signed-off-by: Peng Liang <liangpeng10@huawei.com>
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target-arm-Move-DBGDIDR-into-ARMISARegisters.patch
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target-arm-Move-DBGDIDR-into-ARMISARegisters.patch
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@ -0,0 +1,160 @@
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From d90d85c86d98a35a6a51e0ef6edb95ca7f6de6ba Mon Sep 17 00:00:00 2001
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From: Peter Maydell <peter.maydell@linaro.org>
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Date: Fri, 14 Feb 2020 17:51:06 +0000
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Subject: [PATCH] target/arm: Move DBGDIDR into ARMISARegisters
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We're going to want to read the DBGDIDR register from KVM in
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a subsequent commit, which means it needs to be in the
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ARMISARegisters sub-struct. Move it.
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20200214175116.9164-12-peter.maydell@linaro.org
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(cherry-picked from commit 4426d3617d64922d97b74ed22e67e33b6fb7de0a)
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Signed-off-by: Peng Liang <liangpeng10@huawei.com>
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---
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target/arm/cpu.c | 8 ++++----
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target/arm/cpu.h | 2 +-
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target/arm/cpu64.c | 6 +++---
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target/arm/helper.c | 2 +-
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target/arm/internals.h | 6 +++---
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5 files changed, 12 insertions(+), 12 deletions(-)
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diff --git a/target/arm/cpu.c b/target/arm/cpu.c
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index bb2edf4e18..a23c71dbf7 100644
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--- a/target/arm/cpu.c
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+++ b/target/arm/cpu.c
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@@ -2070,7 +2070,7 @@ static void cortex_a8_initfn(Object *obj)
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cpu->isar.id_isar2 = 0x21232031;
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cpu->isar.id_isar3 = 0x11112131;
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cpu->isar.id_isar4 = 0x00111142;
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- cpu->dbgdidr = 0x15141000;
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+ cpu->isar.dbgdidr = 0x15141000;
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cpu->clidr = (1 << 27) | (2 << 24) | 3;
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cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
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cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
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@@ -2143,7 +2143,7 @@ static void cortex_a9_initfn(Object *obj)
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cpu->isar.id_isar2 = 0x21232041;
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cpu->isar.id_isar3 = 0x11112131;
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cpu->isar.id_isar4 = 0x00111142;
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- cpu->dbgdidr = 0x35141000;
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+ cpu->isar.dbgdidr = 0x35141000;
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cpu->clidr = (1 << 27) | (1 << 24) | 3;
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cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
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cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
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@@ -2211,7 +2211,7 @@ static void cortex_a7_initfn(Object *obj)
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cpu->isar.id_isar2 = 0x21232041;
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cpu->isar.id_isar3 = 0x11112131;
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cpu->isar.id_isar4 = 0x10011142;
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- cpu->dbgdidr = 0x3515f005;
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+ cpu->isar.dbgdidr = 0x3515f005;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
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@@ -2254,7 +2254,7 @@ static void cortex_a15_initfn(Object *obj)
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cpu->isar.id_isar2 = 0x21232041;
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cpu->isar.id_isar3 = 0x11112131;
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cpu->isar.id_isar4 = 0x10011142;
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- cpu->dbgdidr = 0x3515f021;
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+ cpu->isar.dbgdidr = 0x3515f021;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index 4b1ae32bd2..3040aa4027 100644
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--- a/target/arm/cpu.h
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+++ b/target/arm/cpu.h
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@@ -861,6 +861,7 @@ struct ARMCPU {
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uint32_t mvfr1;
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uint32_t mvfr2;
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uint32_t id_dfr0;
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+ uint32_t dbgdidr;
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uint64_t id_aa64isar0;
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uint64_t id_aa64isar1;
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uint64_t id_aa64pfr0;
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@@ -888,7 +889,6 @@ struct ARMCPU {
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uint32_t id_mmfr4;
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uint64_t id_aa64afr0;
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uint64_t id_aa64afr1;
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- uint32_t dbgdidr;
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uint32_t clidr;
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uint64_t mp_affinity; /* MP ID without feature bits */
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/* The elements of this array are the CCSIDR values for each cache,
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diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
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index aa96548f10..7ad8b5e237 100644
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--- a/target/arm/cpu64.c
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+++ b/target/arm/cpu64.c
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@@ -140,7 +140,7 @@ static void aarch64_a57_initfn(Object *obj)
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cpu->isar.id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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- cpu->dbgdidr = 0x3516d000;
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+ cpu->isar.dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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@@ -194,7 +194,7 @@ static void aarch64_a53_initfn(Object *obj)
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cpu->isar.id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
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- cpu->dbgdidr = 0x3516d000;
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+ cpu->isar.dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
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@@ -247,7 +247,7 @@ static void aarch64_a72_initfn(Object *obj)
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cpu->isar.id_aa64dfr0 = 0x10305106;
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cpu->isar.id_aa64isar0 = 0x00011120;
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cpu->isar.id_aa64mmfr0 = 0x00001124;
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- cpu->dbgdidr = 0x3516d000;
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+ cpu->isar.dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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index c1ff4b6bd0..60ff7c0fa1 100644
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--- a/target/arm/helper.c
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+++ b/target/arm/helper.c
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@@ -5597,7 +5597,7 @@ static void define_debug_regs(ARMCPU *cpu)
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ARMCPRegInfo dbgdidr = {
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.name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL0_R, .accessfn = access_tda,
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- .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
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+ .type = ARM_CP_CONST, .resetvalue = cpu->isar.dbgdidr,
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};
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/* Note that all these register fields hold "number of Xs minus 1". */
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diff --git a/target/arm/internals.h b/target/arm/internals.h
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index a72d0a6cd1..1d01ecc413 100644
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--- a/target/arm/internals.h
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+++ b/target/arm/internals.h
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@@ -867,7 +867,7 @@ static inline int arm_num_brps(ARMCPU *cpu)
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if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
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return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
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} else {
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- return FIELD_EX32(cpu->dbgdidr, DBGDIDR, BRPS) + 1;
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+ return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;
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}
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}
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@@ -881,7 +881,7 @@ static inline int arm_num_wrps(ARMCPU *cpu)
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if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
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return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
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} else {
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- return FIELD_EX32(cpu->dbgdidr, DBGDIDR, WRPS) + 1;
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+ return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;
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}
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}
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@@ -895,7 +895,7 @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu)
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if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
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return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
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} else {
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- return FIELD_EX32(cpu->dbgdidr, DBGDIDR, CTX_CMPS) + 1;
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+ return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;
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}
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}
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--
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2.23.0
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