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target/arm: Add more CPU features

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Add i8mm, bf16, and dgh CPU features for AArch64.

Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
(cherry-picked from commit 8acf8dd1a20c53453d028a7b86f593019329d8c1)
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Huawei Technologies Co., Ltd 2020-08-11 10:28:10 +08:00 committed by Euler Robot
parent 53269940a0
commit 6e86afded6
1 changed files with 31 additions and 0 deletions
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target-arm-Add-more-CPU-features.patch Normal file
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@ -0,0 +1,31 @@
From f4948980bd6ede3255643982afe01f56c93fec71 Mon Sep 17 00:00:00 2001
From: Peng Liang <liangpeng10@huawei.com>
Date: Tue, 11 Aug 2020 10:28:10 +0800
Subject: [PATCH] target/arm: Add more CPU features
Add i8mm, bf16, and dgh CPU features for AArch64.
Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
(cherry-picked from commit 8acf8dd1a20c53453d028a7b86f593019329d8c1)
---
target/arm/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index dcf9f49ed3..7ae2d3da56 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1132,6 +1132,9 @@ static struct CPUFeatureInfo cpu_features[] = {
FIELD_INFO("fhm", ID_ISAR6, FHM, false, 1, 0, true),
FIELD_INFO("sb", ID_ISAR6, SB, false, 1, 0, true),
FIELD_INFO("specres", ID_ISAR6, SPECRES, false, 1, 0, true),
+ FIELD_INFO("i8mm", ID_AA64ISAR1, I8MM, false, 1, 0, false),
+ FIELD_INFO("bf16", ID_AA64ISAR1, BF16, false, 1, 0, false),
+ FIELD_INFO("dgh", ID_AA64ISAR1, DGH, false, 1, 0, false),
FIELD_INFO("cmaintva", ID_MMFR3, CMAINTVA, false, 1, 0, true),
FIELD_INFO("cmaintsw", ID_MMFR3, CMAINTSW, false, 1, 0, true),
--
2.23.0