6e86afded6
Add i8mm, bf16, and dgh CPU features for AArch64. Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com> Signed-off-by: Peng Liang <liangpeng10@huawei.com> (cherry-picked from commit 8acf8dd1a20c53453d028a7b86f593019329d8c1)
32 lines
1.2 KiB
Diff
32 lines
1.2 KiB
Diff
From f4948980bd6ede3255643982afe01f56c93fec71 Mon Sep 17 00:00:00 2001
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From: Peng Liang <liangpeng10@huawei.com>
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Date: Tue, 11 Aug 2020 10:28:10 +0800
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Subject: [PATCH] target/arm: Add more CPU features
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Add i8mm, bf16, and dgh CPU features for AArch64.
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Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
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Signed-off-by: Peng Liang <liangpeng10@huawei.com>
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(cherry-picked from commit 8acf8dd1a20c53453d028a7b86f593019329d8c1)
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---
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target/arm/cpu.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/target/arm/cpu.c b/target/arm/cpu.c
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index dcf9f49ed3..7ae2d3da56 100644
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--- a/target/arm/cpu.c
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+++ b/target/arm/cpu.c
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@@ -1132,6 +1132,9 @@ static struct CPUFeatureInfo cpu_features[] = {
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FIELD_INFO("fhm", ID_ISAR6, FHM, false, 1, 0, true),
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FIELD_INFO("sb", ID_ISAR6, SB, false, 1, 0, true),
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FIELD_INFO("specres", ID_ISAR6, SPECRES, false, 1, 0, true),
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+ FIELD_INFO("i8mm", ID_AA64ISAR1, I8MM, false, 1, 0, false),
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+ FIELD_INFO("bf16", ID_AA64ISAR1, BF16, false, 1, 0, false),
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+ FIELD_INFO("dgh", ID_AA64ISAR1, DGH, false, 1, 0, false),
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FIELD_INFO("cmaintva", ID_MMFR3, CMAINTVA, false, 1, 0, true),
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FIELD_INFO("cmaintsw", ID_MMFR3, CMAINTSW, false, 1, 0, true),
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--
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2.23.0
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