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!33 Add support for RISC-V

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From: @zhang-liang-pengkun 
Reviewed-by: @Charlie_li 
Signed-off-by: @Charlie_li
This commit is contained in:
openeuler-ci-bot 2023-10-26 08:40:55 +00:00 committed by Gitee
commit 7e17e3a398
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GPG Key ID: 173E9B9CA92EEF8F
2 changed files with 68 additions and 1 deletions
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63
0001-Add-support-for-RISC-V.patch Normal file
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@ -0,0 +1,63 @@
From b3e28228b0f5af506f38d1a211ed0794dd66fafe Mon Sep 17 00:00:00 2001
From: Andreas Schwab <schwab@suse.de>
Date: Thu, 19 Jul 2018 18:38:31 +0200
Subject: [PATCH] Add support for RISC-V
---
platform/switch_riscv_unix.h | 32 ++++++++++++++++++++++++++++++++
slp_platformselect.h | 2 ++
2 files changed, 34 insertions(+)
create mode 100644 platform/switch_riscv_unix.h
diff --git a/platform/switch_riscv_unix.h b/platform/switch_riscv_unix.h
new file mode 100644
index 0000000..5b5ea98
--- /dev/null
+++ b/platform/switch_riscv_unix.h
@@ -0,0 +1,32 @@
+#define STACK_REFPLUS 1
+
+#ifdef SLP_EVAL
+#define STACK_MAGIC 0
+
+#define REGS_TO_SAVE "s0", "s1", "s2", "s3", "s4", "s5", \
+ "s6", "s7", "s8", "s9", "s10", "s11", "fs0", "fs1", \
+ "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", \
+ "fs10", "fs11"
+
+static int
+slp_switch(void)
+{
+ register int ret;
+ register long *stackref, stsizediff;
+ __asm__ volatile ("" : : : REGS_TO_SAVE);
+ __asm__ volatile ("mv %0, sp" : "=r" (stackref) : );
+ {
+ SLP_SAVE_STATE(stackref, stsizediff);
+ __asm__ volatile (
+ "add sp, sp, %0\n\t"
+ : /* no outputs */
+ : "r" (stsizediff)
+ );
+ SLP_RESTORE_STATE();
+ }
+ __asm__ volatile ("" : : : REGS_TO_SAVE);
+ __asm__ volatile ("mv %0, zero" : "=r" (ret) : );
+ return ret;
+}
+
+#endif
diff --git a/slp_platformselect.h b/slp_platformselect.h
index e6cdc9f..b52c287 100644
--- a/slp_platformselect.h
+++ b/slp_platformselect.h
@@ -49,4 +49,6 @@
#include "platform/switch_m68k_gcc.h" /* gcc on m68k */
#elif defined(__GNUC__) && defined(__csky__)
#include "platform/switch_csky_gcc.h" /* gcc on csky */
+#elif defined(__GNUC__) && defined(__riscv)
+#include "platform/switch_riscv_unix.h" /* gcc on RISC-V */
#endif
--
2.39.0.windows.2

6
python-greenlet.spec
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@ -1,10 +1,11 @@
Name: python-greenlet
Version: 0.4.14
Release: 4
Release: 5
Summary: lightweight coroutines for in-process concurrent programming
License: MIT
URL: https://github.com/python-greenlet/greenlet
Source0: https://github.com/python-greenlet/greenlet/archive/0.4.14.tar.gz
Patch0001: 0001-Add-support-for-RISC-V.patch
BuildRequires: python2-devel python2-setuptools python3-devel python3-setuptools
BuildRequires: gcc-c++
@ -83,6 +84,9 @@ that use python3-greenlet.
%{_includedir}/python%{python3_version}*/greenlet/
%changelog
* Tue Oct 24 2023 zhangliangpengkun<zhangliangpengkun@xfusion.com> - 0.4.14-5
- Add support for RISC-V
* Thu Sep 17 2020 liuweibo <liuweibo10@huawei.com> - 0.4.14-4
- Fix Source0