91 lines
3.4 KiB
Diff
91 lines
3.4 KiB
Diff
From 574ebcfb7fa23c87ee9bf03f46db5e4a9fb99b7d Mon Sep 17 00:00:00 2001
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From: Leo Yan <leo.yan@linaro.org>
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Date: Fri, 31 Dec 2021 13:32:15 +0800
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Subject: [PATCH 18/21] perf arm-spe: Add more sub classes for operation packet
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mainline inclusion
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from mainline-v5.11-rc1
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commit 3d829724b16c5d2de42e6c9601c696c93a10bc61
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I4NGPV
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CVE: NA
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-------------------------------------------------
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For the operation type packet payload with load/store class, it misses
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to support these sub classes:
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- A load/store targeting the general-purpose registers;
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- A load/store targeting unspecified registers;
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- The ARMv8.4 nested virtualisation extension can redirect system
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register accesses to a memory page controlled by the hypervisor.
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The SPE profiling feature in newer implementations can tag those
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memory accesses accordingly.
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Add the bit pattern describing load/store sub classes, so that the perf
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tool can decode it properly.
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Inspired by Andre Przywara, refined the commit log and code for more
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clear description.
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Co-developed-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: Leo Yan <leo.yan@linaro.org>
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Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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Acked-by: Will Deacon <will@kernel.org>
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Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Cc: Al Grant <Al.Grant@arm.com>
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Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
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Cc: Dave Martin <Dave.Martin@arm.com>
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Cc: Ingo Molnar <mingo@redhat.com>
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Cc: James Clark <james.clark@arm.com>
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Cc: Jiri Olsa <jolsa@redhat.com>
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Cc: John Garry <john.garry@huawei.com>
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Cc: Mark Rutland <mark.rutland@arm.com>
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Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
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Cc: Namhyung Kim <namhyung@kernel.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Wei Li <liwei391@huawei.com>
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Link: https://lore.kernel.org/r/20201119152441.6972-15-leo.yan@linaro.org
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Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Signed-off-by: Wei Li <liwei391@huawei.com>
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Reviewed-by: Yang Jihong <yangjihong1@huawei.com>
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Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
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---
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.../util/arm-spe-decoder/arm-spe-pkt-decoder.c | 18 ++++++++++++++++--
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1 file changed, 16 insertions(+), 2 deletions(-)
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diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
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index 1d1354a0eef4..84d661aab54f 100644
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--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
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+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
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@@ -343,9 +343,23 @@ static int arm_spe_pkt_desc_op_type(const struct arm_spe_pkt *packet,
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arm_spe_pkt_out_string(&err, &buf, &buf_len, " EXCL");
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if (payload & SPE_OP_PKT_AR)
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arm_spe_pkt_out_string(&err, &buf, &buf_len, " AR");
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- } else if (SPE_OP_PKT_LDST_SUBCLASS_GET(payload) ==
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- SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP) {
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+ }
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+
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+ switch (SPE_OP_PKT_LDST_SUBCLASS_GET(payload)) {
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+ case SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP:
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arm_spe_pkt_out_string(&err, &buf, &buf_len, " SIMD-FP");
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+ break;
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+ case SPE_OP_PKT_LDST_SUBCLASS_GP_REG:
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+ arm_spe_pkt_out_string(&err, &buf, &buf_len, " GP-REG");
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+ break;
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+ case SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG:
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+ arm_spe_pkt_out_string(&err, &buf, &buf_len, " UNSPEC-REG");
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+ break;
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+ case SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG:
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+ arm_spe_pkt_out_string(&err, &buf, &buf_len, " NV-SYSREG");
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+ break;
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+ default:
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+ break;
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}
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break;
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case SPE_OP_PKT_HDR_CLASS_BR_ERET:
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--
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2.27.0
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