133 lines
5.3 KiB
Diff
133 lines
5.3 KiB
Diff
From 57b8735c25b887a4233ddf7930c821acc78ca3f1 Mon Sep 17 00:00:00 2001
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From: Yicong Yang <yangyicong@hisilicon.com>
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Date: Thu, 17 Nov 2022 16:41:36 +0800
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Subject: [PATCH 40/55] drivers/perf: hisi: Add TLP filter support
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mainline inclusion
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from mainline-v6.2-rc1
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commit 17d573984d4d5ad73c7cb5edcf2024c585475b0c
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I8AU2M
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=17d573984d4d5ad73c7cb5edcf2024c585475b0c
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-----------------------------------------------------------------------
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The PMU support to filter the TLP when counting the bandwidth with below
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options:
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- only count the TLP headers
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- only count the TLP payloads
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- count both TLP headers and payloads
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In the current driver it's default to count the TLP payloads only, which
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will have an implicity side effects that on the traffic only have header
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only TLPs, we'll get no data.
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Make this user configuration through "len_mode" parameter and make it
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default to count both TLP headers and payloads when user not specified.
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Also update the documentation for it.
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Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
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Link: https://lore.kernel.org/r/20221117084136.53572-5-yangyicong@huawei.com
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Signed-off-by: Will Deacon <will@kernel.org>
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Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
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---
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.../admin-guide/perf/hisi-pcie-pmu.rst | 22 +++++++++++++++++--
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drivers/perf/hisilicon/hisi_pcie_pmu.c | 14 +++++++++++-
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2 files changed, 33 insertions(+), 3 deletions(-)
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diff --git a/Documentation/admin-guide/perf/hisi-pcie-pmu.rst b/Documentation/admin-guide/perf/hisi-pcie-pmu.rst
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index bbe66480ff85..6bace0e24c3f 100644
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--- a/Documentation/admin-guide/perf/hisi-pcie-pmu.rst
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+++ b/Documentation/admin-guide/perf/hisi-pcie-pmu.rst
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@@ -101,6 +101,24 @@ For example, "thr_len=4" means threshold is 2^4 DW, "thr_mode=0" means
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counter counts when TLP length >= threshold, and "thr_mode=1" means counts
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when TLP length < threshold.
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-Example usage of perf::
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+ Example usage of perf::
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+
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+ $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,thr_len=0x4,thr_mode=1/ sleep 5
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+
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+4. TLP Length filter
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+
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+ When counting bandwidth, the data can be composed of certain parts of TLP
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+ packets. You can specify it through "len_mode":
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+
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+ - 2'b00: Reserved (Do not use this since the behaviour is undefined)
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+ - 2'b01: Bandwidth of TLP payloads
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+ - 2'b10: Bandwidth of TLP headers
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+ - 2'b11: Bandwidth of both TLP payloads and headers
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+
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+ For example, "len_mode=2" means only counting the bandwidth of TLP headers
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+ and "len_mode=3" means the final bandwidth data is composed of both TLP
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+ headers and payloads. Default value if not specified is 2'b11.
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+
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+ Example usage of perf::
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- $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,thr_len=0x4,thr_mode=1/ sleep 5
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+ $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,len_mode=0x1/ sleep 5
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diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilicon/hisi_pcie_pmu.c
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index c115f5c77acb..6ded72383bb6 100644
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--- a/drivers/perf/hisilicon/hisi_pcie_pmu.c
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+++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c
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@@ -47,10 +47,14 @@
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#define HISI_PCIE_EVENT_M GENMASK_ULL(15, 0)
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#define HISI_PCIE_THR_MODE_M GENMASK_ULL(27, 27)
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#define HISI_PCIE_THR_M GENMASK_ULL(31, 28)
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+#define HISI_PCIE_LEN_M GENMASK_ULL(35, 34)
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#define HISI_PCIE_TARGET_M GENMASK_ULL(52, 36)
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#define HISI_PCIE_TRIG_MODE_M GENMASK_ULL(53, 53)
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#define HISI_PCIE_TRIG_M GENMASK_ULL(59, 56)
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+/* Default config of TLP length mode, will count both TLP headers and payloads */
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+#define HISI_PCIE_LEN_M_DEFAULT 3ULL
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+
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#define HISI_PCIE_MAX_COUNTERS 8
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#define HISI_PCIE_REG_STEP 8
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#define HISI_PCIE_THR_MAX_VAL 10
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@@ -91,6 +95,7 @@ HISI_PCIE_PMU_FILTER_ATTR(thr_len, config1, 3, 0);
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HISI_PCIE_PMU_FILTER_ATTR(thr_mode, config1, 4, 4);
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HISI_PCIE_PMU_FILTER_ATTR(trig_len, config1, 8, 5);
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HISI_PCIE_PMU_FILTER_ATTR(trig_mode, config1, 9, 9);
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+HISI_PCIE_PMU_FILTER_ATTR(len_mode, config1, 11, 10);
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HISI_PCIE_PMU_FILTER_ATTR(port, config2, 15, 0);
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HISI_PCIE_PMU_FILTER_ATTR(bdf, config2, 31, 16);
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@@ -218,8 +223,8 @@ static void hisi_pcie_pmu_config_filter(struct perf_event *event)
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{
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struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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+ u64 port, trig_len, thr_len, len_mode;
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u64 reg = HISI_PCIE_INIT_SET;
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- u64 port, trig_len, thr_len;
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/* Config HISI_PCIE_EVENT_CTRL according to event. */
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reg |= FIELD_PREP(HISI_PCIE_EVENT_M, hisi_pcie_get_real_event(event));
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@@ -248,6 +253,12 @@ static void hisi_pcie_pmu_config_filter(struct perf_event *event)
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reg |= HISI_PCIE_THR_EN;
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}
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+ len_mode = hisi_pcie_get_len_mode(event);
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+ if (len_mode)
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+ reg |= FIELD_PREP(HISI_PCIE_LEN_M, len_mode);
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+ else
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+ reg |= FIELD_PREP(HISI_PCIE_LEN_M, HISI_PCIE_LEN_M_DEFAULT);
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+
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hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, reg);
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}
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@@ -714,6 +725,7 @@ static struct attribute *hisi_pcie_pmu_format_attr[] = {
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HISI_PCIE_PMU_FORMAT_ATTR(thr_mode, "config1:4"),
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HISI_PCIE_PMU_FORMAT_ATTR(trig_len, "config1:5-8"),
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HISI_PCIE_PMU_FORMAT_ATTR(trig_mode, "config1:9"),
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+ HISI_PCIE_PMU_FORMAT_ATTR(len_mode, "config1:10-11"),
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HISI_PCIE_PMU_FORMAT_ATTR(port, "config2:0-15"),
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HISI_PCIE_PMU_FORMAT_ATTR(bdf, "config2:16-31"),
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NULL
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--
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2.27.0
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