58 lines
1.6 KiB
Diff
58 lines
1.6 KiB
Diff
From 52b22aa2df42650d15ff80d32c827a55e6907a49 Mon Sep 17 00:00:00 2001
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From: Chen Jun <chenjun102@huawei.com>
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Date: Thu, 19 May 2022 20:09:49 +0800
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Subject: [PATCH 24/55] perf: hisi: Fix read sccl_id and ccl_id error in some
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platform
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hulk inclusion
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I584X2
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CVE: NA
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--------------------------------
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Some platforms with TSV200 or CORTEX_A55, sccl and ccl are keep in
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aff2 if mt.
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Signed-off-by: Chen Jun <chenjun102@huawei.com>
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Reviewed-by: Weilong Chen <chenweilong@huawei.com>
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Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
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---
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drivers/perf/hisilicon/hisi_uncore_pmu.c | 19 +++++++++++++------
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1 file changed, 13 insertions(+), 6 deletions(-)
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diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c
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index eceff43c89f7..4a781c2e1992 100644
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--- a/drivers/perf/hisilicon/hisi_uncore_pmu.c
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+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
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@@ -437,12 +437,19 @@ static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp)
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bool mt = mpidr & MPIDR_MT_BITMASK;
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int sccl, ccl;
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- if (mt && read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
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- sccl = aff2 >> 3;
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- ccl = aff2 & 0x7;
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- } else if (mt) {
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- sccl = aff3;
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- ccl = aff2;
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+ if (mt) {
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+ switch (read_cpuid_part_number()) {
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+ case HISI_CPU_PART_TSV110:
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+ case HISI_CPU_PART_TSV200:
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+ case ARM_CPU_PART_CORTEX_A55:
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+ sccl = aff2 >> 3;
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+ ccl = aff2 & 0x7;
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+ break;
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+ default:
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+ sccl = aff3;
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+ ccl = aff2;
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+ break;
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+ }
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} else {
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sccl = aff2;
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ccl = aff1;
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--
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2.27.0
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