341 lines
11 KiB
Diff
341 lines
11 KiB
Diff
From 77e91e65e043b7cec81e193b005ead3183316bb6 Mon Sep 17 00:00:00 2001
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From: Shaokun Zhang <zhangshaokun@hisilicon.com>
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Date: Fri, 30 Jul 2021 15:44:06 +0800
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Subject: [PATCH 17/55] drivers/perf: hisi: Add new functions for HHA PMU
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mainline inclusion
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from mainline-v5.12-rc3
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commit 932f6a99f9b0c6b7039a5e2ce961009a8dc8c07c
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category: feature
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bugzilla: 175148
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=932f6a99f9b0c6b7039a5e2ce961009a8dc8c07c
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------------------------------------------------------------------------
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On HiSilicon Hip09 platform, some new functions are also supported on
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HHA PMU.
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* tracetag_en: it is the abbreviation of tracetag enable and allows user
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to count events according to tt_req or tt_core set in L3C PMU.
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* datasrc_skt: it is the abbreviation of data source from another
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socket and it is used in the multi-chips. It's the same as L3C PMU.
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* srcid_cmd & srcid_msk: pair of the fields are used to filter
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statistics that come from the specific CCL/ICL by the configuration.
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These are the abbreviation of source ID command and mask. The source
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ID is 11-bit and detailed descriptions are documented in
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Documentation/admin-guide/perf/hisi-pmu.rst.
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Cc: Mark Rutland <mark.rutland@arm.com>
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Cc: Will Deacon <will@kernel.org>
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Cc: John Garry <john.garry@huawei.com>
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Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Reviewed-by: John Garry <john.garry@huawei.com>
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Co-developed-by: Qi Liu <liuqi115@huawei.com>
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Signed-off-by: Qi Liu <liuqi115@huawei.com>
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Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
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Link: https://lore.kernel.org/r/1615186237-22263-6-git-send-email-zhangshaokun@hisilicon.com
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Signed-off-by: Will Deacon <will@kernel.org>
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Reviewed-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
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Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
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---
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drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 203 +++++++++++++++++--
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1 file changed, 188 insertions(+), 15 deletions(-)
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diff --git a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
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index 7941900ea667..a7e1749fc3e4 100644
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--- a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
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+++ b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c
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@@ -28,19 +28,136 @@
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#define HHA_VERSION 0x1cf0
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#define HHA_PERF_CTRL 0x1E00
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#define HHA_EVENT_CTRL 0x1E04
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+#define HHA_SRCID_CTRL 0x1E08
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+#define HHA_DATSRC_CTRL 0x1BF0
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#define HHA_EVENT_TYPE0 0x1E80
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/*
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- * Each counter is 48-bits and [48:63] are reserved
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- * which are Read-As-Zero and Writes-Ignored.
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+ * If the HW version only supports a 48-bit counter, then
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+ * bits [63:48] are reserved, which are Read-As-Zero and
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+ * Writes-Ignored.
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*/
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#define HHA_CNT0_LOWER 0x1F00
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-/* HHA has 16-counters */
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+/* HHA PMU v1 has 16 counters and v2 only has 8 counters */
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#define HHA_V1_NR_COUNTERS 0x10
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+#define HHA_V2_NR_COUNTERS 0x8
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#define HHA_PERF_CTRL_EN 0x1
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+#define HHA_TRACETAG_EN BIT(31)
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+#define HHA_SRCID_EN BIT(2)
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+#define HHA_SRCID_CMD_SHIFT 6
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+#define HHA_SRCID_MSK_SHIFT 20
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+#define HHA_SRCID_CMD GENMASK(16, 6)
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+#define HHA_SRCID_MSK GENMASK(30, 20)
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+#define HHA_DATSRC_SKT_EN BIT(23)
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#define HHA_EVTYPE_NONE 0xff
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#define HHA_V1_NR_EVENT 0x65
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+#define HHA_V2_NR_EVENT 0xCE
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+
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+HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_cmd, config1, 10, 0);
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+HISI_PMU_EVENT_ATTR_EXTRACTOR(srcid_msk, config1, 21, 11);
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+HISI_PMU_EVENT_ATTR_EXTRACTOR(tracetag_en, config1, 22, 22);
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+HISI_PMU_EVENT_ATTR_EXTRACTOR(datasrc_skt, config1, 23, 23);
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+
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+static void hisi_hha_pmu_enable_tracetag(struct perf_event *event)
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+{
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+ struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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+ u32 tt_en = hisi_get_tracetag_en(event);
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+
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+ if (tt_en) {
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+ u32 val;
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+
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+ val = readl(hha_pmu->base + HHA_SRCID_CTRL);
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+ val |= HHA_TRACETAG_EN;
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+ writel(val, hha_pmu->base + HHA_SRCID_CTRL);
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+ }
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+}
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+
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+static void hisi_hha_pmu_clear_tracetag(struct perf_event *event)
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+{
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+ struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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+ u32 val;
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+
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+ val = readl(hha_pmu->base + HHA_SRCID_CTRL);
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+ val &= ~HHA_TRACETAG_EN;
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+ writel(val, hha_pmu->base + HHA_SRCID_CTRL);
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+}
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+
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+static void hisi_hha_pmu_config_ds(struct perf_event *event)
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+{
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+ struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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+ u32 ds_skt = hisi_get_datasrc_skt(event);
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+
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+ if (ds_skt) {
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+ u32 val;
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+
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+ val = readl(hha_pmu->base + HHA_DATSRC_CTRL);
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+ val |= HHA_DATSRC_SKT_EN;
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+ writel(ds_skt, hha_pmu->base + HHA_DATSRC_CTRL);
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+ }
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+}
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+
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+static void hisi_hha_pmu_clear_ds(struct perf_event *event)
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+{
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+ struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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+ u32 ds_skt = hisi_get_datasrc_skt(event);
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+
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+ if (ds_skt) {
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+ u32 val;
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+
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+ val = readl(hha_pmu->base + HHA_DATSRC_CTRL);
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+ val &= ~HHA_DATSRC_SKT_EN;
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+ writel(ds_skt, hha_pmu->base + HHA_DATSRC_CTRL);
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+ }
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+}
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+
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+static void hisi_hha_pmu_config_srcid(struct perf_event *event)
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+{
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+ struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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+ u32 cmd = hisi_get_srcid_cmd(event);
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+
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+ if (cmd) {
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+ u32 val, msk;
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+
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+ msk = hisi_get_srcid_msk(event);
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+ val = readl(hha_pmu->base + HHA_SRCID_CTRL);
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+ val |= HHA_SRCID_EN | (cmd << HHA_SRCID_CMD_SHIFT) |
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+ (msk << HHA_SRCID_MSK_SHIFT);
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+ writel(val, hha_pmu->base + HHA_SRCID_CTRL);
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+ }
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+}
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+
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+static void hisi_hha_pmu_disable_srcid(struct perf_event *event)
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+{
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+ struct hisi_pmu *hha_pmu = to_hisi_pmu(event->pmu);
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+ u32 cmd = hisi_get_srcid_cmd(event);
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+
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+ if (cmd) {
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+ u32 val;
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+
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+ val = readl(hha_pmu->base + HHA_SRCID_CTRL);
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+ val &= ~(HHA_SRCID_EN | HHA_SRCID_MSK | HHA_SRCID_CMD);
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+ writel(val, hha_pmu->base + HHA_SRCID_CTRL);
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+ }
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+}
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+
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+static void hisi_hha_pmu_enable_filter(struct perf_event *event)
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+{
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+ if (event->attr.config1 != 0x0) {
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+ hisi_hha_pmu_enable_tracetag(event);
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+ hisi_hha_pmu_config_ds(event);
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+ hisi_hha_pmu_config_srcid(event);
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+ }
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+}
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+
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+static void hisi_hha_pmu_disable_filter(struct perf_event *event)
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+{
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+ if (event->attr.config1 != 0x0) {
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+ hisi_hha_pmu_disable_srcid(event);
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+ hisi_hha_pmu_clear_ds(event);
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+ hisi_hha_pmu_clear_tracetag(event);
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+ }
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+}
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/*
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* Select the counter register offset using the counter index
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@@ -170,7 +287,8 @@ static void hisi_hha_pmu_clear_int_status(struct hisi_pmu *hha_pmu, int idx)
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static const struct acpi_device_id hisi_hha_pmu_acpi_match[] = {
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{ "HISI0243", },
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- {},
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+ { "HISI0244", },
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+ {}
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};
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MODULE_DEVICE_TABLE(acpi, hisi_hha_pmu_acpi_match);
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@@ -180,13 +298,6 @@ static int hisi_hha_pmu_init_data(struct platform_device *pdev,
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unsigned long long id;
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acpi_status status;
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- status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
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- "_UID", NULL, &id);
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- if (ACPI_FAILURE(status))
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- return -EINVAL;
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-
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- hha_pmu->index_id = id;
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-
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/*
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* Use SCCL_ID and UID to identify the HHA PMU, while
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* SCCL_ID is in MPIDR[aff2].
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@@ -196,6 +307,22 @@ static int hisi_hha_pmu_init_data(struct platform_device *pdev,
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dev_err(&pdev->dev, "Can not read hha sccl-id!\n");
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return -EINVAL;
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}
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+
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+ /*
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+ * Early versions of BIOS support _UID by mistake, so we support
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+ * both "hisilicon, idx-id" as preference, if available.
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+ */
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+ if (device_property_read_u32(&pdev->dev, "hisilicon,idx-id",
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+ &hha_pmu->index_id)) {
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+ status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
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+ "_UID", NULL, &id);
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+ if (ACPI_FAILURE(status)) {
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+ dev_err(&pdev->dev, "Cannot read idx-id!\n");
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+ return -EINVAL;
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+ }
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+
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+ hha_pmu->index_id = id;
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+ }
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/* HHA PMUs only share the same SCCL */
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hha_pmu->ccl_id = -1;
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@@ -220,6 +347,20 @@ static const struct attribute_group hisi_hha_pmu_v1_format_group = {
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.attrs = hisi_hha_pmu_v1_format_attr,
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};
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+static struct attribute *hisi_hha_pmu_v2_format_attr[] = {
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+ HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
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+ HISI_PMU_FORMAT_ATTR(srcid_cmd, "config1:0-10"),
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+ HISI_PMU_FORMAT_ATTR(srcid_msk, "config1:11-21"),
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+ HISI_PMU_FORMAT_ATTR(tracetag_en, "config1:22"),
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+ HISI_PMU_FORMAT_ATTR(datasrc_skt, "config1:23"),
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+ NULL
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+};
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+
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+static const struct attribute_group hisi_hha_pmu_v2_format_group = {
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+ .name = "format",
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+ .attrs = hisi_hha_pmu_v2_format_attr,
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+};
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+
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static struct attribute *hisi_hha_pmu_v1_events_attr[] = {
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HISI_PMU_EVENT_ATTR(rx_ops_num, 0x00),
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HISI_PMU_EVENT_ATTR(rx_outer, 0x01),
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@@ -255,6 +396,20 @@ static const struct attribute_group hisi_hha_pmu_v1_events_group = {
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.attrs = hisi_hha_pmu_v1_events_attr,
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};
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+static struct attribute *hisi_hha_pmu_v2_events_attr[] = {
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+ HISI_PMU_EVENT_ATTR(rx_ops_num, 0x00),
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+ HISI_PMU_EVENT_ATTR(rx_outer, 0x01),
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+ HISI_PMU_EVENT_ATTR(rx_sccl, 0x02),
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+ HISI_PMU_EVENT_ATTR(hha_retry, 0x2e),
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+ HISI_PMU_EVENT_ATTR(cycles, 0x55),
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+ NULL
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+};
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+
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+static const struct attribute_group hisi_hha_pmu_v2_events_group = {
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+ .name = "events",
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+ .attrs = hisi_hha_pmu_v2_events_attr,
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+};
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+
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static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
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static struct attribute *hisi_hha_pmu_cpumask_attrs[] = {
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@@ -286,6 +441,14 @@ static const struct attribute_group *hisi_hha_pmu_v1_attr_groups[] = {
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NULL,
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};
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+static const struct attribute_group *hisi_hha_pmu_v2_attr_groups[] = {
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+ &hisi_hha_pmu_v2_format_group,
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+ &hisi_hha_pmu_v2_events_group,
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+ &hisi_hha_pmu_cpumask_attr_group,
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+ &hisi_hha_pmu_identifier_group,
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+ NULL
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+};
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+
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static const struct hisi_uncore_ops hisi_uncore_hha_ops = {
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.write_evtype = hisi_hha_pmu_write_evtype,
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.get_event_idx = hisi_uncore_pmu_get_event_idx,
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@@ -299,6 +462,8 @@ static const struct hisi_uncore_ops hisi_uncore_hha_ops = {
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.read_counter = hisi_hha_pmu_read_counter,
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.get_int_status = hisi_hha_pmu_get_int_status,
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.clear_int_status = hisi_hha_pmu_clear_int_status,
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+ .enable_filter = hisi_hha_pmu_enable_filter,
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+ .disable_filter = hisi_hha_pmu_disable_filter,
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};
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static int hisi_hha_pmu_dev_probe(struct platform_device *pdev,
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@@ -314,12 +479,20 @@ static int hisi_hha_pmu_dev_probe(struct platform_device *pdev,
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if (ret)
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return ret;
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- hha_pmu->num_counters = HHA_V1_NR_COUNTERS;
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- hha_pmu->counter_bits = 48;
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+ if (hha_pmu->identifier >= HISI_PMU_V2) {
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+ hha_pmu->counter_bits = 64;
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+ hha_pmu->check_event = HHA_V2_NR_EVENT;
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+ hha_pmu->pmu_events.attr_groups = hisi_hha_pmu_v2_attr_groups;
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+ hha_pmu->num_counters = HHA_V2_NR_COUNTERS;
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+ } else {
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+ hha_pmu->counter_bits = 48;
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+ hha_pmu->check_event = HHA_V1_NR_EVENT;
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+ hha_pmu->pmu_events.attr_groups = hisi_hha_pmu_v1_attr_groups;
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+ hha_pmu->num_counters = HHA_V1_NR_COUNTERS;
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+ }
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hha_pmu->ops = &hisi_uncore_hha_ops;
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hha_pmu->dev = &pdev->dev;
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hha_pmu->on_cpu = -1;
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- hha_pmu->check_event = HHA_V1_NR_EVENT;
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return 0;
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}
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@@ -361,7 +534,7 @@ static int hisi_hha_pmu_probe(struct platform_device *pdev)
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.start = hisi_uncore_pmu_start,
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.stop = hisi_uncore_pmu_stop,
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.read = hisi_uncore_pmu_read,
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- .attr_groups = hisi_hha_pmu_v1_attr_groups,
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+ .attr_groups = hha_pmu->pmu_events.attr_groups,
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
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};
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--
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2.27.0
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