135 lines
5.3 KiB
Diff
135 lines
5.3 KiB
Diff
From a396cef35ddf1a20786e8bd5e08396af11906316 Mon Sep 17 00:00:00 2001
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From: Jiaran Zhang <zhangjiaran@huawei.com>
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Date: Sat, 24 Jul 2021 15:45:15 +0800
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Subject: [PATCH 080/283] net: hns3: add error handling compatibility during
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initialization
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mainline inclusion
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from mainline-v5.14-rc1
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commit 1c360a4a077fc0f74a350fe2ef267cbe8a9388e3
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category: feature
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bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1c360a4a077fc0f74a350fe2ef267cbe8a9388e3
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----------------------------------------------------------------------
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During initialization, the driver logs and clears the hw errors that
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already occurred. For device supports imp-handle ras capability, it
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needs handle different error status, otherwise it may cause wrong reset.
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So fix it by adding a new processing branch.
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Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
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Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
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Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
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Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
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---
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.../hisilicon/hns3/hns3pf/hclge_err.c | 22 +++++++++++++++++++
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.../hisilicon/hns3/hns3pf/hclge_err.h | 2 ++
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.../hisilicon/hns3/hns3pf/hclge_main.c | 21 +++++++++---------
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3 files changed, 34 insertions(+), 11 deletions(-)
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
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index b303cf2d72bf..a4e9aa9c5d6f 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
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@@ -2155,6 +2155,28 @@ void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev)
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kfree(desc);
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}
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+bool hclge_find_error_source(struct hclge_dev *hdev)
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+{
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+ u32 msix_src_flag, hw_err_src_flag;
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+
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+ msix_src_flag = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
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+ HCLGE_VECTOR0_REG_MSIX_MASK;
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+
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+ hw_err_src_flag = hclge_read_dev(&hdev->hw,
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+ HCLGE_RAS_PF_OTHER_INT_STS_REG) &
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+ HCLGE_RAS_REG_ERR_MASK;
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+
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+ return msix_src_flag || hw_err_src_flag;
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+}
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+
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+void hclge_handle_occurred_error(struct hclge_dev *hdev)
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+{
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+ struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
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+
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+ if (hclge_find_error_source(hdev))
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+ hclge_handle_error_info_log(ae_dev);
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+}
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+
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static void
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hclge_handle_error_type_reg_log(struct device *dev,
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struct hclge_mod_err_info *mod_info,
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
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index aa9bd5a5e7dd..a53781491473 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
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@@ -242,6 +242,8 @@ int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
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int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
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int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
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void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);
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+bool hclge_find_error_source(struct hclge_dev *hdev);
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+void hclge_handle_occurred_error(struct hclge_dev *hdev);
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pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
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int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
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unsigned long *reset_requests);
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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index b7e3b4e399c9..f81c6f8bb030 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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@@ -4176,18 +4176,11 @@ static void hclge_handle_err_reset_request(struct hclge_dev *hdev)
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static void hclge_handle_err_recovery(struct hclge_dev *hdev)
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{
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- u32 mask_val = HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK;
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struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
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- u32 msix_src_flag, hw_err_src_flag;
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- msix_src_flag = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
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- HCLGE_VECTOR0_REG_MSIX_MASK;
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+ ae_dev->hw_err_reset_req = 0;
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- hw_err_src_flag = hclge_read_dev(&hdev->hw,
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- HCLGE_RAS_PF_OTHER_INT_STS_REG) &
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- mask_val;
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-
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- if (msix_src_flag || hw_err_src_flag) {
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+ if (hclge_find_error_source(hdev)) {
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hclge_handle_error_info_log(ae_dev);
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hclge_handle_mac_tnl(hdev);
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}
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@@ -10734,7 +10727,10 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
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hclge_clear_resetting_state(hdev);
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/* Log and clear the hw errors those already occurred */
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- hclge_handle_all_hns_hw_errors(ae_dev);
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+ if (hnae3_dev_ras_imp_supported(hdev))
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+ hclge_handle_occurred_error(hdev);
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+ else
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+ hclge_handle_all_hns_hw_errors(ae_dev);
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/* request delayed reset for the error recovery because an immediate
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* global reset on a PF affecting pending initialization of other PFs
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@@ -11088,7 +11084,10 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
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set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &hdev->state);
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/* Log and clear the hw errors those already occurred */
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- hclge_handle_all_hns_hw_errors(ae_dev);
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+ if (hnae3_dev_ras_imp_supported(hdev))
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+ hclge_handle_occurred_error(hdev);
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+ else
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+ hclge_handle_all_hns_hw_errors(ae_dev);
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/* Re-enable the hw error interrupts because
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* the interrupts get disabled on global reset.
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--
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2.34.1
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