121 lines
4.0 KiB
Diff
121 lines
4.0 KiB
Diff
From d1286fe7f4e98918dd074a4e0a4d593fb6378d42 Mon Sep 17 00:00:00 2001
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From: Wei Li <liwei391@huawei.com>
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Date: Fri, 30 Jul 2021 15:44:00 +0800
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Subject: [PATCH 21/21] drivers/perf: Add support for ARMv8.3-SPE
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mainline inclusion
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from mainline-v5.11-rc4
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commit 4a669e2432fce9c01522a8453460e89f877dccd4
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I4NGPV
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4a669e2432fce9c01522a8453460e89f877dccd4
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------------------------------------------------------------------------
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Armv8.3 extends the SPE by adding:
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- Alignment field in the Events packet, and filtering on this event
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using PMSEVFR_EL1.
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- Support for the Scalable Vector Extension (SVE).
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The main additions for SVE are:
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- Recording the vector length for SVE operations in the Operation Type
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packet. It is not possible to filter on vector length.
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- Incomplete predicate and empty predicate fields in the Events packet,
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and filtering on these events using PMSEVFR_EL1.
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Update the check of pmsevfr for empty/partial predicated SVE and
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alignment event in SPE driver.
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Signed-off-by: Wei Li <liwei391@huawei.com>
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Link: https://lore.kernel.org/r/20201203141609.14148-1-liwei391@huawei.com
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Signed-off-by: Will Deacon <will@kernel.org>
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Reviewed-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
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Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
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---
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arch/arm64/include/asm/sysreg.h | 9 ++++++++-
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drivers/perf/arm_spe_pmu.c | 17 +++++++++++++++--
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2 files changed, 23 insertions(+), 3 deletions(-)
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diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
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index 0fd51d253648..f993af239247 100644
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--- a/arch/arm64/include/asm/sysreg.h
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+++ b/arch/arm64/include/asm/sysreg.h
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@@ -252,7 +252,11 @@
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#define SYS_PMSFCR_EL1_ST_SHIFT 18
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#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5)
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-#define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL
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+#define SYS_PMSEVFR_EL1_RES0_8_2 \
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+ (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
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+ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
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+#define SYS_PMSEVFR_EL1_RES0_8_3 \
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+ (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
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#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6)
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#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0
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@@ -619,6 +623,9 @@
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#define ID_AA64DFR0_TRACEVER_SHIFT 4
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#define ID_AA64DFR0_DEBUGVER_SHIFT 0
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+#define ID_AA64DFR0_PMSVER_8_2 0x1
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+#define ID_AA64DFR0_PMSVER_8_3 0x2
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+
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#define ID_ISAR5_RDM_SHIFT 24
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#define ID_ISAR5_CRC32_SHIFT 16
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#define ID_ISAR5_SHA2_SHIFT 12
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diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
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index af84f3a61e96..74318410774c 100644
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--- a/drivers/perf/arm_spe_pmu.c
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+++ b/drivers/perf/arm_spe_pmu.c
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@@ -65,7 +65,7 @@ struct arm_spe_pmu {
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struct hlist_node hotplug_node;
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int irq; /* PPI */
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-
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+ u16 pmsver;
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u16 min_period;
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u16 counter_sz;
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@@ -666,6 +666,18 @@ static irqreturn_t arm_spe_pmu_irq_handler(int irq, void *dev)
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return IRQ_HANDLED;
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}
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+static u64 arm_spe_pmsevfr_res0(u16 pmsver)
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+{
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+ switch (pmsver) {
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+ case ID_AA64DFR0_PMSVER_8_2:
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+ return SYS_PMSEVFR_EL1_RES0_8_2;
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+ case ID_AA64DFR0_PMSVER_8_3:
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+ /* Return the highest version we support in default */
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+ default:
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+ return SYS_PMSEVFR_EL1_RES0_8_3;
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+ }
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+}
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+
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/* Perf callbacks */
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static int arm_spe_pmu_event_init(struct perf_event *event)
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{
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@@ -681,7 +693,7 @@ static int arm_spe_pmu_event_init(struct perf_event *event)
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!cpumask_test_cpu(event->cpu, &spe_pmu->supported_cpus))
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return -ENOENT;
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- if (arm_spe_event_to_pmsevfr(event) & SYS_PMSEVFR_EL1_RES0)
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+ if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver))
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return -EOPNOTSUPP;
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if (attr->exclude_idle)
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@@ -948,6 +960,7 @@ static void __arm_spe_pmu_dev_probe(void *info)
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fld, smp_processor_id());
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return;
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}
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+ spe_pmu->pmsver = (u16)fld;
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/* Read PMBIDR first to determine whether or not we have access */
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reg = read_sysreg_s(SYS_PMBIDR_EL1);
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--
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2.27.0
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