53 lines
1.8 KiB
Diff
53 lines
1.8 KiB
Diff
From fc96a37739f1017fb91a0339f7f9b101704ca130 Mon Sep 17 00:00:00 2001
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From: Dongdong Liu <liudongdong3@huawei.com>
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Date: Tue, 18 Jan 2022 17:21:17 +0800
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Subject: [PATCH 01/19] PCI: Support BAR sizes up to 8TB
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mainline inclusion
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from mainline-v5.18-rc1
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commit 3dc8a1f6f64481a8a5a669633e880f26dae0d752
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I6XOIU
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3dc8a1f6f64481a8a5a669633e880f26dae0d752
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----------------------------------------------------------------------
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Current kernel reports that BARs larger than 128GB, e.g., this 4TB BAR, are
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disabled:
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pci 0000:01:00.0: disabling BAR 4: [mem 0x00000000-0x3ffffffffff 64bit pref] (bad alignment 0x40000000000)
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Increase the maximum BAR size from 128GB to 8TB for future expansion.
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[bhelgaas: commit log]
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Link: https://lore.kernel.org/r/20220118092117.10089-1-liudongdong3@huawei.com
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Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Signed-off-by: huangfangrun <huangfangrun1@h-partners.com>
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Signed-off-by: YunYi Yang <yangyunyi2@huawei.com>
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Conflicts:
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drivers/pci/setup-bus.c
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---
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drivers/pci/setup-bus.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
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index 39d19302f3cb..426d21c1db31 100644
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--- a/drivers/pci/setup-bus.c
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+++ b/drivers/pci/setup-bus.c
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@@ -968,7 +968,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
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{
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struct pci_dev *dev;
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resource_size_t min_align, align, size, size0, size1;
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- resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */
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+ resource_size_t aligns[24]; /* Alignments from 1MB to 8TB */
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int order, max_order;
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struct resource *b_res = find_free_bus_resource(bus,
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mask | IORESOURCE_PREFETCH, type);
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--
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2.27.0
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