109 lines
4.5 KiB
Diff
109 lines
4.5 KiB
Diff
From 6dd6e7a54d395f1a7a9ab7e4534ac54657d7496d Mon Sep 17 00:00:00 2001
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From: Jiantao Xiao <xiaojiantao1@h-partners.com>
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Date: Fri, 31 Mar 2023 16:25:49 +0800
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Subject: [PATCH 198/283] net: hns3: disbable pfc en before the reset
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driver inclusion
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category: feature
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bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
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CVE: NA
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----------------------------------------------------------------------
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To prevent the system from abnormally sending PFC frames after an
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abnormal reset. If the reset type is not imp reset or global reset,
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the system notifies the firmware to disable pfc before the reset.
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Signed-off-by: shaojijie <shaojijie@huawei.com>
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Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
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Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
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Conflicts:
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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
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---
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.../ethernet/hisilicon/hns3/hns3pf/hclge_ext.c | 1 +
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.../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 15 +++++++++------
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.../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 4 ++--
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.../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h | 5 +++++
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4 files changed, 17 insertions(+), 8 deletions(-)
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
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index 0f4eff899e94..801737b11732 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
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@@ -590,6 +590,7 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
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[HNAE3_EXT_OPC_GET_PORT_EXT_ID_INFO] = hclge_get_extend_port_id_info,
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[HNAE3_EXT_OPC_GET_PORT_EXT_NUM_INFO] = hclge_get_extend_port_num_info,
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[HNAE3_EXT_OPC_GET_PORT_NUM] = hclge_get_port_num,
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+ [HNAE3_EXT_OPC_SET_PFC_TIME] = hclge_set_pause_trans_time,
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};
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int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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index 3779181b8f59..47c526b5271b 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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@@ -7790,12 +7790,15 @@ static void hclge_ae_stop(struct hnae3_handle *handle)
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/* If it is not PF reset or FLR, the firmware will disable the MAC,
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* so it only need to stop phy here.
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*/
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- if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
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- hdev->reset_type != HNAE3_FUNC_RESET &&
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- hdev->reset_type != HNAE3_FLR_RESET) {
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- hclge_mac_stop_phy(hdev);
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- hclge_update_link_status(hdev);
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- return;
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+ if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
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+ hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE,
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+ HCLGE_PFC_DISABLE);
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+ if (hdev->reset_type != HNAE3_FUNC_RESET &&
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+ hdev->reset_type != HNAE3_FLR_RESET) {
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+ hclge_mac_stop_phy(hdev);
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+ hclge_update_link_status(hdev);
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+ return;
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+ }
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}
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hclge_reset_tqp(handle);
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
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index ca93919ed817..b535f3dd842b 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
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@@ -171,8 +171,8 @@ int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
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return hclge_cmd_send(&hdev->hw, &desc, 1);
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}
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-static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
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- u8 pfc_bitmap)
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+int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
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+ u8 pfc_bitmap)
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{
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struct hclge_desc desc;
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struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
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index 34eb52d3d7ee..98d0f871ee61 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
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@@ -134,6 +134,9 @@ struct hclge_bp_to_qs_map_cmd {
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u32 rsvd1;
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};
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+#define HCLGE_PFC_DISABLE 0
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+#define HCLGE_PFC_TX_RX_DISABLE 0
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+
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struct hclge_pfc_en_cmd {
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u8 tx_rx_en_bitmap;
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u8 pri_en_bitmap;
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@@ -192,6 +195,8 @@ void hclge_tm_pfc_info_update(struct hclge_dev *hdev);
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int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
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int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
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int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
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+int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
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+ u8 pfc_bitmap);
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int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
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u8 pause_trans_gap, u16 pause_trans_time);
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int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
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--
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2.34.1
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