105 lines
3.5 KiB
Diff
105 lines
3.5 KiB
Diff
From a009f74ef5b6cf1953abd034da40e4ba27e7e1a1 Mon Sep 17 00:00:00 2001
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From: Yicong Yang <yangyicong@hisilicon.com>
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Date: Thu, 8 Dec 2022 21:45:25 +0800
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Subject: [PATCH 36/39] spi: hisi-sfc-v3xx: add address mode check
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mainline inclusion
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from mainline-v5.12-rc1
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commit 6d2386e36440165da782dbc5c0de40f31665e108
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I8CSBP
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6d2386e36440165da782dbc5c0de40f31665e108
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--------------------------------------------------------------------------
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The address mode is either 3 or 4 for the controller, which is configured
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by the firmware and cannot be modified in the OS driver. Get the
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firmware configuration and add address mode check in the .supports_op()
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to block invalid operations.
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Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
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Acked-by: John Garry <john.garry@huawei.com>
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Link: https://lore.kernel.org/r/1611740450-47975-3-git-send-email-yangyicong@hisilicon.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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Signed-off-by: Wangming Shao <shaowangming@h-partners.com>
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Reviewed-by: Yicong Yang <yangyicong@huawei.com>
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Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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Signed-off-by: YunYi Yang <yangyunyi2@huawei.com>
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---
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drivers/spi/spi-hisi-sfc-v3xx.c | 25 ++++++++++++++++++++++++-
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1 file changed, 24 insertions(+), 1 deletion(-)
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diff --git a/drivers/spi/spi-hisi-sfc-v3xx.c b/drivers/spi/spi-hisi-sfc-v3xx.c
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index e679321c7e23..3cb6735aaf34 100644
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--- a/drivers/spi/spi-hisi-sfc-v3xx.c
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+++ b/drivers/spi/spi-hisi-sfc-v3xx.c
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@@ -19,6 +19,8 @@
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#define HISI_SFC_V3XX_VERSION (0x1f8)
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+#define HISI_SFC_V3XX_GLB_CFG (0x100)
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+#define HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE BIT(2)
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#define HISI_SFC_V3XX_RAW_INT_STAT (0x120)
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#define HISI_SFC_V3XX_INT_STAT (0x124)
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#define HISI_SFC_V3XX_INT_MASK (0x128)
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@@ -75,6 +77,7 @@ struct hisi_sfc_v3xx_host {
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void __iomem *regbase;
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int max_cmd_dword;
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struct completion *completion;
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+ u8 address_mode;
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int irq;
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};
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@@ -172,10 +175,18 @@ static int hisi_sfc_v3xx_adjust_op_size(struct spi_mem *mem,
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static bool hisi_sfc_v3xx_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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+ struct spi_device *spi = mem->spi;
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+ struct hisi_sfc_v3xx_host *host;
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+
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+ host = spi_controller_get_devdata(spi->master);
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+
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if (op->data.buswidth > 4 || op->dummy.buswidth > 4 ||
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op->addr.buswidth > 4 || op->cmd.buswidth > 4)
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return false;
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+ if (op->addr.nbytes != host->address_mode && op->addr.nbytes)
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+ return false;
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+
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return spi_mem_default_supports_op(mem, op);
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}
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@@ -425,7 +436,7 @@ static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
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struct device *dev = &pdev->dev;
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struct hisi_sfc_v3xx_host *host;
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struct spi_controller *ctlr;
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- u32 version;
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+ u32 version, glb_config;
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int ret;
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ctlr = spi_alloc_master(&pdev->dev, sizeof(*host));
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@@ -474,6 +485,18 @@ static int hisi_sfc_v3xx_probe(struct platform_device *pdev)
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ctlr->num_chipselect = 1;
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ctlr->mem_ops = &hisi_sfc_v3xx_mem_ops;
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+ /*
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+ * The address mode of the controller is either 3 or 4,
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+ * which is indicated by the address mode bit in
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+ * the global config register. The register is read only
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+ * for the OS driver.
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+ */
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+ glb_config = readl(host->regbase + HISI_SFC_V3XX_GLB_CFG);
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+ if (glb_config & HISI_SFC_V3XX_GLB_CFG_CS0_ADDR_MODE)
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+ host->address_mode = 4;
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+ else
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+ host->address_mode = 3;
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+
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version = readl(host->regbase + HISI_SFC_V3XX_VERSION);
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if (version >= 0x351)
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--
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2.27.0
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