135 lines
4.0 KiB
Diff
135 lines
4.0 KiB
Diff
From 8061299b4e8c67438cacec2896d52d7440987798 Mon Sep 17 00:00:00 2001
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From: Qi Liu <liuqi115@huawei.com>
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Date: Wed, 30 Nov 2022 19:01:38 +0800
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Subject: [PATCH 189/201] perf jevents: Add support for HiSilicon HHA PMU
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aliasing
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driver inclusion
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I63VF5
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--------------------------------------------------------------------------
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Add support for HiSilicon HHA PMU aliasing on Hip09 platform.
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Signed-off-by: Qi Liu <liuqi115@huawei.com>
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Signed-off-by: Junhao He <hejunhao3@huawei.com>
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Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
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---
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.../arm64/hisilicon/hip09/sys/uncore-hha.json | 102 ++++++++++++++++++
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1 file changed, 102 insertions(+)
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create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json
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diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json
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new file mode 100644
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index 000000000000..e49dceeaa263
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--- /dev/null
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+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json
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@@ -0,0 +1,102 @@
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+[
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+ {
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+ "EventCode": "0x00",
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+ "EventName": "rx_ops_num",
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+ "BriefDescription": "The number of all operations received by the HHA",
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+ "Compat": "0x00000030",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "EventCode": "0x01",
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+ "EventName": "rx_outer",
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+ "BriefDescription": "The number of all operations received by the HHA from another socket",
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+ "Compat": "0x00000030",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "EventCode": "0x02",
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+ "EventName": "rx_sccl",
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+ "BriefDescription": "The number of all operations received by the HHA from another SCCL in this socket",
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+ "Compat": "0x00000030",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "EventCode": "0x1c",
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+ "EventName": "rd_ddr_64b",
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+ "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
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+ "Compat": "0x00000030",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "EventCode": "0x1d",
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+ "EventName": "wr_ddr_64b",
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+ "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
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+ "Compat": "0x00000030",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "EventCode": "0x1e",
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+ "EventName": "rd_ddr_128b",
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+ "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
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+ "Compat": "0x00000030",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "EventCode": "0x1f",
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+ "EventName": "wr_ddr_128b",
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+ "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
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+ "Compat": "0x00000030",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "EventCode": "0x2e",
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+ "EventName": "hha_retry",
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+ "BriefDescription": "Count of the HHA retry",
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+ "Compat": "0x00000030",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "EventCode": "0x55",
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+ "EventName": "hha_cycles",
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+ "BriefDescription": "Count of the HHA cycles",
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+ "Compat": "0x00000030",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "EventName": "cycles",
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+ "Compat": "0x00000030",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "MetricExpr": "(rd_ddr_64b * 64 + rd_ddr_128b *128) / duration_time",
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+ "BriefDescription": "Average bandwidth of reading DDRC(Byte/s)",
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+ "Compat": "0x00000030",
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+ "MetricGroup": "HHA",
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+ "MetricName": "hha_read_ddrc_bw",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "MetricExpr": "(wr_ddr_64b * 64 + wr_ddr_128b *128) / duration_time",
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+ "BriefDescription": "Average bandwidth of writing DDRC(Byte/s)",
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+ "Compat": "0x00000030",
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+ "MetricGroup": "HHA",
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+ "MetricName": "hha_write_ddrc_bw",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "MetricExpr": "rx_outer / rx_ops_num",
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+ "BriefDescription": "Rate of cross-chip operations received by HHA",
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+ "Compat": "0x00000030",
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+ "MetricGroup": "HHA",
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+ "MetricName": "cross_chip_ops_rate",
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+ "Unit": "hisi_sccl,hha"
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+ },
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+ {
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+ "MetricExpr": "rx_sccl / rx_ops_num",
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+ "BriefDescription": "Rate of cross-die operations received by HHA",
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+ "Compat": "0x00000030",
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+ "MetricGroup": "HHA",
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+ "MetricName": "cross_die_ops_rate",
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+ "Unit": "hisi_sccl,hha"
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+ }
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+]
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\ No newline at end of file
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--
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2.27.0
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