311c3bde26
Backport patches from upstream to fix the issue I8K8XV of PMU. Signed-off-by: Yuan Zhang <zhangyuan162@huawei.com>
90 lines
3.2 KiB
Diff
90 lines
3.2 KiB
Diff
From 6a416c5efa3ce99f5f0f7e9c603b42b0e047481c Mon Sep 17 00:00:00 2001
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From: Andrew Murray <andrew.murray@arm.com>
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Date: Tue, 28 Nov 2023 15:46:33 +0800
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Subject: [PATCH 2/2] KVM: arm64: limit PMU version to PMUv3 for ARMv8.1
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mainline inclusion
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from mainline-v5.7-rc1
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commit c854188ea01062f5a5fd7f05658feb1863774eaa
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category: bugfix
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bugzilla: https://gitee.com/openeuler/kernel/issues/I8K8XV
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c854188ea01062f5a5fd7f05658feb1863774eaa
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-----------------------------------
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commit c854188ea01062f5a5fd7f05658feb1863774eaa upstream.
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We currently expose the PMU version of the host to the guest via
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emulation of the DFR0_EL1 and AA64DFR0_EL1 debug feature registers.
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However many of the features offered beyond PMUv3 for 8.1 are not
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supported in KVM. Examples of this include support for the PMMIR
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registers (added in PMUv3 for ARMv8.4) and 64-bit event counters
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added in (PMUv3 for ARMv8.5).
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Let's trap the Debug Feature Registers in order to limit
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PMUVer/PerfMon in the Debug Feature Registers to PMUv3 for ARMv8.1
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to avoid unexpected behaviour.
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Both ID_AA64DFR0.PMUVer and ID_DFR0.PerfMon follow the "Alternative ID
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scheme used for the Performance Monitors Extension version" where 0xF
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means an IMPLEMENTATION DEFINED PMU is implemented, and values 0x0-0xE
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are treated as with an unsigned field (with 0x0 meaning no PMU is
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present). As we don't expect to expose an IMPLEMENTATION DEFINED PMU,
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and our cap is below 0xF, we can treat these fields as unsigned when
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applying the cap.
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Signed-off-by: Andrew Murray <andrew.murray@arm.com>
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Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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[Mark: make field names consistent, use perfmon cap]
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Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Signed-off-by: Will Deacon <will@kernel.org>
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Signed-off-by: zhangyuan <zhangyuan162@huawei.com>
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---
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arch/arm64/include/asm/sysreg.h | 6 ++++++
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arch/arm64/kvm/sys_regs.c | 10 ++++++++++
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2 files changed, 16 insertions(+)
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diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
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index de4c31f073bb..041100c28cab 100644
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--- a/arch/arm64/include/asm/sysreg.h
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+++ b/arch/arm64/include/asm/sysreg.h
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@@ -637,6 +637,12 @@
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#define ID_AA64DFR0_TRACEVER_SHIFT 4
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#define ID_AA64DFR0_DEBUGVER_SHIFT 0
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+#define ID_AA64DFR0_PMUVER_8_1 0x4
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+
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+#define ID_DFR0_PERFMON_SHIFT 24
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+
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+#define ID_DFR0_PERFMON_8_1 0x4
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+
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#define ID_AA64DFR0_PMSVER_8_2 0x1
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#define ID_AA64DFR0_PMSVER_8_3 0x2
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diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
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index 25caa9ec95e4..cc824a208684 100644
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--- a/arch/arm64/kvm/sys_regs.c
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+++ b/arch/arm64/kvm/sys_regs.c
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@@ -1082,6 +1082,16 @@ static u64 read_id_reg(struct kvm_vcpu *vcpu,
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kvm_debug("LORegions unsupported for guests, suppressing\n");
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val &= ~(0xfUL << ID_AA64MMFR1_LOR_SHIFT);
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+ } else if (id == SYS_ID_AA64DFR0_EL1) {
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+ /* Limit guests to PMUv3 for ARMv8.1 */
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+ val = cpuid_feature_cap_perfmon_field(val,
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+ ID_AA64DFR0_PMUVER_SHIFT,
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+ ID_AA64DFR0_PMUVER_8_1);
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+ } else if (id == SYS_ID_DFR0_EL1) {
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+ /* Limit guests to PMUv3 for ARMv8.1 */
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+ val = cpuid_feature_cap_perfmon_field(val,
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+ ID_DFR0_PERFMON_SHIFT,
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+ ID_DFR0_PERFMON_8_1);
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}
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return val;
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--
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2.33.0
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