470 lines
14 KiB
Diff
470 lines
14 KiB
Diff
From a42c8f603e8d0aa7d67023014604d919227581dd Mon Sep 17 00:00:00 2001
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From: hongrongxuan <hongrongxuan@huawei.com>
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Date: Wed, 25 Oct 2023 15:04:16 +0800
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Subject: [PATCH 03/55] Revert "perf: hisi: Add support for HiSilicon SoC
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LPDDRC PMU driver"
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driver inclusion
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I8AU2M
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-------------------------------------------------------------
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This reverts commit be4e2dae37269ece33d54f906323b00208a569b0.
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Now, revert it, then we will inclusion the newer version of LPDRRC PMU
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driver.
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Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
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---
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drivers/perf/hisilicon/Makefile | 2 +-
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.../perf/hisilicon/hisi_uncore_lpddrc_pmu.c | 429 ------------------
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2 files changed, 1 insertion(+), 430 deletions(-)
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delete mode 100644 drivers/perf/hisilicon/hisi_uncore_lpddrc_pmu.c
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diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
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index 3651f18260e5..2621d51ae87a 100644
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--- a/drivers/perf/hisilicon/Makefile
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+++ b/drivers/perf/hisilicon/Makefile
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@@ -1 +1 @@
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-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o hisi_uncore_hha_pmu.o hisi_uncore_ddrc_pmu.o hisi_uncore_lpddrc_pmu.o
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+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o hisi_uncore_hha_pmu.o hisi_uncore_ddrc_pmu.o
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diff --git a/drivers/perf/hisilicon/hisi_uncore_lpddrc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_lpddrc_pmu.c
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deleted file mode 100644
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index 8f8b211788e0..000000000000
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--- a/drivers/perf/hisilicon/hisi_uncore_lpddrc_pmu.c
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+++ /dev/null
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@@ -1,429 +0,0 @@
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-// SPDX-License-Identifier: GPL-2.0
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-/*
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- * HiSilicon SoC LPDDRC uncore Hardware event counters support
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- *
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- * Copyright (C) 2021 Hisilicon Limited
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- * Author: Fang Lijun <fanglijun3@huawei.com>
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- * Shaokun Zhang <zhangshaokun@hisilicon.com>
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- * Anurup M <anurup.m@huawei.com>
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- *
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- * This code is based on the uncore PMUs like arm-cci and arm-ccn.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- */
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-#include <linux/acpi.h>
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-#include <linux/bug.h>
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-#include <linux/cpuhotplug.h>
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-#include <linux/interrupt.h>
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-#include <linux/irq.h>
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-#include <linux/list.h>
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-#include <linux/of.h>
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-#include <linux/platform_device.h>
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-#include <linux/smp.h>
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-
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-#include "hisi_uncore_pmu.h"
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-
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-/* LPDDRC register definition */
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-#define LPDDRC_PERF_CTRL 0x4930
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-#define LPDDRC_FLUX_WR 0x4948
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-#define LPDDRC_FLUX_RD 0x494c
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-#define LPDDRC_FLUX_WCMD 0x4950
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-#define LPDDRC_FLUX_RCMD 0x4954
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-#define LPDDRC_PRE_CMD 0x4984
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-#define LPDDRC_ACT_CMD 0x4988
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-#define LPDDRC_RNK_CHG 0x4990
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-#define LPDDRC_RW_CHG 0x4994
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-#define LPDDRC_EVENT_CTRL 0x4d60
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-#define LPDDRC_INT_MASK 0x6c8
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-#define LPDDRC_INT_STATUS 0x6cc
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-#define LPDDRC_INT_CLEAR 0x6d0
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-
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-/* LPDDRC has 8-counters */
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-#define LPDDRC_NR_COUNTERS 0x8
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-#define LPDDRC_PERF_CTRL_EN 0x1
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-
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-/*
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- * For LPDDRC PMU, there are eight-events and every event has been mapped
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- * to fixed-purpose counters which register offset is not consistent.
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- * Therefore there is no write event type and we assume that event
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- * code (0 to 7) is equal to counter index in PMU driver.
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- */
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-#define GET_LPDDRC_EVENTID(hwc) (hwc->config_base & 0x7)
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-
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-static const u32 lpddrc_reg_off[] = {
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- LPDDRC_FLUX_WR, LPDDRC_FLUX_RD, LPDDRC_FLUX_WCMD, LPDDRC_FLUX_RCMD,
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- LPDDRC_PRE_CMD, LPDDRC_ACT_CMD, LPDDRC_RNK_CHG, LPDDRC_RW_CHG
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-};
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-
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-/*
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- * Select the counter register offset using the counter index.
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- * In LPDDRC there are no programmable counter, the count
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- * is readed form the statistics counter register itself.
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- */
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-static u32 hisi_lpddrc_pmu_get_counter_offset(int cntr_idx)
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-{
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- return lpddrc_reg_off[cntr_idx];
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-}
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-
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-static u64 hisi_lpddrc_pmu_read_counter(struct hisi_pmu *lpddrc_pmu,
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- struct hw_perf_event *hwc)
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-{
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- /* Use event code as counter index */
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- u32 idx = GET_LPDDRC_EVENTID(hwc);
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-
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- if (!hisi_uncore_pmu_counter_valid(lpddrc_pmu, idx)) {
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- dev_err(lpddrc_pmu->dev, "Unsupported event index:%d!\n", idx);
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- return 0;
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- }
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-
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- return readl(lpddrc_pmu->base + hisi_lpddrc_pmu_get_counter_offset(idx));
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-}
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-
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-/*
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- * For LPDDRC PMU, event counter should be reset when start counters,
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- * reset the prev_count by software, because the counter register was RO.
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- */
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-static void hisi_lpddrc_pmu_write_counter(struct hisi_pmu *lpddrc_pmu,
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- struct hw_perf_event *hwc, u64 val)
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-{
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- local64_set(&hwc->prev_count, 0);
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-}
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-
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-/*
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- * For LPDDRC PMU, event has been mapped to fixed-purpose counter by hardware,
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- * so there is no need to write event type.
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- */
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-static void hisi_lpddrc_pmu_write_evtype(struct hisi_pmu *hha_pmu, int idx,
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- u32 type)
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-{
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-}
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-
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-static void hisi_lpddrc_pmu_start_counters(struct hisi_pmu *lpddrc_pmu)
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-{
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- u32 val;
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-
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- /* Set perf_enable in LPDDRC_PERF_CTRL to start event counting */
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- val = readl(lpddrc_pmu->base + LPDDRC_PERF_CTRL);
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- val |= LPDDRC_PERF_CTRL_EN;
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- writel(val, lpddrc_pmu->base + LPDDRC_PERF_CTRL);
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-}
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-
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-static void hisi_lpddrc_pmu_stop_counters(struct hisi_pmu *lpddrc_pmu)
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-{
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- u32 val;
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-
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- /* Clear perf_enable in LPDDRC_PERF_CTRL to stop event counting */
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- val = readl(lpddrc_pmu->base + LPDDRC_PERF_CTRL);
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- val &= ~LPDDRC_PERF_CTRL_EN;
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- writel(val, lpddrc_pmu->base + LPDDRC_PERF_CTRL);
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-}
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-
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-static void hisi_lpddrc_pmu_enable_counter(struct hisi_pmu *lpddrc_pmu,
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- struct hw_perf_event *hwc)
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-{
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- u32 val;
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-
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- /* Set counter index(event code) in LPDDRC_EVENT_CTRL register */
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- val = readl(lpddrc_pmu->base + LPDDRC_EVENT_CTRL);
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- val |= (1 << GET_LPDDRC_EVENTID(hwc));
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- writel(val, lpddrc_pmu->base + LPDDRC_EVENT_CTRL);
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-}
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-
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-static void hisi_lpddrc_pmu_disable_counter(struct hisi_pmu *lpddrc_pmu,
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- struct hw_perf_event *hwc)
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-{
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- u32 val;
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-
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- /* Clear counter index(event code) in LPDDRC_EVENT_CTRL register */
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- val = readl(lpddrc_pmu->base + LPDDRC_EVENT_CTRL);
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- val &= ~(1 << GET_LPDDRC_EVENTID(hwc));
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- writel(val, lpddrc_pmu->base + LPDDRC_EVENT_CTRL);
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-}
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-
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-static int hisi_lpddrc_pmu_get_event_idx(struct perf_event *event)
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-{
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- struct hisi_pmu *lpddrc_pmu = to_hisi_pmu(event->pmu);
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- unsigned long *used_mask = lpddrc_pmu->pmu_events.used_mask;
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- struct hw_perf_event *hwc = &event->hw;
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- /* For LPDDRC PMU, we use event code as counter index */
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- int idx = GET_LPDDRC_EVENTID(hwc);
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-
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- if (test_bit(idx, used_mask))
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- return -EAGAIN;
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-
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- set_bit(idx, used_mask);
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-
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- return idx;
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-}
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-
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-static void hisi_lpddrc_pmu_enable_counter_int(struct hisi_pmu *lpddrc_pmu,
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- struct hw_perf_event *hwc)
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-{
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- u32 val;
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-
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- /* Write 0 to enable interrupt */
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- val = readl(lpddrc_pmu->base + LPDDRC_INT_MASK);
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- val &= ~(1 << GET_LPDDRC_EVENTID(hwc));
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- writel(val, lpddrc_pmu->base + LPDDRC_INT_MASK);
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-}
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-
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-static void hisi_lpddrc_pmu_disable_counter_int(struct hisi_pmu *lpddrc_pmu,
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- struct hw_perf_event *hwc)
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-{
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- u32 val;
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-
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- /* Write 1 to mask interrupt */
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- val = readl(lpddrc_pmu->base + LPDDRC_INT_MASK);
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- val |= (1 << GET_LPDDRC_EVENTID(hwc));
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- writel(val, lpddrc_pmu->base + LPDDRC_INT_MASK);
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-}
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-
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-static irqreturn_t hisi_lpddrc_pmu_isr(int irq, void *dev_id)
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-{
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- struct hisi_pmu *lpddrc_pmu = dev_id;
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- struct perf_event *event;
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- unsigned long overflown;
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- int idx;
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-
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- /* Read the LPDDRC_INT_STATUS register */
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- overflown = readl(lpddrc_pmu->base + LPDDRC_INT_STATUS);
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- if (!overflown)
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- return IRQ_NONE;
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-
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- /*
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- * Find the counter index which overflowed if the bit was set
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- * and handle it
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- */
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- for_each_set_bit(idx, &overflown, LPDDRC_NR_COUNTERS) {
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- /* Write 1 to clear the IRQ status flag */
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- writel((1 << idx), lpddrc_pmu->base + LPDDRC_INT_CLEAR);
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-
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- /* Get the corresponding event struct */
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- event = lpddrc_pmu->pmu_events.hw_events[idx];
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- if (!event)
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- continue;
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-
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- hisi_uncore_pmu_event_update(event);
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- hisi_uncore_pmu_set_event_period(event);
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- }
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-
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- return IRQ_HANDLED;
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-}
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-
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-static int hisi_lpddrc_pmu_init_irq(struct hisi_pmu *lpddrc_pmu,
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- struct platform_device *pdev)
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-{
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- int irq, ret;
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-
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- /* Read and init IRQ */
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- irq = platform_get_irq(pdev, 0);
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- if (irq < 0) {
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- dev_err(&pdev->dev, "LPDDRC PMU get irq fail; irq:%d\n", irq);
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- return irq;
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- }
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-
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- ret = devm_request_irq(&pdev->dev, irq, hisi_lpddrc_pmu_isr,
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- IRQF_NOBALANCING | IRQF_NO_THREAD | IRQF_SHARED,
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- dev_name(&pdev->dev), lpddrc_pmu);
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- if (ret < 0) {
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- dev_err(&pdev->dev,
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- "Fail to request IRQ:%d ret:%d\n", irq, ret);
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- return ret;
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- }
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-
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- lpddrc_pmu->irq = irq;
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-
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- return 0;
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-}
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-
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-static const struct of_device_id lpddrc_of_match[] = {
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- { .compatible = "hisilicon,lpddrc-pmu", },
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- {},
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-}
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-MODULE_DEVICE_TABLE(of, lpddrc_of_match);
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-
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-static int hisi_lpddrc_pmu_init_data(struct platform_device *pdev,
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- struct hisi_pmu *lpddrc_pmu)
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-{
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- struct resource *res;
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-
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- /*
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- * Use the SCCL_ID and LPDDRC channel ID to identify the
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- * LPDDRC PMU, while SCCL_ID is in MPIDR[aff2].
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- */
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- if (device_property_read_u32(&pdev->dev, "hisilicon,ch-id",
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- &lpddrc_pmu->index_id)) {
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- dev_err(&pdev->dev, "Can not read lpddrc channel-id!\n");
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- return -EINVAL;
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- }
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-
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- if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
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- &lpddrc_pmu->sccl_id)) {
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- dev_err(&pdev->dev, "Can not read lpddrc sccl-id!\n");
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- return -EINVAL;
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- }
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- /* LPDDRC PMUs only share the same SCCL */
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- lpddrc_pmu->ccl_id = -1;
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-
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- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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- lpddrc_pmu->base = devm_ioremap_resource(&pdev->dev, res);
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- if (IS_ERR(lpddrc_pmu->base)) {
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- dev_err(&pdev->dev, "ioremap failed for lpddrc_pmu resource\n");
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- return PTR_ERR(lpddrc_pmu->base);
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- }
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-
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- return 0;
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-}
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-
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-static struct attribute *hisi_lpddrc_pmu_format_attr[] = {
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- HISI_PMU_FORMAT_ATTR(event, "config:0-4"),
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- NULL,
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-};
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-
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-static const struct attribute_group hisi_lpddrc_pmu_format_group = {
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- .name = "format",
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- .attrs = hisi_lpddrc_pmu_format_attr,
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-};
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-
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-static struct attribute *hisi_lpddrc_pmu_events_attr[] = {
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- HISI_PMU_EVENT_ATTR(flux_wr, 0x00),
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- HISI_PMU_EVENT_ATTR(flux_rd, 0x01),
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- HISI_PMU_EVENT_ATTR(flux_wcmd, 0x02),
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- HISI_PMU_EVENT_ATTR(flux_rcmd, 0x03),
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- HISI_PMU_EVENT_ATTR(pre_cmd, 0x04),
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- HISI_PMU_EVENT_ATTR(act_cmd, 0x05),
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- HISI_PMU_EVENT_ATTR(rnk_chg, 0x06),
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- HISI_PMU_EVENT_ATTR(rw_chg, 0x07),
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- NULL,
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-};
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-
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-static const struct attribute_group hisi_lpddrc_pmu_events_group = {
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- .name = "events",
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- .attrs = hisi_lpddrc_pmu_events_attr,
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-};
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-
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-static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
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-
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-static struct attribute *hisi_lpddrc_pmu_cpumask_attrs[] = {
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- &dev_attr_cpumask.attr,
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- NULL,
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-};
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-
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-static const struct attribute_group hisi_lpddrc_pmu_cpumask_attr_group = {
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- .attrs = hisi_lpddrc_pmu_cpumask_attrs,
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-};
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-
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-static const struct attribute_group *hisi_lpddrc_pmu_attr_groups[] = {
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- &hisi_lpddrc_pmu_format_group,
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- &hisi_lpddrc_pmu_events_group,
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- &hisi_lpddrc_pmu_cpumask_attr_group,
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- NULL,
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-};
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-
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-static const struct hisi_uncore_ops hisi_uncore_lpddrc_ops = {
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- .write_evtype = hisi_lpddrc_pmu_write_evtype,
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- .get_event_idx = hisi_lpddrc_pmu_get_event_idx,
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- .start_counters = hisi_lpddrc_pmu_start_counters,
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- .stop_counters = hisi_lpddrc_pmu_stop_counters,
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- .enable_counter = hisi_lpddrc_pmu_enable_counter,
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- .disable_counter = hisi_lpddrc_pmu_disable_counter,
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- .enable_counter_int = hisi_lpddrc_pmu_enable_counter_int,
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- .disable_counter_int = hisi_lpddrc_pmu_disable_counter_int,
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- .write_counter = hisi_lpddrc_pmu_write_counter,
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- .read_counter = hisi_lpddrc_pmu_read_counter,
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-};
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-
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-static int hisi_lpddrc_pmu_dev_probe(struct platform_device *pdev,
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- struct hisi_pmu *lpddrc_pmu)
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-{
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- int ret;
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-
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- ret = hisi_lpddrc_pmu_init_data(pdev, lpddrc_pmu);
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- if (ret)
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- return ret;
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-
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- ret = hisi_lpddrc_pmu_init_irq(lpddrc_pmu, pdev);
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- if (ret)
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- return ret;
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-
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- lpddrc_pmu->num_counters = LPDDRC_NR_COUNTERS;
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- lpddrc_pmu->counter_bits = 32;
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- lpddrc_pmu->ops = &hisi_uncore_lpddrc_ops;
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- lpddrc_pmu->dev = &pdev->dev;
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- lpddrc_pmu->on_cpu = -1;
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- lpddrc_pmu->check_event = 7;
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-
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- return 0;
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-}
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-
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-static int hisi_lpddrc_pmu_probe(struct platform_device *pdev)
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-{
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- struct hisi_pmu *lpddrc_pmu;
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- char *name;
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- int ret;
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-
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- lpddrc_pmu = devm_kzalloc(&pdev->dev, sizeof(*lpddrc_pmu), GFP_KERNEL);
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- if (!lpddrc_pmu)
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- return -ENOMEM;
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-
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- platform_set_drvdata(pdev, lpddrc_pmu);
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-
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- ret = hisi_lpddrc_pmu_dev_probe(pdev, lpddrc_pmu);
|
|
- if (ret)
|
|
- return ret;
|
|
-
|
|
- name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_lpddrc%u",
|
|
- lpddrc_pmu->sccl_id, lpddrc_pmu->index_id);
|
|
- HISI_INIT_PMU(&lpddrc_pmu->pmu, name, hisi_lpddrc_pmu_attr_groups);
|
|
- ret = perf_pmu_register(&lpddrc_pmu->pmu, name, -1);
|
|
- if (ret) {
|
|
- dev_err(lpddrc_pmu->dev, "LPDDRC PMU register failed!\n");
|
|
- return ret;
|
|
- }
|
|
-
|
|
- /* Pick one core to use for cpumask attributes */
|
|
- cpumask_set_cpu(smp_processor_id(), &lpddrc_pmu->associated_cpus);
|
|
-
|
|
- lpddrc_pmu->on_cpu = cpumask_first(&lpddrc_pmu->associated_cpus);
|
|
- if (lpddrc_pmu->on_cpu >= nr_cpu_ids)
|
|
- return -EINVAL;
|
|
-
|
|
- return 0;
|
|
-}
|
|
-
|
|
-static int hisi_lpddrc_pmu_remove(struct platform_device *pdev)
|
|
-{
|
|
- struct hisi_pmu *lpddrc_pmu = platform_get_drvdata(pdev);
|
|
-
|
|
- perf_pmu_unregister(&lpddrc_pmu->pmu);
|
|
-
|
|
- return 0;
|
|
-}
|
|
-
|
|
-static struct platform_driver hisi_lpddrc_pmu_driver = {
|
|
- .driver = {
|
|
- .name = "hisi_lpddrc_pmu",
|
|
- .of_match_table = lpddrc_of_match,
|
|
- },
|
|
- .probe = hisi_lpddrc_pmu_probe,
|
|
- .remove = hisi_lpddrc_pmu_remove,
|
|
-};
|
|
-
|
|
-static int __init hisi_lpddrc_pmu_module_init(void)
|
|
-{
|
|
- return platform_driver_register(&hisi_lpddrc_pmu_driver);
|
|
-}
|
|
-module_init(hisi_lpddrc_pmu_module_init);
|
|
-
|
|
-static void __exit hisi_lpddrc_pmu_module_exit(void)
|
|
-{
|
|
- platform_driver_unregister(&hisi_lpddrc_pmu_driver);
|
|
-}
|
|
-module_exit(hisi_lpddrc_pmu_module_exit);
|
|
-
|
|
-MODULE_DESCRIPTION("HiSilicon SoC LPDDRC uncore PMU driver");
|
|
-MODULE_LICENSE("GPL v2");
|
|
-MODULE_AUTHOR("Fang Lijun <fanglijun3@huawei.com>");
|
|
-MODULE_AUTHOR("HUAWEI TECHNOLOGIES CO., LTD.");
|
|
--
|
|
2.27.0
|
|
|