97 lines
3.7 KiB
Diff
97 lines
3.7 KiB
Diff
From 4eb7b05822b08060912123ccd681845c9fae435d Mon Sep 17 00:00:00 2001
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From: Luo Jiaxing <luojiaxing@huawei.com>
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Date: Tue, 1 Sep 2020 19:13:05 +0800
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Subject: [PATCH 053/108] scsi: hisi_sas: Do not modify upper fields of
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PROG_PHY_LINK_RATE reg
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mainline inclusion
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from mainline-v5.10-rc1
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commit caeddc0453b9215669a39ea335f1af1f3f91cc99
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category: feature
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bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8F81L
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=caeddc0453b9215669a39ea335f1af1f3f91cc99
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----------------------------------------------------------------------
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When updating PROG_PHY_LINK_RATE to set linkrate for a phy we used a
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hard-coded initial value instead of getting the current value from the
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register. The assumption was that this register would not be modified, but
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in fact it was partially modified in a new version of hardware. The
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hard-coded value we used changed the default value of the register to a an
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incorrect setting and as a result the SAS controller could not change
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linkrate for the phy.
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Delete hard-coded value and always read the latest value of register before
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updating it.
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Link: https://lore.kernel.org/r/1598958790-232272-4-git-send-email-john.garry@huawei.com
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Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com>
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Signed-off-by: John Garry <john.garry@huawei.com>
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Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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Signed-off-by: YunYi Yang <yangyunyi2@huawei.com>
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Conflicts:
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drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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---
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drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 21 ++++++++++++---------
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1 file changed, 12 insertions(+), 9 deletions(-)
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diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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index 343160b1f6a3..e278d5d8c0d9 100644
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--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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@@ -199,6 +199,8 @@
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#define PHY_CFG_PHY_RST_OFF 3
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#define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF)
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#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
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+#define CFG_PROG_PHY_LINK_RATE_OFF 0
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+#define CFG_PROG_PHY_LINK_RATE_MSK (0xff << CFG_PROG_PHY_LINK_RATE_OFF)
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#define CFG_PROG_OOB_PHY_LINK_RATE_OFF 8
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#define CFG_PROG_OOB_PHY_LINK_RATE_MSK (0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
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#define PHY_CTRL (PORT_BASE + 0x14)
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@@ -659,20 +661,20 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
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}
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for (i = 0; i < hisi_hba->n_phy; i++) {
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+ enum sas_linkrate max;
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struct hisi_sas_phy *phy = &hisi_hba->phy[i];
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struct asd_sas_phy *sas_phy = &phy->sas_phy;
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- u32 prog_phy_link_rate = 0x800;
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+ u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
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+ PROG_PHY_LINK_RATE);
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+ prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
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if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
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SAS_LINK_RATE_1_5_GBPS)) {
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- prog_phy_link_rate = 0x855;
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+ max = SAS_LINK_RATE_12_0_GBPS;
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} else {
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- enum sas_linkrate max = sas_phy->phy->maximum_linkrate;
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-
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- prog_phy_link_rate =
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- hisi_sas_get_prog_phy_linkrate_mask(max) |
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- 0x800;
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+ max = sas_phy->phy->maximum_linkrate;
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}
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+ prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
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if (skip_bus_flag) {
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hisi_sas_phy_write32(hisi_hba, i,
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@@ -2836,9 +2838,10 @@ static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
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struct sas_phy_linkrates *r)
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{
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enum sas_linkrate max = r->maximum_linkrate;
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- /* init OOB link rate as 1.5 Gbits */
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- u32 prog_phy_link_rate = 0x800;
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+ u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
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+ PROG_PHY_LINK_RATE);
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+ prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
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prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
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hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
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prog_phy_link_rate);
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--
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2.27.0
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