82 lines
2.7 KiB
Diff
82 lines
2.7 KiB
Diff
From 44fcad1ae412d4d1743c3242302c05f1f3400a4a Mon Sep 17 00:00:00 2001
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From: Luo Jiaxing <luojiaxing@huawei.com>
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Date: Mon, 20 Jan 2020 20:22:33 +0800
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Subject: [PATCH 041/108] scsi: hisi_sas: Replace magic number when handle
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channel interrupt
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mainline inclusion
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from mainline-v5.6-rc1
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commit d2815fdf9a0e6c629d062f9a7e24cb7cdbef3dee
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category: feature
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bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EKNE
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d2815fdf9a0e6c629d062f9a7e24cb7cdbef3dee
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----------------------------------------------------------------------
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We use magic number as offset and mask when handle channel interrupt, so
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use macro to replace it.
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Link: https://lore.kernel.org/r/1579522957-4393-4-git-send-email-john.garry@huawei.com
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Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com>
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Signed-off-by: John Garry <john.garry@huawei.com>
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Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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Signed-off-by: YunYi Yang <yangyunyi2@huawei.com>
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Conflicts:
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drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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---
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drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 18 +++++++++++++-----
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1 file changed, 13 insertions(+), 5 deletions(-)
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diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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index 500fd6e54f38..c8328e1ef166 100644
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--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
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@@ -540,6 +540,13 @@ struct hisi_sas_err_record_v3 {
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(op == READ_16) || (op == WRITE_16) || \
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(op == READ_32) || (op == WRITE_32))
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+#define CHNL_INT_STS_MSK 0xeeeeeeee
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+#define CHNL_INT_STS_PHY_MSK 0xe
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+#define CHNL_INT_STS_INT0_MSK BIT(1)
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+#define CHNL_INT_STS_INT1_MSK BIT(2)
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+#define CHNL_INT_STS_INT2_MSK BIT(3)
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+#define CHNL_WIDTH 4
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+
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enum {
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DSM_FUNC_ERR_HANDLE_MSI = 0,
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};
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@@ -1945,22 +1952,23 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
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int phy_no = 0;
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irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
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- & 0xeeeeeeee;
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+ & CHNL_INT_STS_MSK;
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+
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/*
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* These three irqs mask save at high 3 bit, the last bit
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* is reserved. So we use 0xe to clear those after handle.
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*/
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while (irq_msk) {
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- if (irq_msk & (2 << (phy_no * 4)))
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+ if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
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handle_chl_int0_v3_hw(hisi_hba, phy_no);
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- if (irq_msk & (4 << (phy_no * 4)))
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+ if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
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handle_chl_int1_v3_hw(hisi_hba, phy_no);
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- if (irq_msk & (8 << (phy_no * 4)))
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+ if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
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handle_chl_int2_v3_hw(hisi_hba, phy_no);
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- irq_msk &= ~(0xe << (phy_no * 4));
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+ irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
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phy_no++;
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}
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--
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2.27.0
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