77 lines
3.0 KiB
Diff
77 lines
3.0 KiB
Diff
From a391ba966923aedcf9caec80df612cacafa5202a Mon Sep 17 00:00:00 2001
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From: Guangbin Huang <huangguangbin2@huawei.com>
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Date: Thu, 18 Nov 2021 20:45:02 +0800
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Subject: [PATCH 157/283] net: hns3: allow configure ETS bandwidth of all TCs
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mainline inclusion
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from mainline-v5.16-rc1
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commit 688db0c7a4a69ddc8b8143a1cac01eb20082a3aa
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category: bugfix
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bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=688db0c7a4a69ddc8b8143a1cac01eb20082a3aa
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----------------------------------------------------------------------
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Currently, driver only allow configuring ETS bandwidth of TCs according
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to the max TC number queried from firmware. However, the hardware actually
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supports 8 TCs and users may need to configure ETS bandwidth of all TCs,
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so remove the restriction.
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Fixes: 330baff5423b ("net: hns3: add ETS TC weight setting in SSU module")
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Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
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Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
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Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
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---
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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c | 2 +-
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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 9 +--------
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2 files changed, 2 insertions(+), 9 deletions(-)
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
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index d748c6404436..428bb7d6ab94 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
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@@ -129,7 +129,7 @@ static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev,
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u32 total_ets_bw = 0;
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u8 i;
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- for (i = 0; i < hdev->tc_max; i++) {
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+ for (i = 0; i < HNAE3_MAX_TC; i++) {
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switch (ets->tc_tsa[i]) {
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case IEEE_8021QAZ_TSA_STRICT:
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if (hdev->tm_info.tc_info[i].tc_sch_mode !=
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
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index 434e6dfca032..48382bfc84f6 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
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@@ -1057,7 +1057,6 @@ static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
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static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
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{
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-#define DEFAULT_TC_WEIGHT 1
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#define DEFAULT_TC_OFFSET 14
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struct hclge_ets_tc_weight_cmd *ets_weight;
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@@ -1070,13 +1069,7 @@ static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
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for (i = 0; i < HNAE3_MAX_TC; i++) {
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struct hclge_pg_info *pg_info;
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- ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
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-
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- if (!(hdev->hw_tc_map & BIT(i)))
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- continue;
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-
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- pg_info =
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- &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
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+ pg_info = &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
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ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
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}
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--
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2.34.1
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