61 lines
2.3 KiB
Diff
61 lines
2.3 KiB
Diff
From 37eebb9dc894682b3f816a2d4905646b29a8fc90 Mon Sep 17 00:00:00 2001
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From: Guangbin Huang <huangguangbin2@huawei.com>
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Date: Mon, 15 Nov 2021 19:47:18 +0800
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Subject: [PATCH 133/283] net: hns3: add limit ets dwrr bandwidth cannot be 0
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mainline inclusion
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from mainline-v5.15-rc7
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commit 731797fdffa3d083db536e2fdd07ceb050bb40b1
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category: bugfix
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bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=731797fdffa3d083db536e2fdd07ceb050bb40b1
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--------------------------------
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[ Upstream commit 731797fdffa3d083db536e2fdd07ceb050bb40b1 ]
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If ets dwrr bandwidth of tc is set to 0, the hardware will switch to SP
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mode. In this case, this tc may occupy all the tx bandwidth if it has
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huge traffic, so it violates the purpose of the user setting.
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To fix this problem, limit the ets dwrr bandwidth must greater than 0.
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Fixes: cacde272dd00 ("net: hns3: Add hclge_dcb module for the support of DCB feature")
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Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Sasha Levin <sashal@kernel.org>
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Signed-off-by: Chen Jun <chenjun102@huawei.com>
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Acked-by: Weilong Chen <chenweilong@huawei.com>
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Signed-off-by: Chen Jun <chenjun102@huawei.com>
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Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
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---
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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c | 9 +++++++++
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1 file changed, 9 insertions(+)
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
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index 65c38d972a4d..188daf75be32 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
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@@ -137,6 +137,15 @@ static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev,
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*changed = true;
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break;
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case IEEE_8021QAZ_TSA_ETS:
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+ /* The hardware will switch to sp mode if bandwidth is
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+ * 0, so limit ets bandwidth must be greater than 0.
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+ */
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+ if (!ets->tc_tx_bw[i]) {
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+ dev_err(&hdev->pdev->dev,
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+ "tc%u ets bw cannot be 0\n", i);
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+ return -EINVAL;
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+ }
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+
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if (hdev->tm_info.tc_info[i].tc_sch_mode !=
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HCLGE_SCH_MODE_DWRR)
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*changed = true;
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--
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2.34.1
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