116 lines
4.8 KiB
Diff
116 lines
4.8 KiB
Diff
From 2c1767861d169a2f9099a9bc1e1b5f22e09fbcbd Mon Sep 17 00:00:00 2001
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From: Guangbin Huang <huangguangbin2@huawei.com>
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Date: Tue, 28 Sep 2021 11:52:03 +0800
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Subject: [PATCH 111/283] net: hns3: refactor function hclge_parse_capability()
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mainline inclusion
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from mainline-v5.15-rc1
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commit e1d93bc6ef3bf497675f9ac2b35b79c48577b970
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category: feature
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bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e1d93bc6ef3bf497675f9ac2b35b79c48577b970
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----------------------------------------------------------------------
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The function hclge_parse_capability() uses too many if statement, and
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it may add more in the future. To improve code readability, maintainability
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and simplicity, refactor this function by using a bit mapping array of IMP
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capabilities and driver capabilities.
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Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
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Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
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Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
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Conflicts:
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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
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---
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.../hisilicon/hns3/hns3pf/hclge_cmd.c | 43 ++++++++++---------
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.../hisilicon/hns3/hns3pf/hclge_cmd.h | 6 +++
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2 files changed, 28 insertions(+), 21 deletions(-)
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
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index 26e9d03da720..1471330ee5d9 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
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@@ -373,33 +373,34 @@ static void hclge_set_default_capability(struct hclge_dev *hdev)
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set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
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}
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+const struct hclge_caps_bit_map hclge_cmd_caps_bit_map0[] = {
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+ {HCLGE_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
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+ {HCLGE_CAP_PTP_B, HNAE3_DEV_SUPPORT_PTP_B},
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+ {HCLGE_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
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+ {HCLGE_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
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+ {HCLGE_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
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+ {HCLGE_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
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+ {HCLGE_CAP_FD_FORWARD_TC_B, HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B},
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+ {HCLGE_CAP_FEC_B, HNAE3_DEV_SUPPORT_FEC_B},
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+ {HCLGE_CAP_PAUSE_B, HNAE3_DEV_SUPPORT_PAUSE_B},
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+ {HCLGE_CAP_PHY_IMP_B, HNAE3_DEV_SUPPORT_PHY_IMP_B},
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+ {HCLGE_CAP_RAS_IMP_B, HNAE3_DEV_SUPPORT_RAS_IMP_B},
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+ {HCLGE_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
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+ {HCLGE_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B},
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+ {HCLGE_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B},
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+};
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+
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static void hclge_parse_capability(struct hclge_dev *hdev,
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struct hclge_query_version_cmd *cmd)
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{
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struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
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- u32 caps;
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+ u32 caps, i;
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caps = __le32_to_cpu(cmd->caps[0]);
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- if (hnae3_get_bit(caps, HCLGE_CAP_UDP_GSO_B))
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- set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
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- if (hnae3_get_bit(caps, HCLGE_CAP_PTP_B))
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- set_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps);
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- if (hnae3_get_bit(caps, HCLGE_CAP_INT_QL_B))
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- set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
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- if (hnae3_get_bit(caps, HCLGE_CAP_TQP_TXRX_INDEP_B))
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- set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
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- if (hnae3_get_bit(caps, HCLGE_CAP_HW_TX_CSUM_B))
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- set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
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- if (hnae3_get_bit(caps, HCLGE_CAP_PHY_IMP_B))
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- set_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, ae_dev->caps);
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- if (hnae3_get_bit(caps, HCLGE_CAP_RAS_IMP_B))
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- set_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, ae_dev->caps);
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- if (hnae3_get_bit(caps, HCLGE_CAP_RXD_ADV_LAYOUT_B))
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- set_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, ae_dev->caps);
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- if (hnae3_get_bit(caps, HCLGE_CAP_PORT_VLAN_BYPASS_B)) {
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- set_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps);
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- set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
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- }
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+ for (i = 0; i < ARRAY_SIZE(hclge_cmd_caps_bit_map0); i++)
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+ if (hnae3_get_bit(caps, hclge_cmd_caps_bit_map0[i].imp_bit))
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+ set_bit(hclge_cmd_caps_bit_map0[i].local_bit,
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+ ae_dev->caps);
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}
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static enum hclge_cmd_status
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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index 71aaca36e5ea..578217ff9706 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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@@ -1229,6 +1229,12 @@ struct hclge_phy_reg_cmd {
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u8 rsv1[18];
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};
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+/* capabilities bits map between imp firmware and local driver */
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+struct hclge_caps_bit_map {
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+ u16 imp_bit;
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+ u16 local_bit;
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+};
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+
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int hclge_cmd_init(struct hclge_dev *hdev);
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static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
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{
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--
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2.34.1
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