173 lines
6.8 KiB
Diff
173 lines
6.8 KiB
Diff
From 246537a68b01bb2e12a9251437731d92eaa32905 Mon Sep 17 00:00:00 2001
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From: Huazhong Tan <tanhuazhong@huawei.com>
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Date: Sat, 24 Jul 2021 15:45:24 +0800
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Subject: [PATCH 089/283] net: hns3: add support to query tx spare buffer size
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for pf
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mainline inclusion
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from mainline-v5.14-rc1
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commit 1a00197b7d2fe57f0be93037d5090e19a9b178c8
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category: feature
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bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1a00197b7d2fe57f0be93037d5090e19a9b178c8
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----------------------------------------------------------------------
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Add support to query tx spare buffer size from configuration
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file, and use this info to do spare buffer initialization when
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the module parameter 'tx_spare_buf_size' is not specified.
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Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
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Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
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Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
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Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
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Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
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Conflicts:
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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
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---
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drivers/net/ethernet/hisilicon/hns3/hnae3.h | 3 +++
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drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 7 +++++--
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.../ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 4 ++++
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.../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 15 +++++++++++++++
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.../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 4 ++++
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5 files changed, 31 insertions(+), 2 deletions(-)
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
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index 738baccf5a8a..58022716456d 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
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+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
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@@ -801,6 +801,9 @@ struct hnae3_knic_private_info {
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u16 rx_buf_len;
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u16 num_tx_desc;
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u16 num_rx_desc;
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+#ifndef __GENKSYMS__
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+ u32 tx_spare_buf_size;
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+#endif
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struct hnae3_tc_info tc_info;
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
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index fd800aa35f3e..6fbc211facbb 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
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@@ -709,13 +709,16 @@ static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
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{
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struct hns3_tx_spare *tx_spare;
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struct page *page;
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+ u32 alloc_size;
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dma_addr_t dma;
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int order;
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- if (!tx_spare_buf_size)
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+ alloc_size = tx_spare_buf_size ? tx_spare_buf_size :
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+ ring->tqp->handle->kinfo.tx_spare_buf_size;
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+ if (!alloc_size)
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return;
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- order = get_order(tx_spare_buf_size);
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+ order = get_order(alloc_size);
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tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
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GFP_KERNEL);
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if (!tx_spare) {
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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index ba10e18ddb7e..08e02c1c6eb2 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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@@ -534,6 +534,10 @@ struct hclge_pf_res_cmd {
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#define HCLGE_CFG_VLAN_FLTR_CAP_M GENMASK(9, 8)
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#define HCLGE_CFG_UMV_TBL_SPACE_S 16
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#define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
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+#define HCLGE_CFG_PF_RSS_SIZE_S 0
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+#define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0)
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+#define HCLGE_CFG_TX_SPARE_BUF_SIZE_S 4
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+#define HCLGE_CFG_TX_SPARE_BUF_SIZE_M GENMASK(15, 4)
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#define HCLGE_CFG_CMD_CNT 4
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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index d46a1d31c701..047423fd4084 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
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@@ -1256,6 +1256,8 @@ static u32 hclge_get_max_speed(u8 speed_ability)
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static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
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{
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+#define HCLGE_TX_SPARE_SIZE_UNIT 4096
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+
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struct hclge_cfg_param_cmd *req;
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u64 mac_addr_tmp_high;
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u64 mac_addr_tmp;
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@@ -1313,6 +1315,15 @@ static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
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HCLGE_CFG_UMV_TBL_SPACE_S);
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if (!cfg->umv_space)
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cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
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+
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+ /* The unit of the tx spare buffer size queried from configuration
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+ * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is
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+ * needed here.
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+ */
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+ cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]),
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+ HCLGE_CFG_TX_SPARE_BUF_SIZE_M,
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+ HCLGE_CFG_TX_SPARE_BUF_SIZE_S);
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+ cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT;
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}
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/* hclge_get_cfg: query the static parameter from flash
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@@ -1471,6 +1482,7 @@ static int hclge_configure(struct hclge_dev *hdev)
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hdev->tc_max = cfg.tc_num;
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hdev->tm_info.hw_pfc_map = 0;
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hdev->wanted_umv_size = cfg.umv_space;
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+ hdev->tx_spare_buf_size = cfg.tx_spare_buf_size;
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if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF)
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hnae3_set_bit(ae_dev->flag,
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HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 1);
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@@ -1658,6 +1670,7 @@ static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps,
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kinfo->num_rx_desc = num_rx_desc;
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kinfo->rx_buf_len = hdev->rx_buf_len;
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+ kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size;
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kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps,
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sizeof(struct hnae3_queue *), GFP_KERNEL);
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@@ -10274,6 +10287,8 @@ static void hclge_info_show(struct hclge_dev *hdev)
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hdev->flag & HCLGE_FLAG_DCB_ENABLE ? "enable" : "disable");
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dev_info(dev, "MQPRIO %s\n",
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hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE ? "enable" : "disable");
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+ dev_info(dev, "Default tx spare buffer size: %u\n",
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+ hdev->tx_spare_buf_size);
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dev_info(dev, "PF info end.\n");
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}
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diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
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index 660201b8bd11..07a1e7ed734b 100644
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--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
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+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
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@@ -382,6 +382,7 @@ struct hclge_cfg {
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u8 mac_addr[ETH_ALEN];
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u8 default_speed;
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u32 numa_node_map;
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+ u32 tx_spare_buf_size;
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u8 speed_ability;
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u16 umv_space;
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};
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@@ -788,6 +789,9 @@ struct hclge_dev {
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u16 base_tqp_pid; /* Base task tqp physical id of this PF */
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u16 alloc_rss_size; /* Allocated RSS task queue */
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u16 rss_size_max; /* HW defined max RSS task queue */
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+ u16 vf_rss_size_max; /* HW defined VF max RSS task queue */
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+ u16 pf_rss_size_max; /* HW defined PF max RSS task queue */
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+ u32 tx_spare_buf_size; /* HW defined TX spare buffer size */
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u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
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u16 num_alloc_vport; /* Num vports this driver supports */
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--
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2.34.1
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