137 lines
4.1 KiB
Diff
137 lines
4.1 KiB
Diff
From 09f73e2e9bba97398fa7a66affaa0e820ac16b5c Mon Sep 17 00:00:00 2001
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From: Tudor Ambarus <tudor.ambarus@microchip.com>
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Date: Thu, 24 Oct 2019 16:59:55 +0300
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Subject: [PATCH 10/39] mtd: spi-nor: Pointer parameter for CR in
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spi_nor_read_cr()
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mainline inclusion
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from mainline-v5.5-rc1
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commit b662d398ccf114a80c92140287a6507efb3e2dfc
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I8CSBP
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b662d398ccf114a80c92140287a6507efb3e2dfc
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----------------------------------------------------------------------------
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Let the callers pass the pointer to the DMA-able buffer where
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the value of the Configuration Register will be written. This way we
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avoid the casts between int and u8, which can be confusing.
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Callers stop compare the return value of spi_nor_read_cr() with negative,
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spi_nor_read_cr() returns 0 on success and -errno otherwise.
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Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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Signed-off-by: YunYi Yang <yangyunyi2@huawei.com>
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Conflicts:
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drivers/mtd/spi-nor/spi-nor.c
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---
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drivers/mtd/spi-nor/spi-nor.c | 46 ++++++++++++++++++++---------------
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1 file changed, 27 insertions(+), 19 deletions(-)
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diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
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index 766ad458197e..f1e92f63cab6 100644
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -306,12 +306,16 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
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return ret;
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}
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-/*
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- * Read configuration register, returning its value in the
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- * location. Return the configuration register value.
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- * Returns negative if error occurred.
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+/**
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+ * spi_nor_read_cr() - Read the Configuration Register using the
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+ * SPINOR_OP_RDCR (35h) command.
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+ * @nor: pointer to 'struct spi_nor'
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+ * @cr: pointer to a DMA-able buffer where the value of the
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+ * Configuration Register will be written.
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+ *
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+ * Return: 0 on success, -errno otherwise.
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*/
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-static int spi_nor_read_cr(struct spi_nor *nor)
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+static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
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{
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int ret;
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@@ -320,19 +324,17 @@ static int spi_nor_read_cr(struct spi_nor *nor)
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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- SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
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+ SPI_MEM_OP_DATA_IN(1, cr, 1));
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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- ret = nor->read_reg(nor, SPINOR_OP_RDCR, nor->bouncebuf, 1);
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+ ret = nor->read_reg(nor, SPINOR_OP_RDCR, cr, 1);
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}
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- if (ret) {
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+ if (ret)
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dev_err(nor->dev, "error %d reading CR\n", ret);
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- return ret;
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- }
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- return nor->bouncebuf[0];
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+ return ret;
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}
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/*
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@@ -1971,8 +1973,11 @@ static int spansion_quad_enable(struct spi_nor *nor)
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return ret;
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/* read back and check it */
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- ret = spi_nor_read_cr(nor);
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- if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
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+ ret = spi_nor_read_cr(nor, nor->bouncebuf);
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+ if (ret)
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+ return ret;
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+
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+ if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) {
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dev_err(nor->dev, "Spansion Quad bit not set\n");
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return -EINVAL;
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}
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@@ -2029,16 +2034,16 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
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int ret;
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/* Check current Quad Enable bit value. */
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- ret = spi_nor_read_cr(nor);
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- if (ret < 0) {
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+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
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+ if (ret) {
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dev_err(dev, "error while reading configuration register\n");
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return -EINVAL;
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}
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- if (ret & CR_QUAD_EN_SPAN)
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+ if (sr_cr[1] & CR_QUAD_EN_SPAN)
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return 0;
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- sr_cr[1] = ret | CR_QUAD_EN_SPAN;
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+ sr_cr[1] |= CR_QUAD_EN_SPAN;
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/* Keep the current value of the Status Register. */
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ret = spi_nor_read_sr(nor, sr_cr);
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@@ -2052,8 +2057,11 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
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return ret;
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/* Read back and check it. */
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- ret = spi_nor_read_cr(nor);
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- if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
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+ ret = spi_nor_read_cr(nor, &sr_cr[1]);
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+ if (ret)
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+ return ret;
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+
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+ if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
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dev_err(nor->dev, "Spansion Quad bit not set\n");
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return -EINVAL;
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}
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--
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2.27.0
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