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kernel/patches/0328-mtd-spi-nor-Prepend-spi_nor_-to-all-Reg-Ops-methods.patch

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From 2a3bbff9e6e53d35b55a9439b14ba3a81662bb11 Mon Sep 17 00:00:00 2001
From: Tudor Ambarus <tudor.ambarus@microchip.com>
Date: Tue, 29 Oct 2019 11:16:49 +0000
Subject: [PATCH 06/39] mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methods
mainline inclusion
from mainline-v5.5-rc1
commit 567c2983efb9a4b3d26a221b477346d927092b8a
category: cleanup
bugzilla: https://gitee.com/openeuler/kernel/issues/I8CSBP
CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=567c2983efb9a4b3d26a221b477346d927092b8a
----------------------------------------------------------------------------
All the core functions should begin with "spi_nor_".
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: YunYi Yang <yangyunyi2@huawei.com>
Conflicts:
drivers/mtd/spi-nor/spi-nor.c
---
drivers/mtd/spi-nor/spi-nor.c | 97 ++++++++++++++++++-----------------
1 file changed, 49 insertions(+), 48 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 33dace0b4c8b..0809018daf4c 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -251,7 +251,7 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,
* Return the status register value.
* Returns negative if error occurred.
*/
-static int read_sr(struct spi_nor *nor)
+static int spi_nor_read_sr(struct spi_nor *nor)
{
int ret;
@@ -280,7 +280,7 @@ static int read_sr(struct spi_nor *nor)
* Return the status register value.
* Returns negative if error occurred.
*/
-static int read_fsr(struct spi_nor *nor)
+static int spi_nor_read_fsr(struct spi_nor *nor)
{
int ret;
@@ -309,7 +309,7 @@ static int read_fsr(struct spi_nor *nor)
* location. Return the configuration register value.
* Returns negative if error occurred.
*/
-static int read_cr(struct spi_nor *nor)
+static int spi_nor_read_cr(struct spi_nor *nor)
{
int ret;
@@ -337,7 +337,7 @@ static int read_cr(struct spi_nor *nor)
* Write status register 1 byte
* Returns negative if error occurred.
*/
-static inline int write_sr(struct spi_nor *nor, u8 val)
+static int spi_nor_write_sr(struct spi_nor *nor, u8 val)
{
nor->bouncebuf[0] = val;
if (nor->spimem) {
@@ -357,7 +357,7 @@ static inline int write_sr(struct spi_nor *nor, u8 val)
* Set write enable latch with Write Enable command.
* Returns negative if error occurred.
*/
-static inline int write_enable(struct spi_nor *nor)
+static int spi_nor_write_enable(struct spi_nor *nor)
{
if (nor->spimem) {
struct spi_mem_op op =
@@ -375,7 +375,7 @@ static inline int write_enable(struct spi_nor *nor)
/*
* Send write disable instruction to the chip.
*/
-static inline int write_disable(struct spi_nor *nor)
+static int spi_nor_write_disable(struct spi_nor *nor)
{
if (nor->spimem) {
struct spi_mem_op op =
@@ -538,11 +538,11 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
case SNOR_MFR_MACRONIX:
case SNOR_MFR_WINBOND:
if (need_wren)
- write_enable(nor);
+ spi_nor_write_enable(nor);
status = macronix_set_4byte(nor, enable);
if (need_wren)
- write_disable(nor);
+ spi_nor_write_disable(nor);
if (!status && !enable &&
JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
@@ -552,9 +552,9 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
* 3-byte-address reads come from the second 16M.
* We must clear the register to enable normal behavior.
*/
- write_enable(nor);
+ spi_nor_write_enable(nor);
spi_nor_write_ear(nor, 0);
- write_disable(nor);
+ spi_nor_write_disable(nor);
}
return status;
@@ -609,7 +609,7 @@ static int spi_nor_clear_sr(struct spi_nor *nor)
static inline int spi_nor_sr_ready(struct spi_nor *nor)
{
- int sr = read_sr(nor);
+ int sr = spi_nor_read_sr(nor);
if (sr < 0)
return sr;
@@ -643,7 +643,7 @@ static int spi_nor_clear_fsr(struct spi_nor *nor)
static inline int spi_nor_fsr_ready(struct spi_nor *nor)
{
- int fsr = read_fsr(nor);
+ int fsr = spi_nor_read_fsr(nor);
if (fsr < 0)
return fsr;
@@ -721,7 +721,7 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
*
* Returns 0 if successful, non-zero otherwise.
*/
-static int erase_chip(struct spi_nor *nor)
+static int spi_nor_erase_chip(struct spi_nor *nor)
{
dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
@@ -848,9 +848,9 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
unsigned long timeout;
- write_enable(nor);
+ spi_nor_write_enable(nor);
- if (erase_chip(nor)) {
+ if (spi_nor_erase_chip(nor)) {
ret = -EIO;
goto erase_err;
}
@@ -876,7 +876,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
/* "sector"-at-a-time erase */
} else {
while (len) {
- write_enable(nor);
+ spi_nor_write_enable(nor);
ret = spi_nor_erase_sector(nor, addr);
if (ret)
@@ -891,7 +891,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
}
}
- write_disable(nor);
+ spi_nor_write_disable(nor);
erase_err:
spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
@@ -900,12 +900,13 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
}
/* Write status register and ensure bits in mask match written values */
-static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
+static int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 status_new,
+ u8 mask)
{
int ret;
- write_enable(nor);
- ret = write_sr(nor, status_new);
+ spi_nor_write_enable(nor);
+ ret = spi_nor_write_sr(nor, status_new);
if (ret)
return ret;
@@ -913,7 +914,7 @@ static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
if (ret)
return ret;
- ret = read_sr(nor);
+ ret = spi_nor_read_sr(nor);
if (ret < 0)
return ret;
@@ -1019,7 +1020,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
- status_old = read_sr(nor);
+ status_old = spi_nor_read_sr(nor);
if (status_old < 0)
return status_old;
@@ -1081,7 +1082,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
if ((status_new & mask) < (status_old & mask))
return -EINVAL;
- return write_sr_and_check(nor, status_new, mask);
+ return spi_nor_write_sr_and_check(nor, status_new, mask);
}
/*
@@ -1099,7 +1100,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
- status_old = read_sr(nor);
+ status_old = spi_nor_read_sr(nor);
if (status_old < 0)
return status_old;
@@ -1164,7 +1165,7 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
if ((status_new & mask) > (status_old & mask))
return -EINVAL;
- return write_sr_and_check(nor, status_new, mask);
+ return spi_nor_write_sr_and_check(nor, status_new, mask);
}
/*
@@ -1178,7 +1179,7 @@ static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
int status;
- status = read_sr(nor);
+ status = spi_nor_read_sr(nor);
if (status < 0)
return status;
@@ -1709,7 +1710,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
if (ret)
return ret;
- write_enable(nor);
+ spi_nor_write_enable(nor);
nor->sst_write_second = false;
@@ -1748,14 +1749,14 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
}
nor->sst_write_second = false;
- write_disable(nor);
+ spi_nor_write_disable(nor);
ret = spi_nor_wait_till_ready(nor);
if (ret)
goto sst_write_err;
/* Write out trailing byte if it exists. */
if (actual != len) {
- write_enable(nor);
+ spi_nor_write_enable(nor);
nor->program_opcode = SPINOR_OP_BP;
ret = spi_nor_write_data(nor, to, 1, buf + actual);
@@ -1766,7 +1767,7 @@ static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
ret = spi_nor_wait_till_ready(nor);
if (ret)
goto sst_write_err;
- write_disable(nor);
+ spi_nor_write_disable(nor);
actual += 1;
}
sst_write_err:
@@ -1819,7 +1820,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
if (nor->flags & SNOR_F_S3AN_ADDR_DEFAULT)
addr = spi_nor_s3an_addr_convert(nor, addr);
- write_enable(nor);
+ spi_nor_write_enable(nor);
ret = spi_nor_write_data(nor, addr, page_remain, buf + i);
if (ret < 0)
goto write_err;
@@ -1858,21 +1859,21 @@ static int macronix_quad_enable(struct spi_nor *nor)
{
int ret, val;
- val = read_sr(nor);
+ val = spi_nor_read_sr(nor);
if (val < 0)
return val;
if (val & SR_QUAD_EN_MX)
return 0;
- write_enable(nor);
+ spi_nor_write_enable(nor);
- write_sr(nor, val | SR_QUAD_EN_MX);
+ spi_nor_write_sr(nor, val | SR_QUAD_EN_MX);
ret = spi_nor_wait_till_ready(nor);
if (ret)
return ret;
- ret = read_sr(nor);
+ ret = spi_nor_read_sr(nor);
if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
dev_err(nor->dev, "Macronix Quad bit not set\n");
return -EINVAL;
@@ -1887,11 +1888,11 @@ static int macronix_quad_enable(struct spi_nor *nor)
* second byte will be written to the configuration register.
* Return negative if error occurred.
*/
-static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
+static int spi_nor_write_sr_cr(struct spi_nor *nor, u8 *sr_cr)
{
int ret;
- write_enable(nor);
+ spi_nor_write_enable(nor);
if (nor->spimem) {
struct spi_mem_op op =
@@ -1952,12 +1953,12 @@ static int spansion_quad_enable(struct spi_nor *nor)
sr_cr[0] = 0;
sr_cr[1] = CR_QUAD_EN_SPAN;
- ret = write_sr_cr(nor, sr_cr);
+ ret = spi_nor_write_sr_cr(nor, sr_cr);
if (ret)
return ret;
/* read back and check it */
- ret = read_cr(nor);
+ ret = spi_nor_read_cr(nor);
if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
dev_err(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
@@ -1985,7 +1986,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
int ret;
/* Keep the current value of the Status Register. */
- ret = read_sr(nor);
+ ret = spi_nor_read_sr(nor);
if (ret < 0) {
dev_err(nor->dev, "error while reading status register\n");
return -EINVAL;
@@ -1993,7 +1994,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
sr_cr[0] = ret;
sr_cr[1] = CR_QUAD_EN_SPAN;
- return write_sr_cr(nor, sr_cr);
+ return spi_nor_write_sr_cr(nor, sr_cr);
}
/**
@@ -2016,7 +2017,7 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
int ret;
/* Check current Quad Enable bit value. */
- ret = read_cr(nor);
+ ret = spi_nor_read_cr(nor);
if (ret < 0) {
dev_err(dev, "error while reading configuration register\n");
return -EINVAL;
@@ -2028,19 +2029,19 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
sr_cr[1] = ret | CR_QUAD_EN_SPAN;
/* Keep the current value of the Status Register. */
- ret = read_sr(nor);
+ ret = spi_nor_read_sr(nor);
if (ret < 0) {
dev_err(dev, "error while reading status register\n");
return -EINVAL;
}
sr_cr[0] = ret;
- ret = write_sr_cr(nor, sr_cr);
+ ret = spi_nor_write_sr_cr(nor, sr_cr);
if (ret)
return ret;
/* Read back and check it. */
- ret = read_cr(nor);
+ ret = spi_nor_read_cr(nor);
if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
dev_err(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
@@ -2076,7 +2077,7 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor)
/* Update the Quad Enable bit. */
*sr2 |= SR2_QUAD_EN_BIT7;
- write_enable(nor);
+ spi_nor_write_enable(nor);
ret = spi_nor_write_sr2(nor, sr2);
if (ret < 0) {
@@ -3123,8 +3124,8 @@ static int spi_nor_init(struct spi_nor *nor)
JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
nor->info->flags & SPI_NOR_HAS_LOCK) {
- write_enable(nor);
- write_sr(nor, 0);
+ spi_nor_write_enable(nor);
+ spi_nor_write_sr(nor, 0);
spi_nor_wait_till_ready(nor);
}
--
2.27.0
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