123 lines
4.3 KiB
Diff
123 lines
4.3 KiB
Diff
From f4a40e041840155d7afdda97249fdcf394814905 Mon Sep 17 00:00:00 2001
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From: John Garry <john.garry@huawei.com>
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Date: Tue, 17 Mar 2020 19:02:13 +0800
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Subject: [PATCH 064/201] perf jevents: Add some test events
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mainline inclusion
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from mainline-v5.7-rc1
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commit c52db67a74b3a9b834af4588489cfea22ec280a3
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I8C0CX
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c52db67a74b3a9b834af4588489cfea22ec280a3
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----------------------------------------------------------------------
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Add some test PMU events. The events are randomly chosen from x86 and
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arm64 JSONs. The events include CPU and uncore events.
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Signed-off-by: John Garry <john.garry@huawei.com>
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Acked-by: Jiri Olsa <jolsa@redhat.com>
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Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Cc: Andi Kleen <ak@linux.intel.com>
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Cc: James Clark <james.clark@arm.com>
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Cc: Joakim Zhang <qiangqing.zhang@nxp.com>
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Cc: Mark Rutland <mark.rutland@arm.com>
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Cc: Namhyung Kim <namhyung@kernel.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will@kernel.org>
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Cc: linuxarm@huawei.com
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Link: http://lore.kernel.org/lkml/1584442939-8911-2-git-send-email-john.garry@huawei.com
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Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
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---
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.../pmu-events/arch/test/test_cpu/branch.json | 12 +++++++++
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.../pmu-events/arch/test/test_cpu/other.json | 26 +++++++++++++++++++
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.../pmu-events/arch/test/test_cpu/uncore.json | 21 +++++++++++++++
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3 files changed, 59 insertions(+)
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create mode 100644 tools/perf/pmu-events/arch/test/test_cpu/branch.json
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create mode 100644 tools/perf/pmu-events/arch/test/test_cpu/other.json
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create mode 100644 tools/perf/pmu-events/arch/test/test_cpu/uncore.json
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diff --git a/tools/perf/pmu-events/arch/test/test_cpu/branch.json b/tools/perf/pmu-events/arch/test/test_cpu/branch.json
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new file mode 100644
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index 000000000000..93ddfd8053ca
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--- /dev/null
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+++ b/tools/perf/pmu-events/arch/test/test_cpu/branch.json
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@@ -0,0 +1,12 @@
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+[
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+ {
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+ "EventName": "bp_l1_btb_correct",
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+ "EventCode": "0x8a",
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+ "BriefDescription": "L1 BTB Correction."
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+ },
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+ {
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+ "EventName": "bp_l2_btb_correct",
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+ "EventCode": "0x8b",
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+ "BriefDescription": "L2 BTB Correction."
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+ }
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+]
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diff --git a/tools/perf/pmu-events/arch/test/test_cpu/other.json b/tools/perf/pmu-events/arch/test/test_cpu/other.json
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new file mode 100644
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index 000000000000..7d53d7ecd723
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--- /dev/null
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+++ b/tools/perf/pmu-events/arch/test/test_cpu/other.json
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@@ -0,0 +1,26 @@
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+[
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+ {
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+ "EventCode": "0x6",
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+ "Counter": "0,1",
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+ "UMask": "0x80",
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+ "EventName": "SEGMENT_REG_LOADS.ANY",
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+ "SampleAfterValue": "200000",
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+ "BriefDescription": "Number of segment register loads."
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+ },
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+ {
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+ "EventCode": "0x9",
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+ "Counter": "0,1",
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+ "UMask": "0x20",
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+ "EventName": "DISPATCH_BLOCKED.ANY",
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+ "SampleAfterValue": "200000",
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+ "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason"
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+ },
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+ {
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+ "EventCode": "0x3A",
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+ "Counter": "0,1",
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+ "UMask": "0x0",
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+ "EventName": "EIST_TRANS",
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+ "SampleAfterValue": "200000",
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+ "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions"
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+ }
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+]
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\ No newline at end of file
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diff --git a/tools/perf/pmu-events/arch/test/test_cpu/uncore.json b/tools/perf/pmu-events/arch/test/test_cpu/uncore.json
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new file mode 100644
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index 000000000000..d0a890cc814d
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--- /dev/null
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+++ b/tools/perf/pmu-events/arch/test/test_cpu/uncore.json
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@@ -0,0 +1,21 @@
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+[
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+ {
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+ "EventCode": "0x02",
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+ "EventName": "uncore_hisi_ddrc.flux_wcmd",
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+ "BriefDescription": "DDRC write commands",
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+ "PublicDescription": "DDRC write commands",
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+ "Unit": "hisi_sccl,ddrc"
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+ },
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+ {
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+ "Unit": "CBO",
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+ "EventCode": "0x22",
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+ "UMask": "0x81",
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+ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
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+ "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
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+ "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
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+ "Counter": "0,1",
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+ "CounterMask": "0",
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+ "Invert": "0",
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+ "EdgeDetect": "0"
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+ }
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+]
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--
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2.27.0
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