68 lines
3.0 KiB
Diff
68 lines
3.0 KiB
Diff
From 515c2917ae3bc768e8793dac6b27ea4dff36b40c Mon Sep 17 00:00:00 2001
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From: Julien Grall <julien.grall@arm.com>
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Date: Mon, 14 Oct 2019 11:21:13 +0100
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Subject: [PATCH openEuler-20.03-LTS-SP4 4/4] arm64: cpufeature: Treat
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ID_AA64ZFR0_EL1 as RAZ when SVE is not enabled
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mainline inclusion
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from mainline-v5.4-rc4
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commit ec52c7134b1fcef0edfc56d55072fd4f261ef198
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I8B82O
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CVE: NA
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ec52c7134b1fcef0edfc56d55072fd4f261ef198
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--------------------------------
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If CONFIG_ARM64_SVE=n then we fail to report ID_AA64ZFR0_EL1 as 0 when
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read by userspace, despite being required by the architecture. Although
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this is theoretically a change in ABI, userspace will first check for
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the presence of SVE via the HWCAP or the ID_AA64PFR0_EL1.SVE field
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before probing the ID_AA64ZFR0_EL1 register. Given that these are
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reported correctly for this configuration, we can safely tighten up the
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current behaviour.
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Ensure ID_AA64ZFR0_EL1 is treated as RAZ when CONFIG_ARM64_SVE=n.
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Signed-off-by: Julien Grall <julien.grall@arm.com>
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Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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Reviewed-by: Mark Rutland <mark.rutland@arm.com>
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Reviewed-by: Dave Martin <dave.martin@arm.com>
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Fixes: 06a916feca2b ("arm64: Expose SVE2 features for userspace")
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Signed-off-by: Will Deacon <will@kernel.org>
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Signed-off-by: Yu Liao <liaoyu15@huawei.com>
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---
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arch/arm64/kernel/cpufeature.c | 15 ++++++++++-----
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1 file changed, 10 insertions(+), 5 deletions(-)
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diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
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index 8e7473df2660..98a8b2703f84 100644
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--- a/arch/arm64/kernel/cpufeature.c
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+++ b/arch/arm64/kernel/cpufeature.c
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@@ -184,11 +184,16 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
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};
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static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
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- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
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- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
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- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
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- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
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- ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
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+ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
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+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
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+ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
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+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
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+ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
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+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
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+ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
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+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
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+ ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
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+ FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
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ARM64_FTR_END,
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};
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--
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2.25.1
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