198 lines
6.8 KiB
Diff
198 lines
6.8 KiB
Diff
From b917df0a2ab2eba9cc49d2019f5222e70f42dc60 Mon Sep 17 00:00:00 2001
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From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
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Date: Tue, 26 Mar 2019 15:17:53 +0000
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Subject: [PATCH 53/55] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk
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mainline inclusion
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from mainline-v5.2-rc1
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commit 24062fe85860debfdae0eeaa495f27c9971ec163
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I8AU2M
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Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=24062fe85860debfdae0eeaa495f27c9971ec163
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----------------------------------------------------------
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HiSilicon erratum 162001800 describes the limitation of
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SMMUv3 PMCG implementation on HiSilicon Hip08 platforms.
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On these platforms, the PMCG event counter registers
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(SMMU_PMCG_EVCNTRn) are read only and as a result it
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is not possible to set the initial counter period value
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on event monitor start.
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To work around this, the current value of the counter
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is read and used for delta calculations. OEM information
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from ACPI header is used to identify the affected hardware
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platforms.
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Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
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Reviewed-by: Hanjun Guo <hanjun.guo@linaro.org>
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Reviewed-by: Robin Murphy <robin.murphy@arm.com>
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Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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[will: update silicon-errata.txt and add reason string to acpi match]
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Signed-off-by: Will Deacon <will.deacon@arm.com>
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Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
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Conflicts:
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Documentation/arm64/silicon-errata.txt
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---
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Documentation/arm64/silicon-errata.txt | 1 +
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drivers/acpi/arm64/iort.c | 16 ++++++++-
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drivers/perf/arm_smmuv3_pmu.c | 48 ++++++++++++++++++++++----
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include/linux/acpi_iort.h | 1 +
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4 files changed, 58 insertions(+), 8 deletions(-)
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diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
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index 5016158f5e67..e733d13d7b98 100644
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--- a/Documentation/arm64/silicon-errata.txt
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+++ b/Documentation/arm64/silicon-errata.txt
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@@ -79,6 +79,7 @@ stable kernels.
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| Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 |
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| Hisilicon | TSV{110,200} | #1980005 | HISILICON_ERRATUM_1980005 |
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| Hisilicon | Hip09 | #162100801 | HISILICON_ERRATUM_161600801 |
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+| Hisilicon | Hip08 SMMU PMCG | #162001800 | N/A |
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| | | | |
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| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
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| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
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diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
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index d507556d508f..abc62558e818 100644
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--- a/drivers/acpi/arm64/iort.c
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+++ b/drivers/acpi/arm64/iort.c
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@@ -1476,9 +1476,23 @@ static void __init arm_smmu_v3_pmcg_init_resources(struct resource *res,
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ACPI_EDGE_SENSITIVE, &res[2]);
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}
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+static struct acpi_platform_list pmcg_plat_info[] __initdata = {
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+ /* HiSilicon Hip08 Platform */
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+ {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal,
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+ "Erratum #162001800", IORT_SMMU_V3_PMCG_HISI_HIP08},
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+ { }
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+};
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+
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static int __init arm_smmu_v3_pmcg_add_platdata(struct platform_device *pdev)
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{
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- u32 model = IORT_SMMU_V3_PMCG_GENERIC;
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+ u32 model;
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+ int idx;
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+
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+ idx = acpi_match_platform_list(pmcg_plat_info);
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+ if (idx >= 0)
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+ model = pmcg_plat_info[idx].data;
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+ else
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+ model = IORT_SMMU_V3_PMCG_GENERIC;
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return platform_device_add_data(pdev, &model, sizeof(model));
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}
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diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
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index e9cd120f4268..3df836fd2f70 100644
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--- a/drivers/perf/arm_smmuv3_pmu.c
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+++ b/drivers/perf/arm_smmuv3_pmu.c
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@@ -35,6 +35,7 @@
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*/
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#include <linux/acpi.h>
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+#include <linux/acpi_iort.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/cpuhotplug.h>
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@@ -93,6 +94,8 @@
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#define SMMU_PMCG_PA_SHIFT 12
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+#define SMMU_PMCG_EVCNTR_RDONLY BIT(0)
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+
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static int cpuhp_state_num;
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struct smmu_pmu {
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@@ -108,6 +111,7 @@ struct smmu_pmu {
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void __iomem *reg_base;
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void __iomem *reloc_base;
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u64 counter_mask;
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+ u32 options;
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bool global_filter;
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};
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@@ -220,15 +224,27 @@ static void smmu_pmu_set_period(struct smmu_pmu *smmu_pmu,
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u32 idx = hwc->idx;
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u64 new;
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- /*
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- * We limit the max period to half the max counter value of the counter
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- * size, so that even in the case of extreme interrupt latency the
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- * counter will (hopefully) not wrap past its initial value.
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- */
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- new = smmu_pmu->counter_mask >> 1;
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+ if (smmu_pmu->options & SMMU_PMCG_EVCNTR_RDONLY) {
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+ /*
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+ * On platforms that require this quirk, if the counter starts
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+ * at < half_counter value and wraps, the current logic of
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+ * handling the overflow may not work. It is expected that,
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+ * those platforms will have full 64 counter bits implemented
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+ * so that such a possibility is remote(eg: HiSilicon HIP08).
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+ */
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+ new = smmu_pmu_counter_get_value(smmu_pmu, idx);
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+ } else {
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+ /*
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+ * We limit the max period to half the max counter value
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+ * of the counter size, so that even in the case of extreme
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+ * interrupt latency the counter will (hopefully) not wrap
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+ * past its initial value.
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+ */
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+ new = smmu_pmu->counter_mask >> 1;
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+ smmu_pmu_counter_set_value(smmu_pmu, idx, new);
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+ }
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local64_set(&hwc->prev_count, new);
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- smmu_pmu_counter_set_value(smmu_pmu, idx, new);
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}
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static void smmu_pmu_set_event_filter(struct perf_event *event,
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@@ -702,6 +718,22 @@ static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu)
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smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
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}
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+static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
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+{
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+ u32 model;
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+
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+ model = *(u32 *)dev_get_platdata(smmu_pmu->dev);
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+
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+ switch (model) {
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+ case IORT_SMMU_V3_PMCG_HISI_HIP08:
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+ /* HiSilicon Erratum 162001800 */
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+ smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
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+ break;
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+ }
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+
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+ dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
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+}
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+
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static int smmu_pmu_probe(struct platform_device *pdev)
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{
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struct smmu_pmu *smmu_pmu;
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@@ -781,6 +813,8 @@ static int smmu_pmu_probe(struct platform_device *pdev)
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return -EINVAL;
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}
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+ smmu_pmu_get_acpi_options(smmu_pmu);
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+
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/* Pick one CPU to be the preferred one to use */
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smmu_pmu->on_cpu = raw_smp_processor_id();
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WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu)));
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diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h
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index 832bd6ae9ad4..bdb69125854e 100644
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--- a/include/linux/acpi_iort.h
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+++ b/include/linux/acpi_iort.h
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@@ -31,6 +31,7 @@
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* that, this is not part of the IORT specification.
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*/
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#define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */
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+#define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */
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int iort_register_domain_token(int trans_id, phys_addr_t base,
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struct fwnode_handle *fw_node);
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--
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2.27.0
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