163 lines
5.0 KiB
Diff
163 lines
5.0 KiB
Diff
From 418fb2ed339c7856662bb6244ac5477cba81f80f Mon Sep 17 00:00:00 2001
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From: hongrongxuan <hongrongxuan@huawei.com>
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Date: Fri, 27 Oct 2023 18:49:23 +0800
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Subject: [PATCH 52/55] Revert "perf/smmuv3_pmu: Enable HiSilicon Erratum
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162001800 quirk"
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driver inclusion
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category: feature
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bugzilla: https://gitee.com/openeuler/kernel/issues/I8AU2M
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-----------------------------------------------------------
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This reverts commit 68088650bec0647cef4d822b31f818a094f5eead.
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We inclusion it again from upstream later.
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Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
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---
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drivers/acpi/arm64/iort.c | 16 +-----------
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drivers/perf/arm_smmuv3_pmu.c | 48 +++++------------------------------
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include/linux/acpi_iort.h | 1 -
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3 files changed, 8 insertions(+), 57 deletions(-)
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diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
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index 9ad4ee8884de..d507556d508f 100644
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--- a/drivers/acpi/arm64/iort.c
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+++ b/drivers/acpi/arm64/iort.c
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@@ -1476,23 +1476,9 @@ static void __init arm_smmu_v3_pmcg_init_resources(struct resource *res,
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ACPI_EDGE_SENSITIVE, &res[2]);
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}
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-static struct acpi_platform_list pmcg_plat_info[] __initdata = {
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- /* HiSilicon Hip08 Platform */
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- {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, 0,
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- IORT_SMMU_V3_PMCG_HISI_HIP08},
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- { }
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-};
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-
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static int __init arm_smmu_v3_pmcg_add_platdata(struct platform_device *pdev)
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{
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- u32 model;
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- int idx;
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-
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- idx = acpi_match_platform_list(pmcg_plat_info);
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- if (idx >= 0)
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- model = pmcg_plat_info[idx].data;
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- else
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- model = IORT_SMMU_V3_PMCG_GENERIC;
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+ u32 model = IORT_SMMU_V3_PMCG_GENERIC;
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return platform_device_add_data(pdev, &model, sizeof(model));
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}
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diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c
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index bda901e2a5fc..e9cd120f4268 100644
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--- a/drivers/perf/arm_smmuv3_pmu.c
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+++ b/drivers/perf/arm_smmuv3_pmu.c
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@@ -35,7 +35,6 @@
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*/
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#include <linux/acpi.h>
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-#include <linux/acpi_iort.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/cpuhotplug.h>
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@@ -94,8 +93,6 @@
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#define SMMU_PMCG_PA_SHIFT 12
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-#define SMMU_PMCG_EVCNTR_RDONLY BIT(0)
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-
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static int cpuhp_state_num;
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struct smmu_pmu {
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@@ -110,7 +107,6 @@ struct smmu_pmu {
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struct device *dev;
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void __iomem *reg_base;
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void __iomem *reloc_base;
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- u32 options;
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u64 counter_mask;
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bool global_filter;
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};
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@@ -224,27 +220,15 @@ static void smmu_pmu_set_period(struct smmu_pmu *smmu_pmu,
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u32 idx = hwc->idx;
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u64 new;
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- if (smmu_pmu->options & SMMU_PMCG_EVCNTR_RDONLY) {
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- /*
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- * On platforms that require this quirk, if the counter starts
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- * at < half_counter value and wraps, the current logic of
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- * handling the overflow may not work. It is expected that,
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- * those platforms will have full 64 counter bits implemented
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- * so that such a possibility is remote(eg: HiSilicon HIP08).
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- */
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- new = smmu_pmu_counter_get_value(smmu_pmu, idx);
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- } else {
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- /*
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- * We limit the max period to half the max counter value
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- * of the counter size, so that even in the case of extreme
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- * interrupt latency the counter will (hopefully) not wrap
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- * past its initial value.
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- */
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- new = smmu_pmu->counter_mask >> 1;
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- smmu_pmu_counter_set_value(smmu_pmu, idx, new);
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- }
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+ /*
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+ * We limit the max period to half the max counter value of the counter
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+ * size, so that even in the case of extreme interrupt latency the
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+ * counter will (hopefully) not wrap past its initial value.
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+ */
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+ new = smmu_pmu->counter_mask >> 1;
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local64_set(&hwc->prev_count, new);
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+ smmu_pmu_counter_set_value(smmu_pmu, idx, new);
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}
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static void smmu_pmu_set_event_filter(struct perf_event *event,
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@@ -718,22 +702,6 @@ static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu)
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smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0);
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}
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-static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu)
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-{
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- u32 model;
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-
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- model = *(u32 *)dev_get_platdata(smmu_pmu->dev);
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-
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- switch (model) {
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- case IORT_SMMU_V3_PMCG_HISI_HIP08:
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- /* HiSilicon Erratum 162001800 */
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- smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY;
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- break;
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- }
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-
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- dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options);
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-}
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-
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static int smmu_pmu_probe(struct platform_device *pdev)
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{
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struct smmu_pmu *smmu_pmu;
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@@ -813,8 +781,6 @@ static int smmu_pmu_probe(struct platform_device *pdev)
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return -EINVAL;
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}
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- smmu_pmu_get_acpi_options(smmu_pmu);
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-
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/* Pick one CPU to be the preferred one to use */
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smmu_pmu->on_cpu = raw_smp_processor_id();
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WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu->on_cpu)));
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diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h
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index bdb69125854e..832bd6ae9ad4 100644
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--- a/include/linux/acpi_iort.h
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+++ b/include/linux/acpi_iort.h
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@@ -31,7 +31,6 @@
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* that, this is not part of the IORT specification.
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*/
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#define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */
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-#define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */
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int iort_register_domain_token(int trans_id, phys_addr_t base,
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struct fwnode_handle *fw_node);
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--
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2.27.0
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