From 3f570dd14632b40ebaf1606b57f04d2eb3c59385 Mon Sep 17 00:00:00 2001
From: Xiaodong Li <lixiaodong67@huawei.com>
Date: Fri, 17 Nov 2023 14:19:46 +0800
Subject: [PATCH] NIC feature enhancement

---
 kernel.spec                                   |  287 ++-
 ...for-loopback-selftest-failed-problem.patch |   54 +
 ...date-mac-configuation-when-necessary.patch |   48 +
 ...64-net-hns3-Add-default-irq-affinity.patch |   57 +
 ...-hns3-Add-unlikely-for-buf_num-check.patch |   73 +
 ...linkmode-helpers-to-somewhere-public.patch |  201 ++
 ...function-hclge_set_all_vf_rst-static.patch |   45 +
 ...0-and-print-warning-when-hit-duplica.patch |   84 +
 ...Use-LLDP-ethertype-define-ETH_P_LLDP.patch |   68 +
 ...pile-warning-without-CONFIG_RFS_ACCE.patch |   53 +
 ...hns3_uninit_phy-s-location-in-the-hn.patch |   81 +
 .../0372-net-hns3-remove-unused-macros.patch  |   42 +
 ...an-unsuitable-log-in-hclge_map_ring_.patch |   46 +
 ...reject-unsupported-coalescing-params.patch |  138 ++
 ...-clear-port-base-VLAN-when-unload-PF.patch |   72 +
 ...ustom-driver-version-in-favour-of-gl.patch |  128 ++
 ...a-redundant-register-macro-definitio.patch |   95 +
 ...ns3-modify-two-uncorrect-macro-names.patch |   70 +
 ...a-duplicated-printing-in-hclge_confi.patch |   46 +
 ...0-net-hns3-refactor-hclge_config_tso.patch |   65 +
 ...refactor-hclge_query_bd_num_cmd_send.patch |   61 +
 ...an-incorrect-type-in-struct-hclge_cf.patch |   59 +
 ...an-incorrect-type-in-struct-hclgevf_.patch |   59 +
 ...some-unused-fields-in-struct-hns3_ni.patch |   76 +
 ...unused-struct-hnae3_unic_private_inf.patch |   58 +
 ...two-duplicated-register-macros-in-hc.patch |   86 +
 ...some-unused-fields-in-struct-hclge_d.patch |   45 +
 ...rint-format-issue-in-hclge_mac_mdio_.patch |   41 +
 ...-remove-an-unused-macro-hclge_is_csq.patch |   41 +
 ...e-two-unused-macros-in-hclgevf_cmd.c.patch |   42 +
 ...-coding-style-issues-in-hclgevf_main.patch |   53 +
 ...some-unused-codes-in-hns3_nic_set_fe.patch |   53 +
 ...3-net-hns3-remove-some-unused-macros.patch |   57 +
 ...vice-version-to-replace-pci-revision.patch |  692 ++++++
 ...d-support-to-query-device-capability.patch |  185 ++
 ...e-capabilities-queried-from-firmware.patch |  324 +++
 ...add-UDP-segmentation-offload-support.patch |   73 +
 ...ize-the-message-content-in-hclge_get.patch |   51 +
 ...port-for-TX-hardware-checksum-offloa.patch |  343 +++
 ...tructure-for-IR-shaper-s-parameter-i.patch |  272 +++
 ...remove-the-shaper-param-magic-number.patch |   89 +
 ...p-unnecessary-parentheses-in-macro-d.patch |  196 ++
 ...-change-hclge_parse_speed-param-type.patch |   46 +
 ...change-hclge_query_bd_num-param-type.patch |   56 +
 ...-hns3-remove-unused-macro-definition.patch |   65 +
 ...actor-out-hclge_cmd_convert_err_code.patch |  102 +
 ...tor-out-hclgevf_cmd_convert_err_code.patch |  103 +
 ...08-net-hns3-use-ipv6_addr_any-helper.patch |   74 +
 ...efactor-out-hclge_set_vf_vlan_common.patch |  190 ++
 ...ns3-refactor-out-hclge_get_rss_tuple.patch |  129 ++
 ...3-refactor-out-hclgevf_get_rss_tuple.patch |  137 ++
 ...12-net-hns3-split-out-hclge_cmd_send.patch |  172 ++
 ...-net-hns3-split-out-hclgevf_cmd_send.patch |  242 +++
 ...I-for-ethtools-supported_coalesce_pa.patch |   37 +
 ...I-for-deletion-of-hnae3_unic_private.patch |   55 +
 ...I-for-The-dev_version-caps-element-i.patch |   38 +
 ...-add-support-for-imp-controlled-PHYs.patch |  413 ++++
 ...-set-pause-parameters-support-for-im.patch |   75 +
 ...octl-support-for-imp-controlled-PHYs.patch |  168 ++
 ...-loopback-support-for-imp-controlled.patch |  314 +++
 ...pport-to-query-device-specifications.patch |  286 +++
 ...-net-hns3-remove-unused-code-of-vmdq.patch |  497 +++++
 ...et-hns3-remove-redundant-blank-lines.patch |  206 ++
 ...redundant-query-in-hclge_config_tm_h.patch |   53 +
 ...3-split-function-hclge_reset_rebuild.patch |   91 +
 ...it-out-hclge_tm_vport_tc_info_update.patch |   67 +
 ...ns3-Trivial-spell-fix-in-hns3-driver.patch |   69 +
 ...-inappropriate-spaces-in-struct-hlcg.patch |   49 +
 ...nnecessary-reset-request-in-hclge_re.patch |   55 +
 ...port-for-configuring-interrupt-quant.patch |  297 +++
 ...r-s-coalesce-configuration-lost-issu.patch |  352 ++++
 ...GE_VPORT_STATE_PROMISC_CHANGE-to-rep.patch |  125 ++
 ...3-add-a-separate-error-handling-task.patch |  111 +
 ...eduling-logic-for-error-handling-tas.patch |   85 +
 ...add-log-for-workqueue-scheduled-late.patch |  143 ++
 ...now-redundant-logic-related-to-HNAE3.patch |   50 +
 ...port-for-handling-all-errors-through.patch |  187 ++
 ...-RAS-compatibility-adaptation-soluti.patch |  625 ++++++
 ...upport-for-imp-handle-ras-capability.patch |  205 ++
 ...pdate-error-recovery-module-and-type.patch |  191 ++
 ...or-handling-compatibility-during-ini.patch |  134 ++
 ...t_move_tail-instead-of-list_del-list.patch |   67 +
 ...r-dev-capability-and-dev-spec-of-deb.patch |  697 +++++++
 .../0444-net-hns3-add-support-for-PTP.patch   | 1167 +++++++++++
 ...0445-net-hns3-fix-a-double-shift-bug.patch |   56 +
 ...refactor-related-to-desc_cb-handling.patch |  180 ++
 ...refactor-for-hns3_fill_desc-function.patch |  159 ++
 ...v-flags-support-to-switch-limit-prom.patch |  382 ++++
 ...e-tx-bounce-buffer-for-small-packets.patch |  719 +++++++
 ...port-to-query-tx-spare-buffer-size-f.patch |  172 ++
 ...pport-dma_map_sg-for-multi-frags-skb.patch |  276 +++
 ...nce-buffer-when-rx-page-can-not-be-r.patch |  245 +++
 ...et-hns3-fix-different-snprintf-limit.patch |   58 +
 ...emory-leak-in-an-error-handling-path.patch |   52 +
 ...dd-support-for-FD-counter-in-debugfs.patch |  184 ++
 ...VLAN-offload-state-inconsistent-issu.patch |   61 +
 ...the-method-of-obtaining-default-ptp-.patch |  156 ++
 ...port-for-triggering-reset-by-ethtool.patch |  171 ++
 ...-two-link-extended-substates-of-bad-.patch | 1432 +++++++++++++
 ...link-extended-substates-of-bad-signa.patch |  123 ++
 ...t-hns3-add-header-file-hns3_ethtoo.h.patch |  104 +
 ...-support-ethtool-extended-link-state.patch |  247 +++
 ...s3-fix-speed-unknown-issue-in-bond-4.patch |   55 +
 ...-GRO-configuration-error-after-reset.patch |  193 ++
 ...ros-for-mac-speeds-of-firmware-comma.patch |  170 ++
 ...3_state_init-to-do-state-initializat.patch |  115 +
 ...net-hns3-use-memcpy-to-simplify-code.patch |   60 +
 ...ove-redundant-param-to-simplify-code.patch |   56 +
 ...-new-functions-to-simplify-hclgevf_m.patch |  176 ++
 ...et-hns3-merge-some-repetitive-macros.patch |  229 ++
 ...iform-type-of-function-parameter-cmd.patch |   50 +
 ...ctor-function-hclge_parse_capability.patch |  115 +
 ...or-function-hclgevf_parse_capability.patch |  105 +
 ...add-new-function-hclge_get_speed_bit.patch |  381 ++++
 ...-t-config-TM-DWRR-twice-when-set-ETS.patch |   56 +
 ...unnecessary-static-of-local-variable.patch |   63 +
 ...t-hns3-add-required-space-in-comment.patch |   87 +
 ...ize-each-member-of-structure-array-o.patch | 1854 +++++++++++++++++
 ...-reconstruct-function-hns3_self_test.patch |  190 ++
 ...onstruct-function-hclge_ets_validate.patch |  106 +
 ...efine-function-hclge_dbg_dump_tm_pri.patch |  144 ++
 ...2-net-hnss3-use-max-to-simplify-code.patch |   46 +
 ...-parameter-name-of-hclge_ptp_clean_t.patch |   48 +
 ...ne-function-hns3_set_default_feature.patch |  134 ++
 ...ns3-clean-up-a-type-mismatch-warning.patch |   68 +
 ...86-net-hns3-add-some-required-spaces.patch |  160 ++
 ...7-net-hns3-remove-unnecessary-spaces.patch |   59 +
 ...lgevf_cmd_caps_bit_map0-and-hclge_cm.patch |   70 +
 ...suse-vf-id-and-vport-id-in-some-logs.patch |   54 +
 ...e-the-rx-page-reuse-handling-process.patch |  166 ++
 ...allow-call-hns3_nic_net_open-repeate.patch |   99 +
 ...w-wrong-state-when-add-existing-uc-m.patch |   78 +
 ...ays-enable-rx-vlan-filter-problem-af.patch |   57 +
 ...limit-ets-dwrr-bandwidth-cannot-be-0.patch |   60 +
 ...able-sriov-before-unload-hclge-layer.patch |  104 +
 ...-max-tx-size-according-to-user-manua.patch |   80 +
 ...ue-where-the-trace_mem_disconnect-fu.patch |   36 +
 ...fix-hclge_dbg_dump_tm_pg-stack-usage.patch |   95 +
 ...-t-rollback-when-destroy-mqprio-fail.patch |   73 +
 ...le-promisc-for-VF-when-mac-table-is-.patch |   58 +
 ...for-miscalculation-of-rx-unused-desc.patch |  111 +
 ...e-the-polling-again-when-allocation-.patch |  115 +
 ...mac-statistics-update-process-for-co.patch |  238 +++
 ...specifications-add-number-of-mac-sta.patch |  138 ++
 ...port-pause-pfc-durations-for-mac-sta.patch |  514 +++++
 ...functions-of-converting-speed-abilit.patch |  230 ++
 ...ate-ethtool-advertised-link-modes-fo.patch |  179 ++
 ...hns3-add-new-ras-error-type-for-roce.patch |   62 +
 ...or-recovery-module-and-type-for-hima.patch |   83 +
 ...a-endian-problem-of-some-functions-o.patch |   53 +
 ...e-string-spaces-for-dumping-packets-.patch |   49 +
 ...string-spaces-of-some-parameters-of-.patch |   46 +
 ...fix-hsn3_ethtool-kernel-doc-warnings.patch |   59 +
 ...port-for-pf-querying-new-interrupt-r.patch |  483 +++++
 ...E-base-interrupt-vector-initializati.patch |  120 ++
 ...ync-rx-ring-head-in-echo-common-pull.patch |  177 ++
 ...e-mac-statistics-is-always-0-in-devi.patch |   75 +
 ...w-configure-ETS-bandwidth-of-all-TCs.patch |   76 +
 ...19-ethtool-move-to-its-own-directory.patch |   76 +
 ...-move-string-arrays-into-common-file.patch |  276 +++
 ...vide-link-mode-names-as-a-string-set.patch |  213 ++
 ...-introduce-ethtool-netlink-interface.patch | 1471 +++++++++++++
 ...lper-functions-for-netlink-interface.patch |  497 +++++
 ...de-ring-sizes-with-RINGS_GET-request.patch | 1342 ++++++++++++
 ...ce-ring-sizes-with-RINGS_SET-request.patch |  239 +++
 ...ort-to-set-get-tx-copybreak-buf-size.patch |   72 +
 ...port-to-set-get-tx-copybreak-buf-siz.patch |  163 ++
 ...ort-to-set-get-rx-buf-len-via-ethtoo.patch |  348 ++++
 ...port-to-set-get-rx-buf-len-via-ethto.patch |  183 ++
 ...the-way-to-set-tx-spare-buf-via-modu.patch |   61 +
 ...-add-drop-packet-statistics-of-multi.patch |   55 +
 ...et-hns3-add-dql-info-when-tx-timeout.patch |   51 +
 ...orrect-components-info-of-ethtool-re.patch |   67 +
 ...new-cmdq-hardware-description-struct.patch |  154 ++
 ...uct-hclge_desc-to-replace-hclgevf_de.patch |  304 +++
 ...new-set-of-unified-hclge_comm_cmd_se.patch |  388 ++++
 ...et-hns3-add-support-for-TX-push-mode.patch |  333 +++
 ...andle-empty-unknown-interrupt-for-VF.patch |   51 +
 ...tware-vlan-talbe-of-vlan-0-inconsist.patch |   58 +
 ...d-querying-fec-ability-from-firmware.patch |  140 ++
 ...rying-and-setting-fec-llrs-mode-from.patch |  196 ++
 ...3-add-querying-and-setting-fec-off-m.patch |  131 ++
 ...d-support-for-external-loopback-test.patch |  349 ++++
 ...ting-incorrect-phy-link-ksettings-fo.patch |   66 +
 ...refine-the-handling-for-VF-heartbeat.patch |  856 ++++++++
 ...port-for-queue-bonding-mode-of-flow-.patch |  693 ++++++
 ...dd-queue-bonding-mode-support-for-VF.patch |  412 ++++
 ...llocate-fd-counter-for-queue-bonding.patch |  150 ++
 ...ctor-the-debugfs-for-dumping-FD-tcam.patch |  255 +++
 ...-wake-on-lan-configuration-and-query.patch |  815 ++++++++
 ...-fix-miss-L3E-checking-for-rx-packet.patch |   49 +
 ...port-customized-exception-handling-i.patch |  774 +++++++
 ...ns3-add-support-clear-mac-statistics.patch |  170 ++
 ...port-configuring-function-level-inte.patch |  100 +
 ...ports-fast-reporting-of-faulty-nodes.patch |  304 +++
 ...dd-support-to-get-set-1d-torus-param.patch |  373 ++++
 ...d-support-query-port-ext-information.patch |  351 ++++
 ...ns3-support-set-pfc-pause-trans-time.patch |  247 +++
 ...ns3-disbable-pfc-en-before-the-reset.patch |  108 +
 ...port-query-the-presence-of-optical-m.patch |  100 +
 ...ports-configure-optical-module-enabl.patch |  100 +
 ...port-config-and-query-serdes-lane-st.patch |  110 +
 ...t-hns3-add-support-disable-nic-clock.patch |   80 +
 ...port-PF-provides-customized-interfac.patch |  237 +++
 ...s3-add-support-detect-port-wire-type.patch |  127 ++
 ...6-net-hns3-add-support-set-mac-state.patch |  176 ++
 .../0567-net-hns3-add-support-set-led.patch   |  191 ++
 ...end-interface-support-for-read-and-w.patch |  776 +++++++
 ...net-ethtool-add-VxLAN-to-the-NFC-API.patch |  107 +
 ...orts-to-set-and-query-lane_num-by-sy.patch |  305 +++
 ...r-for-function-hclge_fd_convert_tupl.patch |  299 +++
 ...-set-get-VxLAN-rule-of-rx-flow-direc.patch |  467 +++++
 ...-correct-style-for-SPDX-License-Iden.patch |  109 +
 ...dd-support-for-getting-GE-port-lanes.patch |   47 +
 ...reset-delay-time-to-avoid-configurat.patch |   46 +
 ...ix-reset-timeout-when-enable-full-VF.patch |  260 +++
 ...put-information-incomplete-for-dumpi.patch |   61 +
 ...pport-for-registering-devlink-for-PF.patch |  212 ++
 ...pport-for-registering-devlink-for-VF.patch |  197 ++
 ...e-always-exist-devlink-pointer-check.patch |  188 ++
 ...-the-compilation-problem-of-hclge_co.patch |  232 +++
 ...s-resolved-when-the-rx_buf_len-exten.patch |   39 +
 ...d-the-kabi-change-issue-caused-by-ne.patch |   39 +
 ...-link-modes-settings-uAPI-with-lanes.patch |  787 +++++++
 ...port-to-query-and-set-lane-number-by.patch |  358 ++++
 ...id-mult-div-op-in-critical-data-path.patch |   77 +
 ...0587-ethtool-netlink-bitset-handling.patch |  871 ++++++++
 ...ol-support-FEC-settings-over-netlink.patch |  585 ++++++
 ..._prepare_data-jump-to-error-handling.patch |   60 +
 patches/0590-ethtool-add-FEC-statistics.patch |  599 ++++++
 ...net-hns3-add-querying-fec-statistics.patch |  370 ++++
 ...i-issue-is-resolved-when-the-lane-me.patch |   63 +
 ...the-Kabi-problem-is-caused-by-the-ne.patch |   61 +
 ...r-hclge_update_desc_vfid-for-extensi.patch |   74 +
 ...s3-add-support-config-dscp-map-to-tc.patch |  392 ++++
 ...ncpy-not-using-dest-buf-length-as-le.patch |  123 ++
 ...-hns3-fix-GRE-checksum-offload-issue.patch |   85 +
 ...-imp-capability-bit-cannot-exceed-32.patch |   95 +
 ...et-hns3-add-tm-flush-when-setting-tm.patch |  246 +++
 ...-user-pause-configure-when-disable-a.patch |   72 +
 ...fix-set-cpu-affinity-when-state-down.patch |   43 +
 ...et-hns3-add-wait-until-mac-link-down.patch |   61 +
 ...r-hclge_mac_link_status_wait-for-int.patch |   81 +
 ...setting-wrong-tx_timeout-value-issue.patch |   63 +
 ...r-hclge_cmd_send-with-new-hclge_comm.patch | 1314 ++++++++++++
 ...r-hclgevf_cmd_send-with-new-hclge_co.patch |  810 +++++++
 ...common-cmdq-resource-allocate-free-q.patch |  697 +++++++
 ...r-PF-cmdq-resource-APIs-with-new-com.patch |  988 +++++++++
 ...r-VF-cmdq-resource-APIs-with-new-com.patch |  398 ++++
 ...ate-common-cmdq-init-and-uninit-APIs.patch |   89 +
 ...r-PF-cmdq-init-and-uninit-APIs-with-.patch |  413 ++++
 ...r-VF-cmdq-init-and-uninit-APIs-with-.patch |  453 ++++
 ...te-the-hclge_cmd.c-and-hclgevf_cmd.c.patch |  127 ++
 ...bugfs-support-for-interrupt-coalesce.patch |  217 ++
 ...hns3-support-debugfs-for-wake-on-lan.patch |  140 ++
 ...-hns3-debugfs-add-dump-dscp-map-info.patch |  147 ++
 ...ports-pfc-storm-detection-and-suppre.patch |  210 ++
 ...ting-supported-parameter-from-driver.patch |   45 +
 ...-HCLGE_OPC_WOL_CFG-opcode-id-for-wol.patch |   41 +
 ...inter-cast-to-different-type-for-wol.patch |   56 +
 ...c-linux-kernel-hns3-wol-to-openeuler.patch |  284 +++
 ...upport-for-Hisilicon-ptp-sync-device.patch | 1127 ++++++++++
 ...ate-gettime64-in-favor-of-gettimex64.patch |  111 +
 patches/0624-NIC-hns3-fix-kabi.patch          |  132 ++
 ...-not-calculating-TX-BD-send-size-cor.patch |   68 +
 ...pplication-of-verbose-no_mask-bitset.patch |   69 +
 patches/0627-ethtool-limit-bitset-size.patch  |   73 +
 ...ol-reset-lanes-when-lanes-is-omitted.patch |  103 +
 ...ol-Fix-uninitialized-number-of-lanes.patch |  136 ++
 ...dlock-issue-when-externel_lb-and-res.patch |   96 +
 ...tool-tx-copybreak-buf-size-indicatin.patch |  116 ++
 ...-order-judgement-for-tx-spare-buffer.patch |   50 +
 ...rk-netlink-family-as-__ro_after_init.patch |   48 +
 ...dev-reset-check-for-hns3_set_tunable.patch |   59 +
 ...turn-value-check-bug-of-rx-copybreak.patch |   46 +
 ...-configuration-of-TM-QCN-error-event.patch |   62 +
 ...-MAC-type-definitions-and-support-qu.patch |  148 ++
 ...framework-add-support-for-ROH-client.patch |  463 ++++
 ...lback-ethtool-s-modification-of-lane.patch | 1000 +++++++++
 ...ck-Ethtool-s-modifications-to-extack.patch |   61 +
 ...-about-nla_-Modification-of-kabi-cha.patch |  340 +++
 ...i-issue-caused-by-ptp-introducing-ge.patch |  123 ++
 ...tool_-Ops-gen_-Improper-modification.patch |  100 +
 ...easonable-modifications-caused-by-ro.patch |  278 +++
 series.conf                                   |  283 +++
 285 files changed, 60401 insertions(+), 1 deletion(-)
 create mode 100644 patches/0362-net-hns3-Fix-for-loopback-selftest-failed-problem.patch
 create mode 100644 patches/0363-net-hns3-Only-update-mac-configuation-when-necessary.patch
 create mode 100644 patches/0364-net-hns3-Add-default-irq-affinity.patch
 create mode 100644 patches/0365-net-hns3-Add-unlikely-for-buf_num-check.patch
 create mode 100644 patches/0366-net-phy-Move-linkmode-helpers-to-somewhere-public.patch
 create mode 100644 patches/0367-net-hns3-make-function-hclge_set_all_vf_rst-static.patch
 create mode 100644 patches/0368-net-hns3-return-0-and-print-warning-when-hit-duplica.patch
 create mode 100644 patches/0369-net-hns3-Use-LLDP-ethertype-define-ETH_P_LLDP.patch
 create mode 100644 patches/0370-net-hns3-fix-compile-warning-without-CONFIG_RFS_ACCE.patch
 create mode 100644 patches/0371-net-hns3-adjust-hns3_uninit_phy-s-location-in-the-hn.patch
 create mode 100644 patches/0372-net-hns3-remove-unused-macros.patch
 create mode 100644 patches/0373-net-hns3-modify-an-unsuitable-log-in-hclge_map_ring_.patch
 create mode 100644 patches/0374-net-hns3-reject-unsupported-coalescing-params.patch
 create mode 100644 patches/0375-net-hns3-clear-port-base-VLAN-when-unload-PF.patch
 create mode 100644 patches/0376-net-hns-Remove-custom-driver-version-in-favour-of-gl.patch
 create mode 100644 patches/0377-net-hns3-remove-a-redundant-register-macro-definitio.patch
 create mode 100644 patches/0378-net-hns3-modify-two-uncorrect-macro-names.patch
 create mode 100644 patches/0379-net-hns3-remove-a-duplicated-printing-in-hclge_confi.patch
 create mode 100644 patches/0380-net-hns3-refactor-hclge_config_tso.patch
 create mode 100644 patches/0381-net-hns3-refactor-hclge_query_bd_num_cmd_send.patch
 create mode 100644 patches/0382-net-hns3-modify-an-incorrect-type-in-struct-hclge_cf.patch
 create mode 100644 patches/0383-net-hns3-modify-an-incorrect-type-in-struct-hclgevf_.patch
 create mode 100644 patches/0384-net-hns3-remove-some-unused-fields-in-struct-hns3_ni.patch
 create mode 100644 patches/0385-net-hns3-remove-unused-struct-hnae3_unic_private_inf.patch
 create mode 100644 patches/0386-net-hns3-remove-two-duplicated-register-macros-in-hc.patch
 create mode 100644 patches/0387-net-hns3-remove-some-unused-fields-in-struct-hclge_d.patch
 create mode 100644 patches/0388-net-hns3-fix-a-print-format-issue-in-hclge_mac_mdio_.patch
 create mode 100644 patches/0389-net-hns3-remove-an-unused-macro-hclge_is_csq.patch
 create mode 100644 patches/0390-net-hns3-remove-two-unused-macros-in-hclgevf_cmd.c.patch
 create mode 100644 patches/0391-net-hns3-fix-two-coding-style-issues-in-hclgevf_main.patch
 create mode 100644 patches/0392-net-hns3-remove-some-unused-codes-in-hns3_nic_set_fe.patch
 create mode 100644 patches/0393-net-hns3-remove-some-unused-macros.patch
 create mode 100644 patches/0394-net-hns3-add-device-version-to-replace-pci-revision.patch
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 create mode 100644 patches/0638-net-hns3-HNAE3-framework-add-support-for-ROH-client.patch
 create mode 100644 patches/0639-net-hns3-Fallback-ethtool-s-modification-of-lane.patch
 create mode 100644 patches/0640-net-hns3-Fallback-Ethtool-s-modifications-to-extack.patch
 create mode 100644 patches/0641-Fallback-ethtool-about-nla_-Modification-of-kabi-cha.patch
 create mode 100644 patches/0642-net-hns3-Fix-Kabi-issue-caused-by-ptp-introducing-ge.patch
 create mode 100644 patches/0643-net-hns3-Fix-ethtool_-Ops-gen_-Improper-modification.patch
 create mode 100644 patches/0644-net-hns3-Fix-unreasonable-modifications-caused-by-ro.patch

diff --git a/kernel.spec b/kernel.spec
index 39fc740..6b3719d 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -32,7 +32,7 @@
 
 Name:	 kernel
 Version: 4.19.90
-Release: %{hulkrelease}.0244
+Release: %{hulkrelease}.0245
 Summary: Linux Kernel
 License: GPLv2
 URL:	 http://www.kernel.org/
@@ -850,6 +850,291 @@ fi
 
 %changelog
 
+* Fri Nov 17 2023 Luo Shengwei <luoshengwei@huawei.com> - 4.19.90-2311.3.0.0245
+- net: hns3: Fix unreasonable modifications caused by rollback extension ringparam parameters
+- net: hns3: Fix ethtool_ Ops&gen_ Improper modification of kabi changes caused by adding members in the ops structure
+- net: hns3: Fix Kabi issue caused by ptp introducing gettimex64()
+- Fallback ethtool about nla_ Modification of kabi changes caused by the addition of new associations in the policy structure
+- net: hns3: Fallback Ethtool's modifications to extack
+- net: hns3: Fallback ethtool's modification of lane
+- net: hns3: HNAE3 framework add support for ROH client
+- net: hns3: add ROH MAC type definitions and support query MAC type
+- net: hns3: Add configuration of TM QCN error event
+- net: hns3: fix return value check bug of rx copybreak
+- net: hns3: add netdev reset check for hns3_set_tunable()
+- ethtool: mark netlink family as __ro_after_init
+- net: hns3: add max order judgement for tx spare buffer
+- net: hns3: fix ethtool tx copybreak buf size indicating not aligned issue
+- net: hns3: fix deadlock issue when externel_lb and reset are executed together
+- ethtool: Fix uninitialized number of lanes
+- ethtool: reset lanes when lanes is omitted
+- ethtool: limit bitset size
+- ethtool: fix application of verbose no_mask bitset
+- net: hns3: fix for not calculating TX BD send size correctly
+- NIC: hns3: fix kabi
+- ptp: deprecate gettime64() in favor of gettimex64()
+- net: hns3: add support for Hisilicon ptp sync device
+- net: hns3: sync linux kernel hns3 wol to openeuler
+- net: hns3: fix pointer cast to different type for wol
+- net: hns3: fix the HCLGE_OPC_WOL_CFG opcode id for wol
+- net: hns3: fix getting supported parameter from driver in hclge_set_wol
+- net: hns3: add supports pfc storm detection and suppression
+- net: hns3: debugfs add dump dscp map info
+- net: hns3: support debugfs for wake on lan
+- net: hns3: add debugfs support for interrupt coalesce
+- net: hns3: delete the hclge_cmd.c and hclgevf_cmd.c
+- net: hns3: refactor VF cmdq init and uninit APIs with new common APIs
+- net: hns3: refactor PF cmdq init and uninit APIs with new common APIs
+- net: hns3: create common cmdq init and uninit APIs
+- net: hns3: refactor VF cmdq resource APIs with new common APIs
+- net: hns3: refactor PF cmdq resource APIs with new common APIs
+- net: hns3: create common cmdq resource allocate/free/query APIs
+- net: hns3: refactor hclgevf_cmd_send with new hclge_comm_cmd_send API
+- net: hns3: refactor hclge_cmd_send with new hclge_comm_cmd_send API
+- net: hns3: fix setting wrong tx_timeout value issue
+- net: hns3: refactor hclge_mac_link_status_wait for interface reuse
+- net: hns3: add wait until mac link down
+- net: hns3: fix set cpu affinity when state down
+- net: hns3: restore user pause configure when disable autoneg
+- net: hns3: add tm flush when setting tm
+- net: hns3: fix the imp capability bit cannot exceed 32 bits issue
+- net: hns3: fix GRE checksum offload issue
+- net: hns3: fix strncpy() not using dest-buf length as length issue
+- net: hns3: add support config dscp map to tc
+- net: hns3: refactor hclge_update_desc_vfid for extension
+- net:ethtool Fix the Kabi problem is caused by the new FEC callback function in ethtool_ops
+- net:hns3 The kabi issue is resolved when the lane members are added to the ethtool_link_ksettings structure
+- net: hns3: add querying fec statistics
+- ethtool: add FEC statistics
+- ethtool: fec_prepare_data() - jump to error handling
+- ethtool: support FEC settings over netlink
+- ethtool: netlink bitset handling
+- net: hns3: avoid mult + div op in critical data path
+- net: hns3: add support to query and set lane number by ethtool
+- ethtool: Extend link modes settings uAPI with lanes
+- net: hns3: Resolved the kabi change issue caused by new members in the devlink structure
+- The kabi issue is resolved when the rx_buf_len extension ring is used to set parameters or obtain APIs
+- net: hns3: Fix for the compilation problem of hclge_comm_cmd
+- net: hns3: remove always exist devlink pointer check
+- net: hns3: add support for registering devlink for VF
+- net: hns3: add support for registering devlink for PF
+- net: hns3: fix output information incomplete for dumping tx queue info with debugfs
+- net: hns3: fix reset timeout when enable full VF
+- net: hns3: modify reset delay time to avoid configuration timeout
+- net: hns3: add support for getting GE port lanes
+- net: hns3: Use the correct style for SPDX License Identifier
+- net: hns3: support set/get VxLAN rule of rx flow director by ethtool
+- net: hns3: refactor for function hclge_fd_convert_tuple
+- net: hns3: PF supports to set and query lane_num by sysfs
+- net: ethtool: add VxLAN to the NFC API
+- net: hns3: add extend interface support for read and write phy register
+- net: hns3: add support set led
+- net: hns3: add support set mac state
+- net: hns3: add support detect port wire type
+- net: hns3: add support PF provides customized interfaces to detect port faults.
+- net: hns3: add support disable nic clock
+- net: hns3: add support config and query serdes lane status
+- net: hns3: add supports configure optical module enable
+- net: hns3: add support query the presence of optical module
+- net: hns3: disbable pfc en before the reset
+- net: hns3: support set pfc pause trans time
+- net: hns3: add support query port ext information
+- net: hns3: add support to get/set 1d torus param
+- net: hns3: add supports fast reporting of faulty nodes
+- net: hns3: add support configuring function-level interrupt affinity
+- net: hns3: add support clear mac statistics
+- net: hns3: add support customized exception handling interfaces.
+- net: hns3: fix miss L3E checking for rx packet
+- net: hns3: support wake on lan configuration and query
+- net: hns3: refactor the debugfs for dumping FD tcam
+- net: hns3: allocate fd counter for queue bonding
+- net: hns3: add queue bonding mode support for VF
+- net: hns3: add support for queue bonding mode of flow director
+- net: hns3: refine the handling for VF heartbeat
+- net: hns3: fix setting incorrect phy link ksettings for firmware in resetting process
+- net: hns3: add support for external loopback test
+- net: hns3: net: hns3: add querying and setting fec off mode from firmware
+- net: hns3: add querying and setting fec llrs mode from firmware
+- net: hns3: add querying fec ability from firmware
+- net: hns3: fix software vlan talbe of vlan 0 inconsistent with hardware
+- net: hns3: handle empty unknown interrupt for VF
+- net: hns3: add support for TX push mode
+- net: hns3: create new set of unified hclge_comm_cmd_send APIs
+- net: hns3: use struct hclge_desc to replace hclgevf_desc in VF cmdq module
+- net: hns3: create new cmdq hardware description structure hclge_comm_hw
+- net: hns3: fix incorrect components info of ethtool --reset command
+- net: hns3: add dql info when tx timeout
+- net: hns3: debugfs add drop packet statistics of multicast and broadcast for igu
+- net: hns3: remove the way to set tx spare buf via module parameter
+- net: hns3: add support to set/get rx buf len via ethtool for hns3 driver
+- ethtool: add support to set/get rx buf len via ethtool
+- net: hns3: add support to set/get tx copybreak buf size via ethtool for hns3 driver
+- ethtool: add support to set/get tx copybreak buf size via ethtool
+- ethtool: set device ring sizes with RINGS_SET request
+- ethtool: provide ring sizes with RINGS_GET request
+- ethtool: helper functions for netlink interface
+- ethtool: introduce ethtool netlink interface
+- ethtool: provide link mode names as a string set
+- ethtool: move string arrays into common file
+- ethtool: move to its own directory
+- net: hns3: allow configure ETS bandwidth of all TCs
+- net: hns3: fix some mac statistics is always 0 in device version V2
+- net: hns3: sync rx ring head in echo common pull
+- net: hns3: fix ROCE base interrupt vector initialization bug
+- net: hns3: add support for pf querying new interrupt resources
+- net: hisilicon: fix hsn3_ethtool kernel-doc warnings
+- net: hns3: adjust string spaces of some parameters of tx bd info in debugfs
+- net: hns3: add more string spaces for dumping packets number of queue info in debugfs
+- net: hns3: fix data endian problem of some functions of debugfs
+- net: hns3: add error recovery module and type for himac
+- net: hns3: add new ras error type for roce
+- net: hns3: add update ethtool advertised link modes for FIBRE port when autoneg off
+- net: hns3: modify functions of converting speed ability to ethtool link mode
+- net: hns3: add support pause/pfc durations for mac statistics
+- net: hns3: device specifications add number of mac statistics
+- net: hns3: modify mac statistics update process for compatibility
+- net: hns3: schedule the polling again when allocation fails
+- net: hns3: fix for miscalculation of rx unused desc
+- net: hns3: PF enable promisc for VF when mac table is overflow
+- net: hns3: don't rollback when destroy mqprio fail
+- net: hns3: fix hclge_dbg_dump_tm_pg() stack usage
+- xdp: Fixed an issue where the trace_mem_disconnect function cannot find the definition.
+- net: hns3: fix the max tx size according to user manual
+- net: hns3: disable sriov before unload hclge layer
+- net: hns3: add limit ets dwrr bandwidth cannot be 0
+- net: hns3: fix always enable rx vlan filter problem after selftest
+- net: hns3: fix show wrong state when add existing uc mac address
+- net: hns3: do not allow call hns3_nic_net_open repeatedly
+- net: hns3: optimize the rx page reuse handling process
+- net: hns3: fix misuse vf id and vport id in some logs
+- net: hns3: make hclgevf_cmd_caps_bit_map0 and hclge_cmd_caps_bit_map0 static
+- net: hns3: remove unnecessary spaces
+- net: hns3: add some required spaces
+- net: hns3: clean up a type mismatch warning
+- net: hns3: refine function hns3_set_default_feature()
+- net: hns3: uniform parameter name of hclge_ptp_clean_tx_hwts()
+- net: hnss3: use max() to simplify code
+- net: hns3: refine function hclge_dbg_dump_tm_pri()
+- net: hns3: reconstruct function hclge_ets_validate()
+- net: hns3: reconstruct function hns3_self_test
+- net: hns3: initialize each member of structure array on a separate line
+- net: hns3: add required space in comment
+- net: hns3: remove unnecessary "static" of local variables in function
+- net: hns3: don't config TM DWRR twice when set ETS
+- net: hns3: add new function hclge_get_speed_bit()
+- net: hns3: refactor function hclgevf_parse_capability()
+- net: hns3: refactor function hclge_parse_capability()
+- net: hns3: uniform type of function parameter cmd
+- net: hns3: merge some repetitive macros
+- net: hns3: package new functions to simplify hclgevf_mbx_handler code
+- net: hns3: remove redundant param to simplify code
+- net: hns3: use memcpy to simplify code
+- net: hns3: add hns3_state_init() to do state initialization
+- net: hns3: add macros for mac speeds of firmware command
+- net: hns3: fix GRO configuration error after reset
+- net: hns3: fix speed unknown issue in bond 4
+- net: hns3: add support ethtool extended link state
+- net: hns3: add header file hns3_ethtoo.h
+- ethtool: add two link extended substates of bad signal integrity
+- docs: ethtool: Add two link extended substates of bad signal integrity
+- net: hns3: add support for triggering reset by ethtool
+- net: hns3: change the method of obtaining default ptp cycle
+- net: hns3: fix rx VLAN offload state inconsistent issue
+- net: hns3: add support for FD counter in debugfs
+- net: hns3: Fix a memory leak in an error handling path in 'hclge_handle_error_info_log()'
+- net: hns3: fix different snprintf() limit
+- net: hns3: use bounce buffer when rx page can not be reused
+- net: hns3: support dma_map_sg() for multi frags skb
+- net: hns3: add support to query tx spare buffer size for pf
+- net: hns3: use tx bounce buffer for small packets
+- net: hns3: add priv flags support to switch limit promisc mode
+- net: hns3: refactor for hns3_fill_desc() function
+- net: hns3: minor refactor related to desc_cb handling
+- net: hns3: fix a double shift bug
+- net: hns3: add support for PTP
+- net: hns3: refactor dev capability and dev spec of debugfs
+- net: hns3: use list_move_tail instead of list_del/list_add_tail in hclgevf_main.c
+- net: hns3: add error handling compatibility during initialization
+- net: hns3: update error recovery module and type
+- net: hns3: add support for imp-handle ras capability
+- net: hns3: add the RAS compatibility adaptation solution
+- net: hns3: add support for handling all errors through MSI-X
+- net: hns3: remove now redundant logic related to HNAE3_UNKNOWN_RESET
+- net: hns3: add log for workqueue scheduled late
+- net: hns3: add scheduling logic for error handling task
+- net: hns3: add a separate error handling task
+- net: hns3: use HCLGE_VPORT_STATE_PROMISC_CHANGE to replace HCLGE_STATE_PROMISC_CHANGED
+- net: hns3: fix user's coalesce configuration lost issue
+- net: hns3: add support for configuring interrupt quantity limiting
+- net: hns3: clear unnecessary reset request in hclge_reset_rebuild
+- net: hns3: cleanup inappropriate spaces in struct hlcgevf_tqp_stats
+- net: hns3: Trivial spell fix in hns3 driver
+- net: hns3: split out hclge_tm_vport_tc_info_update()
+- net: hns3: split function hclge_reset_rebuild()
+- net: hns3: remove redundant query in hclge_config_tm_hw_err_int()
+- net: hns3: remove redundant blank lines
+- net: hns3: remove unused code of vmdq
+- net: hns3: add support to query device specifications
+- net: hns3: add phy loopback support for imp-controlled PHYs
+- net: hns3: add ioctl support for imp-controlled PHYs
+- net: hns3: add get/set pause parameters support for imp-controlled PHYs
+- net: hns3: add support for imp-controlled PHYs
+- net:hns3 Fix KABI for The dev_version & caps element is added to the hnae3_ae_dev structure.
+- net:hns3 Fix KABI for deletion of hnae3_unic_private_info in hnae3_handle
+- net:hns3 Fix KABI for ethtools->supported_coalesce_params
+- net: hns3: split out hclgevf_cmd_send()
+- net: hns3: split out hclge_cmd_send()
+- net: hns3: refactor out hclgevf_get_rss_tuple()
+- net: hns3: refactor out hclge_get_rss_tuple()
+- net: hns3: refactor out hclge_set_vf_vlan_common()
+- net: hns3: use ipv6_addr_any() helper
+- net: hns3: refactor out hclgevf_cmd_convert_err_code()
+- net: hns3: refactor out hclge_cmd_convert_err_code()
+- net: hns3: remove unused macro definition
+- net: hns3: change hclge_query_bd_num() param type
+- net: hns3: change hclge_parse_speed() param type
+- net: hns3: clean up unnecessary parentheses in macro definitions
+- net: hns3: remove the shaper param magic number
+- net: hns3: add a structure for IR shaper's parameter in hclge_shaper_para_calc()
+- net: hns3: add support for TX hardware checksum offload
+- net: hns3: initialize the message content in hclge_get_link_mode()
+- net: hns3: add UDP segmentation offload support
+- net: hns3: use capabilities queried from firmware
+- net: hns3: add support to query device capability
+- net: hns3: add device version to replace pci revision
+- net: hns3: remove some unused macros
+- net: hns3: remove some unused codes in hns3_nic_set_features()
+- net: hns3: fix two coding style issues in hclgevf_main.c
+- net: hns3: remove two unused macros in hclgevf_cmd.c
+- net: hns3: remove an unused macro hclge_is_csq
+- net: hns3: fix a print format issue in hclge_mac_mdio_config()
+- net: hns3: remove some unused fields in struct hclge_dev
+- net: hns3: remove two duplicated register macros in hclgevf_main.h
+- net: hns3: remove unused struct hnae3_unic_private_info
+- net: hns3: remove some unused fields in struct hns3_nic_priv
+- net: hns3: modify an incorrect type in struct hclgevf_cfg_gro_status_cmd
+- net: hns3: modify an incorrect type in struct hclge_cfg_gro_status_cmd
+- net: hns3: refactor hclge_query_bd_num_cmd_send()
+- net: hns3: refactor hclge_config_tso()
+- net: hns3: remove a duplicated printing in hclge_configure()
+- net: hns3: modify two uncorrect macro names
+- net: hns3: remove a redundant register macro definition
+- net/hns: Remove custom driver version in favour of global one
+- net: hns3: clear port base VLAN when unload PF
+- net: hns3: reject unsupported coalescing params
+- net: hns3: modify an unsuitable log in hclge_map_ring_to_vector()
+- net: hns3: remove unused macros
+- net: hns3: adjust hns3_uninit_phy()'s location in the hns3_client_uninit()
+- net: hns3: fix compile warning without CONFIG_RFS_ACCEL
+- net: hns3: Use LLDP ethertype define ETH_P_LLDP
+- net: hns3: return 0 and print warning when hit duplicate MAC
+- net: hns3: make function hclge_set_all_vf_rst() static
+- net: phy: Move linkmode helpers to somewhere public
+- net: hns3: Add unlikely for buf_num check
+- net: hns3: Add default irq affinity
+- net: hns3: Only update mac configuation when necessary
+- net: hns3: Fix for loopback selftest failed problem
+
 * Wed Nov 15 2023 Luo Shengwei <luoshengwei@huawei.com> - 4.19.90-2311.3.0.0244
 - !2803 drivers/gmjstcm: fix a dev_err() call in spi tcm device probe
 - !2841  drm/qxl: fix UAF on handle creation
diff --git a/patches/0362-net-hns3-Fix-for-loopback-selftest-failed-problem.patch b/patches/0362-net-hns3-Fix-for-loopback-selftest-failed-problem.patch
new file mode 100644
index 0000000..4976457
--- /dev/null
+++ b/patches/0362-net-hns3-Fix-for-loopback-selftest-failed-problem.patch
@@ -0,0 +1,54 @@
+From 06d65b6bd4d2fe5a1c020dda207b70d4211caf50 Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Mon, 3 Sep 2018 11:21:50 +0100
+Subject: [PATCH 001/283] net: hns3: Fix for loopback selftest failed problem
+
+mainline inclusion
+from mainline-v4.20-rc1
+commit 0f29fc23b21d3cbd966537bfabba07c00466b787
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0f29fc23b21d3cbd966537bfabba07c00466b787
+
+--------------------------------
+
+Tqp and mac need to be enabled when doing loopback selftest,
+ae_algo->ops->start/stop is used to do the job, there is a
+time window between ae_algo->ops->start/stop and loopback setup,
+which will cause selftest failed problem when there is frame
+coming in during that time window.
+
+This patch fixes it by enabling the tqp and mac during loopback
+setup process.
+
+Fixes: c39c4d98dc65 ("net: hns3: Add mac loopback selftest support in hns3 driver")
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index be771c75e37e..d18e8141f7e4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -125,7 +125,7 @@ static int hns3_lp_up(struct net_device *ndev, enum hnae3_loop loop_mode)
+ 	ret = hns3_lp_setup(ndev, loop_mode, true);
+ 	usleep_range(HNS3_NIC_LB_SETUP_USEC, HNS3_NIC_LB_SETUP_USEC * 2);
+ 
+-	return ret;
++	return 0;
+ }
+ 
+ static int hns3_lp_down(struct net_device *ndev, enum hnae3_loop loop_mode)
+-- 
+2.34.1
+
diff --git a/patches/0363-net-hns3-Only-update-mac-configuation-when-necessary.patch b/patches/0363-net-hns3-Only-update-mac-configuation-when-necessary.patch
new file mode 100644
index 0000000..3954270
--- /dev/null
+++ b/patches/0363-net-hns3-Only-update-mac-configuation-when-necessary.patch
@@ -0,0 +1,48 @@
+From 3cd7ff62b371e10e7f66cee74c75e69708a98c63 Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Mon, 3 Sep 2018 11:21:53 +0100
+Subject: [PATCH 002/283] net: hns3: Only update mac configuation when
+ necessary
+
+mainline inclusion
+from mainline-v4.20-rc1
+commit 2d03eacc0b7e7aeedce6032f79872f3fd3d1a94f
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2d03eacc0b7e7aeedce6032f79872f3fd3d1a94f
+
+--------------------------------
+
+Currently only fiber port checks if it is necessay to set the
+mac through firmware when link is changed, this patch unify the
+checking to allow the copper port do the checking too.
+
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index b4b1e440fba4..9f9edbdc518a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -2424,7 +2424,7 @@ static u8 hclge_check_speed_dup(u8 duplex, int speed)
+ 	return duplex;
+ }
+ 
+-static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
++int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
+ 				      u8 duplex)
+ {
+ 	struct hclge_config_mac_speed_dup_cmd *req;
+-- 
+2.34.1
+
diff --git a/patches/0364-net-hns3-Add-default-irq-affinity.patch b/patches/0364-net-hns3-Add-default-irq-affinity.patch
new file mode 100644
index 0000000..dd4596c
--- /dev/null
+++ b/patches/0364-net-hns3-Add-default-irq-affinity.patch
@@ -0,0 +1,57 @@
+From a5bb8b792691fabf9bb61ae5328eb47d7d5da7fb Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Wed, 19 Sep 2018 18:29:47 +0100
+Subject: [PATCH 003/283] net: hns3: Add default irq affinity
+
+mainline inclusion
+from mainline-v4.20-rc1
+commit 874bff0ba6cf884dde0220bfa8945f164e6da1d1
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=874bff0ba6cf884dde0220bfa8945f164e6da1d1
+
+--------------------------------
+
+All irq will float to cpu0 if do not set irq affinity.
+This patch adds default irq affinity in hns3 driver, users can
+also change the irq affinity in OS.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 20703ce86281..1495e972dc89 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -100,6 +100,10 @@ static irqreturn_t hns3_irq_handle(int irq, void *vector)
+ 	return IRQ_HANDLED;
+ }
+ 
++/* This callback function is used to set affinity changes to the irq affinity
++ * masks when the irq_set_affinity_notifier function is used.
++ */
++
+ static void hns3_nic_uninit_irq(struct hns3_nic_priv *priv)
+ {
+ 	struct hns3_enet_tqp_vector *tqp_vectors;
+@@ -3673,6 +3677,8 @@ static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
+ 
+ 	hns3_nic_set_cpumask(priv);
+ 
++	hns3_nic_set_cpumask(priv);
++
+ 	for (i = 0; i < priv->vector_num; i++) {
+ 		tqp_vector = &priv->tqp_vector[i];
+ 		hns3_vector_gl_rl_init_hw(tqp_vector, priv);
+-- 
+2.34.1
+
diff --git a/patches/0365-net-hns3-Add-unlikely-for-buf_num-check.patch b/patches/0365-net-hns3-Add-unlikely-for-buf_num-check.patch
new file mode 100644
index 0000000..988548e
--- /dev/null
+++ b/patches/0365-net-hns3-Add-unlikely-for-buf_num-check.patch
@@ -0,0 +1,73 @@
+From 1c09e1a8da3599ede304788c1af8cb8345d3b634 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Wed, 19 Sep 2018 18:29:48 +0100
+Subject: [PATCH 004/283] net: hns3: Add unlikely for buf_num check
+
+mainline inclusion
+from mainline-v4.20-rc1
+commit 932d1252aded755bfd6f53183ab6211f711c6435
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=932d1252aded755bfd6f53183ab6211f711c6435
+
+--------------------------------
+
+This patch adds unlikely for buf_num check.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 8 ++------
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 7 +++++++
+ 2 files changed, 9 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 1495e972dc89..b184c3e83e05 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -1282,16 +1282,12 @@ static int hns3_skb_linearize(struct hns3_enet_ring *ring, struct sk_buff *skb,
+ 	 */
+ 	if (skb->len > HNS3_MAX_TSO_SIZE ||
+ 	    (!skb_is_gso(skb) && skb->len > HNS3_MAX_NON_TSO_SIZE)) {
+-		u64_stats_update_begin(&ring->syncp);
+-		ring->stats.hw_limitation++;
+-		u64_stats_update_end(&ring->syncp);
++		hns3_ring_stats_update(ring, hw_limitation);
+ 		return -ENOMEM;
+ 	}
+ 
+ 	if (__skb_linearize(skb)) {
+-		u64_stats_update_begin(&ring->syncp);
+-		ring->stats.sw_err_cnt++;
+-		u64_stats_update_end(&ring->syncp);
++		hns3_ring_stats_update(ring, sw_err_cnt);
+ 		return -ENOMEM;
+ 	}
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index ef4463ae26cf..19f83dfb32aa 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -604,6 +604,13 @@ static inline bool hns3_nic_resetting(struct net_device *netdev)
+ 
+ #define hns3_buf_size(_ring) ((_ring)->buf_size)
+ 
++#define hns3_ring_stats_update(ring, cnt) do { \
++	typeof(ring) (tmp) = (ring); \
++	u64_stats_update_begin(&(tmp)->syncp); \
++	((tmp)->stats.cnt)++; \
++	u64_stats_update_end(&(tmp)->syncp); \
++} while (0) \
++
+ static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
+ {
+ #if (PAGE_SIZE < 8192)
+-- 
+2.34.1
+
diff --git a/patches/0366-net-phy-Move-linkmode-helpers-to-somewhere-public.patch b/patches/0366-net-phy-Move-linkmode-helpers-to-somewhere-public.patch
new file mode 100644
index 0000000..873f818
--- /dev/null
+++ b/patches/0366-net-phy-Move-linkmode-helpers-to-somewhere-public.patch
@@ -0,0 +1,201 @@
+From d6164056687c7cd8ab664995c7a386c257a6b5a3 Mon Sep 17 00:00:00 2001
+From: Andrew Lunn <andrew@lunn.ch>
+Date: Sat, 29 Sep 2018 23:04:09 +0200
+Subject: [PATCH 005/283] net: phy: Move linkmode helpers to somewhere public
+
+mainline inclusion
+from mainline-v4.20-rc1
+commit b31cdffa2329fe330cd304ca26c250dd1520fb0a
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b31cdffa2329fe330cd304ca26c250dd1520fb0a
+
+--------------------------------
+
+phylink has some useful helpers to working with linkmode bitmaps.
+Move them to there own header so other code can use them.
+
+Signed-off-by: Andrew Lunn <andrew@lunn.ch>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com>
+Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/kcompat.h | 20 ------
+ drivers/net/phy/phylink.c                     | 27 --------
+ include/linux/linkmode.h                      | 67 +++++++++++++++++++
+ include/linux/mii.h                           |  1 +
+ include/linux/phy.h                           |  1 +
+ 5 files changed, 69 insertions(+), 47 deletions(-)
+ create mode 100644 include/linux/linkmode.h
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/kcompat.h b/drivers/net/ethernet/hisilicon/hns3/kcompat.h
+index 5cf3a35ca607..8b5de09fa7f7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/kcompat.h
++++ b/drivers/net/ethernet/hisilicon/hns3/kcompat.h
+@@ -383,26 +383,6 @@ static inline __must_check size_t array3_size(size_t a, size_t b, size_t c)
+ 
+ #include <linux/bitmap.h>
+ 
+-static inline void linkmode_set_bit(int nr, volatile unsigned long *addr)
+-{
+-	__set_bit(nr, addr);
+-}
+-
+-static inline void linkmode_copy(unsigned long *dst, const unsigned long *src)
+-{
+-	bitmap_copy(dst, src, __ETHTOOL_LINK_MODE_MASK_NBITS);
+-}
+-
+-static inline void linkmode_clear_bit(int nr, volatile unsigned long *addr)
+-{
+-	__clear_bit(nr, addr);
+-}
+-
+-static inline void linkmode_zero(unsigned long *dst)
+-{
+-	bitmap_zero(dst, __ETHTOOL_LINK_MODE_MASK_NBITS);
+-}
+-
+ #else
+ 
+ #define HAS_LINK_MODE_OPS
+diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
+index 723611ac9102..227d5a1ef963 100644
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -72,33 +72,6 @@ struct phylink {
+ 	struct sfp_bus *sfp_bus;
+ };
+ 
+-static inline void linkmode_zero(unsigned long *dst)
+-{
+-	bitmap_zero(dst, __ETHTOOL_LINK_MODE_MASK_NBITS);
+-}
+-
+-static inline void linkmode_copy(unsigned long *dst, const unsigned long *src)
+-{
+-	bitmap_copy(dst, src, __ETHTOOL_LINK_MODE_MASK_NBITS);
+-}
+-
+-static inline void linkmode_and(unsigned long *dst, const unsigned long *a,
+-				const unsigned long *b)
+-{
+-	bitmap_and(dst, a, b, __ETHTOOL_LINK_MODE_MASK_NBITS);
+-}
+-
+-static inline void linkmode_or(unsigned long *dst, const unsigned long *a,
+-				const unsigned long *b)
+-{
+-	bitmap_or(dst, a, b, __ETHTOOL_LINK_MODE_MASK_NBITS);
+-}
+-
+-static inline bool linkmode_empty(const unsigned long *src)
+-{
+-	return bitmap_empty(src, __ETHTOOL_LINK_MODE_MASK_NBITS);
+-}
+-
+ /**
+  * phylink_set_port_modes() - set the port type modes in the ethtool mask
+  * @mask: ethtool link mode mask
+diff --git a/include/linux/linkmode.h b/include/linux/linkmode.h
+new file mode 100644
+index 000000000000..014fb86c7114
+--- /dev/null
++++ b/include/linux/linkmode.h
+@@ -0,0 +1,67 @@
++#ifndef __LINKMODE_H
++#define __LINKMODE_H
++
++#include <linux/bitmap.h>
++#include <linux/ethtool.h>
++#include <uapi/linux/ethtool.h>
++
++static inline void linkmode_zero(unsigned long *dst)
++{
++	bitmap_zero(dst, __ETHTOOL_LINK_MODE_MASK_NBITS);
++}
++
++static inline void linkmode_copy(unsigned long *dst, const unsigned long *src)
++{
++	bitmap_copy(dst, src, __ETHTOOL_LINK_MODE_MASK_NBITS);
++}
++
++static inline void linkmode_and(unsigned long *dst, const unsigned long *a,
++				const unsigned long *b)
++{
++	bitmap_and(dst, a, b, __ETHTOOL_LINK_MODE_MASK_NBITS);
++}
++
++static inline void linkmode_or(unsigned long *dst, const unsigned long *a,
++				const unsigned long *b)
++{
++	bitmap_or(dst, a, b, __ETHTOOL_LINK_MODE_MASK_NBITS);
++}
++
++static inline bool linkmode_empty(const unsigned long *src)
++{
++	return bitmap_empty(src, __ETHTOOL_LINK_MODE_MASK_NBITS);
++}
++
++static inline int linkmode_andnot(unsigned long *dst, const unsigned long *src1,
++				  const unsigned long *src2)
++{
++	return bitmap_andnot(dst, src1, src2,  __ETHTOOL_LINK_MODE_MASK_NBITS);
++}
++
++static inline void linkmode_set_bit(int nr, volatile unsigned long *addr)
++{
++	__set_bit(nr, addr);
++}
++
++static inline void linkmode_clear_bit(int nr, volatile unsigned long *addr)
++{
++	__clear_bit(nr, addr);
++}
++
++static inline void linkmode_change_bit(int nr, volatile unsigned long *addr)
++{
++	__change_bit(nr, addr);
++}
++
++static inline int linkmode_test_bit(int nr, volatile unsigned long *addr)
++{
++	return test_bit(nr, addr);
++}
++
++static inline int linkmode_equal(const unsigned long *src1,
++				 const unsigned long *src2)
++{
++	return bitmap_equal(src1, src2, __ETHTOOL_LINK_MODE_MASK_NBITS);
++}
++
++#endif /* __LINKMODE_H */
+diff --git a/include/linux/mii.h b/include/linux/mii.h
+index 55000ee5c6ad..567047ef0309 100644
+--- a/include/linux/mii.h
++++ b/include/linux/mii.h
+@@ -10,6 +10,7 @@
+ 
+ 
+ #include <linux/if.h>
++#include <linux/linkmode.h>
+ #include <uapi/linux/mii.h>
+ 
+ struct ethtool_cmd;
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index cd6f637cbbfb..81532a61e995 100644
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -19,6 +19,7 @@
+ #include <linux/compiler.h>
+ #include <linux/spinlock.h>
+ #include <linux/ethtool.h>
++#include <linux/linkmode.h>
+ #include <linux/mdio.h>
+ #include <linux/mii.h>
+ #include <linux/module.h>
+-- 
+2.34.1
+
diff --git a/patches/0367-net-hns3-make-function-hclge_set_all_vf_rst-static.patch b/patches/0367-net-hns3-make-function-hclge_set_all_vf_rst-static.patch
new file mode 100644
index 0000000..548f498
--- /dev/null
+++ b/patches/0367-net-hns3-make-function-hclge_set_all_vf_rst-static.patch
@@ -0,0 +1,45 @@
+From 9207408757116d3192c5a1e9e630e1419c81a85c Mon Sep 17 00:00:00 2001
+From: Wei Yongjun <weiyongjun1@huawei.com>
+Date: Sat, 16 Feb 2019 08:15:52 +0000
+Subject: [PATCH 006/283] net: hns3: make function hclge_set_all_vf_rst()
+ static
+
+mainline inclusion
+from mainline-v5.10-rc1
+commit e511f17b1fb40248e63677a6ab81a29b9b32080d
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e511f17b1fb40248e63677a6ab81a29b9b32080d
+
+--------------------------------
+
+Fixes the following sparse warning:
+
+drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c:2431:5: warning:
+ symbol 'hclge_set_all_vf_rst' was not declared. Should it be static?
+
+Fixes: aa5c4f175be6 ("net: hns3: add reset handling for VF when doing PF reset")
+Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 9f9edbdc518a..118e5097b384 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3361,7 +3361,7 @@ static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
+ 	return hclge_cmd_send(&hdev->hw, &desc, 1);
+ }
+ 
+-int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
++static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
+ {
+ 	int i;
+ 
+-- 
+2.34.1
+
diff --git a/patches/0368-net-hns3-return-0-and-print-warning-when-hit-duplica.patch b/patches/0368-net-hns3-return-0-and-print-warning-when-hit-duplica.patch
new file mode 100644
index 0000000..f26d213
--- /dev/null
+++ b/patches/0368-net-hns3-return-0-and-print-warning-when-hit-duplica.patch
@@ -0,0 +1,84 @@
+From 1bd2f0085ef31d7db11f198e41d08f20295b9f01 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Thu, 4 Apr 2019 16:17:51 +0800
+Subject: [PATCH 007/283] net: hns3: return 0 and print warning when hit
+ duplicate MAC
+
+mainline inclusion
+from mainline-v5.2-rc1
+commit 72110b567479f0282489a9b3747e76d8c67d75f5
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=72110b567479f0282489a9b3747e76d8c67d75f5
+
+--------------------------------
+
+When set 2 same MAC to different function of one port, IMP
+will return error as the later one may modify the origin one.
+This will cause bond fail for 2 VFs of one port.
+
+Driver just print warning and return 0 with this patch, so
+if set same MAC address, it will return 0 but do not really
+configure HW.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c    | 10 +++++++++-
+ drivers/scsi/smartpqi/smartpqi_init.c                  |  6 +++---
+ 2 files changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 118e5097b384..3c68cbf19d48 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -7565,7 +7565,7 @@ int hclge_add_uc_addr_common(struct hclge_vport *vport,
+ 	struct hclge_dev *hdev = vport->back;
+ 	struct hclge_mac_vlan_tbl_entry_cmd req;
+ 	u16 egress_port = 0;
+-	int ret;
++	int ret = 0;
+ 
+ 	/* mac addr check */
+ 	if (is_zero_ether_addr(addr) ||
+@@ -7604,6 +7604,14 @@ int hclge_add_uc_addr_common(struct hclge_vport *vport,
+ 		dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
+ 			hdev->priv_umv_size);
+ 
++	/* check if we just hit the duplicate */
++	if (!ret)
++		return -EEXIST;
++
++	dev_err(&hdev->pdev->dev,
++		"PF failed to add unicast entry(%pM) in the MAC table\n",
++		addr);
++
+ 	return -ENOSPC;
+ }
+ 
+diff --git a/drivers/scsi/smartpqi/smartpqi_init.c b/drivers/scsi/smartpqi/smartpqi_init.c
+index d9df5627cfb6..ed046c586724 100644
+--- a/drivers/scsi/smartpqi/smartpqi_init.c
++++ b/drivers/scsi/smartpqi/smartpqi_init.c
+@@ -3374,9 +3374,9 @@ static int pqi_alloc_admin_queues(struct pqi_ctrl_info *ctrl_info)
+ 
+ 	ctrl_info->admin_queue_memory_base =
+ 		dma_zalloc_coherent(&ctrl_info->pci_dev->dev,
+-			alloc_length,
+-			&ctrl_info->admin_queue_memory_base_dma_handle,
+-			GFP_KERNEL);
++				    alloc_length,
++				    &ctrl_info->admin_queue_memory_base_dma_handle,
++				    GFP_KERNEL);
+ 
+ 	if (!ctrl_info->admin_queue_memory_base)
+ 		return -ENOMEM;
+-- 
+2.34.1
+
diff --git a/patches/0369-net-hns3-Use-LLDP-ethertype-define-ETH_P_LLDP.patch b/patches/0369-net-hns3-Use-LLDP-ethertype-define-ETH_P_LLDP.patch
new file mode 100644
index 0000000..cab0886
--- /dev/null
+++ b/patches/0369-net-hns3-Use-LLDP-ethertype-define-ETH_P_LLDP.patch
@@ -0,0 +1,68 @@
+From b95d33965a3e12cf307ea8d33cfef022a110b711 Mon Sep 17 00:00:00 2001
+From: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
+Date: Thu, 11 Apr 2019 09:11:36 -0700
+Subject: [PATCH 008/283] net: hns3: Use LLDP ethertype define ETH_P_LLDP
+
+mainline inclusion
+from mainline-v5.3-rc1
+commit 7efffc64435e51a5fc21baee5988769538aabc63
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7efffc64435e51a5fc21baee5988769538aabc63
+
+--------------------------------
+
+Remove references to HCLGE_MAC_ETHERTYPE_LLDP and use ETH_P_LLDP instead.
+
+Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
+Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
+Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h  | 1 -
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 +-
+ include/uapi/linux/if_ether.h                           | 1 +
+ 3 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 9c49d2760ab5..c57f0ccf624f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -727,7 +727,6 @@ struct hclge_umv_spc_alc_cmd {
+ #define HCLGE_MAC_MGR_MASK_VLAN_B		BIT(0)
+ #define HCLGE_MAC_MGR_MASK_MAC_B		BIT(1)
+ #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B		BIT(2)
+-#define HCLGE_MAC_ETHERTYPE_LLDP		0x88cc
+ 
+ struct hclge_mac_mgr_tbl_entry_cmd {
+ 	u8      flags;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 3c68cbf19d48..e34611e70699 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -323,8 +323,8 @@ static const struct hclge_comm_stats_str g_mac_stats_string[] = {
+ static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
+ 	{
+ 		.flags = HCLGE_MAC_MGR_MASK_VLAN_B,
+-		.ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
+ 		.mac_addr = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e},
++		.ethter_type = cpu_to_le16(ETH_P_LLDP),
+ 		.i_port_bitmap = 0x1,
+ 	},
+ };
+diff --git a/include/uapi/linux/if_ether.h b/include/uapi/linux/if_ether.h
+index 3a45b4ad71a3..0e706a76418c 100644
+--- a/include/uapi/linux/if_ether.h
++++ b/include/uapi/linux/if_ether.h
+@@ -91,6 +91,7 @@
+ #define ETH_P_802_EX1	0x88B5		/* 802.1 Local Experimental 1.  */
+ #define ETH_P_PREAUTH	0x88C7		/* 802.11 Preauthentication */
+ #define ETH_P_TIPC	0x88CA		/* TIPC 			*/
++#define ETH_P_LLDP     0x88CC          /* Link Layer Discovery Protocol */
+ #define ETH_P_MACSEC	0x88E5		/* 802.1ae MACsec */
+ #define ETH_P_8021AH	0x88E7          /* 802.1ah Backbone Service Tag */
+ #define ETH_P_MVRP	0x88F5          /* 802.1Q MVRP                  */
+-- 
+2.34.1
+
diff --git a/patches/0370-net-hns3-fix-compile-warning-without-CONFIG_RFS_ACCE.patch b/patches/0370-net-hns3-fix-compile-warning-without-CONFIG_RFS_ACCE.patch
new file mode 100644
index 0000000..eac4c17
--- /dev/null
+++ b/patches/0370-net-hns3-fix-compile-warning-without-CONFIG_RFS_ACCE.patch
@@ -0,0 +1,53 @@
+From eb53e8ee1acddb28605ba4b2c718ca350f4233df Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Tue, 28 May 2019 17:02:51 +0800
+Subject: [PATCH 009/283] net: hns3: fix compile warning without
+ CONFIG_RFS_ACCEL
+
+mainline inclusion
+from mainline-v5.3-rc1
+commit 4c1522765ca84e45d147557bf7f19e85e40c81e0
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4c1522765ca84e45d147557bf7f19e85e40c81e0
+
+--------------------------------
+
+The ifdef condition of function hclge_add_fd_entry_by_arfs() is
+unnecessary. It may cause compile warning when CONFIG_RFS_ACCEL
+is not chosen. This patch fixes it by removing the ifdef condition.
+
+Fixes: d93ed94fbeaf ("net: hns3: add aRFS support for PF")
+Reported-by: kbuild test robot <lkp@intel.com>
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index e34611e70699..35a08f8b97ed 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -6401,7 +6401,6 @@ static void hclge_fd_build_arfs_rule(const struct hclge_fd_rule_tuples *tuples,
+ static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id,
+ 				      u16 flow_id, struct flow_keys *fkeys)
+ {
+-#ifdef CONFIG_RFS_ACCEL
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_fd_rule_tuples new_tuples;
+ 	struct hclge_dev *hdev = vport->back;
+@@ -6473,7 +6472,6 @@ static int hclge_add_fd_entry_by_arfs(struct hnae3_handle *handle, u16 queue_id,
+ 	}
+ 
+ 	return rule->location;
+-#endif
+ }
+ 
+ static void hclge_rfs_filter_expire(struct hclge_dev *hdev)
+-- 
+2.34.1
+
diff --git a/patches/0371-net-hns3-adjust-hns3_uninit_phy-s-location-in-the-hn.patch b/patches/0371-net-hns3-adjust-hns3_uninit_phy-s-location-in-the-hn.patch
new file mode 100644
index 0000000..07969be
--- /dev/null
+++ b/patches/0371-net-hns3-adjust-hns3_uninit_phy-s-location-in-the-hn.patch
@@ -0,0 +1,81 @@
+From f0fe0a6e0c0030488aacf862fdabbbc93f95e9a5 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Tue, 28 May 2019 17:03:01 +0800
+Subject: [PATCH 010/283] net: hns3: adjust hns3_uninit_phy()'s location in the
+ hns3_client_uninit()
+
+mainline inclusion
+from mainline-v5.3-rc1
+commit 0d2f68c7bcf4c7bbdd6f810f7b6e658f43d4461e
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d2f68c7bcf4c7bbdd6f810f7b6e658f43d4461e
+
+--------------------------------
+
+hns3_uninit_phy() should be called before checking
+HNS3_NIC_STATE_INITED flags, otherwise when this checking fails,
+there is nobody to call hns3_uninit_phy().
+
+Fixes: c8a8045b2d0a ("net: hns3: Fix NULL deref when unloading driver")
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 14 +-------------
+ 1 file changed, 1 insertion(+), 13 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index b184c3e83e05..6c474df3e5c4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -4111,14 +4111,6 @@ static void hns3_uninit_phy(struct net_device *netdev)
+ 		h->ae_algo->ops->mac_disconnect_phy(h);
+ }
+ 
+-static void hns3_del_all_fd_rules(struct net_device *netdev, bool clear_list)
+-{
+-	struct hnae3_handle *h = hns3_get_handle(netdev);
+-
+-	if (h->ae_algo->ops->del_all_fd_entries)
+-		h->ae_algo->ops->del_all_fd_entries(h, clear_list);
+-}
+-
+ static int hns3_client_start(struct hnae3_handle *handle)
+ {
+ 	if (!handle->ae_algo->ops->client_start)
+@@ -4299,7 +4291,6 @@ static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
+ {
+ 	struct net_device *netdev = handle->kinfo.netdev;
+ 	struct hns3_nic_priv *priv = netdev_priv(netdev);
+-	int ret;
+ 
+ 	if (netdev->reg_state != NETREG_UNINITIALIZED)
+ 		unregister_netdev(netdev);
+@@ -4317,7 +4308,6 @@ static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
+ 
+ 	hns3_nic_uninit_irq(priv);
+ 
+-	hns3_del_all_fd_rules(netdev, true);
+ 
+ 	hns3_clear_all_ring(handle, true);
+ 
+@@ -4325,9 +4315,7 @@ static void hns3_client_uninit(struct hnae3_handle *handle, bool reset)
+ 
+ 	hns3_nic_dealloc_vector_data(priv);
+ 
+-	ret = hns3_uninit_all_ring(priv);
+-	if (ret)
+-		netdev_err(netdev, "uninit ring error\n");
++	hns3_uninit_all_ring(priv);
+ 
+ 	hns3_put_ring_config(priv);
+ 
+-- 
+2.34.1
+
diff --git a/patches/0372-net-hns3-remove-unused-macros.patch b/patches/0372-net-hns3-remove-unused-macros.patch
new file mode 100644
index 0000000..c478b72
--- /dev/null
+++ b/patches/0372-net-hns3-remove-unused-macros.patch
@@ -0,0 +1,42 @@
+From 6e95de54372965e1b91ff655a93c91ac2e94de29 Mon Sep 17 00:00:00 2001
+From: Colin Ian King <colin.king@canonical.com>
+Date: Sun, 3 Nov 2019 13:15:38 +0000
+Subject: [PATCH 011/283] net: hns3: remove unused macros
+
+mainline inclusion
+from mainline-v5.5-rc1
+commit a5ec65169c6000bb525b45cb5615dd98356dbf73
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a5ec65169c6000bb525b45cb5615dd98356dbf73
+
+--------------------------------
+
+The macros HCLGE_MPF_ENBALE and HCLGEVF_MPF_ENBALE are defined but never
+used.  I was going to fix the spelling mistake "ENBALE" -> "ENABLE" but
+found these macros are not used, so they can be removed.
+
+Signed-off-by: Colin Ian King <colin.king@canonical.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 2a84772783ef..7c1bbe626b17 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -235,8 +235,6 @@ enum hclge_evt_cause {
+ 	HCLGE_VECTOR0_EVENT_OTHER,
+ };
+ 
+-#define HCLGE_MPF_ENBALE 1
+-
+ enum HCLGE_MAC_SPEED {
+ 	HCLGE_MAC_SPEED_UNKNOWN = 0,		/* unknown */
+ 	HCLGE_MAC_SPEED_10M	= 10,		/* 10 Mbps */
+-- 
+2.34.1
+
diff --git a/patches/0373-net-hns3-modify-an-unsuitable-log-in-hclge_map_ring_.patch b/patches/0373-net-hns3-modify-an-unsuitable-log-in-hclge_map_ring_.patch
new file mode 100644
index 0000000..8ac68cf
--- /dev/null
+++ b/patches/0373-net-hns3-modify-an-unsuitable-log-in-hclge_map_ring_.patch
@@ -0,0 +1,46 @@
+From 74a9e760c255fdfc577b7d5020b88d91628ce178 Mon Sep 17 00:00:00 2001
+From: Yonglong Liu <liuyonglong@huawei.com>
+Date: Sat, 4 Jan 2020 10:49:27 +0800
+Subject: [PATCH 012/283] net: hns3: modify an unsuitable log in
+ hclge_map_ring_to_vector()
+
+mainline inclusion
+from mainline-v5.6-rc1
+commit 7ab2b53e4657ee0289878b09f9748a35b0e6010b
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7ab2b53e4657ee0289878b09f9748a35b0e6010b
+
+--------------------------------
+
+When the returned vector_id less than 0, the message should print
+out the vector who is getting vector index fail.
+
+So this patch replaces vector_id with vector, and re-format the
+message.
+
+Signed-off-by: Yonglong Liu <liuyonglong@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 35a08f8b97ed..7b60829d8bba 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -4791,7 +4791,7 @@ static int hclge_map_ring_to_vector(struct hnae3_handle *handle, int vector,
+ 	vector_id = hclge_get_vector_index(hdev, vector);
+ 	if (vector_id < 0) {
+ 		dev_err(&hdev->pdev->dev,
+-			"Get vector index fail. vector_id =%d\n", vector_id);
++			"failed to get vector index. vector=%d\n", vector);
+ 		return vector_id;
+ 	}
+ 
+-- 
+2.34.1
+
diff --git a/patches/0374-net-hns3-reject-unsupported-coalescing-params.patch b/patches/0374-net-hns3-reject-unsupported-coalescing-params.patch
new file mode 100644
index 0000000..f594915
--- /dev/null
+++ b/patches/0374-net-hns3-reject-unsupported-coalescing-params.patch
@@ -0,0 +1,138 @@
+From 9c0ab6c6b497b9f9c37c1f9ab3da570122d47151 Mon Sep 17 00:00:00 2001
+From: Jakub Kicinski <kuba@kernel.org>
+Date: Wed, 11 Mar 2020 15:32:53 -0700
+Subject: [PATCH 013/283] net: hns3: reject unsupported coalescing params
+
+mainline inclusion
+from mainline-v5.7-rc1
+commit 7b8fda64b29d433712575c99eb97545899667d06
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7b8fda64b29d433712575c99eb97545899667d06
+
+--------------------------------
+
+Set ethtool_ops->supported_coalesce_params to let
+the core reject unsupported coalescing parameters.
+
+This driver did not previously reject unsupported parameters.
+
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+---
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  7 +++
+ include/linux/ethtool.h                       | 44 +++++++++++++++++--
+ 2 files changed, 48 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index d18e8141f7e4..cfd35b5f14b7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1483,7 +1483,13 @@ static int hns3_get_module_eeprom(struct net_device *netdev,
+ 	return ops->get_module_eeprom(handle, ee->offset, ee->len, data);
+ }
+ 
++#define HNS3_ETHTOOL_COALESCE	(ETHTOOL_COALESCE_USECS |		\
++				 ETHTOOL_COALESCE_USE_ADAPTIVE |	\
++				 ETHTOOL_COALESCE_RX_USECS_HIGH |	\
++				 ETHTOOL_COALESCE_TX_USECS_HIGH)
++
+ static const struct ethtool_ops hns3vf_ethtool_ops = {
++	.supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
+ 	.get_drvinfo = hns3_get_drvinfo,
+ 	.get_ringparam = hns3_get_ringparam,
+ 	.set_ringparam = hns3_set_ringparam,
+@@ -1509,6 +1515,7 @@ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ };
+ 
+ static const struct ethtool_ops hns3_ethtool_ops = {
++	.supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
+ 	.self_test = hns3_self_test,
+ 	.get_drvinfo = hns3_get_drvinfo,
+ 	.get_link = hns3_get_link,
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 3e398b8ac212..217f56d2462c 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -182,8 +182,43 @@ void ethtool_convert_legacy_u32_to_link_mode(unsigned long *dst,
+ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+ 				     const unsigned long *src);
+ 
++#define ETHTOOL_COALESCE_RX_USECS              BIT(0)
++#define ETHTOOL_COALESCE_RX_MAX_FRAMES         BIT(1)
++#define ETHTOOL_COALESCE_RX_USECS_IRQ          BIT(2)
++#define ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ     BIT(3)
++#define ETHTOOL_COALESCE_TX_USECS              BIT(4)
++#define ETHTOOL_COALESCE_TX_MAX_FRAMES         BIT(5)
++#define ETHTOOL_COALESCE_TX_USECS_IRQ          BIT(6)
++#define ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ     BIT(7)
++#define ETHTOOL_COALESCE_STATS_BLOCK_USECS     BIT(8)
++#define ETHTOOL_COALESCE_USE_ADAPTIVE_RX       BIT(9)
++#define ETHTOOL_COALESCE_USE_ADAPTIVE_TX       BIT(10)
++#define ETHTOOL_COALESCE_PKT_RATE_LOW          BIT(11)
++#define ETHTOOL_COALESCE_RX_USECS_LOW          BIT(12)
++#define ETHTOOL_COALESCE_RX_MAX_FRAMES_LOW     BIT(13)
++#define ETHTOOL_COALESCE_TX_USECS_LOW          BIT(14)
++#define ETHTOOL_COALESCE_TX_MAX_FRAMES_LOW     BIT(15)
++#define ETHTOOL_COALESCE_PKT_RATE_HIGH         BIT(16)
++#define ETHTOOL_COALESCE_RX_USECS_HIGH         BIT(17)
++#define ETHTOOL_COALESCE_RX_MAX_FRAMES_HIGH    BIT(18)
++#define ETHTOOL_COALESCE_TX_USECS_HIGH         BIT(19)
++#define ETHTOOL_COALESCE_TX_MAX_FRAMES_HIGH    BIT(20)
++#define ETHTOOL_COALESCE_RATE_SAMPLE_INTERVAL  BIT(21)
++
++#define ETHTOOL_COALESCE_USECS						\
++	(ETHTOOL_COALESCE_RX_USECS | ETHTOOL_COALESCE_TX_USECS)
++#define ETHTOOL_COALESCE_MAX_FRAMES					\
++	(ETHTOOL_COALESCE_RX_MAX_FRAMES | ETHTOOL_COALESCE_TX_MAX_FRAMES)
++#define ETHTOOL_COALESCE_USECS_IRQ					\
++	(ETHTOOL_COALESCE_RX_USECS_IRQ | ETHTOOL_COALESCE_TX_USECS_IRQ)
++#define ETHTOOL_COALESCE_MAX_FRAMES_IRQ					\
++	(ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ |				\
++	ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ)
++#define ETHTOOL_COALESCE_USE_ADAPTIVE					\
++	(ETHTOOL_COALESCE_USE_ADAPTIVE_RX | ETHTOOL_COALESCE_USE_ADAPTIVE_TX)
+ /**
+  * struct ethtool_ops - optional netdev operations
++ * @supported_coalesce_params: supported types of interrupt coalescing.
+  * @get_settings: DEPRECATED, use %get_link_ksettings/%set_link_ksettings
+  *	API. Get various device settings including Ethernet link
+  *	settings. The @cmd parameter is expected to have been cleared
+@@ -220,8 +255,9 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+  *	or zero.
+  * @get_coalesce: Get interrupt coalescing parameters.  Returns a negative
+  *	error code or zero.
+- * @set_coalesce: Set interrupt coalescing parameters.  Returns a negative
+- *	error code or zero.
++ * @set_coalesce: Set interrupt coalescing parameters.  Supported coalescing
++ *     types should be set in @supported_coalesce_params.
++ *     Returns a negative error code or zero.
+  * @get_ringparam: Report ring sizes
+  * @set_ringparam: Set ring sizes.  Returns a negative error code or zero.
+  * @get_pauseparam: Report pause parameters
+@@ -291,7 +327,8 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+  * @get_per_queue_coalesce: Get interrupt coalescing parameters per queue.
+  *	It must check that the given queue number is valid. If neither a RX nor
+  *	a TX queue has this number, return -EINVAL. If only a RX queue or a TX
+- *	queue has this number, set the inapplicable fields to ~0 and return 0.
++ *     queue has this number, ignore the inapplicable fields. Supported
++ *     coalescing types should be set in @supported_coalesce_params.
+  *	Returns a negative error code or zero.
+  * @set_per_queue_coalesce: Set interrupt coalescing parameters per queue.
+  *	It must check that the given queue number is valid. If neither a RX nor
+@@ -330,6 +367,7 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+  * of the generic netdev features interface.
+  */
+ struct ethtool_ops {
++	u32     supported_coalesce_params;
+ 	int	(*get_settings)(struct net_device *, struct ethtool_cmd *);
+ 	int	(*set_settings)(struct net_device *, struct ethtool_cmd *);
+ 	void	(*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);
+-- 
+2.34.1
+
diff --git a/patches/0375-net-hns3-clear-port-base-VLAN-when-unload-PF.patch b/patches/0375-net-hns3-clear-port-base-VLAN-when-unload-PF.patch
new file mode 100644
index 0000000..1f64a64
--- /dev/null
+++ b/patches/0375-net-hns3-clear-port-base-VLAN-when-unload-PF.patch
@@ -0,0 +1,72 @@
+From c0087473b7918d790771c873f0e63afb381ad5c2 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Thu, 12 Mar 2020 15:11:06 +0800
+Subject: [PATCH 014/283] net: hns3: clear port base VLAN when unload PF
+
+mainline inclusion
+from mainline-v5.6-rc1
+commit 59359fc8a2f7af062777692e6a7aae73483729ec
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=59359fc8a2f7af062777692e6a7aae73483729ec
+
+--------------------------------
+
+Currently, PF missed to clear the port base VLAN for VF when
+unload. In this case, the VLAN id will remain in the VLAN
+table. This patch fixes it.
+
+Fixes: 92f11ea177cd ("net: hns3: fix set port based VLAN issue for VF")
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 23 +++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 7b60829d8bba..fa19e8514710 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -9307,6 +9307,28 @@ static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
+ 	return 0;
+ }
+ 
++static void hclge_clear_vf_vlan(struct hclge_dev *hdev)
++{
++	struct hclge_vlan_info *vlan_info;
++	struct hclge_vport *vport;
++	int ret;
++	int vf;
++
++	/* clear port base vlan for all vf */
++	for (vf = HCLGE_VF_VPORT_START_NUM; vf < hdev->num_alloc_vport; vf++) {
++		vport = &hdev->vport[vf];
++		vlan_info = &vport->port_base_vlan_cfg.vlan_info;
++
++		ret = hclge_set_vlan_filter_hw(hdev, htons(ETH_P_8021Q),
++					       vport->vport_id,
++					       vlan_info->vlan_tag, true);
++		if (ret)
++			dev_err(&hdev->pdev->dev,
++				"failed to clear vf vlan for vf%d, ret = %d\n",
++				vf - HCLGE_VF_VPORT_START_NUM, ret);
++	}
++}
++
+ int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
+ 			  u16 vlan_id, bool is_kill)
+ {
+@@ -10843,6 +10865,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	struct hclge_mac *mac = &hdev->hw.mac;
+ 
+ 	hclge_reset_vf_rate(hdev);
++	hclge_clear_vf_vlan(hdev);
+ 	hclge_misc_affinity_teardown(hdev);
+ 	hclge_state_uninit(hdev);
+ 	hclge_uninit_vport_mac_table(hdev);
+-- 
+2.34.1
+
diff --git a/patches/0376-net-hns-Remove-custom-driver-version-in-favour-of-gl.patch b/patches/0376-net-hns-Remove-custom-driver-version-in-favour-of-gl.patch
new file mode 100644
index 0000000..db78772
--- /dev/null
+++ b/patches/0376-net-hns-Remove-custom-driver-version-in-favour-of-gl.patch
@@ -0,0 +1,128 @@
+From db462fe92a37cfabd1fe29f9f0f4e46dd8fb7130 Mon Sep 17 00:00:00 2001
+From: Leon Romanovsky <leonro@mellanox.com>
+Date: Sun, 19 Apr 2020 17:18:48 +0300
+Subject: [PATCH 015/283] net/hns: Remove custom driver version in favour of
+ global one
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit cad99e506887e257ce8bce826ec25f7854b7e69a
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cad99e506887e257ce8bce826ec25f7854b7e69a
+
+--------------------------------
+
+Use globally defined kernel version instead of custom driver variant.
+
+Reported-by: Borislav Petkov <bp@suse.de>
+Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c           | 7 ++-----
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h           | 4 ----
+ drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c        | 4 ----
+ .../ethernet/hisilicon/hns3/hns3_extension/hns3_enet_it.c | 8 +++-----
+ 4 files changed, 5 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 6c474df3e5c4..384ee4606051 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -14,7 +14,6 @@
+ #include <linux/aer.h>
+ #include <linux/skbuff.h>
+ #include <linux/sctp.h>
+-#include <linux/vermagic.h>
+ #include <net/gre.h>
+ #include <net/ip6_checksum.h>
+ #include <net/pkt_cls.h>
+@@ -43,9 +42,8 @@
+ 
+ static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
+ 
+-const char hns3_driver_name[] = "hns3";
+-char hns3_driver_version[] = VERMAGIC_STRING;
+-const char hns3_driver_string[] =
++static const char hns3_driver_name[] = "hns3";
++static const char hns3_driver_string[] =
+ 			"Hisilicon Ethernet Network Driver for Hip08 Family";
+ const char hns3_copyright[] = "Copyright (c) 2017 Huawei Corporation.";
+ struct hnae3_client client;
+@@ -4847,4 +4845,3 @@ MODULE_DESCRIPTION("HNS3: Hisilicon Ethernet Driver");
+ MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
+ MODULE_LICENSE("GPL");
+ MODULE_ALIAS("pci:hns-nic");
+-MODULE_VERSION(HNS3_MOD_VERSION);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 19f83dfb32aa..ac1659c18b16 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -8,10 +8,6 @@
+ 
+ #include "hnae3.h"
+ 
+-#define HNS3_MOD_VERSION "23.7.1"
+-
+-extern char hns3_driver_version[];
+-
+ enum hns3_nic_state {
+ 	HNS3_NIC_STATE_TESTING,
+ 	HNS3_NIC_STATE_RESETTING,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index cfd35b5f14b7..11480bb99055 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -562,10 +562,6 @@ static void hns3_get_drvinfo(struct net_device *netdev,
+ 		return;
+ 	}
+ 
+-	strncpy(drvinfo->version, hns3_driver_version,
+-		sizeof(drvinfo->version));
+-	drvinfo->version[sizeof(drvinfo->version) - 1] = '\0';
+-
+ 	strncpy(drvinfo->driver, h->pdev->driver->name,
+ 		sizeof(drvinfo->driver));
+ 	drvinfo->driver[sizeof(drvinfo->driver) - 1] = '\0';
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3_enet_it.c b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3_enet_it.c
+index a6a724da0548..9a4ac499fbb2 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3_enet_it.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3_enet_it.c
+@@ -12,7 +12,6 @@
+ #include "hns3_enet_it.h"
+ #include "hns3_enet.h"
+ 
+-extern const char hns3_driver_string[];
+ extern const char hns3_copyright[];
+ 
+ #ifdef CONFIG_IT_VALIDATION
+@@ -21,7 +20,9 @@ extern struct net_device_ops hns3_nic_netdev_ops;
+ extern const struct hnae3_client_ops client_ops;
+ extern struct hnae3_client client;
+ extern struct pci_driver hns3_driver;
+-extern const char hns3_driver_name[];
++static const char hns3_driver_name[] = "hns3";
++static const char hns3_driver_string[] =
++			"Hisilicon Ethernet Network Driver for Hip08 Family";
+ 
+ #if (KERNEL_VERSION(4, 19, 0) > LINUX_VERSION_CODE)
+ u16 hns3_nic_select_queue_it(struct net_device *ndev, struct sk_buff *skb,
+@@ -51,9 +52,6 @@ static int __init hns3_init_module_it(void)
+ 	pr_info("%s: %s - version\n", hns3_driver_name, hns3_driver_string);
+ 	pr_info("%s: %s\n", hns3_driver_name, hns3_copyright);
+ 
+-	strncpy(hns3_driver_version, HNS3_MOD_VERSION,
+-		strlen(hns3_driver_version));
+-
+ 	client.type = HNAE3_CLIENT_KNIC;
+ 	snprintf(client.name, HNAE3_CLIENT_NAME_LENGTH, "%s", hns3_driver_name);
+ 
+-- 
+2.34.1
+
diff --git a/patches/0377-net-hns3-remove-a-redundant-register-macro-definitio.patch b/patches/0377-net-hns3-remove-a-redundant-register-macro-definitio.patch
new file mode 100644
index 0000000..40155d2
--- /dev/null
+++ b/patches/0377-net-hns3-remove-a-redundant-register-macro-definitio.patch
@@ -0,0 +1,95 @@
+From 9c269c2d725496997391d87a01f5fc11c05c441d Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 9 May 2020 17:27:37 +0800
+Subject: [PATCH 016/283] net: hns3: remove a redundant register macro
+ definition
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 5705b45155c404a1eb2ccc92e95851cfa21d4f37
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5705b45155c404a1eb2ccc92e95851cfa21d4f37
+
+--------------------------------
+
+HCLGE_MISC_VECTOR_INT_STS and HCLGE_VECTOR_PF_OTHER_INT_STS_REG
+both represent the misc interrupt status register(0x20800), so
+removes HCLGE_VECTOR_PF_OTHER_INT_STS_REG and replaces it with
+HCLGE_MISC_VECTOR_INT_STS.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h  |  1 -
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 13 +++++--------
+ 2 files changed, 5 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+index 67e972a25f47..fcaf4f472379 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+@@ -19,7 +19,6 @@
+ #define HCLGE_RAS_REG_NFE_MASK   0xFF00
+ #define HCLGE_RAS_REG_ROCEE_ERR_MASK   0x3000000
+ 
+-#define HCLGE_VECTOR0_PF_OTHER_INT_STS_REG   0x20800
+ #define HCLGE_VECTOR0_REG_MSIX_MASK   0x1FF00
+ 
+ #define HCLGE_IMP_TCM_ECC_ERR_INT_EN	0xFFFF0000
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index fa19e8514710..b405a9d7f365 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3039,13 +3039,11 @@ static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
+ 
+ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
+ {
+-	u32 rst_src_reg, cmdq_src_reg, msix_src_reg;
++	u32 cmdq_src_reg, msix_src_reg;
+ 
+ 	/* fetch the events from their corresponding regs */
+-	rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
+ 	cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
+-	msix_src_reg = hclge_read_dev(&hdev->hw,
+-				      HCLGE_VECTOR0_PF_OTHER_INT_STS_REG);
++	msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
+ 
+ 	/* Assumption: If by any chance reset and mailbox events are reported
+ 	 * together then we will only process reset event in this go and will
+@@ -3055,7 +3053,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
+ 	 *
+ 	 * check for vector0 reset event sources
+ 	 */
+-	if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
++	if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
+ 		dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
+ 		set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
+ 		set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
+@@ -3064,7 +3062,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
+ 		return HCLGE_VECTOR0_EVENT_RST;
+ 	}
+ 
+-	if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
++	if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
+ 		dev_info(&hdev->pdev->dev, "global reset interrupt\n");
+ 		set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
+ 		set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
+@@ -3998,8 +3996,7 @@ static void hclge_misc_err_recovery(struct hclge_dev *hdev)
+ 	struct device *dev = &hdev->pdev->dev;
+ 	u32 msix_sts_reg;
+ 
+-	msix_sts_reg = hclge_read_dev(&hdev->hw,
+-				      HCLGE_VECTOR0_PF_OTHER_INT_STS_REG);
++	msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
+ 
+ 	if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) {
+ 		if (hclge_handle_hw_msix_error(hdev,
+-- 
+2.34.1
+
diff --git a/patches/0378-net-hns3-modify-two-uncorrect-macro-names.patch b/patches/0378-net-hns3-modify-two-uncorrect-macro-names.patch
new file mode 100644
index 0000000..b3d6425
--- /dev/null
+++ b/patches/0378-net-hns3-modify-two-uncorrect-macro-names.patch
@@ -0,0 +1,70 @@
+From 8bfab91ccbe8979e74fd89575d4bb468f1b8ed53 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 9 May 2020 17:27:38 +0800
+Subject: [PATCH 017/283] net: hns3: modify two uncorrect macro names
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 4279b4d5ec9c58f63fde23b2d86de4a1e494dc06
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4279b4d5ec9c58f63fde23b2d86de4a1e494dc06
+
+--------------------------------
+
+According to the UM, command 0x0B03 and 0x0B13 are used to
+query the statistics about TX and RX, not the status, so
+modifies the unsuitable macro name of these two command.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h  | 4 ++--
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index c57f0ccf624f..013292889601 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -187,11 +187,11 @@ enum hclge_opcode_type {
+ 	/* TQP commands */
+ 	HCLGE_OPC_CFG_TX_QUEUE		= 0x0B01,
+ 	HCLGE_OPC_QUERY_TX_POINTER	= 0x0B02,
+-	HCLGE_OPC_QUERY_TX_STATUS	= 0x0B03,
++	HCLGE_OPC_QUERY_TX_STATS	= 0x0B03,
+ 	HCLGE_OPC_TQP_TX_QUEUE_TC	= 0x0B04,
+ 	HCLGE_OPC_CFG_RX_QUEUE		= 0x0B11,
+ 	HCLGE_OPC_QUERY_RX_POINTER	= 0x0B12,
+-	HCLGE_OPC_QUERY_RX_STATUS	= 0x0B13,
++	HCLGE_OPC_QUERY_RX_STATS	= 0x0B13,
+ 	HCLGE_OPC_STASH_RX_QUEUE_LRO	= 0x0B16,
+ 	HCLGE_OPC_CFG_RX_QUEUE_LRO	= 0x0B17,
+ 	HCLGE_OPC_CFG_COM_TQP_QUEUE	= 0x0B20,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index b405a9d7f365..57a8cb114e28 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -552,7 +552,7 @@ static int hclge_tqps_update_stats(struct hnae3_handle *handle)
+ 		queue = handle->kinfo.tqp[i];
+ 		tqp = container_of(queue, struct hclge_tqp, q);
+ 		/* command : HCLGE_OPC_QUERY_IGU_STAT */
+-		hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_RX_STATUS,
++		hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_RX_STATS,
+ 					   true);
+ 
+ 		desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
+@@ -572,7 +572,7 @@ static int hclge_tqps_update_stats(struct hnae3_handle *handle)
+ 		tqp = container_of(queue, struct hclge_tqp, q);
+ 		/* command : HCLGE_OPC_QUERY_IGU_STAT */
+ 		hclge_cmd_setup_basic_desc(&desc[0],
+-					   HCLGE_OPC_QUERY_TX_STATUS,
++					   HCLGE_OPC_QUERY_TX_STATS,
+ 					   true);
+ 
+ 		desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
+-- 
+2.34.1
+
diff --git a/patches/0379-net-hns3-remove-a-duplicated-printing-in-hclge_confi.patch b/patches/0379-net-hns3-remove-a-duplicated-printing-in-hclge_confi.patch
new file mode 100644
index 0000000..8b5fad9
--- /dev/null
+++ b/patches/0379-net-hns3-remove-a-duplicated-printing-in-hclge_confi.patch
@@ -0,0 +1,46 @@
+From 5b602038a70319bf26e3b7b75eedfa05cd47dbc6 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 14 May 2020 20:41:23 +0800
+Subject: [PATCH 018/283] net: hns3: remove a duplicated printing in
+ hclge_configure()
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 727f514bd677420d4253ad84509710040e808899
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=727f514bd677420d4253ad84509710040e808899
+
+--------------------------------
+
+Since hclge_get_cfg() already has error print, so hclge_configure()
+should not print error when calling hclge_get_cfg() fail.
+
+Reported-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 57a8cb114e28..14c7ef0fe807 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1395,10 +1395,8 @@ static int hclge_configure(struct hclge_dev *hdev)
+ 	int node, ret;
+ 
+ 	ret = hclge_get_cfg(hdev, &cfg);
+-	if (ret) {
+-		dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
++	if (ret)
+ 		return ret;
+-	}
+ 
+ 	hdev->num_vmdq_vport = cfg.vmdq_vport_num;
+ 	hdev->base_tqp_pid = 0;
+-- 
+2.34.1
+
diff --git a/patches/0380-net-hns3-refactor-hclge_config_tso.patch b/patches/0380-net-hns3-refactor-hclge_config_tso.patch
new file mode 100644
index 0000000..d2d879b
--- /dev/null
+++ b/patches/0380-net-hns3-refactor-hclge_config_tso.patch
@@ -0,0 +1,65 @@
+From 2cf7b0ff6f0f960fbccfc32ead53d4362baa85a0 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 28 May 2020 21:48:10 +0800
+Subject: [PATCH 019/283] net: hns3: refactor hclge_config_tso()
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 9f5a9816065f92683fd5f23cd8ec98719f20144f
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9f5a9816065f92683fd5f23cd8ec98719f20144f
+
+--------------------------------
+
+Since parameters 'tso_mss_min' and 'tso_mss_max' only indicate
+the minimum and maximum MSS, the hnae3_set_field() calls are
+meaningless, remove them and change the type of these two
+parameters to u16.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 17 ++++-------------
+ 1 file changed, 4 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 14c7ef0fe807..cc2be3366409 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1466,26 +1466,17 @@ static int hclge_configure(struct hclge_dev *hdev)
+ 	return ret;
+ }
+ 
+-static int hclge_config_tso(struct hclge_dev *hdev, unsigned int tso_mss_min,
+-			    unsigned int tso_mss_max)
++static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min,
++			    u16 tso_mss_max)
+ {
+ 	struct hclge_cfg_tso_status_cmd *req;
+ 	struct hclge_desc desc;
+-	u16 tso_mss;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
+ 
+ 	req = (struct hclge_cfg_tso_status_cmd *)desc.data;
+-
+-	tso_mss = 0;
+-	hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
+-			HCLGE_TSO_MSS_MIN_S, tso_mss_min);
+-	req->tso_mss_min = cpu_to_le16(tso_mss);
+-
+-	tso_mss = 0;
+-	hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
+-			HCLGE_TSO_MSS_MIN_S, tso_mss_max);
+-	req->tso_mss_max = cpu_to_le16(tso_mss);
++	req->tso_mss_min = cpu_to_le16(tso_mss_min);
++	req->tso_mss_max = cpu_to_le16(tso_mss_max);
+ 
+ 	return hclge_cmd_send(&hdev->hw, &desc, 1);
+ }
+-- 
+2.34.1
+
diff --git a/patches/0381-net-hns3-refactor-hclge_query_bd_num_cmd_send.patch b/patches/0381-net-hns3-refactor-hclge_query_bd_num_cmd_send.patch
new file mode 100644
index 0000000..c549b77
--- /dev/null
+++ b/patches/0381-net-hns3-refactor-hclge_query_bd_num_cmd_send.patch
@@ -0,0 +1,61 @@
+From 3b5b110024e122cc3578d8b5e3a581cee79175ab Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 28 May 2020 21:48:11 +0800
+Subject: [PATCH 020/283] net: hns3: refactor hclge_query_bd_num_cmd_send()
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 5caa039f320d023fb2a40c8c7ededfca3ce85501
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5caa039f320d023fb2a40c8c7ededfca3ce85501
+
+--------------------------------
+
+In order to improve code maintainability and readability, rewrite
+the process of BDs' initialization in hclge_query_bd_num_cmd_send().
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 21 +++++++++++--------
+ 1 file changed, 12 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index cc2be3366409..65af9a80f17e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -11115,16 +11115,19 @@ static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
+ 
+ int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc)
+ {
+-	/*prepare 4 commands to query DFX BD number*/
+-	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_DFX_BD_NUM, true);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
+-	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_DFX_BD_NUM, true);
+-	desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
+-	hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_DFX_BD_NUM, true);
+-	desc[2].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
+-	hclge_cmd_setup_basic_desc(&desc[3], HCLGE_OPC_DFX_BD_NUM, true);
++	int i;
++
++	/* initialize command BD except the last one */
++	for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) {
++		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM,
++					   true);
++		desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	}
++
++	/* initialize the last command BD */
++	hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM, true);
+ 
+-	return hclge_cmd_send(&hdev->hw, desc, 4);
++	return hclge_cmd_send(&hdev->hw, desc, HCLGE_GET_DFX_REG_TYPE_CNT);
+ }
+ 
+ static int hclge_get_dfx_reg_bd_num(struct hclge_dev *hdev,
+-- 
+2.34.1
+
diff --git a/patches/0382-net-hns3-modify-an-incorrect-type-in-struct-hclge_cf.patch b/patches/0382-net-hns3-modify-an-incorrect-type-in-struct-hclge_cf.patch
new file mode 100644
index 0000000..99b6ae3
--- /dev/null
+++ b/patches/0382-net-hns3-modify-an-incorrect-type-in-struct-hclge_cf.patch
@@ -0,0 +1,59 @@
+From 235e2439919790fe01c2faad087fc9a4460bf080 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 28 May 2020 21:48:12 +0800
+Subject: [PATCH 021/283] net: hns3: modify an incorrect type in struct
+ hclge_cfg_gro_status_cmd
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 639d84d0c4281e6d8814bb2cc230bfe7ccf5019d
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=639d84d0c4281e6d8814bb2cc230bfe7ccf5019d
+
+--------------------------------
+
+Modify field .gro_en in struct hclge_cfg_gro_status_cmd to u8
+according to the UM, otherwise, it will overwrite the reserved
+byte which may be used for other purpose.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h  | 4 ++--
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 +-
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 013292889601..aacb75eb8ea8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -918,8 +918,8 @@ struct hclge_cfg_tso_status_cmd {
+ 
+ #define HCLGE_GRO_EN_B		0
+ struct hclge_cfg_gro_status_cmd {
+-	__le16 gro_en;
+-	u8 rsv[22];
++	u8 gro_en;
++	u8 rsv[23];
+ };
+ 
+ #define HCLGE_TSO_MSS_MIN	256
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 65af9a80f17e..e0ab39ae5c91 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1493,7 +1493,7 @@ static int hclge_config_gro(struct hclge_dev *hdev, bool en)
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
+ 	req = (struct hclge_cfg_gro_status_cmd *)desc.data;
+ 
+-	req->gro_en = cpu_to_le16(en ? 1 : 0);
++	req->gro_en = en ? 1 : 0;
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret)
+-- 
+2.34.1
+
diff --git a/patches/0383-net-hns3-modify-an-incorrect-type-in-struct-hclgevf_.patch b/patches/0383-net-hns3-modify-an-incorrect-type-in-struct-hclgevf_.patch
new file mode 100644
index 0000000..9f574d4
--- /dev/null
+++ b/patches/0383-net-hns3-modify-an-incorrect-type-in-struct-hclgevf_.patch
@@ -0,0 +1,59 @@
+From 9d2581a53f40fb8e2b932e234b6be0d33efc4845 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 28 May 2020 21:48:13 +0800
+Subject: [PATCH 022/283] net: hns3: modify an incorrect type in struct
+ hclgevf_cfg_gro_status_cmd
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit fb9e44d63dc33b455a50b772a37faf43e793da91
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fb9e44d63dc33b455a50b772a37faf43e793da91
+
+--------------------------------
+
+Modify field .gro_en in struct hclgevf_cfg_gro_status_cmd to u8
+according to the UM, otherwise, it will overwrite the reserved
+byte which may be used for other purpose.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h  | 4 ++--
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 2 +-
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index c87ec29f4f38..69ddfad488a5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -162,8 +162,8 @@ struct hclgevf_query_res_cmd {
+ 
+ #define HCLGEVF_GRO_EN_B               0
+ struct hclgevf_cfg_gro_status_cmd {
+-	__le16 gro_en;
+-	u8 rsv[22];
++	u8 gro_en;
++	u8 rsv[23];
+ };
+ 
+ #define HCLGEVF_RSS_DEFAULT_OUTPORT_B	4
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index ebe09a304aed..35a2f0415ef5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -2488,7 +2488,7 @@ static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en)
+ 				     false);
+ 	req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
+ 
+-	req->gro_en = cpu_to_le16(en ? 1 : 0);
++	req->gro_en = en ? 1 : 0;
+ 
+ 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret)
+-- 
+2.34.1
+
diff --git a/patches/0384-net-hns3-remove-some-unused-fields-in-struct-hns3_ni.patch b/patches/0384-net-hns3-remove-some-unused-fields-in-struct-hns3_ni.patch
new file mode 100644
index 0000000..fa206cf
--- /dev/null
+++ b/patches/0384-net-hns3-remove-some-unused-fields-in-struct-hns3_ni.patch
@@ -0,0 +1,76 @@
+From 33c240aba8e2f8b7e8f7bba2e60739d3dcf942cd Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 28 May 2020 21:48:14 +0800
+Subject: [PATCH 023/283] net: hns3: remove some unused fields in struct
+ hns3_nic_priv
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 5e86178dcead4941fcdadc963f31ed4e859e58ce
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5e86178dcead4941fcdadc963f31ed4e859e58ce
+
+--------------------------------
+
+Remove some fileds which defined in struct hns3_nic_priv,
+but not used, and remove the related definition of struct
+hns3_udp_tunnel and enum hns3_udp_tnl_type.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   | 22 -------------------
+ 1 file changed, 22 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index ac1659c18b16..7f19a8b82036 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -493,21 +493,8 @@ struct hns3_enet_tqp_vector {
+ 	unsigned long last_jiffies;
+ } ____cacheline_internodealigned_in_smp;
+ 
+-enum hns3_udp_tnl_type {
+-	HNS3_UDP_TNL_VXLAN,
+-	HNS3_UDP_TNL_GENEVE,
+-	HNS3_UDP_TNL_MAX,
+-};
+-
+-struct hns3_udp_tunnel {
+-	u16 dst_port;
+-	int used;
+-};
+-
+ struct hns3_nic_priv {
+ 	struct hnae3_handle *ae_handle;
+-	u32 enet_ver;
+-	u32 port_id;
+ 	struct net_device *netdev;
+ 	struct device *dev;
+ 
+@@ -519,19 +506,10 @@ struct hns3_nic_priv {
+ 	struct hns3_enet_tqp_vector *tqp_vector;
+ 	u16 vector_num;
+ 
+-	/* The most recently read link state */
+-	int link;
+ 	u64 tx_timeout_count;
+ 
+ 	unsigned long state;
+ 
+-	struct timer_list service_timer;
+-
+-	struct work_struct service_task;
+-
+-	struct notifier_block notifier_block;
+-	/* Vxlan/Geneve information */
+-	struct hns3_udp_tunnel udp_tnl[HNS3_UDP_TNL_MAX];
+ 	struct hns3_enet_coalesce tx_coal;
+ 	struct hns3_enet_coalesce rx_coal;
+ };
+-- 
+2.34.1
+
diff --git a/patches/0385-net-hns3-remove-unused-struct-hnae3_unic_private_inf.patch b/patches/0385-net-hns3-remove-unused-struct-hnae3_unic_private_inf.patch
new file mode 100644
index 0000000..6af6a69
--- /dev/null
+++ b/patches/0385-net-hns3-remove-unused-struct-hnae3_unic_private_inf.patch
@@ -0,0 +1,58 @@
+From eadef93b6f79f1abad6d60d4bd8328a111ce7396 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 28 May 2020 21:48:16 +0800
+Subject: [PATCH 024/283] net: hns3: remove unused struct
+ hnae3_unic_private_info
+
+ainline inclusion
+from mainline-v5.8-rc1
+commit 4828b5766a69e93ca76b15f820c97f03ebd3a48c
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4828b5766a69e93ca76b15f820c97f03ebd3a48c
+
+--------------------------------
+
+Since field .uinfo in struct hnae3_handle never be used,
+so remove it and its structure definition.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h | 11 -----------
+ 1 file changed, 11 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index a978ab96c7ad..7ab3c4012b44 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -718,16 +718,6 @@ struct hnae3_roce_private_info {
+ 	unsigned long state;
+ };
+ 
+-struct hnae3_unic_private_info {
+-	struct net_device *netdev;
+-	u16 rx_buf_len;
+-	u16 num_tx_desc;
+-	u16 num_rx_desc;
+-
+-	u16 num_tqps;	/* total number of tqps in this handle */
+-	struct hnae3_queue **tqp;  /* array base of all TQPs of this instance */
+-};
+-
+ #define HNAE3_SUPPORT_APP_LOOPBACK    BIT(0)
+ #define HNAE3_SUPPORT_PHY_LOOPBACK    BIT(1)
+ #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK	BIT(2)
+@@ -754,7 +744,6 @@ struct hnae3_handle {
+ 	union {
+ 		struct net_device *netdev; /* first member */
+ 		struct hnae3_knic_private_info kinfo;
+-		struct hnae3_unic_private_info uinfo;
+ 		struct hnae3_roce_private_info rinfo;
+ 	};
+ 
+-- 
+2.34.1
+
diff --git a/patches/0386-net-hns3-remove-two-duplicated-register-macros-in-hc.patch b/patches/0386-net-hns3-remove-two-duplicated-register-macros-in-hc.patch
new file mode 100644
index 0000000..ea1b8e6
--- /dev/null
+++ b/patches/0386-net-hns3-remove-two-duplicated-register-macros-in-hc.patch
@@ -0,0 +1,86 @@
+From 6224bf81772210b3564b1aacef98ce13a0841ab6 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 28 May 2020 21:48:17 +0800
+Subject: [PATCH 025/283] net: hns3: remove two duplicated register macros in
+ hclgevf_main.h
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 9cee2e8d303940a413d20c5d275bdaf418b09b17
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9cee2e8d303940a413d20c5d275bdaf418b09b17
+
+--------------------------------
+
+HCLGEVF_CMDQ_INTR_SRC_REG and HCLGEVF_CMDQ_INTR_STS_REG are same
+as HCLGEVF_VECTOR0_CMDQ_SRC_REG and HCLGEVF_VECTOR0_CMDQ_STAT_REG,
+replace the former with the latter, and rename macro
+HCLGEVF_VECTOR0_CMDQ_STAT_REG since 'stat' is not abbreviation of
+'state'.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 6 +++---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 4 +---
+ 2 files changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 35a2f0415ef5..0ff126b5d688 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -47,7 +47,7 @@ static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
+ 					 HCLGEVF_CMDQ_RX_TAIL_REG,
+ 					 HCLGEVF_CMDQ_RX_HEAD_REG,
+ 					 HCLGEVF_VECTOR0_CMDQ_SRC_REG,
+-					 HCLGEVF_CMDQ_INTR_STS_REG,
++					 HCLGEVF_VECTOR0_CMDQ_STATE_REG,
+ 					 HCLGEVF_CMDQ_INTR_EN_REG,
+ 					 HCLGEVF_CMDQ_INTR_GEN_REG};
+ 
+@@ -1904,7 +1904,7 @@ static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
+ 	dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
+ 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
+ 	dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
+-		 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STAT_REG));
++		 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
+ 	dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
+ 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG));
+ 	dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
+@@ -2336,7 +2336,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
+ 
+ 	/* fetch the events from their corresponding regs */
+ 	cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
+-					 HCLGEVF_VECTOR0_CMDQ_STAT_REG);
++					 HCLGEVF_VECTOR0_CMDQ_STATE_REG);
+ 
+ 	if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
+ 		rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index 101b3fa9e2db..fe0c87a9e2ff 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -42,8 +42,6 @@
+ #define HCLGEVF_CMDQ_RX_DEPTH_REG		0x27020
+ #define HCLGEVF_CMDQ_RX_TAIL_REG		0x27024
+ #define HCLGEVF_CMDQ_RX_HEAD_REG		0x27028
+-#define HCLGEVF_CMDQ_INTR_SRC_REG		0x27100
+-#define HCLGEVF_CMDQ_INTR_STS_REG		0x27104
+ #define HCLGEVF_CMDQ_INTR_EN_REG		0x27108
+ #define HCLGEVF_CMDQ_INTR_GEN_REG		0x2710C
+ 
+@@ -88,7 +86,7 @@
+ /* Vector0 interrupt CMDQ event source register(RW) */
+ #define HCLGEVF_VECTOR0_CMDQ_SRC_REG	0x27100
+ /* Vector0 interrupt CMDQ event status register(RO) */
+-#define HCLGEVF_VECTOR0_CMDQ_STAT_REG	0x27104
++#define HCLGEVF_VECTOR0_CMDQ_STATE_REG	0x27104
+ /* CMDQ register bits for RX event(=MBX event) */
+ #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B	1
+ /* RST register bits for RESET event */
+-- 
+2.34.1
+
diff --git a/patches/0387-net-hns3-remove-some-unused-fields-in-struct-hclge_d.patch b/patches/0387-net-hns3-remove-some-unused-fields-in-struct-hclge_d.patch
new file mode 100644
index 0000000..49938c8
--- /dev/null
+++ b/patches/0387-net-hns3-remove-some-unused-fields-in-struct-hclge_d.patch
@@ -0,0 +1,45 @@
+From 8f9fda742f4c45d483b6876033d754878117054b Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 28 May 2020 21:48:18 +0800
+Subject: [PATCH 026/283] net: hns3: remove some unused fields in struct
+ hclge_dev
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 7c6643cac0ed78395ec10fe5b3b279e61b0ee51f
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7c6643cac0ed78395ec10fe5b3b279e61b0ee51f
+
+--------------------------------
+
+Remove some fields in struct hclge_dev which have not been used.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 7c1bbe626b17..c5cad1122788 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -817,12 +817,6 @@ struct hclge_dev {
+ 	u16 num_roce_msi;	/* Num of roce vectors for this PF */
+ 	int roce_base_vector;
+ 
+-	u16 pending_udp_bitmap;
+-
+-	u16 rx_itr_default;
+-	u16 tx_itr_default;
+-
+-	u16 adminq_work_limit; /* Num of admin receive queue desc to process */
+ 	unsigned long service_timer_period;
+ 	unsigned long service_timer_previous;
+ 	struct timer_list reset_timer;
+-- 
+2.34.1
+
diff --git a/patches/0388-net-hns3-fix-a-print-format-issue-in-hclge_mac_mdio_.patch b/patches/0388-net-hns3-fix-a-print-format-issue-in-hclge_mac_mdio_.patch
new file mode 100644
index 0000000..43347e5
--- /dev/null
+++ b/patches/0388-net-hns3-fix-a-print-format-issue-in-hclge_mac_mdio_.patch
@@ -0,0 +1,41 @@
+From a96f4ce9ec69c9bdd8b5fc10cbfbbf5e83d12ff6 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 30 May 2020 09:08:27 +0800
+Subject: [PATCH 027/283] net: hns3: fix a print format issue in
+ hclge_mac_mdio_config()
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 1f4982ef56f794101cae7ec0fa3b7605f78bd25f
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1f4982ef56f794101cae7ec0fa3b7605f78bd25f
+
+--------------------------------
+
+Use %d to print int variable 'ret' in hclge_mac_mdio_config().
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+index d0247f4ab1e8..3eea4870a56a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+@@ -155,7 +155,7 @@ int hclge_mac_mdio_config(struct hclge_dev *hdev)
+ 	ret = mdiobus_register(mdio_bus);
+ 	if (ret) {
+ 		dev_err(mdio_bus->parent,
+-			"Failed to register MDIO bus ret = %#x\n", ret);
++			"failed to register MDIO bus, ret = %d\n", ret);
+ 		return ret;
+ 	}
+ 
+-- 
+2.34.1
+
diff --git a/patches/0389-net-hns3-remove-an-unused-macro-hclge_is_csq.patch b/patches/0389-net-hns3-remove-an-unused-macro-hclge_is_csq.patch
new file mode 100644
index 0000000..f53f694
--- /dev/null
+++ b/patches/0389-net-hns3-remove-an-unused-macro-hclge_is_csq.patch
@@ -0,0 +1,41 @@
+From f38968ed91f63e71c5ff5431902ea1e6e4ebad02 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 30 May 2020 09:08:28 +0800
+Subject: [PATCH 028/283] net: hns3: remove an unused macro hclge_is_csq
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit d62805087e7fbbd7582403b972dd75581256e585
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d62805087e7fbbd7582403b972dd75581256e585
+
+--------------------------------
+
+Macro hclge_is_csq defined in hcgle_cmd.c has not been used,
+so remove it.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 16262eb39605..55bdfd95a0fd 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -12,8 +12,6 @@
+ #include "hnae3.h"
+ #include "hclge_main.h"
+ 
+-#define hclge_is_csq(ring) ((ring)->flag & HCLGE_TYPE_CSQ)
+-
+ #define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
+ 
+ static int hclge_ring_space(struct hclge_cmq_ring *ring)
+-- 
+2.34.1
+
diff --git a/patches/0390-net-hns3-remove-two-unused-macros-in-hclgevf_cmd.c.patch b/patches/0390-net-hns3-remove-two-unused-macros-in-hclgevf_cmd.c.patch
new file mode 100644
index 0000000..2c8119b
--- /dev/null
+++ b/patches/0390-net-hns3-remove-two-unused-macros-in-hclgevf_cmd.c.patch
@@ -0,0 +1,42 @@
+From 5c278cc123c9987e3b5692da81156605c9c10618 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 30 May 2020 09:08:29 +0800
+Subject: [PATCH 029/283] net: hns3: remove two unused macros in hclgevf_cmd.c
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit fc68aed15648c70db0377a6abd2b34ec328dd12a
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fc68aed15648c70db0377a6abd2b34ec328dd12a
+
+--------------------------------
+
+Macro hclgevf_ring_to_dma_dir and hclgevf_is_csq defined in
+hclgevf_cmd.c, but not used, so remove them.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 84f54a7c2e4d..842c37d2a4fe 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -12,9 +12,6 @@
+ #include "hclgevf_main.h"
+ #include "hnae3.h"
+ 
+-#define hclgevf_is_csq(ring) ((ring)->flag & HCLGEVF_TYPE_CSQ)
+-#define hclgevf_ring_to_dma_dir(ring) (hclgevf_is_csq(ring) ? \
+-					DMA_TO_DEVICE : DMA_FROM_DEVICE)
+ #define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
+ 
+ static int hclgevf_ring_space(struct hclgevf_cmq_ring *ring)
+-- 
+2.34.1
+
diff --git a/patches/0391-net-hns3-fix-two-coding-style-issues-in-hclgevf_main.patch b/patches/0391-net-hns3-fix-two-coding-style-issues-in-hclgevf_main.patch
new file mode 100644
index 0000000..22435d7
--- /dev/null
+++ b/patches/0391-net-hns3-fix-two-coding-style-issues-in-hclgevf_main.patch
@@ -0,0 +1,53 @@
+From 13f4fb34280d2e2c92e7f8ba8eda9fce4291ca0e Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 30 May 2020 09:08:31 +0800
+Subject: [PATCH 030/283] net: hns3: fix two coding style issues in
+ hclgevf_main.c
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 2adb8187e5439e5066c9893586e5079e89f9060a
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2adb8187e5439e5066c9893586e5079e89f9060a
+
+--------------------------------
+
+Remove a redundant blank line in hclgevf_cmd_set_promisc_mode(),
+and fix a reverse xmas tree coding style issue in
+hclgevf_set_rss_tc_mode().
+
+Reported-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 0ff126b5d688..c8b7b3ede445 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -677,8 +677,8 @@ static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev,  u16 rss_size)
+ 	u16 tc_size[HCLGEVF_MAX_TC_NUM];
+ 	struct hclgevf_desc desc;
+ 	u16 roundup_size;
+-	int status;
+ 	unsigned int i;
++	int status;
+ 
+ 	req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
+ 
+@@ -1171,7 +1171,6 @@ static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
+ 	send_msg.en_mc = en_mc_pmc ? 1 : 0;
+ 
+ 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
+-
+ 	if (ret)
+ 		dev_err(&hdev->pdev->dev,
+ 			"Set promisc mode fail, status is %d.\n", ret);
+-- 
+2.34.1
+
diff --git a/patches/0392-net-hns3-remove-some-unused-codes-in-hns3_nic_set_fe.patch b/patches/0392-net-hns3-remove-some-unused-codes-in-hns3_nic_set_fe.patch
new file mode 100644
index 0000000..2c5a18c
--- /dev/null
+++ b/patches/0392-net-hns3-remove-some-unused-codes-in-hns3_nic_set_fe.patch
@@ -0,0 +1,53 @@
+From 5edf6687e835e1f3e0104d52e5fb7abe29b2cabe Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 30 May 2020 09:08:32 +0800
+Subject: [PATCH 031/283] net: hns3: remove some unused codes in
+ hns3_nic_set_features()
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit 996aade998ac0e9f6f0bf09531c32f1106d9d559
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=996aade998ac0e9f6f0bf09531c32f1106d9d559
+
+--------------------------------
+
+NETIF_F_HW_VLAN_CTAG_FILTER is not set in netdev->hw_feature for
+the HNS3 driver, so the handler of NETIF_F_HW_VLAN_CTAG_FILTER
+in hns3_nic_set_features() won't be called, remove it.
+
+Reported-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 8 --------
+ 1 file changed, 8 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 384ee4606051..8279aa124ac9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -1596,14 +1596,6 @@ static int hns3_nic_set_features(struct net_device *netdev,
+ 	}
+ #endif
+ 
+-	if ((changed & NETIF_F_HW_VLAN_CTAG_FILTER) &&
+-	    h->ae_algo->ops->enable_vlan_filter) {
+-		enable = !!(features & NETIF_F_HW_VLAN_CTAG_FILTER);
+-		ret = h->ae_algo->ops->enable_vlan_filter(h, enable);
+-		if (ret)
+-			return ret;
+-	}
+-
+ 	if ((changed & NETIF_F_HW_VLAN_CTAG_RX) &&
+ 	    h->ae_algo->ops->enable_hw_strip_rxvtag) {
+ 		enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
+-- 
+2.34.1
+
diff --git a/patches/0393-net-hns3-remove-some-unused-macros.patch b/patches/0393-net-hns3-remove-some-unused-macros.patch
new file mode 100644
index 0000000..f4a0569
--- /dev/null
+++ b/patches/0393-net-hns3-remove-some-unused-macros.patch
@@ -0,0 +1,57 @@
+From 9fb48951348ec72c4f9de5edc0282329a2a4c3ca Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 14 May 2020 20:41:25 +0800
+Subject: [PATCH 032/283] net: hns3: remove some unused macros
+
+mainline inclusion
+from mainline-v5.8-rc1
+commit bd13f7e12936b83a363ffada725bdf0fe229f337
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EJ0A
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bd13f7e12936b83a363ffada725bdf0fe229f337
+
+--------------------------------
+
+There are some macros defined in hns3_enet.h, but not used in
+anywhere.
+
+Reported-by: Yonglong Liu <liuyonglong@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 17 -----------------
+ 1 file changed, 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 7f19a8b82036..0588642f906c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -46,23 +46,6 @@ enum hns3_nic_state {
+ #define HNS3_RING_CFG_VF_NUM_REG		0x00080
+ #define HNS3_RING_ASID_REG			0x0008C
+ #define HNS3_RING_EN_REG			0x00090
+-#define HNS3_RING_T0_BE_RST			0x00094
+-#define HNS3_RING_COULD_BE_RST			0x00098
+-#define HNS3_RING_WRR_WEIGHT_REG		0x0009c
+-
+-#define HNS3_RING_INTMSK_RXWL_REG		0x000A0
+-#define HNS3_RING_INTSTS_RX_RING_REG		0x000A4
+-#define HNS3_RX_RING_INT_STS_REG		0x000A8
+-#define HNS3_RING_INTMSK_TXWL_REG		0x000AC
+-#define HNS3_RING_INTSTS_TX_RING_REG		0x000B0
+-#define HNS3_TX_RING_INT_STS_REG		0x000B4
+-#define HNS3_RING_INTMSK_RX_OVERTIME_REG	0x000B8
+-#define HNS3_RING_INTSTS_RX_OVERTIME_REG	0x000BC
+-#define HNS3_RING_INTMSK_TX_OVERTIME_REG	0x000C4
+-#define HNS3_RING_INTSTS_TX_OVERTIME_REG	0x000C8
+-
+-#define HNS3_RING_MB_CTRL_REG			0x00100
+-#define HNS3_RING_MB_DATA_BASE_REG		0x00200
+ 
+ #define HNS3_TX_REG_OFFSET			0x40
+ 
+-- 
+2.34.1
+
diff --git a/patches/0394-net-hns3-add-device-version-to-replace-pci-revision.patch b/patches/0394-net-hns3-add-device-version-to-replace-pci-revision.patch
new file mode 100644
index 0000000..a775814
--- /dev/null
+++ b/patches/0394-net-hns3-add-device-version-to-replace-pci-revision.patch
@@ -0,0 +1,692 @@
+From 00ebd53ab1af1addac638a8b012daa03ee396f9b Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 15 Jun 2023 14:40:50 +0800
+Subject: [PATCH 033/283] net: hns3: add device version to replace pci revision
+
+mainline inclusion
+from mainline-v5.10-rc1
+commit 295ba232a8c3c5547f9fb470a62f3585025ccd00
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=295ba232a8c3c5547f9fb470a62f3585025ccd00
+
+--------------------------------
+
+To better identify the device version, struct hnae3_handle adds a
+member dev_version to replace pci revision. The dev_version consists
+of hardware version and PCI revision. The hardware version is queried
+from firmware by an existing firmware version query command.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  7 ++++
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  7 ++--
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 30 +++++++++-----
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         | 38 ++++++++++--------
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  3 +-
+ .../hisilicon/hns3/hns3pf/hclge_err.c         | 13 +++---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 33 +++++++--------
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       | 40 ++++++++++---------
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       |  3 +-
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 17 ++++----
+ 10 files changed, 110 insertions(+), 81 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 7ab3c4012b44..61e549bbbf9a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -36,6 +36,12 @@
+ 
+ #define HNAE3_MIN_VECTOR_NUM	2 /* first one for misc, another for IO */
+ 
++/* Device version */
++#define HNAE3_DEVICE_VERSION_V1   0x00020
++#define HNAE3_DEVICE_VERSION_V2   0x00021
++#define HNAE3_DEVICE_VERSION_V3   0x00030
++
++#define HNAE3_PCI_REVISION_BIT_SIZE            8
+ /* Device IDs */
+ #define HNAE3_DEV_ID_GE				0xA220
+ #define HNAE3_DEV_ID_25GE			0xA221
+@@ -288,6 +294,7 @@ struct hnae3_ae_dev {
+ 	struct list_head node;
+ 	u32 flag;
+ 	unsigned long hw_err_reset_req;
++	u32 dev_version;
+ 	void *priv;
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 8279aa124ac9..3784001b09a7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -2165,7 +2165,7 @@ static void hns3_disable_sriov(struct pci_dev *pdev)
+ static void hns3_get_dev_capability(struct pci_dev *pdev,
+ 				    struct hnae3_ae_dev *ae_dev)
+ {
+-	if (pdev->revision >= 0x21) {
++	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ 		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
+ 		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
+ 	}
+@@ -2424,7 +2424,7 @@ static void hns3_set_default_feature(struct net_device *netdev)
+ 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
+ 		NETIF_F_FRAGLIST;
+ 
+-	if (pdev->revision > HNAE3_REVISION_ID_20) {
++	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ #ifdef NETIF_F_GRO_HW
+ 		netdev->features |= NETIF_F_GRO_HW;
+ 		netdev->hw_features |= NETIF_F_GRO_HW;
+@@ -2930,8 +2930,9 @@ static bool hns3_parse_vlan_tag(struct hns3_enet_ring *ring,
+ {
+ 	struct hnae3_handle *handle = ring->tqp->handle;
+ 	struct pci_dev *pdev = ring->tqp->handle->pdev;
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
+ 
+-	if (pdev->revision == HNAE3_REVISION_ID_20) {
++	if (unlikely(ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)) {
+ 		*vlan_tag = le16_to_cpu(desc->rx.ot_vlan_tag);
+ 		if (!(*vlan_tag & VLAN_VID_MASK))
+ 			*vlan_tag = le16_to_cpu(desc->rx.vlan_tag);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 11480bb99055..e38fb6ef3e75 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -83,6 +83,7 @@ static const struct hns3_stats hns3_rxq_stats[] = {
+ static int hns3_lp_setup(struct net_device *ndev, enum hnae3_loop loop, bool en)
+ {
+ 	struct hnae3_handle *h = hns3_get_handle(ndev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
+ 	int ret;
+ 
+ 	if (!h->ae_algo->ops->set_loopback ||
+@@ -101,7 +102,7 @@ static int hns3_lp_setup(struct net_device *ndev, enum hnae3_loop loop, bool en)
+ 		break;
+ 	}
+ 
+-	if (ret || h->pdev->revision >= 0x21)
++	if (ret || ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+ 		return ret;
+ 
+ 	if (en)
+@@ -149,6 +150,7 @@ static void hns3_lp_setup_skb(struct sk_buff *skb)
+ 
+ 	struct net_device *ndev = skb->dev;
+ 	struct hnae3_handle *handle;
++	struct hnae3_ae_dev *ae_dev;
+ 	unsigned char *packet;
+ 	struct ethhdr *ethh;
+ 	unsigned int i;
+@@ -170,7 +172,8 @@ static void hns3_lp_setup_skb(struct sk_buff *skb)
+ 	 * the purpose of mac or serdes selftest.
+ 	 */
+ 	handle = hns3_get_handle(ndev);
+-	if (handle->pdev->revision == 0x20)
++	ae_dev = pci_get_drvdata(handle->pdev);
++	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		ethh->h_dest[5] += HNS3_NIC_LB_DST_MAC_ADDR;
+ 	eth_zero_addr(ethh->h_source);
+ 	ethh->h_proto = htons(ETH_P_ARP);
+@@ -771,6 +774,7 @@ static int hns3_set_link_ksettings(struct net_device *netdev,
+ 				   const struct ethtool_link_ksettings *cmd)
+ {
+ 	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+ 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
+ 	int ret;
+ 
+@@ -794,7 +798,7 @@ static int hns3_set_link_ksettings(struct net_device *netdev,
+ 		return phy_ethtool_ksettings_set(netdev->phydev, cmd);
+ 	}
+ 
+-	if (handle->pdev->revision == 0x20)
++	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		return -EOPNOTSUPP;
+ 
+ 	ret = hns3_check_ksettings_param(netdev, cmd);
+@@ -858,11 +862,12 @@ static int hns3_set_rss(struct net_device *netdev, const u32 *indir,
+ 			const u8 *key, const u8 hfunc)
+ {
+ 	struct hnae3_handle *h = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
+ 
+ 	if (!h->ae_algo->ops->set_rss)
+ 		return -EOPNOTSUPP;
+ 
+-	if ((h->pdev->revision == HNAE3_REVISION_ID_20 &&
++	if ((ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 &&
+ 	     hfunc != ETH_RSS_HASH_TOP) || (hfunc != ETH_RSS_HASH_NO_CHANGE &&
+ 	     hfunc != ETH_RSS_HASH_TOP && hfunc != ETH_RSS_HASH_XOR)) {
+ 		netdev_err(netdev, "hash func not supported\n");
+@@ -1055,6 +1060,7 @@ static int hns3_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
+ static int hns3_nway_reset(struct net_device *netdev)
+ {
+ 	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+ 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
+ 	struct phy_device *phy = netdev->phydev;
+ 	int autoneg;
+@@ -1084,7 +1090,7 @@ static int hns3_nway_reset(struct net_device *netdev)
+ 	if (phy)
+ 		return genphy_restart_aneg(phy);
+ 
+-	if (handle->pdev->revision == 0x20)
++	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		return -EOPNOTSUPP;
+ 
+ 	return ops->restart_autoneg(handle);
+@@ -1374,11 +1380,12 @@ static int hns3_get_fecparam(struct net_device *netdev,
+ 			     struct ethtool_fecparam *fec)
+ {
+ 	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+ 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
+ 	u8 fec_ability;
+ 	u8 fec_mode;
+ 
+-	if (handle->pdev->revision == 0x20)
++	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		return -EOPNOTSUPP;
+ 
+ 	if (!ops->get_fec)
+@@ -1396,10 +1403,11 @@ static int hns3_set_fecparam(struct net_device *netdev,
+ 			     struct ethtool_fecparam *fec)
+ {
+ 	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+ 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
+ 	u32 fec_mode;
+ 
+-	if (handle->pdev->revision == 0x20)
++	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		return -EOPNOTSUPP;
+ 
+ 	if (!ops->set_fec)
+@@ -1418,11 +1426,13 @@ static int hns3_get_module_info(struct net_device *netdev,
+ #define HNS3_SFF_8636_V1_3 0x03
+ 
+ 	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+ 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
+ 	struct hns3_sfp_type sfp_type;
+ 	int ret;
+ 
+-	if (handle->pdev->revision == 0x20 || !ops->get_module_eeprom)
++	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 ||
++	    !ops->get_module_eeprom)
+ 		return -EOPNOTSUPP;
+ 
+ 	memset(&sfp_type, 0, sizeof(sfp_type));
+@@ -1466,9 +1476,11 @@ static int hns3_get_module_eeprom(struct net_device *netdev,
+ 				  struct ethtool_eeprom *ee, u8 *data)
+ {
+ 	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+ 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
+ 
+-	if (handle->pdev->revision == 0x20 || !ops->get_module_eeprom)
++	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 ||
++	    !ops->get_module_eeprom)
+ 		return -EOPNOTSUPP;
+ 
+ 	if (!ee->len)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 55bdfd95a0fd..114970c8e21a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -346,9 +346,9 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
+ 	return retval;
+ }
+ 
+-static enum hclge_cmd_status hclge_cmd_query_firmware_version(
+-		struct hclge_hw *hw, u32 *version)
++static enum hclge_cmd_status hclge_cmd_query_version(struct hclge_dev *hdev)
+ {
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct hclge_query_version_cmd *resp;
+ 	struct hclge_desc desc;
+ 	int ret;
+@@ -356,9 +356,15 @@ static enum hclge_cmd_status hclge_cmd_query_firmware_version(
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);
+ 	resp = (struct hclge_query_version_cmd *)desc.data;
+ 
+-	ret = hclge_cmd_send(hw, &desc, 1);
+-	if (!ret)
+-		*version = le32_to_cpu(resp->firmware);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		return ret;
++
++	hdev->fw_version = le32_to_cpu(resp->firmware);
++
++	ae_dev->dev_version = le32_to_cpu(resp->hardware) <<
++					  HNAE3_PCI_REVISION_BIT_SIZE;
++	ae_dev->dev_version |= hdev->pdev->revision;
+ 
+ 	return ret;
+ }
+@@ -426,7 +432,6 @@ static int hclge_firmware_compat_config(struct hclge_dev *hdev, bool en)
+ 
+ int hclge_cmd_init(struct hclge_dev *hdev)
+ {
+-	u32 version;
+ 	int ret;
+ 
+ 	spin_lock_bh(&hdev->hw.cmq.csq.lock);
+@@ -455,23 +460,22 @@ int hclge_cmd_init(struct hclge_dev *hdev)
+ 		goto err_cmd_init;
+ 	}
+ 
+-	ret = hclge_cmd_query_firmware_version(&hdev->hw, &version);
++	ret = hclge_cmd_query_version(hdev);
+ 	if (ret) {
+ 		dev_err(&hdev->pdev->dev,
+-			"firmware version query failed %d\n", ret);
++			"failed to query version ret=%d\n", ret);
+ 		goto err_cmd_init;
+ 	}
+-	hdev->fw_version = version;
+ 
+ 	dev_info(&hdev->pdev->dev, "The firmware version is %lu.%lu.%lu.%lu\n",
+-		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE3_MASK,
+-				 HNAE3_FW_VERSION_BYTE3_SHIFT),
+-		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE2_MASK,
+-				 HNAE3_FW_VERSION_BYTE2_SHIFT),
+-		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE1_MASK,
+-				 HNAE3_FW_VERSION_BYTE1_SHIFT),
+-		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE0_MASK,
+-				 HNAE3_FW_VERSION_BYTE0_SHIFT));
++		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE3_MASK,
++				HNAE3_FW_VERSION_BYTE3_SHIFT),
++		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE2_MASK,
++				HNAE3_FW_VERSION_BYTE2_SHIFT),
++		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE1_MASK,
++				HNAE3_FW_VERSION_BYTE1_SHIFT),
++		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE0_MASK,
++				HNAE3_FW_VERSION_BYTE0_SHIFT));
+ 
+ 	/* ask the firmware to enable some features, driver can work without
+ 	 * it.
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index aacb75eb8ea8..c43bae3ecbfe 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -371,7 +371,8 @@ struct hclge_rx_priv_buff_cmd {
+ 
+ struct hclge_query_version_cmd {
+ 	__le32 firmware;
+-	__le32 firmware_rsv[5];
++	__le32 hardware;
++	__le32 rsv[4];
+ };
+ 
+ #define HCLGE_RX_PRIV_EN_B	15
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 9338f030842c..55990ba4b30e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -729,7 +729,7 @@ static int hclge_config_ncsi_hw_err_int(struct hclge_dev *hdev, bool en)
+ 	struct hclge_desc desc;
+ 	int ret;
+ 
+-	if (hdev->pdev->revision < 0x21)
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		return 0;
+ 
+ 	/* configure NCSI error interrupts */
+@@ -809,7 +809,7 @@ static int hclge_config_ppp_error_interrupt(struct hclge_dev *hdev, u32 cmd,
+ 			cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK);
+ 		desc[1].data[1] =
+ 			cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK);
+-		if (hdev->pdev->revision >= 0x21)
++		if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+ 			desc[1].data[2] =
+ 				cpu_to_le32(HCLGE_PPP_PF_ERR_INT_EN_MASK);
+ 	} else if (cmd == HCLGE_PPP_CMD1_INT_CMD) {
+@@ -1042,7 +1042,7 @@ static int hclge_config_ssu_hw_err_int(struct hclge_dev *hdev, bool en)
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_COMMON_INT_CMD, false);
+ 
+ 	if (en) {
+-		if (hdev->pdev->revision >= 0x21)
++		if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+ 			desc[0].data[0] =
+ 				cpu_to_le32(HCLGE_SSU_COMMON_INT_EN);
+ 		else
+@@ -1551,7 +1551,8 @@ int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en)
+ 	struct hclge_desc desc;
+ 	int ret;
+ 
+-	if (hdev->pdev->revision < 0x21 || !hnae3_dev_roce_supported(hdev))
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 ||
++	    !hnae3_dev_roce_supported(hdev))
+ 		return 0;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_CONFIG_ROCEE_RAS_INT_EN, false);
+@@ -1578,7 +1579,7 @@ int hclge_handle_rocee_ras_error(struct hnae3_ae_dev *ae_dev)
+ 	struct hclge_dev *hdev = ae_dev->priv;
+ 
+ 	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
+-	    hdev->pdev->revision < 0x21)
++	    hdev->pdev->revision < HNAE3_DEVICE_VERSION_V2)
+ 		return reset_type;
+ 
+ 	reset_type = hclge_log_and_clear_rocee_ras_error(hdev);
+@@ -1666,7 +1667,7 @@ pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev)
+ 	}
+ 
+ 	/* Handling Non-fatal Rocee RAS errors */
+-	if (hdev->pdev->revision >= 0x21 &&
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 &&
+ 	    status & HCLGE_RAS_REG_ROCEE_ERR_MASK) {
+ 		dev_err(dev, "ROCEE Non-Fatal RAS error identified\n");
+ 		hclge_handle_rocee_ras_error(ae_dev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index e0ab39ae5c91..307907896ff4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -739,7 +739,7 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
+ 	if (stringset == ETH_SS_TEST) {
+ 		/* clear loopback bit flags at first */
+ 		handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
+-		if (hdev->pdev->revision >= HNAE3_REVISION_ID_21 ||
++		if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 ||
+ 		    hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
+ 		    hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
+ 		    hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
+@@ -1139,7 +1139,7 @@ static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
+ 	hclge_convert_setting_sr(mac, speed_ability);
+ 	hclge_convert_setting_lr(mac, speed_ability);
+ 	hclge_convert_setting_cr(mac, speed_ability);
+-	if (hdev->pdev->revision >= 0x21)
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+ 		hclge_convert_setting_fec(mac);
+ 
+ 	linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported);
+@@ -1168,7 +1168,7 @@ static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev,
+ 
+ #ifdef HAVE_ETHTOOL_CONVERT_U32_AND_LINK_MODE
+ 	hclge_convert_setting_kr(mac, speed_ability);
+-	if (hdev->pdev->revision >= 0x21)
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+ 		hclge_convert_setting_fec(mac);
+ #else
+ 	if (speed_ability & HCLGE_SUPPORT_1G_BIT)
+@@ -2916,7 +2916,7 @@ static int hclge_update_port_info(struct hclge_dev *hdev)
+ 	if (!hdev->support_sfp_query)
+ 		return 0;
+ 
+-	if (hdev->pdev->revision >= 0x21)
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+ 		ret = hclge_get_sfp_info(hdev, mac);
+ 	else
+ 		ret = hclge_get_sfp_speed(hdev, &speed);
+@@ -2928,7 +2928,7 @@ static int hclge_update_port_info(struct hclge_dev *hdev)
+ 		return ret;
+ 	}
+ 
+-	if (hdev->pdev->revision >= 0x21) {
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ 		if (mac->speed_type == QUERY_ACTIVE_SPEED) {
+ 			hclge_update_port_capability(mac);
+ 			return 0;
+@@ -3567,7 +3567,7 @@ static void hclge_clear_reset_cause(struct hclge_dev *hdev)
+ 	/* For revision 0x20, the reset interrupt source
+ 	 * can only be cleared after hardware reset done
+ 	 */
+-	if (hdev->pdev->revision == 0x20)
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG,
+ 				clearval);
+ 
+@@ -4671,7 +4671,7 @@ static void hclge_rss_init_cfg(struct hclge_dev *hdev)
+ 	int i, rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
+ 	struct hclge_vport *vport = hdev->vport;
+ 
+-	if (hdev->pdev->revision >= 0x21)
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+ 		rss_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
+ 
+ 	for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
+@@ -4871,13 +4871,14 @@ static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
+ 				  bool en_mc_pmc)
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_dev *hdev = vport->back;
+ 	bool en_bc_pmc = true;
+ 
+-	/* For revision 0x20, if broadcast promisc enabled, vlan filter is
+-	 * always bypassed. So broadcast promisc should be disabled until
+-	 * user enable promisc mode
++	/* For device whose version below V2, if broadcast promisc enabled,
++	 * vlan filter is always bypassed. So broadcast promisc should be
++	 * disabled until user enable promisc mode
+ 	 */
+-	if (handle->pdev->revision == 0x20)
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		en_bc_pmc = handle->netdev_flags & HNAE3_BPE ? true : false;
+ 
+ 	return hclge_set_vport_promisc_mode(vport, en_uc_pmc, en_mc_pmc,
+@@ -6921,7 +6922,7 @@ static int hclge_set_loopback(struct hnae3_handle *handle,
+ 	 * the same, the packets are looped back in the SSU. If SSU loopback
+ 	 * is disabled, packets can reach MAC even if SMAC is the same as DMAC.
+ 	 */
+-	if (hdev->pdev->revision >= 0x21) {
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ 		u8 switch_param = en ? 0 : BIT(HCLGE_SWITCH_ALW_LPBK_B);
+ 
+ 		ret = hclge_config_switch_param(hdev, PF_VPORT_ID, switch_param,
+@@ -8795,7 +8796,7 @@ static int hclge_init_vlan_config(struct hclge_dev *hdev)
+ 	int ret;
+ 	int i;
+ 
+-	if (hdev->pdev->revision >= HNAE3_REVISION_ID_21) {
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ 		/* for revision 0x21, vf vlan filter is per function */
+ 		for (i = 0; i < hdev->num_alloc_vport; i++) {
+ 			vport = &hdev->vport[i];
+@@ -9251,7 +9252,7 @@ static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
+ 	u16 state;
+ 	int ret;
+ 
+-	if (hdev->pdev->revision == 0x20)
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		return -EOPNOTSUPP;
+ 
+ 	vport = hclge_get_vf_vport(hdev, vfid);
+@@ -10548,7 +10549,7 @@ static int hclge_set_vf_spoofchk(struct hnae3_handle *handle, int vf,
+ 	u32 new_spoofchk = enable ? 1 : 0;
+ 	int ret;
+ 
+-	if (hdev->pdev->revision == 0x20)
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		return -EOPNOTSUPP;
+ 
+ 	vport = hclge_get_vf_vport(hdev, vf);
+@@ -10581,7 +10582,7 @@ static int hclge_reset_vport_spoofchk(struct hclge_dev *hdev)
+ 	int ret;
+ 	int i;
+ 
+-	if (hdev->pdev->revision == 0x20)
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		return 0;
+ 
+ 	/* resume the vf spoof check state after reset */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 842c37d2a4fe..4585a22f0003 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -329,9 +329,9 @@ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
+ 	return status;
+ }
+ 
+-static int  hclgevf_cmd_query_firmware_version(struct hclgevf_hw *hw,
+-					       u32 *version)
++static int hclgevf_cmd_query_version(struct hclgevf_dev *hdev)
+ {
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct hclgevf_query_version_cmd *resp;
+ 	struct hclgevf_desc desc;
+ 	int status;
+@@ -339,9 +339,15 @@ static int  hclgevf_cmd_query_firmware_version(struct hclgevf_hw *hw,
+ 	resp = (struct hclgevf_query_version_cmd *)desc.data;
+ 
+ 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_FW_VER, 1);
+-	status = hclgevf_cmd_send(hw, &desc, 1);
+-	if (!status)
+-		*version = le32_to_cpu(resp->firmware);
++	status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
++	if (status)
++		return status;
++
++	hdev->fw_version = le32_to_cpu(resp->firmware);
++
++	ae_dev->dev_version = le32_to_cpu(resp->hardware) <<
++				HNAE3_PCI_REVISION_BIT_SIZE;
++	ae_dev->dev_version |= hdev->pdev->revision;
+ 
+ 	return status;
+ }
+@@ -385,7 +391,6 @@ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
+ 
+ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ {
+-	u32 version;
+ 	int ret;
+ 
+ 	spin_lock_bh(&hdev->hw.cmq.csq.lock);
+@@ -416,24 +421,21 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ 		goto err_cmd_init;
+ 	}
+ 
+-	/* get firmware version */
+-	ret = hclgevf_cmd_query_firmware_version(&hdev->hw, &version);
++	ret = hclgevf_cmd_query_version(hdev);
+ 	if (ret) {
+-		dev_err(&hdev->pdev->dev,
+-			"failed(%d) to query firmware version\n", ret);
++		dev_err(&hdev->pdev->dev, "failed(%d) to query version\n", ret);
+ 		goto err_cmd_init;
+ 	}
+-	hdev->fw_version = version;
+ 
+ 	dev_info(&hdev->pdev->dev, "The firmware version is %lu.%lu.%lu.%lu\n",
+-		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE3_MASK,
+-				 HNAE3_FW_VERSION_BYTE3_SHIFT),
+-		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE2_MASK,
+-				 HNAE3_FW_VERSION_BYTE2_SHIFT),
+-		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE1_MASK,
+-				 HNAE3_FW_VERSION_BYTE1_SHIFT),
+-		 hnae3_get_field(version, HNAE3_FW_VERSION_BYTE0_MASK,
+-				 HNAE3_FW_VERSION_BYTE0_SHIFT));
++		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE3_MASK,
++				HNAE3_FW_VERSION_BYTE3_SHIFT),
++		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE2_MASK,
++				HNAE3_FW_VERSION_BYTE2_SHIFT),
++		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE1_MASK,
++				HNAE3_FW_VERSION_BYTE1_SHIFT),
++		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE0_MASK,
++				HNAE3_FW_VERSION_BYTE0_SHIFT));
+ 
+ 	return 0;
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 69ddfad488a5..a797f770a9fa 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -144,7 +144,8 @@ struct hclgevf_ctrl_vector_chain {
+ 
+ struct hclgevf_query_version_cmd {
+ 	__le32 firmware;
+-	__le32 firmware_rsv[5];
++	__le32 hardware;
++	__le32 rsv[4];
+ };
+ 
+ #define HCLGEVF_MSIX_OFT_ROCEE_S       0
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index c8b7b3ede445..f688217d4c59 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -757,7 +757,7 @@ static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
+ 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
+ 	int i, ret;
+ 
+-	if (handle->pdev->revision >= HNAE3_REVISION_ID_21) {
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ 		/* Get hash algorithm */
+ 		if (hfunc) {
+ 			switch (rss_cfg->hash_algo) {
+@@ -822,7 +822,7 @@ static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
+ 	u8 hash_algo;
+ 	int ret, i;
+ 
+-	if (handle->pdev->revision >= HNAE3_REVISION_ID_21) {
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ 		ret = hclgevf_parse_rss_hfunc(hdev, hfunc, &hash_algo);
+ 		if (ret)
+ 			return ret;
+@@ -891,7 +891,7 @@ static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
+ 	u8 tuple_sets;
+ 	int ret;
+ 
+-	if (handle->pdev->revision == HNAE3_REVISION_ID_20)
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		return -EOPNOTSUPP;
+ 
+ 	if (nfc->data &
+@@ -969,7 +969,7 @@ static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
+ 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
+ 	u8 tuple_sets;
+ 
+-	if (handle->pdev->revision == HNAE3_REVISION_ID_20)
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+ 		return -EOPNOTSUPP;
+ 
+ 	nfc->data = 0;
+@@ -1182,10 +1182,9 @@ static int hclgevf_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
+ 				    bool en_mc_pmc)
+ {
+ 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
+-	struct pci_dev *pdev = hdev->pdev;
+ 	bool en_bc_pmc;
+ 
+-	en_bc_pmc = pdev->revision != 0x20;
++	en_bc_pmc = hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2;
+ 
+ 	return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc,
+ 					    en_bc_pmc);
+@@ -2364,7 +2363,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
+ 		 * register, so we should just write 0 to the bit we are
+ 		 * handling, and keep other bits as cmdq_stat_reg.
+ 		 */
+-		if (hdev->pdev->revision >= 0x21)
++		if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+ 			*clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
+ 		else
+ 			*clearval = cmdq_stat_reg &
+@@ -2506,7 +2505,7 @@ static void hclgevf_rss_init_cfg(struct hclgevf_dev *hdev)
+ 	rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
+ 	rss_cfg->rss_size = hdev->nic.kinfo.rss_size;
+ 	tuple_sets = &rss_cfg->rss_tuple_sets;
+-	if (hdev->pdev->revision >= 0x21) {
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ 		rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE;
+ 		memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key,
+ 		       HCLGEVF_RSS_KEY_SIZE);
+@@ -2531,7 +2530,7 @@ static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
+ 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
+ 	int ret;
+ 
+-	if (hdev->pdev->revision >= HNAE3_REVISION_ID_21) {
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ 		ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
+ 					       rss_cfg->rss_hash_key);
+ 		if (ret)
+-- 
+2.34.1
+
diff --git a/patches/0395-net-hns3-add-support-to-query-device-capability.patch b/patches/0395-net-hns3-add-support-to-query-device-capability.patch
new file mode 100644
index 0000000..e38452f
--- /dev/null
+++ b/patches/0395-net-hns3-add-support-to-query-device-capability.patch
@@ -0,0 +1,185 @@
+From 90b0e05e773e5dbdf603a7efa64e90e5e9aa42d0 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sun, 27 Sep 2020 15:12:41 +0800
+Subject: [PATCH 034/283] net: hns3: add support to query device capability
+
+mainline inclusion
+from mainline-v5.10-rc1
+commit ca850f2b0ecbb24f03a706d4d11203565030570a
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ca850f2b0ecbb24f03a706d4d11203565030570a
+
+--------------------------------
+
+In order to improve code maintainability and compatibility,
+add support to query the device capability by expanding the
+existing version query command. The device capability refers
+to the features supported by the device.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c   | 10 ----------
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c    | 15 ++++++++++++---
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h    |  4 +++-
+ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c  | 15 ++++++++++++---
+ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h  |  4 +++-
+ 5 files changed, 30 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 3784001b09a7..f55dd10ab554 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -2162,15 +2162,6 @@ static void hns3_disable_sriov(struct pci_dev *pdev)
+ 	pci_disable_sriov(pdev);
+ }
+ 
+-static void hns3_get_dev_capability(struct pci_dev *pdev,
+-				    struct hnae3_ae_dev *ae_dev)
+-{
+-	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+-		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
+-		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
+-	}
+-}
+-
+ /* hns3_probe - Device initialization routine
+  * @pdev: PCI device information struct
+  * @ent: entry in hns3_pci_tbl
+@@ -2192,7 +2183,6 @@ static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ 
+ 	ae_dev->pdev = pdev;
+ 	ae_dev->flag = ent->driver_data;
+-	hns3_get_dev_capability(pdev, ae_dev);
+ 	pci_set_drvdata(pdev, ae_dev);
+ 
+ 	ret = hnae3_register_ae_dev(ae_dev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 114970c8e21a..d9c4e82b0d21 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -346,7 +346,8 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
+ 	return retval;
+ }
+ 
+-static enum hclge_cmd_status hclge_cmd_query_version(struct hclge_dev *hdev)
++static enum hclge_cmd_status
++hclge_cmd_query_version_and_capability(struct hclge_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct hclge_query_version_cmd *resp;
+@@ -366,6 +367,12 @@ static enum hclge_cmd_status hclge_cmd_query_version(struct hclge_dev *hdev)
+ 					  HNAE3_PCI_REVISION_BIT_SIZE;
+ 	ae_dev->dev_version |= hdev->pdev->revision;
+ 
++	if (!resp->caps[0] &&
++	    ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
++		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
++		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
++	}
++
+ 	return ret;
+ }
+ 
+@@ -460,10 +467,12 @@ int hclge_cmd_init(struct hclge_dev *hdev)
+ 		goto err_cmd_init;
+ 	}
+ 
+-	ret = hclge_cmd_query_version(hdev);
++	/* get version and device capabilities */
++	ret = hclge_cmd_query_version_and_capability(hdev);
+ 	if (ret) {
+ 		dev_err(&hdev->pdev->dev,
+-			"failed to query version ret=%d\n", ret);
++			"failed to query version and capabilities, ret = %d\n",
++			ret);
+ 		goto err_cmd_init;
+ 	}
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index c43bae3ecbfe..d565633abab3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -369,10 +369,12 @@ struct hclge_rx_priv_buff_cmd {
+ 	u8 rsv[6];
+ };
+ 
++#define HCLGE_QUERY_CAP_LENGTH		3
+ struct hclge_query_version_cmd {
+ 	__le32 firmware;
+ 	__le32 hardware;
+-	__le32 rsv[4];
++	__le32 rsv;
++	__le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
+ };
+ 
+ #define HCLGE_RX_PRIV_EN_B	15
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 4585a22f0003..20db8fb98604 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -329,7 +329,7 @@ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
+ 	return status;
+ }
+ 
+-static int hclgevf_cmd_query_version(struct hclgevf_dev *hdev)
++static int hclgevf_cmd_query_version_and_capability(struct hclgevf_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct hclgevf_query_version_cmd *resp;
+@@ -349,6 +349,12 @@ static int hclgevf_cmd_query_version(struct hclgevf_dev *hdev)
+ 				HNAE3_PCI_REVISION_BIT_SIZE;
+ 	ae_dev->dev_version |= hdev->pdev->revision;
+ 
++	if (!resp->caps[0] &&
++	    ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
++		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
++		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
++	}
++
+ 	return status;
+ }
+ 
+@@ -421,9 +427,12 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ 		goto err_cmd_init;
+ 	}
+ 
+-	ret = hclgevf_cmd_query_version(hdev);
++	/* get version and device capabilities */
++	ret = hclgevf_cmd_query_version_and_capability(hdev);
+ 	if (ret) {
+-		dev_err(&hdev->pdev->dev, "failed(%d) to query version\n", ret);
++		dev_err(&hdev->pdev->dev,
++			"failed to query version and capabilities, ret = %d\n",
++			ret);
+ 		goto err_cmd_init;
+ 	}
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index a797f770a9fa..b59ca89f52cc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -142,10 +142,12 @@ struct hclgevf_ctrl_vector_chain {
+ 	u8 resv;
+ };
+ 
++#define HCLGEVF_QUERY_CAP_LENGTH		3
+ struct hclgevf_query_version_cmd {
+ 	__le32 firmware;
+ 	__le32 hardware;
+-	__le32 rsv[4];
++	__le32 rsv;
++	__le32 caps[HCLGEVF_QUERY_CAP_LENGTH]; /* capabilities of device */
+ };
+ 
+ #define HCLGEVF_MSIX_OFT_ROCEE_S       0
+-- 
+2.34.1
+
diff --git a/patches/0396-net-hns3-use-capabilities-queried-from-firmware.patch b/patches/0396-net-hns3-use-capabilities-queried-from-firmware.patch
new file mode 100644
index 0000000..73efeb3
--- /dev/null
+++ b/patches/0396-net-hns3-use-capabilities-queried-from-firmware.patch
@@ -0,0 +1,324 @@
+From 6594dcb8488bb746c54752493f35816816904e42 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sun, 27 Sep 2020 15:12:43 +0800
+Subject: [PATCH 035/283] net: hns3: use capabilities queried from firmware
+
+mainline inclusion
+from mainline-v5.10-rc1
+commit 4cc86cb58a9993a318a56aff1d7dacdf5252b2bc
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4cc86cb58a9993a318a56aff1d7dacdf5252b2bc
+
+--------------------------------
+
+In order to improve code maintainability and compatibility, the
+capabilities of new features are queried from firmware.
+
+The member flag in struct hnae3_ae_dev indicates not only
+capabilities, but some initialized status. As capabilities bits
+queried from firmware is too many, it is better to use new member
+to indicate them. So adds member capabs in struce hnae3_ae_dev.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   | 62 +++++++++++++++++--
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  4 +-
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         | 36 +++++++++--
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         | 14 +++++
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       | 34 ++++++++--
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       | 14 +++++
+ 6 files changed, 147 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 61e549bbbf9a..7c00830b712e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -64,10 +64,7 @@
+ #define HNAE3_KNIC_CLIENT_INITED_B		0x3
+ #define HNAE3_UNIC_CLIENT_INITED_B		0x4
+ #define HNAE3_ROCE_CLIENT_INITED_B		0x5
+-#define HNAE3_DEV_SUPPORT_FD_B			0x6
+-#define HNAE3_DEV_SUPPORT_GRO_B			0x7
+ #define HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B	0x8
+-
+ #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\
+ 		BIT(HNAE3_DEV_SUPPORT_ROCE_B))
+ 
+@@ -77,15 +74,68 @@
+ #define hnae3_dev_dcb_supported(hdev) \
+ 	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
+ 
++enum HNAE3_DEV_CAP_BITS {
++	HNAE3_DEV_SUPPORT_FD_B,
++	HNAE3_DEV_SUPPORT_GRO_B,
++	HNAE3_DEV_SUPPORT_FEC_B,
++	HNAE3_DEV_SUPPORT_UDP_GSO_B,
++	HNAE3_DEV_SUPPORT_QB_B,
++	HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,
++	HNAE3_DEV_SUPPORT_PTP_B,
++	HNAE3_DEV_SUPPORT_INT_QL_B,
++	HNAE3_DEV_SUPPORT_SIMPLE_BD_B,
++	HNAE3_DEV_SUPPORT_TX_PUSH_B,
++	HNAE3_DEV_SUPPORT_PHY_IMP_B,
++	HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,
++	HNAE3_DEV_SUPPORT_HW_PAD_B,
++	HNAE3_DEV_SUPPORT_STASH_B,
++};
++
+ #define hnae3_dev_fd_supported(hdev) \
+-	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B)
++	test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps)
+ 
+ #define hnae3_dev_gro_supported(hdev) \
+-	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B)
++	test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps)
+ 
+ #define hnae3_dev_vlan_fltr_mdf_supported(hdev) \
+ 	hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B)
+ 
++#define hnae3_dev_fec_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_udp_gso_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_qb_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_fd_forward_tc_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_ptp_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_int_ql_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_simple_bd_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_SIMPLE_BD_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_tx_push_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_phy_imp_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_tqp_txrx_indep_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_hw_pad_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps)
++
++#define hnae3_dev_stash_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
++
+ enum HNAE3_PF_CAP_BITS {
+ 	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
+ };
+@@ -288,6 +338,7 @@ struct hnae3_client {
+ 	struct list_head node;
+ };
+ 
++#define HNAE3_DEV_CAPS_MAX_NUM	96
+ struct hnae3_ae_dev {
+ 	struct pci_dev *pdev;
+ 	const struct hnae3_ae_ops *ops;
+@@ -295,6 +346,7 @@ struct hnae3_ae_dev {
+ 	u32 flag;
+ 	unsigned long hw_err_reset_req;
+ 	u32 dev_version;
++	unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)];
+ 	void *priv;
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index e38fb6ef3e75..2eb3aac3c711 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1385,7 +1385,7 @@ static int hns3_get_fecparam(struct net_device *netdev,
+ 	u8 fec_ability;
+ 	u8 fec_mode;
+ 
+-	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
++	if (!test_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps))
+ 		return -EOPNOTSUPP;
+ 
+ 	if (!ops->get_fec)
+@@ -1407,7 +1407,7 @@ static int hns3_set_fecparam(struct net_device *netdev,
+ 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
+ 	u32 fec_mode;
+ 
+-	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
++	if (!test_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps))
+ 		return -EOPNOTSUPP;
+ 
+ 	if (!ops->set_fec)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index d9c4e82b0d21..d1e963195259 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -346,6 +346,33 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
+ 	return retval;
+ }
+ 
++static void hclge_set_default_capability(struct hclge_dev *hdev)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++
++	set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
++	set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);
++	set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
++}
++
++static void hclge_parse_capability(struct hclge_dev *hdev,
++				   struct hclge_query_version_cmd *cmd)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	u32 caps;
++
++	caps = __le32_to_cpu(cmd->caps[0]);
++
++	if (hnae3_get_bit(caps, HCLGE_CAP_UDP_GSO_B))
++		set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGE_CAP_PTP_B))
++		set_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGE_CAP_INT_QL_B))
++		set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGE_CAP_TQP_TXRX_INDEP_B))
++		set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
++}
++
+ static enum hclge_cmd_status
+ hclge_cmd_query_version_and_capability(struct hclge_dev *hdev)
+ {
+@@ -367,11 +394,10 @@ hclge_cmd_query_version_and_capability(struct hclge_dev *hdev)
+ 					  HNAE3_PCI_REVISION_BIT_SIZE;
+ 	ae_dev->dev_version |= hdev->pdev->revision;
+ 
+-	if (!resp->caps[0] &&
+-	    ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+-		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
+-		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
+-	}
++	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
++		hclge_set_default_capability(hdev);
++
++	hclge_parse_capability(hdev, resp);
+ 
+ 	return ret;
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index d565633abab3..bd4238f3009c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -369,6 +369,20 @@ struct hclge_rx_priv_buff_cmd {
+ 	u8 rsv[6];
+ };
+ 
++enum HCLGE_CAP_BITS {
++	HCLGE_CAP_UDP_GSO_B,
++	HCLGE_CAP_QB_B,
++	HCLGE_CAP_FD_FORWARD_TC_B,
++	HCLGE_CAP_PTP_B,
++	HCLGE_CAP_INT_QL_B,
++	HCLGE_CAP_SIMPLE_BD_B,
++	HCLGE_CAP_TX_PUSH_B,
++	HCLGE_CAP_PHY_IMP_B,
++	HCLGE_CAP_TQP_TXRX_INDEP_B,
++	HCLGE_CAP_HW_PAD_B,
++	HCLGE_CAP_STASH_B,
++};
++
+ #define HCLGE_QUERY_CAP_LENGTH		3
+ struct hclge_query_version_cmd {
+ 	__le32 firmware;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 20db8fb98604..d120211c3ef5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -329,6 +329,31 @@ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
+ 	return status;
+ }
+ 
++static void hclgevf_set_default_capability(struct hclgevf_dev *hdev)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++
++	set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
++	set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);
++	set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
++}
++
++static void hclgevf_parse_capability(struct hclgevf_dev *hdev,
++				     struct hclgevf_query_version_cmd *cmd)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	u32 caps;
++
++	caps = __le32_to_cpu(cmd->caps[0]);
++
++	if (hnae3_get_bit(caps, HCLGEVF_CAP_UDP_GSO_B))
++		set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGEVF_CAP_INT_QL_B))
++		set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGEVF_CAP_TQP_TXRX_INDEP_B))
++		set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
++}
++
+ static int hclgevf_cmd_query_version_and_capability(struct hclgevf_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+@@ -349,11 +374,10 @@ static int hclgevf_cmd_query_version_and_capability(struct hclgevf_dev *hdev)
+ 				HNAE3_PCI_REVISION_BIT_SIZE;
+ 	ae_dev->dev_version |= hdev->pdev->revision;
+ 
+-	if (!resp->caps[0] &&
+-	    ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+-		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
+-		hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
+-	}
++	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
++		hclgevf_set_default_capability(hdev);
++
++	hclgevf_parse_capability(hdev, resp);
+ 
+ 	return status;
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index b59ca89f52cc..0d1690d9fecf 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -142,6 +142,20 @@ struct hclgevf_ctrl_vector_chain {
+ 	u8 resv;
+ };
+ 
++enum HCLGEVF_CAP_BITS {
++	HCLGEVF_CAP_UDP_GSO_B,
++	HCLGEVF_CAP_QB_B,
++	HCLGEVF_CAP_FD_FORWARD_TC_B,
++	HCLGEVF_CAP_PTP_B,
++	HCLGEVF_CAP_INT_QL_B,
++	HCLGEVF_CAP_SIMPLE_BD_B,
++	HCLGEVF_CAP_TX_PUSH_B,
++	HCLGEVF_CAP_PHY_IMP_B,
++	HCLGEVF_CAP_TQP_TXRX_INDEP_B,
++	HCLGEVF_CAP_HW_PAD_B,
++	HCLGEVF_CAP_STASH_B,
++};
++
+ #define HCLGEVF_QUERY_CAP_LENGTH		3
+ struct hclgevf_query_version_cmd {
+ 	__le32 firmware;
+-- 
+2.34.1
+
diff --git a/patches/0397-net-hns3-add-UDP-segmentation-offload-support.patch b/patches/0397-net-hns3-add-UDP-segmentation-offload-support.patch
new file mode 100644
index 0000000..0b15df8
--- /dev/null
+++ b/patches/0397-net-hns3-add-UDP-segmentation-offload-support.patch
@@ -0,0 +1,73 @@
+From c50c8d104add5d3d4c9a8cf5de7aa26f3088cb38 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Tue, 29 Sep 2020 17:32:01 +0800
+Subject: [PATCH 036/283] net: hns3: add UDP segmentation offload support
+
+mainline inclusion
+from mainline-v5.10-rc1
+commit 0692cfe94a760d17793d2e1c8ca2fe10118e55de
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0692cfe94a760d17793d2e1c8ca2fe10118e55de
+
+--------------------------------
+
+Add support for UDP segmentation offload to the HNS3 driver
+when the device can do it.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 21 ++++++++++++++-----
+ 1 file changed, 16 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index f55dd10ab554..a06c01cd3efe 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -674,12 +674,19 @@ static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
+ 
+ 	/* normal or tunnel packet */
+ 	l4_offset = l4.hdr - skb->data;
+-	hdr_len = (l4.tcp->doff << 2) + l4_offset;
+ 
+ 	/* remove payload length from inner pseudo checksum when tso */
+ 	l4_paylen = skb->len - l4_offset;
+-	csum_replace_by_diff(&l4.tcp->check,
+-			     (__force __wsum)htonl(l4_paylen));
++
++	if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
++		hdr_len = sizeof(*l4.udp) + l4_offset;
++		csum_replace_by_diff(&l4.udp->check,
++				     (__force __wsum)htonl(l4_paylen));
++	} else {
++		hdr_len = (l4.tcp->doff << 2) + l4_offset;
++		csum_replace_by_diff(&l4.tcp->check,
++				     (__force __wsum)htonl(l4_paylen));
++	}
+ 
+ 	*send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
+ 
+@@ -2425,8 +2432,12 @@ static void hns3_set_default_feature(struct net_device *netdev)
+ 		}
+ 	}
+ 
+-	if (hnae3_get_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B))
+-		netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
++	if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) {
++		netdev->hw_features |= NETIF_F_GSO_UDP_L4;
++		netdev->features |= NETIF_F_GSO_UDP_L4;
++		netdev->vlan_features |= NETIF_F_GSO_UDP_L4;
++		netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4;
++	}
+ }
+ 
+ static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
+-- 
+2.34.1
+
diff --git a/patches/0398-net-hns3-initialize-the-message-content-in-hclge_get.patch b/patches/0398-net-hns3-initialize-the-message-content-in-hclge_get.patch
new file mode 100644
index 0000000..460bc67
--- /dev/null
+++ b/patches/0398-net-hns3-initialize-the-message-content-in-hclge_get.patch
@@ -0,0 +1,51 @@
+From b86c90458d7f560c59dc9d7cd6bb15eb27c60e55 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Tue, 25 May 2021 15:30:01 +0000
+Subject: [PATCH 037/283] net: hns3: initialize the message content in
+ hclge_get_link_mode()
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit 568a54bdf70b143f3e0befa298e22ad469ffc732
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=568a54bdf70b143f3e0befa298e22ad469ffc732
+
+--------------------------------
+
+[ Upstream commit 568a54bdf70b143f3e0befa298e22ad469ffc732 ]
+
+The message sent to VF should be initialized, otherwise random
+value of some contents may cause improper processing by the target.
+So add a initialization to message in hclge_get_link_mode().
+
+Fixes: 9194d18b0577 ("net: hns3: fix the problem that the supported port is empty")
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Acked-by: Weilong Chen <chenweilong@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+index 893f6e0ce473..ff283ac443e5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+@@ -583,7 +583,7 @@ static void hclge_get_link_mode(struct hclge_vport *vport,
+ 	unsigned long advertising;
+ 	unsigned long supported;
+ 	unsigned long send_data;
+-	u8 msg_data[10];
++	u8 msg_data[10] = {};
+ 	u8 dest_vfid;
+ 
+ 	memset(msg_data, 0, sizeof(msg_data));
+-- 
+2.34.1
+
diff --git a/patches/0399-net-hns3-add-support-for-TX-hardware-checksum-offloa.patch b/patches/0399-net-hns3-add-support-for-TX-hardware-checksum-offloa.patch
new file mode 100644
index 0000000..ff5f5a2
--- /dev/null
+++ b/patches/0399-net-hns3-add-support-for-TX-hardware-checksum-offloa.patch
@@ -0,0 +1,343 @@
+From f697e257f1481fdbbc7d4ac580ee606d2ee760c5 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Fri, 16 Jul 2021 13:23:28 +0800
+Subject: [PATCH 038/283] net: hns3: add support for TX hardware checksum
+ offload
+
+mainline inclusion
+from mainline-v5.11-rc1
+commit 66d52f3bf385c8d969e9ca6b281ddf773c9691d7
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=66d52f3bf385c8d969e9ca6b281ddf773c9691d7
+
+----------------------------------------------------------------------
+
+For the device that supports TX hardware checksum, the hardware
+can calculate the checksum from the start and fill the checksum
+to the offset position, which reduces the operations of
+calculating the type and header length of L3/L4. So add this
+feature for the HNS3 ethernet driver.
+
+The previous simple BD description is unsuitable, rename it as
+HW TX CSUM.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: li yongxin <liyongxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  6 +-
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    |  2 +-
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 63 +++++++++++++++----
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   | 10 ++-
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         |  2 +
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  2 +-
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       |  2 +
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       |  2 +-
+ 8 files changed, 71 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 7c00830b712e..509bf4f4de1d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -83,7 +83,7 @@ enum HNAE3_DEV_CAP_BITS {
+ 	HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B,
+ 	HNAE3_DEV_SUPPORT_PTP_B,
+ 	HNAE3_DEV_SUPPORT_INT_QL_B,
+-	HNAE3_DEV_SUPPORT_SIMPLE_BD_B,
++	HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
+ 	HNAE3_DEV_SUPPORT_TX_PUSH_B,
+ 	HNAE3_DEV_SUPPORT_PHY_IMP_B,
+ 	HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,
+@@ -118,8 +118,8 @@ enum HNAE3_DEV_CAP_BITS {
+ #define hnae3_dev_int_ql_supported(hdev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps)
+ 
+-#define hnae3_dev_simple_bd_supported(hdev) \
+-	test_bit(HNAE3_DEV_SUPPORT_SIMPLE_BD_B, (hdev)->ae_dev->caps)
++#define hnae3_dev_hw_csum_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, (hdev)->ae_dev->caps)
+ 
+ #define hnae3_dev_tx_push_supported(hdev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 8dbbf597d8a2..59d9dda8f325 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -684,7 +684,7 @@ static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv,
+ 		le32_to_cpu(desc->tx.ol_type_vlan_len_msec));
+ 	sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen));
+ 	sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri));
+-	sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.mss));
++	sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.mss_hw_csum));
+ }
+ 
+ static int hns3_dbg_tx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index a06c01cd3efe..3e3c5b27567e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -997,6 +997,22 @@ static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
+ 	return 0;
+ }
+ 
++/* check if the hardware is capable of checksum offloading */
++static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
++{
++	struct hns3_nic_priv *priv = netdev_priv(skb->dev);
++
++	/* Kindly note, due to backward compatibility of the TX descriptor,
++	 * HW checksum of the non-IP packets and GSO packets is handled at
++	 * different place in the following code
++	 */
++	if (skb->csum_not_inet || skb_is_gso(skb) ||
++	    !test_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state))
++		return false;
++
++	return true;
++}
++
+ static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
+ 			      struct sk_buff *skb, struct hns3_desc *desc,
+ 			      struct hns3_desc_cb *desc_cb)
+@@ -1004,9 +1020,9 @@ static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
+ 	u32 ol_type_vlan_len_msec = 0;
+ 	u32 type_cs_vlan_tso = 0;
+ 	u32 paylen = skb->len;
++	u16 mss_hw_csum = 0;
+ 	u16 inner_vtag = 0;
+ 	u16 out_vtag = 0;
+-	u16 mss = 0;
+ 	int ret;
+ 
+ 	ret = hns3_handle_vtags(ring, skb);
+@@ -1033,6 +1049,17 @@ static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
+ 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ 		u8 ol4_proto, il4_proto;
+ 
++		if (hns3_check_hw_tx_csum(skb)) {
++			/* set checksum start and offset, defined in 2 Bytes */
++			hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
++				       skb_checksum_start_offset(skb) >> 1);
++			hns3_set_field(ol_type_vlan_len_msec,
++				       HNS3_TXD_CSUM_OFFSET_S,
++				       skb->csum_offset >> 1);
++			mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
++			goto out_hw_tx_csum;
++		}
++
+ 		skb_reset_mac_len(skb);
+ 
+ 		ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
+@@ -1053,7 +1080,7 @@ static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
+ 			return ret;
+ 		}
+ 
+-		ret = hns3_set_tso(skb, &paylen, &mss,
++		ret = hns3_set_tso(skb, &paylen, &mss_hw_csum,
+ 				   &type_cs_vlan_tso, &desc_cb->send_bytes);
+ 		if (unlikely(ret < 0)) {
+ 			u64_stats_update_begin(&ring->syncp);
+@@ -1063,12 +1090,13 @@ static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
+ 		}
+ 	}
+ 
++out_hw_tx_csum:
+ 	/* Set txbd */
+ 	desc->tx.ol_type_vlan_len_msec =
+ 		cpu_to_le32(ol_type_vlan_len_msec);
+ 	desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
+ 	desc->tx.paylen = cpu_to_le32(paylen);
+-	desc->tx.mss = cpu_to_le16(mss);
++	desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum);
+ 	desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
+ 	desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
+ 
+@@ -2383,8 +2411,7 @@ static void hns3_set_default_feature(struct net_device *netdev)
+ 
+ 	netdev->priv_flags |= IFF_UNICAST_FLT;
+ 
+-	netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
+-		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
++	netdev->hw_enc_features |= NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
+ 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
+ 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
+ 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
+@@ -2396,8 +2423,7 @@ static void hns3_set_default_feature(struct net_device *netdev)
+ 	netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
+ #endif
+ 
+-	netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
+-		NETIF_F_HW_VLAN_CTAG_FILTER |
++	netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
+ 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
+ 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
+ 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
+@@ -2405,16 +2431,15 @@ static void hns3_set_default_feature(struct net_device *netdev)
+ 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
+ 		NETIF_F_FRAGLIST;
+ 
+-	netdev->vlan_features |=
+-		NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM |
++	netdev->vlan_features |= NETIF_F_RXCSUM |
+ 		NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
+ 		NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
+ 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
+ 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
+ 		NETIF_F_FRAGLIST;
+ 
+-	netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
+-		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
++	netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
++		NETIF_F_HW_VLAN_CTAG_RX |
+ 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
+ 		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
+ 		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
+@@ -2438,6 +2463,18 @@ static void hns3_set_default_feature(struct net_device *netdev)
+ 		netdev->vlan_features |= NETIF_F_GSO_UDP_L4;
+ 		netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4;
+ 	}
++
++	if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) {
++		netdev->hw_features |= NETIF_F_HW_CSUM;
++		netdev->features |= NETIF_F_HW_CSUM;
++		netdev->vlan_features |= NETIF_F_HW_CSUM;
++		netdev->hw_enc_features |= NETIF_F_HW_CSUM;
++	} else {
++		netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
++		netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
++		netdev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
++		netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
++	}
+ }
+ 
+ static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
+@@ -4147,6 +4184,7 @@ static void hns3_state_uninit(struct hnae3_handle *handle)
+ static int hns3_client_init(struct hnae3_handle *handle)
+ {
+ 	struct pci_dev *pdev = handle->pdev;
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
+ 	u16 alloc_tqps, max_rss_size;
+ 	struct hns3_nic_priv *priv;
+ 	struct net_device *netdev;
+@@ -4243,6 +4281,9 @@ static int hns3_client_init(struct hnae3_handle *handle)
+ 	netdev->max_mtu = HNS3_MAX_MTU;
+ #endif
+ 
++	if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
++		set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
++
+ 	set_bit(HNS3_NIC_STATE_INITED, &priv->state);
+ 
+ 	ret = register_netdev(netdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 0588642f906c..00a164343f0c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -18,6 +18,7 @@ enum hns3_nic_state {
+ 	HNS3_NIC_STATE_SERVICE_INITED,
+ 	HNS3_NIC_STATE_SERVICE_SCHED,
+ 	HNS3_NIC_STATE2_RESET_REQUESTED,
++	HNS3_NIC_STATE_HW_TX_CSUM_ENABLE,
+ 	HNS3_NIC_STATE_MAX
+ };
+ 
+@@ -142,6 +143,9 @@ enum hns3_nic_state {
+ #define HNS3_TXD_L4LEN_S			24
+ #define HNS3_TXD_L4LEN_M			(0xff << HNS3_TXD_L4LEN_S)
+ 
++#define HNS3_TXD_CSUM_START_S		8
++#define HNS3_TXD_CSUM_START_M		(0xffff << HNS3_TXD_CSUM_START_S)
++
+ #define HNS3_TXD_OL3T_S				0
+ #define HNS3_TXD_OL3T_M				(0x3 << HNS3_TXD_OL3T_S)
+ #define HNS3_TXD_OVLAN_B			2
+@@ -149,6 +153,9 @@ enum hns3_nic_state {
+ #define HNS3_TXD_TUNTYPE_S			4
+ #define HNS3_TXD_TUNTYPE_M			(0xf << HNS3_TXD_TUNTYPE_S)
+ 
++#define HNS3_TXD_CSUM_OFFSET_S		8
++#define HNS3_TXD_CSUM_OFFSET_M		(0xffff << HNS3_TXD_CSUM_OFFSET_S)
++
+ #define HNS3_TXD_BDTYPE_S			0
+ #define HNS3_TXD_BDTYPE_M			(0xf << HNS3_TXD_BDTYPE_S)
+ #define HNS3_TXD_FE_B				4
+@@ -164,6 +171,7 @@ enum hns3_nic_state {
+ 
+ #define HNS3_TXD_MSS_S				0
+ #define HNS3_TXD_MSS_M				(0x3fff << HNS3_TXD_MSS_S)
++#define HNS3_TXD_HW_CS_B			14
+ 
+ #define HNS3_VECTOR_TX_IRQ			BIT_ULL(0)
+ #define HNS3_VECTOR_RX_IRQ			BIT_ULL(1)
+@@ -254,7 +262,7 @@ struct __packed hns3_desc {
+ 
+ 			__le32 paylen;
+ 			__le16 bdtp_fe_sc_vld_ra_ri;
+-			__le16 mss;
++			__le16 mss_hw_csum;
+ 		} tx;
+ 
+ 		struct {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index d1e963195259..1b986185d145 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -371,6 +371,8 @@ static void hclge_parse_capability(struct hclge_dev *hdev,
+ 		set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
+ 	if (hnae3_get_bit(caps, HCLGE_CAP_TQP_TXRX_INDEP_B))
+ 		set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGE_CAP_HW_TX_CSUM_B))
++		set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
+ }
+ 
+ static enum hclge_cmd_status
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index bd4238f3009c..ed737e7d740a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -375,7 +375,7 @@ enum HCLGE_CAP_BITS {
+ 	HCLGE_CAP_FD_FORWARD_TC_B,
+ 	HCLGE_CAP_PTP_B,
+ 	HCLGE_CAP_INT_QL_B,
+-	HCLGE_CAP_SIMPLE_BD_B,
++	HCLGE_CAP_HW_TX_CSUM_B,
+ 	HCLGE_CAP_TX_PUSH_B,
+ 	HCLGE_CAP_PHY_IMP_B,
+ 	HCLGE_CAP_TQP_TXRX_INDEP_B,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index d120211c3ef5..d0bbbf213d06 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -352,6 +352,8 @@ static void hclgevf_parse_capability(struct hclgevf_dev *hdev,
+ 		set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
+ 	if (hnae3_get_bit(caps, HCLGEVF_CAP_TQP_TXRX_INDEP_B))
+ 		set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGEVF_CAP_HW_TX_CSUM_B))
++		set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
+ }
+ 
+ static int hclgevf_cmd_query_version_and_capability(struct hclgevf_dev *hdev)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 0d1690d9fecf..40632d8b6d79 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -148,7 +148,7 @@ enum HCLGEVF_CAP_BITS {
+ 	HCLGEVF_CAP_FD_FORWARD_TC_B,
+ 	HCLGEVF_CAP_PTP_B,
+ 	HCLGEVF_CAP_INT_QL_B,
+-	HCLGEVF_CAP_SIMPLE_BD_B,
++	HCLGEVF_CAP_HW_TX_CSUM_B,
+ 	HCLGEVF_CAP_TX_PUSH_B,
+ 	HCLGEVF_CAP_PHY_IMP_B,
+ 	HCLGEVF_CAP_TQP_TXRX_INDEP_B,
+-- 
+2.34.1
+
diff --git a/patches/0400-net-hns3-add-a-structure-for-IR-shaper-s-parameter-i.patch b/patches/0400-net-hns3-add-a-structure-for-IR-shaper-s-parameter-i.patch
new file mode 100644
index 0000000..7b7c37d
--- /dev/null
+++ b/patches/0400-net-hns3-add-a-structure-for-IR-shaper-s-parameter-i.patch
@@ -0,0 +1,272 @@
+From d2ce4553eb212e9b361ad185abdfb64e18c75c5c Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 17 Jun 2023 12:14:34 +0800
+Subject: [PATCH 039/283] net: hns3: add a structure for IR shaper's parameter
+ in hclge_shaper_para_calc()
+
+mainline inclusion
+from mainline-v5.10-rc1
+commit ff7e4d0df83b8029ee42d3dea5d1939b1ff5446f
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ff7e4d0df83b8029ee42d3dea5d1939b1ff5446f
+
+--------------------------------
+
+As function hclge_shaper_para_calc() has too many arguments to add
+more, so encapsulate its three arguments ir_b, ir_u, ir_s into a
+structure.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 71 ++++++++++---------
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.h |  6 ++
+ 2 files changed, 45 insertions(+), 32 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index f5b59c1c9435..b3564e38eba0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -28,9 +28,8 @@ enum hclge_shaper_level {
+ /* hclge_shaper_para_calc: calculate ir parameter for the shaper
+  * @ir: Rate to be config, its unit is Mbps
+  * @shaper_level: the shaper level. eg: port, pg, priority, queueset
+- * @ir_b: IR_B parameter of IR shaper
+- * @ir_u: IR_U parameter of IR shaper
+- * @ir_s: IR_S parameter of IR shaper
++ * @ir_para: parameters of IR shaper
++ * @max_tm_rate: max tm rate is available to config
+  *
+  * the formula:
+  *
+@@ -41,7 +40,7 @@ enum hclge_shaper_level {
+  * @return: 0: calculate sucessful, negative: fail
+  */
+ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
+-				  u8 *ir_b, u8 *ir_u, u8 *ir_s)
++				  struct hclge_shaper_ir_para *ir_para)
+ {
+ #define DIVISOR_CLK		(1000 * 8)
+ #define DIVISOR_IR_B_126	(126 * DIVISOR_CLK)
+@@ -74,10 +73,10 @@ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
+ 	ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
+ 
+ 	if (ir_calc == ir) {
+-		*ir_b = 126;
+-		*ir_u = 0;
+-		*ir_s = 0;
+-
++		ir_para->ir_b = 126;
++		ir_para->ir_u = 0;
++		ir_para->ir_s = 0;
++		
+ 		return 0;
+ 	} else if (ir_calc > ir) {
+ 		/* Increasing the denominator to select ir_s value */
+@@ -85,9 +84,9 @@ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
+ 			ir_s_calc++;
+ 			ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
+ 		}
++		ir_para->ir_b = (ir * tick * (1 << ir_s_calc) +
++				(DIVISOR_CLK >> 1)) / DIVISOR_CLK;
+ 
+-		*ir_b = (ir * tick * (1 << ir_s_calc) + (DIVISOR_CLK >> 1)) /
+-			DIVISOR_CLK;
+ 	} else {
+ 		/* Increasing the numerator to select ir_u value */
+ 		u32 numerator;
+@@ -99,15 +98,16 @@ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
+ 		}
+ 
+ 		if (ir_calc == ir) {
+-			*ir_b = 126;
++			ir_para->ir_b = 126;
+ 		} else {
+ 			u32 denominator = DIVISOR_CLK * (1 << --ir_u_calc);
+-			*ir_b = (ir * tick + (denominator >> 1)) / denominator;
++			ir_para->ir_b = (ir * tick + (denominator >> 1)) /
++					denominator;
+ 		}
+ 	}
+ 
+-	*ir_u = ir_u_calc;
+-	*ir_s = ir_s_calc;
++	ir_para->ir_u = ir_u_calc;
++	ir_para->ir_s = ir_s_calc;
+ 
+ 	return 0;
+ }
+@@ -400,21 +400,21 @@ static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
+ static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
+ {
+ 	struct hclge_port_shapping_cmd *shap_cfg_cmd;
++	struct hclge_shaper_ir_para ir_para;
+ 	struct hclge_desc desc;
+-	u8 ir_u, ir_b, ir_s;
+ 	u32 shapping_para;
+ 	int ret;
+ 
+-	ret = hclge_shaper_para_calc(hdev->hw.mac.speed,
+-				     HCLGE_SHAPER_LVL_PORT,
+-				     &ir_b, &ir_u, &ir_s);
++	ret = hclge_shaper_para_calc(hdev->hw.mac.speed, HCLGE_SHAPER_LVL_PORT,
++					&ir_para);
+ 	if (ret)
+ 		return ret;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false);
+ 	shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
+ 
+-	shapping_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
++	shapping_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
++						   ir_para.ir_s,
+ 						   HCLGE_SHAPER_BS_U_DEF,
+ 						   HCLGE_SHAPER_BS_S_DEF);
+ 
+@@ -515,6 +515,7 @@ int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate)
+ {
+ 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
+ 	struct hclge_qs_shapping_cmd *shap_cfg_cmd;
++	struct hclge_shaper_ir_para ir_para;
+ 	struct hclge_dev *hdev = vport->back;
+ 	struct hclge_desc desc;
+ 	u8 ir_b, ir_u, ir_s;
+@@ -525,11 +526,12 @@ int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate)
+ 		max_tx_rate = HCLGE_ETHER_MAX_RATE;
+ 
+ 	ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET,
+-				     &ir_b, &ir_u, &ir_s);
++				     &ir_para);
+ 	if (ret)
+ 		return ret;
+ 
+-	shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
++	shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
++						 ir_para.ir_s,
+ 						 HCLGE_SHAPER_BS_U_DEF,
+ 						 HCLGE_SHAPER_BS_S_DEF);
+ 
+@@ -754,7 +756,7 @@ static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev)
+ 
+ static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
+ {
+-	u8 ir_u, ir_b, ir_s;
++	struct hclge_shaper_ir_para ir_para;
+ 	u32 shaper_para;
+ 	int ret;
+ 	u32 i;
+@@ -769,7 +771,7 @@ static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
+ 		ret = hclge_shaper_para_calc(
+ 					hdev->tm_info.pg_info[i].bw_limit,
+ 					HCLGE_SHAPER_LVL_PG,
+-					&ir_b, &ir_u, &ir_s);
++					&ir_para);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -782,7 +784,9 @@ static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
+ 		if (ret)
+ 			return ret;
+ 
+-		shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
++		shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
++							 ir_para.ir_u,
++							 ir_para.ir_s,
+ 							 HCLGE_SHAPER_BS_U_DEF,
+ 							 HCLGE_SHAPER_BS_S_DEF);
+ 		ret = hclge_tm_pg_shapping_cfg(hdev,
+@@ -885,7 +889,7 @@ static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)
+ 
+ static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
+ {
+-	u8 ir_u, ir_b, ir_s;
++	struct hclge_shaper_ir_para ir_para;
+ 	u32 shaper_para;
+ 	int ret;
+ 	u32 i;
+@@ -894,7 +898,7 @@ static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
+ 		ret = hclge_shaper_para_calc(
+ 					hdev->tm_info.tc_info[i].bw_limit,
+ 					HCLGE_SHAPER_LVL_PRI,
+-					&ir_b, &ir_u, &ir_s);
++					&ir_para);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -906,7 +910,9 @@ static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
+ 		if (ret)
+ 			return ret;
+ 
+-		shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
++		shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b,
++							 ir_para.ir_u,
++							 ir_para.ir_s,
+ 							 HCLGE_SHAPER_BS_U_DEF,
+ 							 HCLGE_SHAPER_BS_S_DEF);
+ 		ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i,
+@@ -921,12 +927,12 @@ static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
+ static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport)
+ {
+ 	struct hclge_dev *hdev = vport->back;
+-	u8 ir_u, ir_b, ir_s;
++	struct hclge_shaper_ir_para ir_para;
+ 	u32 shaper_para;
+ 	int ret;
+ 
+ 	ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF,
+-				     &ir_b, &ir_u, &ir_s);
++				     &ir_para);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -938,7 +944,8 @@ static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport)
+ 	if (ret)
+ 		return ret;
+ 
+-	shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
++	shaper_para = hclge_tm_get_shapping_para(ir_para.ir_b, ir_para.ir_u,
++						 ir_para.ir_s,
+ 						 HCLGE_SHAPER_BS_U_DEF,
+ 						 HCLGE_SHAPER_BS_S_DEF);
+ 	ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET,
+@@ -953,7 +960,7 @@ static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport)
+ {
+ 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
+ 	struct hclge_dev *hdev = vport->back;
+-	u8 ir_u, ir_b, ir_s;
++	struct hclge_shaper_ir_para ir_para;
+ 	u32 i;
+ 	int ret;
+ 
+@@ -961,7 +968,7 @@ static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport)
+ 		ret = hclge_shaper_para_calc(
+ 					hdev->tm_info.tc_info[i].bw_limit,
+ 					HCLGE_SHAPER_LVL_QSET,
+-					&ir_b, &ir_u, &ir_s);
++					&ir_para);
+ 		if (ret)
+ 			return ret;
+ 	}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+index f172ce32af20..f2dfffbba8c8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+@@ -166,6 +166,12 @@ struct hclge_tm_shaper_para {
+ 	u8 flag;
+ };
+ 
++struct hclge_shaper_ir_para {
++	u8 ir_b; /* IR_B parameter of IR shaper */
++	u8 ir_u; /* IR_U parameter of IR shaper */
++	u8 ir_s; /* IR_S parameter of IR shaper */
++};
++
+ #define hclge_tm_set_field(dest, string, val) \
+ 			   hnae3_set_field((dest), \
+ 			   (HCLGE_TM_SHAP_##string##_MSK), \
+-- 
+2.34.1
+
diff --git a/patches/0401-net-hns3-remove-the-shaper-param-magic-number.patch b/patches/0401-net-hns3-remove-the-shaper-param-magic-number.patch
new file mode 100644
index 0000000..83412cd
--- /dev/null
+++ b/patches/0401-net-hns3-remove-the-shaper-param-magic-number.patch
@@ -0,0 +1,89 @@
+From cfcca4d7c0378e05efb0d33a5f9e5af32e76194c Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:23 +0800
+Subject: [PATCH 040/283] net: hns3: remove the shaper param magic number
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 9d2a1cea6997ecd4f05833dfffb9907ffaa41bf5
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9d2a1cea6997ecd4f05833dfffb9907ffaa41bf5
+
+----------------------------------------------------------------------
+
+To make the code more readable, this patch adds a definition for
+the magic number 126 used for the default shaper param ir_b, and
+rename macro DIVISOR_IR_B_126.
+
+No functional change.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c  | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index b3564e38eba0..14e8a93bdc31 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -42,8 +42,9 @@ enum hclge_shaper_level {
+ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
+ 				  struct hclge_shaper_ir_para *ir_para)
+ {
++#define DEFAULT_SHAPER_IR_B	126
+ #define DIVISOR_CLK		(1000 * 8)
+-#define DIVISOR_IR_B_126	(126 * DIVISOR_CLK)
++#define DEFAULT_DIVISOR_IR_B	(DEFAULT_SHAPER_IR_B * DIVISOR_CLK)
+ 
+ 	static const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = {
+ 		6 * 256,        /* Prioriy level */
+@@ -70,10 +71,10 @@ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
+ 	 * ir_calc = ---------------- * 1000
+ 	 *		tick * 1
+ 	 */
+-	ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
++	ir_calc = (DEFAULT_DIVISOR_IR_B + (tick >> 1) - 1) / tick;
+ 
+ 	if (ir_calc == ir) {
+-		ir_para->ir_b = 126;
++		ir_para->ir_b = DEFAULT_SHAPER_IR_B;
+ 		ir_para->ir_u = 0;
+ 		ir_para->ir_s = 0;
+ 		
+@@ -82,7 +83,8 @@ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
+ 		/* Increasing the denominator to select ir_s value */
+ 		while (ir_calc >= ir && ir) {
+ 			ir_s_calc++;
+-			ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
++			ir_calc = DEFAULT_DIVISOR_IR_B /
++				  (tick * (1 << ir_s_calc));
+ 		}
+ 		ir_para->ir_b = (ir * tick * (1 << ir_s_calc) +
+ 				(DIVISOR_CLK >> 1)) / DIVISOR_CLK;
+@@ -93,12 +95,12 @@ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
+ 
+ 		while (ir_calc < ir) {
+ 			ir_u_calc++;
+-			numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc);
++			numerator = DEFAULT_DIVISOR_IR_B * (1 << ir_u_calc);
+ 			ir_calc = (numerator + (tick >> 1)) / tick;
+ 		}
+ 
+ 		if (ir_calc == ir) {
+-			ir_para->ir_b = 126;
++			ir_para->ir_b = DEFAULT_SHAPER_IR_B;
+ 		} else {
+ 			u32 denominator = DIVISOR_CLK * (1 << --ir_u_calc);
+ 			ir_para->ir_b = (ir * tick + (denominator >> 1)) /
+-- 
+2.34.1
+
diff --git a/patches/0402-net-hns3-clean-up-unnecessary-parentheses-in-macro-d.patch b/patches/0402-net-hns3-clean-up-unnecessary-parentheses-in-macro-d.patch
new file mode 100644
index 0000000..5733a2c
--- /dev/null
+++ b/patches/0402-net-hns3-clean-up-unnecessary-parentheses-in-macro-d.patch
@@ -0,0 +1,196 @@
+From a52f2923c4b1884ad5ac32d962c54c91d0648eac Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:24 +0800
+Subject: [PATCH 041/283] net: hns3: clean up unnecessary parentheses in macro
+ definitions
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 9393eb5034a040931120f9c6eed9bf0e78029192
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9393eb5034a040931120f9c6eed9bf0e78029192
+
+----------------------------------------------------------------------
+
+In macro definitions, parentheses are unnecessary in some cases,
+such as the calling parameter of a function, the left variable
+of the equal sign, and so on. So remove these unnecessary
+parentheses according to these rules.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h            |  6 +++---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c        |  4 ++--
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h        | 10 +++++-----
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h |  4 ++--
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h    |  2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h  |  6 +++---
+ .../net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h   |  4 ++--
+ 7 files changed, 18 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 509bf4f4de1d..eef5f7a5eb63 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -317,7 +317,7 @@ struct hnae3_ring_chain_node {
+ };
+ 
+ #define HNAE3_IS_TX_RING(node) \
+-	(((node)->flag & (1 << HNAE3_RING_TYPE_B)) == HNAE3_RING_TYPE_TX)
++	(((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX)
+ 
+ struct hnae3_client_ops {
+ 	int (*init_instance)(struct hnae3_handle *handle);
+@@ -832,9 +832,9 @@ struct hnae3_handle {
+ #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift))
+ 
+ #define hnae3_set_bit(origin, shift, val) \
+-	hnae3_set_field((origin), (0x1 << (shift)), (shift), (val))
++	hnae3_set_field(origin, 0x1 << (shift), shift, val)
+ #define hnae3_get_bit(origin, shift) \
+-	hnae3_get_field((origin), (0x1 << (shift)), (shift))
++	hnae3_get_field(origin, 0x1 << (shift), shift)
+ 
+ int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
+ void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 3e3c5b27567e..d2284ce2c250 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -31,8 +31,8 @@
+ #define CREATE_TRACE_POINTS
+ #include "hns3_trace.h"
+ 
+-#define hns3_set_field(origin, shift, val)	((origin) |= ((val) << (shift)))
+-#define hns3_tx_bd_count(S)		DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
++#define hns3_set_field(origin, shift, val)	((origin) |= (val) << (shift))
++#define hns3_tx_bd_count(S)	DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
+ 
+ #define hns3_rl_err(fmt, ...)						\
+ 	do {								\
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 00a164343f0c..c337e4dbe2c6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -548,7 +548,7 @@ static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
+ }
+ 
+ #define hns3_read_dev(a, reg) \
+-	hns3_read_reg((a)->io_base, (reg))
++	hns3_read_reg((a)->io_base, reg)
+ 
+ static inline bool hns3_nic_resetting(struct net_device *netdev)
+ {
+@@ -558,7 +558,7 @@ static inline bool hns3_nic_resetting(struct net_device *netdev)
+ }
+ 
+ #define hns3_write_dev(a, reg, value) \
+-	hns3_write_reg((a)->io_base, (reg), (value))
++	hns3_write_reg((a)->io_base, reg, value)
+ 
+ #define ring_to_dev(ring) ((ring)->dev)
+ 
+@@ -589,15 +589,15 @@ static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
+ 
+ /* iterator for handling rings in ring group */
+ #define hns3_for_each_ring(pos, head) \
+-	for (pos = (head).ring; pos; pos = pos->next)
++	for (pos = (head).ring; (pos); pos = (pos)->next)
+ 
+ #define hns3_get_handle(ndev) \
+ 	(((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
+ 
+-#define hns3_gl_usec_to_reg(int_gl) (int_gl >> 1)
++#define hns3_gl_usec_to_reg(int_gl) ((int_gl) >> 1)
+ #define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
+ 
+-#define hns3_rl_usec_to_reg(int_rl) (int_rl >> 2)
++#define hns3_rl_usec_to_reg(int_rl) ((int_rl) >> 2)
+ #define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
+ 
+ void hns3_ethtool_set_ops(struct net_device *netdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index ed737e7d740a..e6727366028e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -1132,9 +1132,9 @@ static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
+ }
+ 
+ #define hclge_write_dev(a, reg, value) \
+-	hclge_write_reg((a)->io_base, (reg), (value))
++	hclge_write_reg((a)->io_base, reg, value)
+ #define hclge_read_dev(a, reg) \
+-	hclge_read_reg((a)->io_base, (reg))
++	hclge_read_reg((a)->io_base, reg)
+ 
+ static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
+ {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index c5cad1122788..cd98f4821641 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -743,7 +743,7 @@ struct hclge_vf_vlan_cfg {
+  *	x = (~k) & v
+  *	y = (k ^ ~v) & k
+  */
+-#define calc_x(x, k, v) ((x) = (~(k) & (v)))
++#define calc_x(x, k, v) (x = ~(k) & (v))
+ #define calc_y(y, k, v) \
+ 	do { \
+ 		const typeof(k) _k_ = (k); \
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+index f2dfffbba8c8..f4fb9c7e9c5f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+@@ -17,7 +17,7 @@
+ 
+ /* SP or DWRR */
+ #define HCLGE_TM_TX_SCHD_DWRR_MSK	BIT(0)
+-#define HCLGE_TM_TX_SCHD_SP_MSK		(0xFE)
++#define HCLGE_TM_TX_SCHD_SP_MSK		0xFE
+ 
+ #define HCLGE_TM_PF_MAX_PRI_NUM		8
+ #define HCLGE_TM_PF_MAX_QSET_NUM	8
+@@ -177,8 +177,8 @@ struct hclge_shaper_ir_para {
+ 			   (HCLGE_TM_SHAP_##string##_MSK), \
+ 			   (HCLGE_TM_SHAP_##string##_LSH), val)
+ #define hclge_tm_get_field(src, string) \
+-			hnae3_get_field((src), (HCLGE_TM_SHAP_##string##_MSK), \
+-				       (HCLGE_TM_SHAP_##string##_LSH))
++			hnae3_get_field((src), HCLGE_TM_SHAP_##string##_MSK, \
++					HCLGE_TM_SHAP_##string##_LSH)
+ 
+ int hclge_tm_schd_init(struct hclge_dev *hdev);
+ int hclge_tm_vport_map_update(struct hclge_dev *hdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 40632d8b6d79..cb502d88af5f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -286,9 +286,9 @@ static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg)
+ }
+ 
+ #define hclgevf_write_dev(a, reg, value) \
+-	hclgevf_write_reg((a)->io_base, (reg), (value))
++	hclgevf_write_reg((a)->io_base, reg, value)
+ #define hclgevf_read_dev(a, reg) \
+-	hclgevf_read_reg((a)->io_base, (reg))
++	hclgevf_read_reg((a)->io_base, reg)
+ 
+ #define HCLGEVF_SEND_SYNC(flag) \
+ 	((flag) & HCLGEVF_CMD_FLAG_NO_INTR)
+-- 
+2.34.1
+
diff --git a/patches/0403-net-hns3-change-hclge_parse_speed-param-type.patch b/patches/0403-net-hns3-change-hclge_parse_speed-param-type.patch
new file mode 100644
index 0000000..dea482e
--- /dev/null
+++ b/patches/0403-net-hns3-change-hclge_parse_speed-param-type.patch
@@ -0,0 +1,46 @@
+From 2c11c385ef2ec0799953db5568a81a6d70bc8002 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:26 +0800
+Subject: [PATCH 042/283] net: hns3: change hclge_parse_speed() param type
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 6e7f109ee9d8ed94a8c403e4daf34e752602148b
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6e7f109ee9d8ed94a8c403e4daf34e752602148b
+
+----------------------------------------------------------------------
+
+The type of parameters in hclge_parse_speed() should be
+unsigned type, so change them.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 307907896ff4..a7fa93715f73 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -939,7 +939,7 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
+ 	return 0;
+ }
+ 
+-static int hclge_parse_speed(int speed_cmd, int *speed)
++static int hclge_parse_speed(u8 speed_cmd, u32 *speed)
+ {
+ 	switch (speed_cmd) {
+ 	case 6:
+-- 
+2.34.1
+
diff --git a/patches/0404-net-hns3-change-hclge_query_bd_num-param-type.patch b/patches/0404-net-hns3-change-hclge_query_bd_num-param-type.patch
new file mode 100644
index 0000000..3c01a2f
--- /dev/null
+++ b/patches/0404-net-hns3-change-hclge_query_bd_num-param-type.patch
@@ -0,0 +1,56 @@
+From 789c7d8513f196c27f42ef08e98719743c0d95bb Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:27 +0800
+Subject: [PATCH 043/283] net: hns3: change hclge_query_bd_num() param type
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit cad8dfe82a9eb8d889cc550ceb8e61112376ae6f
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cad8dfe82a9eb8d889cc550ceb8e61112376ae6f
+
+----------------------------------------------------------------------
+
+The type of parameter mpf_bd_num and pf_bd_num in
+hclge_query_bd_num() should be u32* instead of int*,
+so change them.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 55990ba4b30e..9265243fbb84 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -1074,7 +1074,7 @@ static int hclge_config_ssu_hw_err_int(struct hclge_dev *hdev, bool en)
+  * This function querys number of mpf and pf buffer descriptors.
+  */
+ static int hclge_query_bd_num(struct hclge_dev *hdev, bool is_ras,
+-			      int *mpf_bd_num, int *pf_bd_num)
++			      u32 *mpf_bd_num, u32 *pf_bd_num)
+ {
+ 	struct device *dev = &hdev->pdev->dev;
+ 	u32 mpf_min_bd_num, pf_min_bd_num;
+@@ -1103,7 +1103,7 @@ static int hclge_query_bd_num(struct hclge_dev *hdev, bool is_ras,
+ 	*mpf_bd_num = le32_to_cpu(desc_bd.data[0]);
+ 	*pf_bd_num = le32_to_cpu(desc_bd.data[1]);
+ 	if (*mpf_bd_num < mpf_min_bd_num || *pf_bd_num < pf_min_bd_num) {
+-		dev_err(dev, "Invalid bd num: mpf(%d), pf(%d)\n",
++		dev_err(dev, "Invalid bd num: mpf(%u), pf(%u)\n",
+ 			*mpf_bd_num, *pf_bd_num);
+ 		return -EINVAL;
+ 	}
+-- 
+2.34.1
+
diff --git a/patches/0405-net-hns3-remove-unused-macro-definition.patch b/patches/0405-net-hns3-remove-unused-macro-definition.patch
new file mode 100644
index 0000000..f9a499e
--- /dev/null
+++ b/patches/0405-net-hns3-remove-unused-macro-definition.patch
@@ -0,0 +1,65 @@
+From 7ae37b7ed54610c699e1c217f6cec32a2cf11ce7 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:30 +0800
+Subject: [PATCH 044/283] net: hns3: remove unused macro definition
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 7ceb40b8207ea4aefed96c6dd22625b93aa121f9
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7ceb40b8207ea4aefed96c6dd22625b93aa121f9
+
+----------------------------------------------------------------------
+
+Some macros are defined but unused, so remove them.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h  | 3 ---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h | 1 -
+ 2 files changed, 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index cd98f4821641..138358b3b16b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -44,15 +44,12 @@
+ #define HCLGE_CMDQ_RX_DEPTH_REG		0x27020
+ #define HCLGE_CMDQ_RX_TAIL_REG		0x27024
+ #define HCLGE_CMDQ_RX_HEAD_REG		0x27028
+-#define HCLGE_CMDQ_INTR_SRC_REG		0x27100
+ #define HCLGE_CMDQ_INTR_STS_REG		0x27104
+ #define HCLGE_CMDQ_INTR_EN_REG		0x27108
+ #define HCLGE_CMDQ_INTR_GEN_REG		0x2710C
+ 
+ /* bar registers for common func */
+ #define HCLGE_VECTOR0_OTER_EN_REG	0x20600
+-#define HCLGE_RAS_OTHER_STS_REG		0x20B00
+-#define HCLGE_FUNC_RESET_STS_REG	0x20C00
+ #define HCLGE_GRO_EN_REG		0x28000
+ 
+ /* bar registers for rcb */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index cb502d88af5f..7d021cb394c5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -269,7 +269,6 @@ struct hclgevf_cfg_tx_queue_pointer_cmd {
+ 
+ #define HCLGEVF_NIC_CMQ_DESC_NUM	1024
+ #define HCLGEVF_NIC_CMQ_DESC_NUM_S	3
+-#define HCLGEVF_NIC_CMDQ_INT_SRC_REG	0x27100
+ 
+ #define HCLGEVF_RING_BASEADDR_SHIFT   32
+ 
+-- 
+2.34.1
+
diff --git a/patches/0406-net-hns3-refactor-out-hclge_cmd_convert_err_code.patch b/patches/0406-net-hns3-refactor-out-hclge_cmd_convert_err_code.patch
new file mode 100644
index 0000000..130cb7e
--- /dev/null
+++ b/patches/0406-net-hns3-refactor-out-hclge_cmd_convert_err_code.patch
@@ -0,0 +1,102 @@
+From c01583344fb7e63df204849214c1a8da0c033e03 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:33 +0800
+Subject: [PATCH 045/283] net: hns3: refactor out hclge_cmd_convert_err_code()
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 1c9a98b0ba1f16490ea0d492a1cd606f3a4b1bee
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1c9a98b0ba1f16490ea0d492a1cd606f3a4b1bee
+
+----------------------------------------------------------------------
+
+To improve code readability and maintainability, refactor
+hclge_cmd_convert_err_code() with an array of imp_errcode
+and common_errno mapping, instead of a bloated switch/case.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         | 55 +++++++++----------
+ 1 file changed, 27 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 1b986185d145..5f0c645eb292 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -205,36 +205,35 @@ static bool hclge_is_special_opcode(u16 opcode)
+ 	return false;
+ }
+ 
++struct errcode {
++	u32 imp_errcode;
++	int common_errno;
++};
++
+ static int hclge_cmd_convert_err_code(u16 desc_ret)
+ {
+-	switch (desc_ret) {
+-	case HCLGE_CMD_EXEC_SUCCESS:
+-		return 0;
+-	case HCLGE_CMD_NO_AUTH:
+-		return -EPERM;
+-	case HCLGE_CMD_NOT_SUPPORTED:
+-		return -EOPNOTSUPP;
+-	case HCLGE_CMD_QUEUE_FULL:
+-		return -EXFULL;
+-	case HCLGE_CMD_NEXT_ERR:
+-		return -ENOSR;
+-	case HCLGE_CMD_UNEXE_ERR:
+-		return -ENOTBLK;
+-	case HCLGE_CMD_PARA_ERR:
+-		return -EINVAL;
+-	case HCLGE_CMD_RESULT_ERR:
+-		return -ERANGE;
+-	case HCLGE_CMD_TIMEOUT:
+-		return -ETIME;
+-	case HCLGE_CMD_HILINK_ERR:
+-		return -ENOLINK;
+-	case HCLGE_CMD_QUEUE_ILLEGAL:
+-		return -ENXIO;
+-	case HCLGE_CMD_INVALID:
+-		return -EBADR;
+-	default:
+-		return -EIO;
+-	}
++	struct errcode hclge_cmd_errcode[] = {
++		{HCLGE_CMD_EXEC_SUCCESS, 0},
++		{HCLGE_CMD_NO_AUTH, -EPERM},
++		{HCLGE_CMD_NOT_SUPPORTED, -EOPNOTSUPP},
++		{HCLGE_CMD_QUEUE_FULL, -EXFULL},
++		{HCLGE_CMD_NEXT_ERR, -ENOSR},
++		{HCLGE_CMD_UNEXE_ERR, -ENOTBLK},
++		{HCLGE_CMD_PARA_ERR, -EINVAL},
++		{HCLGE_CMD_RESULT_ERR, -ERANGE},
++		{HCLGE_CMD_TIMEOUT, -ETIME},
++		{HCLGE_CMD_HILINK_ERR, -ENOLINK},
++		{HCLGE_CMD_QUEUE_ILLEGAL, -ENXIO},
++		{HCLGE_CMD_INVALID, -EBADR},
++	};
++	u32 errcode_count = ARRAY_SIZE(hclge_cmd_errcode);
++	u32 i;
++
++	for (i = 0; i < errcode_count; i++)
++		if (hclge_cmd_errcode[i].imp_errcode == desc_ret)
++			return hclge_cmd_errcode[i].common_errno;
++
++	return -EIO;
+ }
+ 
+ static int hclge_cmd_check_retval(struct hclge_hw *hw, struct hclge_desc *desc,
+-- 
+2.34.1
+
diff --git a/patches/0407-net-hns3-refactor-out-hclgevf_cmd_convert_err_code.patch b/patches/0407-net-hns3-refactor-out-hclgevf_cmd_convert_err_code.patch
new file mode 100644
index 0000000..7a6fcab
--- /dev/null
+++ b/patches/0407-net-hns3-refactor-out-hclgevf_cmd_convert_err_code.patch
@@ -0,0 +1,103 @@
+From 1bf6959cfefbdfa21139f1e04bbc36bdffcdeaa9 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:34 +0800
+Subject: [PATCH 046/283] net: hns3: refactor out
+ hclgevf_cmd_convert_err_code()
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 433e2802775c370604b74378c00977b86623fa12
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=433e2802775c370604b74378c00977b86623fa12
+
+----------------------------------------------------------------------
+
+To improve code readability and maintainability, refactor
+hclgevf_cmd_convert_err_code() with an array of imp_errcode
+and common_errno mapping, instead of a bloated switch/case.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       | 55 +++++++++----------
+ 1 file changed, 27 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index d0bbbf213d06..a09b63a031a5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -192,36 +192,35 @@ void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
+ 		desc->flag &= cpu_to_le16(~HCLGEVF_CMD_FLAG_WR);
+ }
+ 
++struct vf_errcode {
++	u32 imp_errcode;
++	int common_errno;
++};
++
+ static int hclgevf_cmd_convert_err_code(u16 desc_ret)
+ {
+-	switch (desc_ret) {
+-	case HCLGEVF_CMD_EXEC_SUCCESS:
+-		return 0;
+-	case HCLGEVF_CMD_NO_AUTH:
+-		return -EPERM;
+-	case HCLGEVF_CMD_NOT_SUPPORTED:
+-		return -EOPNOTSUPP;
+-	case HCLGEVF_CMD_QUEUE_FULL:
+-		return -EXFULL;
+-	case HCLGEVF_CMD_NEXT_ERR:
+-		return -ENOSR;
+-	case HCLGEVF_CMD_UNEXE_ERR:
+-		return -ENOTBLK;
+-	case HCLGEVF_CMD_PARA_ERR:
+-		return -EINVAL;
+-	case HCLGEVF_CMD_RESULT_ERR:
+-		return -ERANGE;
+-	case HCLGEVF_CMD_TIMEOUT:
+-		return -ETIME;
+-	case HCLGEVF_CMD_HILINK_ERR:
+-		return -ENOLINK;
+-	case HCLGEVF_CMD_QUEUE_ILLEGAL:
+-		return -ENXIO;
+-	case HCLGEVF_CMD_INVALID:
+-		return -EBADR;
+-	default:
+-		return -EIO;
+-	}
++	struct vf_errcode hclgevf_cmd_errcode[] = {
++		{HCLGEVF_CMD_EXEC_SUCCESS, 0},
++		{HCLGEVF_CMD_NO_AUTH, -EPERM},
++		{HCLGEVF_CMD_NOT_SUPPORTED, -EOPNOTSUPP},
++		{HCLGEVF_CMD_QUEUE_FULL, -EXFULL},
++		{HCLGEVF_CMD_NEXT_ERR, -ENOSR},
++		{HCLGEVF_CMD_UNEXE_ERR, -ENOTBLK},
++		{HCLGEVF_CMD_PARA_ERR, -EINVAL},
++		{HCLGEVF_CMD_RESULT_ERR, -ERANGE},
++		{HCLGEVF_CMD_TIMEOUT, -ETIME},
++		{HCLGEVF_CMD_HILINK_ERR, -ENOLINK},
++		{HCLGEVF_CMD_QUEUE_ILLEGAL, -ENXIO},
++		{HCLGEVF_CMD_INVALID, -EBADR},
++	};
++	u32 errcode_count = ARRAY_SIZE(hclgevf_cmd_errcode);
++	u32 i;
++
++	for (i = 0; i < errcode_count; i++)
++		if (hclgevf_cmd_errcode[i].imp_errcode == desc_ret)
++			return hclgevf_cmd_errcode[i].common_errno;
++
++	return -EIO;
+ }
+ 
+ /* hclgevf_cmd_send - send command to command queue
+-- 
+2.34.1
+
diff --git a/patches/0408-net-hns3-use-ipv6_addr_any-helper.patch b/patches/0408-net-hns3-use-ipv6_addr_any-helper.patch
new file mode 100644
index 0000000..e332567
--- /dev/null
+++ b/patches/0408-net-hns3-use-ipv6_addr_any-helper.patch
@@ -0,0 +1,74 @@
+From 7fbc8c268682d044347f911c7df4723ff237809b Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:36 +0800
+Subject: [PATCH 047/283] net: hns3: use ipv6_addr_any() helper
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit eaede835675cbae3b84309255f81e9a5e1b502a2
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=eaede835675cbae3b84309255f81e9a5e1b502a2
+
+----------------------------------------------------------------------
+
+Use common ipv6_addr_any() to determine if an addr is ipv6 any addr.
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 13 +++++--------
+ 1 file changed, 5 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index a7fa93715f73..f4421e6861cb 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -13,6 +13,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/if_vlan.h>
+ #include <linux/crash_dump.h>
++#include <net/ipv6.h>
+ #include <net/rtnetlink.h>
+ #include "kcompat.h"
+ #include "hclge_cmd.h"
+@@ -5426,12 +5427,10 @@ static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec,
+ 		BIT(INNER_IP_TOS);
+ 
+ 	/* check whether src/dst ip address used */
+-	if (!spec->ip6src[0] && !spec->ip6src[1] &&
+-	    !spec->ip6src[2] && !spec->ip6src[3])
++	if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
+ 		*unused_tuple |= BIT(INNER_SRC_IP);
+ 
+-	if (!spec->ip6dst[0] && !spec->ip6dst[1] &&
+-	    !spec->ip6dst[2] && !spec->ip6dst[3])
++	if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
+ 		*unused_tuple |= BIT(INNER_DST_IP);
+ 
+ 	if (!spec->psrc)
+@@ -5456,12 +5455,10 @@ static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec,
+ 		BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
+ 
+ 	/* check whether src/dst ip address used */
+-	if (!spec->ip6src[0] && !spec->ip6src[1] &&
+-	    !spec->ip6src[2] && !spec->ip6src[3])
++	if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
+ 		*unused_tuple |= BIT(INNER_SRC_IP);
+ 
+-	if (!spec->ip6dst[0] && !spec->ip6dst[1] &&
+-	    !spec->ip6dst[2] && !spec->ip6dst[3])
++	if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
+ 		*unused_tuple |= BIT(INNER_DST_IP);
+ 
+ 	if (!spec->l4_proto)
+-- 
+2.34.1
+
diff --git a/patches/0409-net-hns3-refactor-out-hclge_set_vf_vlan_common.patch b/patches/0409-net-hns3-refactor-out-hclge_set_vf_vlan_common.patch
new file mode 100644
index 0000000..cdd4d6d
--- /dev/null
+++ b/patches/0409-net-hns3-refactor-out-hclge_set_vf_vlan_common.patch
@@ -0,0 +1,190 @@
+From 3845cf59d67da6a4877d342fd3af9d3a09a6bbbc Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:37 +0800
+Subject: [PATCH 048/283] net: hns3: refactor out hclge_set_vf_vlan_common()
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 88936e320c1a9971b6b78a38e6bf737e43744f5e
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=88936e320c1a9971b6b78a38e6bf737e43744f5e
+
+----------------------------------------------------------------------
+
+To improve code readability and maintainability, separate
+the command handling part and the status parsing part from
+bloated hclge_set_vf_vlan_common().
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 71 ++++++++++++-------
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.c |  1 -
+ include/linux/ethtool.h                       |  2 +
+ 3 files changed, 49 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index f4421e6861cb..e26373b1f38e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -8447,31 +8447,16 @@ static int hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
+ 	return hclge_enable_vport_vlan_filter(vport, enable);
+ }
+ 
+-static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid,
+-				    bool is_kill, u16 vlan)
++static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid,
++					bool is_kill, u16 vlan,
++					struct hclge_desc *desc)
+ {
+-	struct hclge_vport *vport = &hdev->vport[vfid];
+ 	struct hclge_vlan_filter_vf_cfg_cmd *req0;
+ 	struct hclge_vlan_filter_vf_cfg_cmd *req1;
+-	struct hclge_desc desc[2];
+ 	u8 vf_byte_val;
+ 	u8 vf_byte_off;
+ 	int ret;
+ 
+-	/* if vf vlan table is full, firmware will close vf vlan filter, it
+-	 * is unable and unnecessary to add new vlan id to vf vlan filter.
+-	 * If spoof check is enable, and vf vlan is full, it shouldn't add
+-	 * new vlan, because tx packets with these vlan id will be dropped.
+-	 */
+-	if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) {
+-		if (vport->vf_info.spoofchk && vlan) {
+-			dev_err(&hdev->pdev->dev,
+-				"Can't add vlan due to spoof check is on and vf vlan table is full\n");
+-			return -EPERM;
+-		}
+-		return 0;
+-	}
+-
+ 	hclge_cmd_setup_basic_desc(&desc[0],
+ 				   HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
+ 	hclge_cmd_setup_basic_desc(&desc[1],
+@@ -8501,12 +8486,22 @@ static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid,
+ 		return ret;
+ 	}
+ 
++	return 0;
++}
++
++static int hclge_check_vf_vlan_cmd_status(struct hclge_dev *hdev, u16 vfid,
++					  bool is_kill, struct hclge_desc *desc)
++{
++	struct hclge_vlan_filter_vf_cfg_cmd *req;
++
++	req = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
++
+ 	if (!is_kill) {
+ #define HCLGE_VF_VLAN_NO_ENTRY	2
+-		if (!req0->resp_code || req0->resp_code == 1)
++		if (!req->resp_code || req->resp_code == 1)
+ 			return 0;
+ 
+-		if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
++		if (req->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
+ 			set_bit(vfid, hdev->vf_vlan_full);
+ 			dev_warn(&hdev->pdev->dev,
+ 				 "vf vlan table is full, vf vlan filter is disabled\n");
+@@ -8515,10 +8510,10 @@ static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid,
+ 
+ 		dev_err(&hdev->pdev->dev,
+ 			"Add vf vlan filter fail, ret =%u.\n",
+-			req0->resp_code);
++			req->resp_code);
+ 	} else {
+ #define HCLGE_VF_VLAN_DEL_NO_FOUND	1
+-		if (!req0->resp_code)
++		if (!req->resp_code)
+ 			return 0;
+ 
+ 		/* vf vlan filter is disabled when vf vlan table is full,
+@@ -8526,17 +8521,45 @@ static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid,
+ 		 * Just return 0 without warning, avoid massive verbose
+ 		 * print logs when unload.
+ 		 */
+-		if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND)
++		if (req->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND)
+ 			return 0;
+ 
+ 		dev_err(&hdev->pdev->dev,
+ 			"Kill vf vlan filter fail, ret =%u.\n",
+-			req0->resp_code);
++			req->resp_code);
+ 	}
+ 
+ 	return -EIO;
+ }
+ 
++static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, u16 vfid,
++				    bool is_kill, u16 vlan)
++{
++	struct hclge_vport *vport = &hdev->vport[vfid];
++	struct hclge_desc desc[2];
++	int ret;
++
++	/* if vf vlan table is full, firmware will close vf vlan filter, it
++	 * is unable and unnecessary to add new vlan id to vf vlan filter.
++	 * If spoof check is enable, and vf vlan is full, it shouldn't add
++	 * new vlan, because tx packets with these vlan id will be dropped.
++	 */
++	if (test_bit(vfid, hdev->vf_vlan_full) && !is_kill) {
++		if (vport->vf_info.spoofchk && vlan) {
++			dev_err(&hdev->pdev->dev,
++				"Can't add vlan due to spoof check is on and vf vlan table is full\n");
++			return -EPERM;
++		}
++		return 0;
++	}
++
++	ret = hclge_set_vf_vlan_filter_cmd(hdev, vfid, is_kill, vlan, desc);
++	if (ret)
++		return ret;
++
++	return hclge_check_vf_vlan_cmd_status(hdev, vfid, is_kill, desc);
++}
++
+ static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
+ 				      u16 vlan_id, bool is_kill)
+ {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index 14e8a93bdc31..be641288651f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -520,7 +520,6 @@ int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate)
+ 	struct hclge_shaper_ir_para ir_para;
+ 	struct hclge_dev *hdev = vport->back;
+ 	struct hclge_desc desc;
+-	u8 ir_b, ir_u, ir_s;
+ 	u32 shaper_para;
+ 	int ret, i;
+ 
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 217f56d2462c..65c244c2dc97 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -367,7 +367,9 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+  * of the generic netdev features interface.
+  */
+ struct ethtool_ops {
++#ifndef __GENKSYMS__
+ 	u32     supported_coalesce_params;
++#endif
+ 	int	(*get_settings)(struct net_device *, struct ethtool_cmd *);
+ 	int	(*set_settings)(struct net_device *, struct ethtool_cmd *);
+ 	void	(*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);
+-- 
+2.34.1
+
diff --git a/patches/0410-net-hns3-refactor-out-hclge_get_rss_tuple.patch b/patches/0410-net-hns3-refactor-out-hclge_get_rss_tuple.patch
new file mode 100644
index 0000000..b59b161
--- /dev/null
+++ b/patches/0410-net-hns3-refactor-out-hclge_get_rss_tuple.patch
@@ -0,0 +1,129 @@
+From 611f7edcab5623afa0d88da000b9320c0c111d94 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:38 +0800
+Subject: [PATCH 049/283] net: hns3: refactor out hclge_get_rss_tuple()
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 405642a15cba0c01d14fc6aa9b8deadf325ab7c3
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=405642a15cba0c01d14fc6aa9b8deadf325ab7c3
+
+----------------------------------------------------------------------
+
+To improve code readability and maintainability, separate
+the flow type parsing part and the converting part from
+bloated hclge_get_rss_tuple().
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 59 ++++++++++++-------
+ 1 file changed, 38 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index e26373b1f38e..986d9e5acb3b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -4532,52 +4532,69 @@ static int hclge_set_rss_tuple(struct hnae3_handle *handle,
+ 	return 0;
+ }
+ 
+-static int hclge_get_rss_tuple(struct hnae3_handle *handle,
+-			       struct ethtool_rxnfc *nfc)
++static int hclge_get_vport_rss_tuple(struct hclge_vport *vport, int flow_type,
++				     u8 *tuple_sets)
+ {
+-	struct hclge_vport *vport = hclge_get_vport(handle);
+-	u8 tuple_sets;
+-
+-	nfc->data = 0;
+-
+-	switch (nfc->flow_type) {
++	switch (flow_type) {
+ 	case TCP_V4_FLOW:
+-		tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
++		*tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
+ 		break;
+ 	case UDP_V4_FLOW:
+-		tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
++		*tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
+ 		break;
+ 	case TCP_V6_FLOW:
+-		tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
++		*tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
+ 		break;
+ 	case UDP_V6_FLOW:
+-		tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
++		*tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
+ 		break;
+ 	case SCTP_V4_FLOW:
+-		tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
++		*tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
+ 		break;
+ 	case SCTP_V6_FLOW:
+-		tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
++		*tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
+ 		break;
+ 	case IPV4_FLOW:
+ 	case IPV6_FLOW:
+-		tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
++		*tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
+ 		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+ 
+-	if (!tuple_sets)
+-		return 0;
++	return 0;
++}
++
++static u64 hclge_convert_rss_tuple(u8 tuple_sets)
++{
++	u64 tuple_data = 0;
+ 
+ 	if (tuple_sets & HCLGE_D_PORT_BIT)
+-		nfc->data |= RXH_L4_B_2_3;
++		tuple_data |= RXH_L4_B_2_3;
+ 	if (tuple_sets & HCLGE_S_PORT_BIT)
+-		nfc->data |= RXH_L4_B_0_1;
++		tuple_data |= RXH_L4_B_0_1;
+ 	if (tuple_sets & HCLGE_D_IP_BIT)
+-		nfc->data |= RXH_IP_DST;
++		tuple_data |= RXH_IP_DST;
+ 	if (tuple_sets & HCLGE_S_IP_BIT)
+-		nfc->data |= RXH_IP_SRC;
++		tuple_data |= RXH_IP_SRC;
++
++	return tuple_data;
++}
++
++static int hclge_get_rss_tuple(struct hnae3_handle *handle,
++			       struct ethtool_rxnfc *nfc)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	u8 tuple_sets;
++	int ret;
++
++	nfc->data = 0;
++
++	ret = hclge_get_vport_rss_tuple(vport, nfc->flow_type, &tuple_sets);
++	if (ret || !tuple_sets)
++		return ret;
++
++	nfc->data = hclge_convert_rss_tuple(tuple_sets);
+ 
+ 	return 0;
+ }
+-- 
+2.34.1
+
diff --git a/patches/0411-net-hns3-refactor-out-hclgevf_get_rss_tuple.patch b/patches/0411-net-hns3-refactor-out-hclgevf_get_rss_tuple.patch
new file mode 100644
index 0000000..72fb73f
--- /dev/null
+++ b/patches/0411-net-hns3-refactor-out-hclgevf_get_rss_tuple.patch
@@ -0,0 +1,137 @@
+From 40ebbda8bdcaa94f9a971b9546a54050e7f3ccf9 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:39 +0800
+Subject: [PATCH 050/283] net: hns3: refactor out hclgevf_get_rss_tuple()
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 73f7767ed0f93cd3269e7f5af75902a351faf5da
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=73f7767ed0f93cd3269e7f5af75902a351faf5da
+
+----------------------------------------------------------------------
+
+To improve code readability and maintainability, separate
+the flow type parsing part and the converting part from
+bloated hclgevf_get_rss_tuple().
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 67 ++++++++++++-------
+ 1 file changed, 42 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index f688217d4c59..accec5762d91 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -962,56 +962,73 @@ static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
+ 	return 0;
+ }
+ 
+-static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
+-				 struct ethtool_rxnfc *nfc)
++static int hclgevf_get_rss_tuple_by_flow_type(struct hclgevf_dev *hdev,
++					      int flow_type, u8 *tuple_sets)
+ {
+-	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
+-	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
+-	u8 tuple_sets;
+-
+-	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+-		return -EOPNOTSUPP;
+-
+-	nfc->data = 0;
+-
+-	switch (nfc->flow_type) {
++	switch (flow_type) {
+ 	case TCP_V4_FLOW:
+-		tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
++		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_tcp_en;
+ 		break;
+ 	case UDP_V4_FLOW:
+-		tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en;
++		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_udp_en;
+ 		break;
+ 	case TCP_V6_FLOW:
+-		tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
++		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_tcp_en;
+ 		break;
+ 	case UDP_V6_FLOW:
+-		tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en;
++		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_udp_en;
+ 		break;
+ 	case SCTP_V4_FLOW:
+-		tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
++		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv4_sctp_en;
+ 		break;
+ 	case SCTP_V6_FLOW:
+-		tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
++		*tuple_sets = hdev->rss_cfg.rss_tuple_sets.ipv6_sctp_en;
+ 		break;
+ 	case IPV4_FLOW:
+ 	case IPV6_FLOW:
+-		tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
++		*tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
+ 		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+ 
+-	if (!tuple_sets)
+-		return 0;
++	return 0;
++}
++
++static u64 hclgevf_convert_rss_tuple(u8 tuple_sets)
++{
++	u64 tuple_data = 0;
+ 
+ 	if (tuple_sets & HCLGEVF_D_PORT_BIT)
+-		nfc->data |= RXH_L4_B_2_3;
++		tuple_data |= RXH_L4_B_2_3;
+ 	if (tuple_sets & HCLGEVF_S_PORT_BIT)
+-		nfc->data |= RXH_L4_B_0_1;
++		tuple_data |= RXH_L4_B_0_1;
+ 	if (tuple_sets & HCLGEVF_D_IP_BIT)
+-		nfc->data |= RXH_IP_DST;
++		tuple_data |= RXH_IP_DST;
+ 	if (tuple_sets & HCLGEVF_S_IP_BIT)
+-		nfc->data |= RXH_IP_SRC;
++		tuple_data |= RXH_IP_SRC;
++
++	return tuple_data;
++}
++
++static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
++				 struct ethtool_rxnfc *nfc)
++{
++	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
++	u8 tuple_sets;
++	int ret;
++
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
++		return -EOPNOTSUPP;
++
++	nfc->data = 0;
++
++	ret = hclgevf_get_rss_tuple_by_flow_type(hdev, nfc->flow_type,
++						 &tuple_sets);
++	if (ret || !tuple_sets)
++		return ret;
++
++	nfc->data = hclgevf_convert_rss_tuple(tuple_sets);
+ 
+ 	return 0;
+ }
+-- 
+2.34.1
+
diff --git a/patches/0412-net-hns3-split-out-hclge_cmd_send.patch b/patches/0412-net-hns3-split-out-hclge_cmd_send.patch
new file mode 100644
index 0000000..b8ea114
--- /dev/null
+++ b/patches/0412-net-hns3-split-out-hclge_cmd_send.patch
@@ -0,0 +1,172 @@
+From 33374df5fd3f1c4d0da46856e84e1afd4a16d0fb Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:41 +0800
+Subject: [PATCH 051/283] net: hns3: split out hclge_cmd_send()
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 76f82fd9b1230332db2b3bc3916d097b92acbf29
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=76f82fd9b1230332db2b3bc3916d097b92acbf29
+
+----------------------------------------------------------------------
+
+hclge_cmd_send() is bloated, so split it into separate
+functions for readability and maintainability.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         | 100 +++++++++++-------
+ 1 file changed, 59 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 5f0c645eb292..64476a2629ba 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -210,6 +210,22 @@ struct errcode {
+ 	int common_errno;
+ };
+ 
++static void hclge_cmd_copy_desc(struct hclge_hw *hw, struct hclge_desc *desc,
++				int num)
++{
++	struct hclge_desc *desc_to_use;
++	int handle = 0;
++
++	while (handle < num) {
++		desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
++		*desc_to_use = desc[handle];
++		(hw->cmq.csq.next_to_use)++;
++		if (hw->cmq.csq.next_to_use >= hw->cmq.csq.desc_num)
++			hw->cmq.csq.next_to_use = 0;
++		handle++;
++	}
++}
++
+ static int hclge_cmd_convert_err_code(u16 desc_ret)
+ {
+ 	struct errcode hclge_cmd_errcode[] = {
+@@ -259,6 +275,44 @@ static int hclge_cmd_check_retval(struct hclge_hw *hw, struct hclge_desc *desc,
+ 	return hclge_cmd_convert_err_code(desc_ret);
+ }
+ 
++static int hclge_cmd_check_result(struct hclge_hw *hw, struct hclge_desc *desc,
++				  int num, int ntc)
++{
++	struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
++	bool is_completed = false;
++	u32 timeout = 0;
++	int handle, ret;
++
++	/**
++	 * If the command is sync, wait for the firmware to write back,
++	 * if multi descriptors to be sent, use the first one to check
++	 */
++	if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) {
++		do {
++			if (hclge_cmd_csq_done(hw)) {
++				is_completed = true;
++				break;
++			}
++			udelay(1);
++			timeout++;
++		} while (timeout < hw->cmq.tx_timeout);
++	}
++
++	if (!is_completed)
++		ret = -EBADE;
++	else
++		ret = hclge_cmd_check_retval(hw, desc, num, ntc);
++
++	/* Clean the command send queue */
++	handle = hclge_cmd_csq_clean(hw);
++	if (handle < 0)
++		ret = handle;
++	else if (handle != num)
++		dev_warn(&hdev->pdev->dev,
++			 "cleaned %d, need to clean %d\n", handle, num);
++	return ret;
++}
++
+ /**
+  * hclge_cmd_send - send command to command queue
+  * @hw: pointer to the hw struct
+@@ -272,11 +326,7 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
+ {
+ 	struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
+ 	struct hclge_cmq_ring *csq = &hw->cmq.csq;
+-	struct hclge_desc *desc_to_use;
+-	bool complete = false;
+-	u32 timeout = 0;
+-	int handle = 0;
+-	int retval;
++	int ret;
+ 	int ntc;
+ 
+ 	spin_lock_bh(&hw->cmq.csq.lock);
+@@ -300,49 +350,17 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
+ 	 * which will be use for hardware to write back
+ 	 */
+ 	ntc = hw->cmq.csq.next_to_use;
+-	while (handle < num) {
+-		desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
+-		*desc_to_use = desc[handle];
+-		(hw->cmq.csq.next_to_use)++;
+-		if (hw->cmq.csq.next_to_use >= hw->cmq.csq.desc_num)
+-			hw->cmq.csq.next_to_use = 0;
+-		handle++;
+-	}
++
++	hclge_cmd_copy_desc(hw, desc, num);
+ 
+ 	/* Write to hardware */
+ 	hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, hw->cmq.csq.next_to_use);
+ 
+-	/**
+-	 * If the command is sync, wait for the firmware to write back,
+-	 * if multi descriptors to be sent, use the first one to check
+-	 */
+-	if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) {
+-		do {
+-			if (hclge_cmd_csq_done(hw)) {
+-				complete = true;
+-				break;
+-			}
+-			udelay(1);
+-			timeout++;
+-		} while (timeout < hw->cmq.tx_timeout);
+-	}
+-
+-	if (!complete)
+-		retval = -EBADE;
+-	else
+-		retval = hclge_cmd_check_retval(hw, desc, num, ntc);
+-
+-	/* Clean the command send queue */
+-	handle = hclge_cmd_csq_clean(hw);
+-	if (handle < 0)
+-		retval = handle;
+-	else if (handle != num)
+-		dev_warn(&hdev->pdev->dev,
+-			 "cleaned %d, need to clean %d\n", handle, num);
++	ret = hclge_cmd_check_result(hw, desc, num, ntc);
+ 
+ 	spin_unlock_bh(&hw->cmq.csq.lock);
+ 
+-	return retval;
++	return ret;
+ }
+ 
+ static void hclge_set_default_capability(struct hclge_dev *hdev)
+-- 
+2.34.1
+
diff --git a/patches/0413-net-hns3-split-out-hclgevf_cmd_send.patch b/patches/0413-net-hns3-split-out-hclgevf_cmd_send.patch
new file mode 100644
index 0000000..2b546fe
--- /dev/null
+++ b/patches/0413-net-hns3-split-out-hclgevf_cmd_send.patch
@@ -0,0 +1,242 @@
+From b7b863887a881e152602febf43715e366f714497 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:42 +0800
+Subject: [PATCH 052/283] net: hns3: split out hclgevf_cmd_send()
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit eb0faf32b86e208049b6432197bfeeeac8580fe1
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=eb0faf32b86e208049b6432197bfeeeac8580fe1
+
+----------------------------------------------------------------------
+
+hclgevf_cmd_send() is bloated, so split it into separate
+functions for readability and maintainability.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       | 141 ++++++++++--------
+ include/linux/ethtool.h                       |   2 -
+ include/linux/phy.h                           |   1 -
+ 3 files changed, 81 insertions(+), 63 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index a09b63a031a5..9430334e1c22 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -197,6 +197,22 @@ struct vf_errcode {
+ 	int common_errno;
+ };
+ 
++static void hclgevf_cmd_copy_desc(struct hclgevf_hw *hw,
++				  struct hclgevf_desc *desc, int num)
++{
++	struct hclgevf_desc *desc_to_use;
++	int handle = 0;
++
++	while (handle < num) {
++		desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
++		*desc_to_use = desc[handle];
++		(hw->cmq.csq.next_to_use)++;
++		if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
++			hw->cmq.csq.next_to_use = 0;
++		handle++;
++	}
++}
++
+ static int hclgevf_cmd_convert_err_code(u16 desc_ret)
+ {
+ 	struct vf_errcode hclgevf_cmd_errcode[] = {
+@@ -223,6 +239,66 @@ static int hclgevf_cmd_convert_err_code(u16 desc_ret)
+ 	return -EIO;
+ }
+ 
++static int hclgevf_cmd_check_retval(struct hclgevf_hw *hw,
++				    struct hclgevf_desc *desc, int num, int ntc)
++{
++	u16 opcode, desc_ret;
++	int handle;
++
++	opcode = le16_to_cpu(desc[0].opcode);
++	for (handle = 0; handle < num; handle++) {
++		/* Get the result of hardware write back */
++		desc[handle] = hw->cmq.csq.desc[ntc];
++		ntc++;
++		if (ntc == hw->cmq.csq.desc_num)
++			ntc = 0;
++	}
++	if (likely(!hclgevf_is_special_opcode(opcode)))
++		desc_ret = le16_to_cpu(desc[num - 1].retval);
++	else
++		desc_ret = le16_to_cpu(desc[0].retval);
++	hw->cmq.last_status = desc_ret;
++
++	return hclgevf_cmd_convert_err_code(desc_ret);
++}
++
++static int hclgevf_cmd_check_result(struct hclgevf_hw *hw,
++				    struct hclgevf_desc *desc, int num, int ntc)
++{
++	struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
++	bool is_completed = false;
++	u32 timeout = 0;
++	int handle, ret;
++
++	/* If the command is sync, wait for the firmware to write back,
++	 * if multi descriptors to be sent, use the first one to check
++	 */
++	if (HCLGEVF_SEND_SYNC(le16_to_cpu(desc->flag))) {
++		do {
++			if (hclgevf_cmd_csq_done(hw)) {
++				is_completed = true;
++				break;
++			}
++			udelay(1);
++			timeout++;
++		} while (timeout < hw->cmq.tx_timeout);
++	}
++
++	if (!is_completed)
++		ret = -EBADE;
++	else
++		ret = hclgevf_cmd_check_retval(hw, desc, num, ntc);
++
++	/* Clean the command send queue */
++	handle = hclgevf_cmd_csq_clean(hw);
++	if (handle < 0)
++		ret = handle;
++	else if (handle != num)
++		dev_warn(&hdev->pdev->dev,
++			 "cleaned %d, need to clean %d\n", handle, num);
++	return ret;
++}
++
+ /* hclgevf_cmd_send - send command to command queue
+  * @hw: pointer to the hw struct
+  * @desc: prefilled descriptor for describing the command
+@@ -235,13 +311,7 @@ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
+ {
+ 	struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
+ 	struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
+-	struct hclgevf_desc *desc_to_use;
+-	bool complete = false;
+-	u32 timeout = 0;
+-	int handle = 0;
+-	int status = 0;
+-	u16 retval;
+-	u16 opcode;
++	int ret;
+ 	int ntc;
+ 
+ 	spin_lock_bh(&hw->cmq.csq.lock);
+@@ -265,67 +335,18 @@ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
+ 	 * which will be use for hardware to write back
+ 	 */
+ 	ntc = hw->cmq.csq.next_to_use;
+-	opcode = le16_to_cpu(desc[0].opcode);
+-	while (handle < num) {
+-		desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
+-		*desc_to_use = desc[handle];
+-		(hw->cmq.csq.next_to_use)++;
+-		if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
+-			hw->cmq.csq.next_to_use = 0;
+-		handle++;
+-	}
++
++	hclgevf_cmd_copy_desc(hw, desc, num);
+ 
+ 	/* Write to hardware */
+ 	hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG,
+ 			  hw->cmq.csq.next_to_use);
+ 
+-	/* If the command is sync, wait for the firmware to write back,
+-	 * if multi descriptors to be sent, use the first one to check
+-	 */
+-	if (HCLGEVF_SEND_SYNC(le16_to_cpu(desc->flag))) {
+-		do {
+-			if (hclgevf_cmd_csq_done(hw))
+-				break;
+-			udelay(1);
+-			timeout++;
+-		} while (timeout < hw->cmq.tx_timeout);
+-	}
+-
+-	if (hclgevf_cmd_csq_done(hw)) {
+-		complete = true;
+-		handle = 0;
+-
+-		while (handle < num) {
+-			/* Get the result of hardware write back */
+-			desc_to_use = &hw->cmq.csq.desc[ntc];
+-			desc[handle] = *desc_to_use;
+-
+-			if (likely(!hclgevf_is_special_opcode(opcode)))
+-				retval = le16_to_cpu(desc[handle].retval);
+-			else
+-				retval = le16_to_cpu(desc[0].retval);
+-
+-			status = hclgevf_cmd_convert_err_code(retval);
+-			hw->cmq.last_status = (enum hclgevf_cmd_status)retval;
+-			ntc++;
+-			handle++;
+-			if (ntc == hw->cmq.csq.desc_num)
+-				ntc = 0;
+-		}
+-	}
+-
+-	if (!complete)
+-		status = -EBADE;
+-
+-	/* Clean the command send queue */
+-	handle = hclgevf_cmd_csq_clean(hw);
+-	if (handle != num)
+-		dev_warn(&hdev->pdev->dev,
+-			 "cleaned %d, need to clean %d\n", handle, num);
++	ret = hclgevf_cmd_check_result(hw, desc, num, ntc);
+ 
+ 	spin_unlock_bh(&hw->cmq.csq.lock);
+ 
+-	return status;
++	return ret;
+ }
+ 
+ static void hclgevf_set_default_capability(struct hclgevf_dev *hdev)
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 65c244c2dc97..217f56d2462c 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -367,9 +367,7 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+  * of the generic netdev features interface.
+  */
+ struct ethtool_ops {
+-#ifndef __GENKSYMS__
+ 	u32     supported_coalesce_params;
+-#endif
+ 	int	(*get_settings)(struct net_device *, struct ethtool_cmd *);
+ 	int	(*set_settings)(struct net_device *, struct ethtool_cmd *);
+ 	void	(*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index 81532a61e995..d428623582e5 100644
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -418,7 +418,6 @@ struct phy_device {
+ 	unsigned autoneg:1;
+ 	/* The most recently read link state */
+ 	unsigned link:1;
+-
+ 	enum phy_state state;
+ 
+ 	u32 dev_flags;
+-- 
+2.34.1
+
diff --git a/patches/0414-net-hns3-Fix-KABI-for-ethtools-supported_coalesce_pa.patch b/patches/0414-net-hns3-Fix-KABI-for-ethtools-supported_coalesce_pa.patch
new file mode 100644
index 0000000..edd0074
--- /dev/null
+++ b/patches/0414-net-hns3-Fix-KABI-for-ethtools-supported_coalesce_pa.patch
@@ -0,0 +1,37 @@
+From b29f0fd02ffd9facaedb99ff4a5f713a318c56e6 Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Tue, 20 Jun 2023 10:33:29 +0800
+Subject: [PATCH 053/283] net:hns3 Fix KABI for
+ ethtools->supported_coalesce_params
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+
+--------------------------------
+
+Fix ethtool_ Added supported in the ops structure_ Coalesce_ Kabi
+changes caused by params members.
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ include/linux/ethtool.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 217f56d2462c..65c244c2dc97 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -367,7 +367,9 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+  * of the generic netdev features interface.
+  */
+ struct ethtool_ops {
++#ifndef __GENKSYMS__
+ 	u32     supported_coalesce_params;
++#endif
+ 	int	(*get_settings)(struct net_device *, struct ethtool_cmd *);
+ 	int	(*set_settings)(struct net_device *, struct ethtool_cmd *);
+ 	void	(*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);
+-- 
+2.34.1
+
diff --git a/patches/0415-net-hns3-Fix-KABI-for-deletion-of-hnae3_unic_private.patch b/patches/0415-net-hns3-Fix-KABI-for-deletion-of-hnae3_unic_private.patch
new file mode 100644
index 0000000..eb29b47
--- /dev/null
+++ b/patches/0415-net-hns3-Fix-KABI-for-deletion-of-hnae3_unic_private.patch
@@ -0,0 +1,55 @@
+From c7aa853001a92e3cab9f3bc03fba411ef52458fa Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Tue, 20 Jun 2023 10:40:59 +0800
+Subject: [PATCH 054/283] net:hns3 Fix KABI for deletion of
+ hnae3_unic_private_info in hnae3_handle
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+
+--------------------------------
+
+Fixed due to removal of hnae3_ Unic_ Private_ Kabi
+changes caused by info structure
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index eef5f7a5eb63..6d58e1ccec78 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -776,7 +776,17 @@ struct hnae3_roce_private_info {
+ 	unsigned long instance_state;
+ 	unsigned long state;
+ };
++#ifdef __GENKSYMS__
++struct hnae3_unic_private_info {
++	struct net_device *netdev;
++	u16 rx_buf_len;
++	u16 num_tx_desc;
++	u16 num_rx_desc;
+ 
++	u16 num_tqps;   /* total number of tqps in this handle */
++	struct hnae3_queue **tqp;  /* array base of all TQPs of this instance */
++};
++#endif
+ #define HNAE3_SUPPORT_APP_LOOPBACK    BIT(0)
+ #define HNAE3_SUPPORT_PHY_LOOPBACK    BIT(1)
+ #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK	BIT(2)
+@@ -803,6 +813,9 @@ struct hnae3_handle {
+ 	union {
+ 		struct net_device *netdev; /* first member */
+ 		struct hnae3_knic_private_info kinfo;
++#ifdef __GENKSYMS__
++		struct hnae3_unic_private_info uinfo;
++#endif
+ 		struct hnae3_roce_private_info rinfo;
+ 	};
+ 
+-- 
+2.34.1
+
diff --git a/patches/0416-net-hns3-Fix-KABI-for-The-dev_version-caps-element-i.patch b/patches/0416-net-hns3-Fix-KABI-for-The-dev_version-caps-element-i.patch
new file mode 100644
index 0000000..cdebc1b
--- /dev/null
+++ b/patches/0416-net-hns3-Fix-KABI-for-The-dev_version-caps-element-i.patch
@@ -0,0 +1,38 @@
+From fd278a93071f924014782c34e84f48832e5d52a5 Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Tue, 20 Jun 2023 14:23:51 +0800
+Subject: [PATCH 055/283] net:hns3 Fix KABI for The dev_version & caps element
+ is added to the hnae3_ae_dev structure.
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+
+--------------------------------
+
+Fix it because hnae3_ Ae_ Add dev to the dev structure_ Kabi
+changes caused by version and caps members
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 6d58e1ccec78..0ffb8109fba9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -345,8 +345,10 @@ struct hnae3_ae_dev {
+ 	struct list_head node;
+ 	u32 flag;
+ 	unsigned long hw_err_reset_req;
++#ifndef __GENKSYMS__
+ 	u32 dev_version;
+ 	unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)];
++#endif
+ 	void *priv;
+ };
+ 
+-- 
+2.34.1
+
diff --git a/patches/0417-net-hns3-add-support-for-imp-controlled-PHYs.patch b/patches/0417-net-hns3-add-support-for-imp-controlled-PHYs.patch
new file mode 100644
index 0000000..3887e16
--- /dev/null
+++ b/patches/0417-net-hns3-add-support-for-imp-controlled-PHYs.patch
@@ -0,0 +1,413 @@
+From aec0faec2bfbd8d5a18f52d1778519911fdb3831 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:48 +0800
+Subject: [PATCH 056/283] net: hns3: add support for imp-controlled PHYs
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit f5f2b3e4dcc0e944dc33b522df84576679fbd8eb
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f5f2b3e4dcc0e944dc33b522df84576679fbd8eb
+
+----------------------------------------------------------------------
+
+IMP(Intelligent Management Processor) firmware add a new feature
+to take control of PHYs for some new devices, PF driver adds
+support for this feature.
+
+Driver queries device's capability to check whether IMP supports
+this feature, it will tell IMP to enable this feature by firmware
+compatible command if it is supported.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |   7 +-
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |   9 +-
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         |   4 +
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  50 ++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 149 +++++++++++++++++-
+ include/uapi/linux/ethtool.h                  |   8 +-
+ 6 files changed, 222 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 0ffb8109fba9..99fe5603ef1c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -89,6 +89,8 @@ enum HNAE3_DEV_CAP_BITS {
+ 	HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B,
+ 	HNAE3_DEV_SUPPORT_HW_PAD_B,
+ 	HNAE3_DEV_SUPPORT_STASH_B,
++	HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
++	HNAE3_DEV_SUPPORT_PAUSE_B,
+ };
+ 
+ #define hnae3_dev_fd_supported(hdev) \
+@@ -680,7 +682,10 @@ struct hnae3_ae_ops {
+ 	int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset,
+ 				 u32 len, u8 *data);
+ 	bool (*get_cmdq_stat)(struct hnae3_handle *handle);
+-
++	int (*get_phy_link_ksettings)(struct hnae3_handle *handle,
++				      struct ethtool_link_ksettings *cmd);
++	int (*set_phy_link_ksettings)(struct hnae3_handle *handle,
++				      const struct ethtool_link_ksettings *cmd);
+ /* Notice! If the function is not for test, the definition must before
+  * CONFIG_HNS3_TEST! Because RoCE will use this head file, and it won't
+  * set CONFIG_HNS3_TEST, that may cause RoCE calling the wrong function.
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 2eb3aac3c711..3bad65d1a49d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -671,6 +671,7 @@ static int hns3_get_link_ksettings(struct net_device *netdev,
+ 				   struct ethtool_link_ksettings *cmd)
+ {
+ 	struct hnae3_handle *h = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
+ 	const struct hnae3_ae_ops *ops;
+ 	u8 module_type;
+ 	u8 media_type;
+@@ -701,7 +702,10 @@ static int hns3_get_link_ksettings(struct net_device *netdev,
+ 		break;
+ 	case HNAE3_MEDIA_TYPE_COPPER:
+ 		cmd->base.port = PORT_TP;
+-		if (!netdev->phydev)
++		if (test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, ae_dev->caps) &&
++		    ops->get_phy_link_ksettings)
++			ops->get_phy_link_ksettings(h, cmd);
++		else if (!netdev->phydev)
+ 			hns3_get_ksettings(h, cmd);
+ 		else
+ 			phy_ethtool_ksettings_get(netdev->phydev, cmd);
+@@ -796,6 +800,9 @@ static int hns3_set_link_ksettings(struct net_device *netdev,
+ 			return -EINVAL;
+ 
+ 		return phy_ethtool_ksettings_set(netdev->phydev, cmd);
++	} else if (test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, ae_dev->caps) &&
++		   ops->set_phy_link_ksettings) {
++		return ops->set_phy_link_ksettings(handle, cmd);
+ 	}
+ 
+ 	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 64476a2629ba..c4d30bcc8fa3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -390,6 +390,8 @@ static void hclge_parse_capability(struct hclge_dev *hdev,
+ 		set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
+ 	if (hnae3_get_bit(caps, HCLGE_CAP_HW_TX_CSUM_B))
+ 		set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGE_CAP_PHY_IMP_B))
++		set_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, ae_dev->caps);
+ }
+ 
+ static enum hclge_cmd_status
+@@ -476,6 +478,8 @@ static int hclge_firmware_compat_config(struct hclge_dev *hdev, bool en)
+ 
+ 		hnae3_set_bit(compat, HCLGE_LINK_EVENT_REPORT_EN_B, 1);
+ 		hnae3_set_bit(compat, HCLGE_NCSI_ERROR_REPORT_EN_B, 1);
++		if (hnae3_dev_phy_imp_supported(hdev))
++			hnae3_set_bit(compat, HCLGE_PHY_IMP_EN_B, 1);
+ 		req->compat = cpu_to_le32(compat);
+ 	}
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index e6727366028e..2922cd1bc859 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -308,6 +308,9 @@ enum hclge_opcode_type {
+ 	HCLGE_PPP_MAC_VLAN_IDX_RD	= 0x2104,
+ 	HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
+ 	HCLGE_NCSI_INT_EN		= 0x2401,
++
++	/* PHY command */
++	HCLGE_OPC_PHY_LINK_KSETTING	= 0x7025,
+ };
+ 
+ #define HCLGE_TQP_REG_OFFSET		0x80000
+@@ -1107,6 +1110,7 @@ struct hclge_query_ppu_pf_other_int_dfx_cmd {
+ 
+ #define HCLGE_LINK_EVENT_REPORT_EN_B	0
+ #define HCLGE_NCSI_ERROR_REPORT_EN_B	1
++#define HCLGE_PHY_IMP_EN_B		2
+ struct hclge_firmware_compat_cmd {
+ 	__le32 compat;
+ 	u8 rsv[20];
+@@ -1125,6 +1129,52 @@ struct hclge_sfp_info_bd0_cmd {
+ 	u8 data[HCLGE_SFP_INFO_BD0_LEN];
+ };
+ 
++#define HCLGE_QUERY_DEV_SPECS_BD_NUM		4
++
++struct hclge_dev_specs_0_cmd {
++	__le32 rsv0;
++	__le32 mac_entry_num;
++	__le32 mng_entry_num;
++	__le16 rss_ind_tbl_size;
++	__le16 rss_key_size;
++	__le16 int_ql_max;
++	u8 max_non_tso_bd_num;
++	u8 rsv1;
++	__le32 max_tm_rate;
++};
++
++#define HCLGE_DEF_MAX_INT_GL		0x1FE0U
++
++struct hclge_dev_specs_1_cmd {
++	__le16 max_frm_size;
++	__le16 max_qset_num;
++	__le16 max_int_gl;
++	u8 rsv1[18];
++};
++
++#define HCLGE_PHY_LINK_SETTING_BD_NUM		2
++
++struct hclge_phy_link_ksetting_0_cmd {
++	__le32 speed;
++	u8 duplex;
++	u8 autoneg;
++	u8 eth_tp_mdix;
++	u8 eth_tp_mdix_ctrl;
++	u8 port;
++	u8 transceiver;
++	u8 phy_address;
++	u8 rsv;
++	__le32 supported;
++	__le32 advertising;
++	__le32 lp_advertising;
++};
++
++struct hclge_phy_link_ksetting_1_cmd {
++	u8 master_slave_cfg;
++	u8 master_slave_state;
++	u8 rsv[22];
++};
++
+ int hclge_cmd_init(struct hclge_dev *hdev);
+ static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
+ {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 986d9e5acb3b..115e70fcce36 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -2903,6 +2903,141 @@ static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac)
+ 	return 0;
+ }
+ 
++static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle,
++					struct ethtool_link_ksettings *cmd)
++{
++	struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_phy_link_ksetting_0_cmd *req0;
++	struct hclge_phy_link_ksetting_1_cmd *req1;
++	u32 supported, advertising, lp_advertising;
++	struct hclge_dev *hdev = vport->back;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
++				   true);
++	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
++				   true);
++
++	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get phy link ksetting, ret = %d.\n", ret);
++		return ret;
++	}
++
++	req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
++	cmd->base.autoneg = req0->autoneg;
++	cmd->base.speed = le32_to_cpu(req0->speed);
++	cmd->base.duplex = req0->duplex;
++	cmd->base.port = req0->port;
++	cmd->base.transceiver = req0->transceiver;
++	cmd->base.phy_address = req0->phy_address;
++	cmd->base.eth_tp_mdix = req0->eth_tp_mdix;
++	cmd->base.eth_tp_mdix_ctrl = req0->eth_tp_mdix_ctrl;
++	supported = le32_to_cpu(req0->supported);
++	advertising = le32_to_cpu(req0->advertising);
++	lp_advertising = le32_to_cpu(req0->lp_advertising);
++	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
++						supported);
++	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
++						advertising);
++	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
++						lp_advertising);
++
++	req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
++	cmd->base.master_slave_cfg = req1->master_slave_cfg;
++	cmd->base.master_slave_state = req1->master_slave_state;
++
++	return 0;
++}
++
++static int
++hclge_set_phy_link_ksettings(struct hnae3_handle *handle,
++			     const struct ethtool_link_ksettings *cmd)
++{
++	struct hclge_desc desc[HCLGE_PHY_LINK_SETTING_BD_NUM];
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_phy_link_ksetting_0_cmd *req0;
++	struct hclge_phy_link_ksetting_1_cmd *req1;
++	struct hclge_dev *hdev = vport->back;
++	u32 advertising;
++	int ret;
++
++	if (cmd->base.autoneg == AUTONEG_DISABLE &&
++	    ((cmd->base.speed != SPEED_100 && cmd->base.speed != SPEED_10) ||
++	     (cmd->base.duplex != DUPLEX_HALF &&
++	      cmd->base.duplex != DUPLEX_FULL)))
++		return -EINVAL;
++
++	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
++				   false);
++	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
++				   false);
++
++	req0 = (struct hclge_phy_link_ksetting_0_cmd *)desc[0].data;
++	req0->autoneg = cmd->base.autoneg;
++	req0->speed = cpu_to_le32(cmd->base.speed);
++	req0->duplex = cmd->base.duplex;
++	ethtool_convert_link_mode_to_legacy_u32(&advertising,
++						cmd->link_modes.advertising);
++	req0->advertising = cpu_to_le32(advertising);
++	req0->eth_tp_mdix_ctrl = cmd->base.eth_tp_mdix_ctrl;
++
++	req1 = (struct hclge_phy_link_ksetting_1_cmd *)desc[1].data;
++	req1->master_slave_cfg = cmd->base.master_slave_cfg;
++
++	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PHY_LINK_SETTING_BD_NUM);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to set phy link ksettings, ret = %d.\n", ret);
++		return ret;
++	}
++
++	hdev->hw.mac.autoneg = cmd->base.autoneg;
++	hdev->hw.mac.speed = cmd->base.speed;
++	hdev->hw.mac.duplex = cmd->base.duplex;
++	linkmode_copy(hdev->hw.mac.advertising, cmd->link_modes.advertising);
++
++	return 0;
++}
++
++static int hclge_update_tp_port_info(struct hclge_dev *hdev)
++{
++	struct ethtool_link_ksettings cmd;
++	int ret;
++
++	if (!hnae3_dev_phy_imp_supported(hdev))
++		return 0;
++
++	ret = hclge_get_phy_link_ksettings(&hdev->vport->nic, &cmd);
++	if (ret)
++		return ret;
++
++	hdev->hw.mac.autoneg = cmd.base.autoneg;
++	hdev->hw.mac.speed = cmd.base.speed;
++	hdev->hw.mac.duplex = cmd.base.duplex;
++
++	return 0;
++}
++
++static int hclge_tp_port_init(struct hclge_dev *hdev)
++{
++	struct ethtool_link_ksettings cmd;
++
++	if (!hnae3_dev_phy_imp_supported(hdev))
++		return 0;
++
++	cmd.base.autoneg = hdev->hw.mac.autoneg;
++	cmd.base.speed = hdev->hw.mac.speed;
++	cmd.base.duplex = hdev->hw.mac.duplex;
++	linkmode_copy(cmd.link_modes.advertising, hdev->hw.mac.advertising);
++
++	return hclge_set_phy_link_ksettings(&hdev->vport->nic, &cmd);
++}
++
+ static int hclge_update_port_info(struct hclge_dev *hdev)
+ {
+ 	struct hclge_mac *mac = &hdev->hw.mac;
+@@ -2911,7 +3046,7 @@ static int hclge_update_port_info(struct hclge_dev *hdev)
+ 
+ 	/* get the port info from SFP cmd if not copper port */
+ 	if (mac->media_type == HNAE3_MEDIA_TYPE_COPPER)
+-		return 0;
++		return hclge_update_tp_port_info(hdev);
+ 
+ 	/* if IMP does not support get SFP/qSFP info, return directly */
+ 	if (!hdev->support_sfp_query)
+@@ -10419,7 +10554,8 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	if (ret)
+ 		goto err_msi_irq_uninit;
+ 
+-	if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
++	if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER &&
++	    !hnae3_dev_phy_imp_supported(hdev)) {
+ 		ret = hclge_mac_mdio_config(hdev);
+ 		if (ret)
+ 			goto err_msi_irq_uninit;
+@@ -10796,6 +10932,13 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 		return ret;
+ 	}
+ 
++	ret = hclge_tp_port_init(hdev);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to init tp port, ret = %d\n",
++			ret);
++		return ret;
++	}
++
+ 	ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
+@@ -11791,6 +11934,8 @@ struct hnae3_ae_ops hclge_ops = {
+ 	.set_vf_mac = hclge_set_vf_mac,
+ 	.get_module_eeprom = hclge_get_module_eeprom,
+ 	.get_cmdq_stat = hclge_get_cmdq_stat,
++	.get_phy_link_ksettings = hclge_get_phy_link_ksettings,
++	.set_phy_link_ksettings = hclge_set_phy_link_ksettings,
+ };
+ 
+ static struct hnae3_ae_algo ae_algo = {
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index dc69391d2bba..4a43996de6d0 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -1836,7 +1836,13 @@ struct ethtool_link_settings {
+ 	__u8	eth_tp_mdix_ctrl;
+ 	__s8	link_mode_masks_nwords;
+ 	__u8	transceiver;
+-	__u8	reserved1[3];
++#ifndef __GENKSYMS__
++	__u8    master_slave_cfg;
++	__u8    master_slave_state;
++	__u8    reserved1[1];
++#else
++	__u8   reserved1[3];
++#endif
+ 	__u32	reserved[7];
+ 	__u32	link_mode_masks[0];
+ 	/* layout of link_mode_masks fields:
+-- 
+2.34.1
+
diff --git a/patches/0418-net-hns3-add-get-set-pause-parameters-support-for-im.patch b/patches/0418-net-hns3-add-get-set-pause-parameters-support-for-im.patch
new file mode 100644
index 0000000..8420777
--- /dev/null
+++ b/patches/0418-net-hns3-add-get-set-pause-parameters-support-for-im.patch
@@ -0,0 +1,75 @@
+From 161e7c4611fd6cebddc02d77b245236cb5c87b96 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:49 +0800
+Subject: [PATCH 057/283] net: hns3: add get/set pause parameters support for
+ imp-controlled PHYs
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit 57a8f46b1bd3f5f43b06f48aab7c1f7ca0936be3
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=57a8f46b1bd3f5f43b06f48aab7c1f7ca0936be3
+
+----------------------------------------------------------------------
+
+When the imp-controlled PHYs feature is enabled, phydev is NULL.
+In this case, the autoneg is always off when user uses ethtool -a
+command to get pause parameters because  hclge_get_pauseparam()
+uses phydev to check whether device is TP port. To fit this new
+feature, use media type to check whether device is TP port.
+
+And when user set pause parameters, these parameters need to
+always set to mac, no matter whether autoneg is off.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 115e70fcce36..c73348bc7706 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -9935,9 +9935,10 @@ static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+-	struct phy_device *phydev = hdev->hw.mac.phydev;
++	u8 media_type = hdev->hw.mac.media_type;
+ 
+-	*auto_neg = phydev ? hclge_get_autoneg(handle) : 0;
++	*auto_neg = (media_type == HNAE3_MEDIA_TYPE_COPPER) ?
++		    hclge_get_autoneg(handle) : 0;
+ 
+ 	if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
+ 		*rx_en = 0;
+@@ -9983,7 +9984,7 @@ static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
+ 	struct phy_device *phydev = hdev->hw.mac.phydev;
+ 	u32 fc_autoneg;
+ 
+-	if (phydev) {
++	if (phydev || hnae3_dev_phy_imp_supported(hdev)) {
+ 		fc_autoneg = hclge_get_autoneg(handle);
+ 		if (auto_neg != fc_autoneg) {
+ 			dev_info(&hdev->pdev->dev,
+@@ -10002,7 +10003,7 @@ static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
+ 
+ 	hclge_record_user_pauseparam(hdev, rx_en, tx_en);
+ 
+-	if (!auto_neg)
++	if (!auto_neg || hnae3_dev_phy_imp_supported(hdev))
+ 		return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
+ 
+ 	if (phydev)
+-- 
+2.34.1
+
diff --git a/patches/0419-net-hns3-add-ioctl-support-for-imp-controlled-PHYs.patch b/patches/0419-net-hns3-add-ioctl-support-for-imp-controlled-PHYs.patch
new file mode 100644
index 0000000..8527c3f
--- /dev/null
+++ b/patches/0419-net-hns3-add-ioctl-support-for-imp-controlled-PHYs.patch
@@ -0,0 +1,168 @@
+From 42e18be60daee3fa262b80bf8dff791862fb1137 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:50 +0800
+Subject: [PATCH 058/283] net: hns3: add ioctl support for imp-controlled PHYs
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit 024712f51e5711d69ced729fb3398819ed6e8b53
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=024712f51e5711d69ced729fb3398819ed6e8b53
+
+----------------------------------------------------------------------
+
+When the imp-controlled PHYs feature is enabled, driver will not
+register mdio bus. In order to support ioctl ops for phy tool to
+read or write phy register in this case, the firmware implement
+a new command for driver and driver implement ioctl by using this
+new command.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  8 ++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 26 ++++++++++++-
+ .../hisilicon/hns3/hns3pf/hclge_mdio.c        | 39 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_mdio.h        |  2 +
+ 4 files changed, 74 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 2922cd1bc859..88aefd3685a7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -311,6 +311,7 @@ enum hclge_opcode_type {
+ 
+ 	/* PHY command */
+ 	HCLGE_OPC_PHY_LINK_KSETTING	= 0x7025,
++	HCLGE_OPC_PHY_REG		= 0x7026,
+ };
+ 
+ #define HCLGE_TQP_REG_OFFSET		0x80000
+@@ -1175,6 +1176,13 @@ struct hclge_phy_link_ksetting_1_cmd {
+ 	u8 rsv[22];
+ };
+ 
++struct hclge_phy_reg_cmd {
++	__le16 reg_addr;
++	u8 rsv0[2];
++	__le16 reg_val;
++	u8 rsv1[18];
++};
++
+ int hclge_cmd_init(struct hclge_dev *hdev);
+ static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
+ {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index c73348bc7706..abd79d4bc56d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -8457,6 +8457,30 @@ static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
+ 	return 0;
+ }
+ 
++static int hclge_mii_ioctl(struct hclge_dev *hdev, struct ifreq *ifr, int cmd)
++{
++	struct mii_ioctl_data *data = if_mii(ifr);
++
++	if (!hnae3_dev_phy_imp_supported(hdev))
++		return -EOPNOTSUPP;
++
++	switch (cmd) {
++	case SIOCGMIIPHY:
++		data->phy_id = hdev->hw.mac.phy_addr;
++		data->val_out = hclge_read_phy_reg(hdev, data->reg_num);
++		return 0;
++		/* this command reads phy id and register at the same time */
++	case SIOCGMIIREG:
++		data->val_out = hclge_read_phy_reg(hdev, data->reg_num);
++		return 0;
++
++	case SIOCSMIIREG:
++		return hclge_write_phy_reg(hdev, data->reg_num, data->val_in);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
+ static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
+ 			  int cmd)
+ {
+@@ -8464,7 +8488,7 @@ static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
+ 	struct hclge_dev *hdev = vport->back;
+ 
+ 	if (!hdev->hw.mac.phydev)
+-		return -EOPNOTSUPP;
++		return hclge_mii_ioctl(hdev, ifr, cmd);
+ 
+ 	return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+index 3eea4870a56a..b9c81e2e60b2 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+@@ -293,3 +293,42 @@ void hclge_mac_stop_phy(struct hclge_dev *hdev)
+ 
+ 	phy_stop(phydev);
+ }
++
++u16 hclge_read_phy_reg(struct hclge_dev *hdev, u16 reg_addr)
++{
++	struct hclge_phy_reg_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PHY_REG, true);
++
++	req = (struct hclge_phy_reg_cmd *)desc.data;
++	req->reg_addr = cpu_to_le16(reg_addr);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to read phy reg, ret = %d.\n", ret);
++
++	return le16_to_cpu(req->reg_val);
++}
++
++int hclge_write_phy_reg(struct hclge_dev *hdev, u16 reg_addr, u16 val)
++{
++	struct hclge_phy_reg_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PHY_REG, false);
++
++	req = (struct hclge_phy_reg_cmd *)desc.data;
++	req->reg_addr = cpu_to_le16(reg_addr);
++	req->reg_val = cpu_to_le16(val);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to write phy reg, ret = %d.\n", ret);
++
++	return ret;
++}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h
+index ef095d9c566f..7e019be3816a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h
+@@ -9,5 +9,7 @@ int hclge_mac_connect_phy(struct hnae3_handle *handle);
+ void hclge_mac_disconnect_phy(struct hnae3_handle *handle);
+ void hclge_mac_start_phy(struct hclge_dev *hdev);
+ void hclge_mac_stop_phy(struct hclge_dev *hdev);
++u16 hclge_read_phy_reg(struct hclge_dev *hdev, u16 reg_addr);
++int hclge_write_phy_reg(struct hclge_dev *hdev, u16 reg_addr, u16 val);
+ 
+ #endif
+-- 
+2.34.1
+
diff --git a/patches/0420-net-hns3-add-phy-loopback-support-for-imp-controlled.patch b/patches/0420-net-hns3-add-phy-loopback-support-for-imp-controlled.patch
new file mode 100644
index 0000000..e1303c3
--- /dev/null
+++ b/patches/0420-net-hns3-add-phy-loopback-support-for-imp-controlled.patch
@@ -0,0 +1,314 @@
+From 2c4c382df8cddb5878faaf8ec544ddaf2ae276e2 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:51 +0800
+Subject: [PATCH 059/283] net: hns3: add phy loopback support for
+ imp-controlled PHYs
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit b47cfe1f402dbf10279b8f12131388fdff9d2259
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b47cfe1f402dbf10279b8f12131388fdff9d2259
+
+----------------------------------------------------------------------
+
+If the imp-controlled PHYs feature is enabled, driver can not
+call phy driver interface to set loopback anymore and needs
+to send command to firmware to start phy loopback.
+
+Driver reuses the existing firmware command 0x0315 to start
+phy loopback, just add a setting bit in this command. As this
+command is not only for serdes loopback anymore, rename this
+command to "xxx_COMMON_LOOPBACK", and modify function name,
+macro name and logs related to it.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3_cae/hns3_cae_mac.c    |  4 +-
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  9 +--
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     | 32 ++++++----
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 64 ++++++++++---------
+ 4 files changed, 58 insertions(+), 51 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_mac.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_mac.c
+index acbb684cf43b..fe71b673e00d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_mac.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_mac.c
+@@ -61,7 +61,7 @@ int hns3_cae_mac_loop_cfg(const struct hns3_nic_priv *net_priv,
+ 		out_info->rx2tx_loop_en =
+ 		    hnae3_get_bit(req2->txrx_pad_fcs_loop_en,
+ 				  HCLGE_MAC_LINE_LP_B);
+-		hns3_cae_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
++		hns3_cae_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK,
+ 					      true);
+ 		ret = hns3_cae_cmd_send(hdev, &desc, 1);
+ 		if (ret) {
+@@ -111,7 +111,7 @@ int hns3_cae_mac_loop_cfg(const struct hns3_nic_priv *net_priv,
+ 			}
+ 		} else {
+ 			hns3_cae_cmd_setup_basic_desc(&desc,
+-						      HCLGE_OPC_SERDES_LOOPBACK,
++						      HCLGE_OPC_COMMON_LOOPBACK,
+ 						      true);
+ 			ret = hns3_cae_cmd_send(hdev, &desc, 1);
+ 			if (ret) {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 88aefd3685a7..028ff1722614 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -127,7 +127,7 @@ enum hclge_opcode_type {
+ 	HCLGE_OPC_QUERY_MAC_TNL_INT	= 0x0310,
+ 	HCLGE_OPC_MAC_TNL_INT_EN	= 0x0311,
+ 	HCLGE_OPC_CLEAR_MAC_TNL_INT	= 0x0312,
+-	HCLGE_OPC_SERDES_LOOPBACK       = 0x0315,
++	HCLGE_OPC_COMMON_LOOPBACK       = 0x0315,
+ 	HCLGE_OPC_CONFIG_FEC_MODE	= 0x031A,
+ 	/* check sum command */
+ 	HCLGE_OPC_CFG_CHECKSUM_EN       = 0x0601,
+@@ -976,9 +976,10 @@ struct hclge_pf_rst_done_cmd {
+ 
+ #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B	BIT(0)
+ #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B	BIT(2)
+-#define HCLGE_CMD_SERDES_DONE_B			BIT(0)
+-#define HCLGE_CMD_SERDES_SUCCESS_B		BIT(1)
+-struct hclge_serdes_lb_cmd {
++#define HCLGE_CMD_GE_PHY_INNER_LOOP_B		BIT(3)
++#define HCLGE_CMD_COMMON_LB_DONE_B		BIT(0)
++#define HCLGE_CMD_COMMON_LB_SUCCESS_B		BIT(1)
++struct hclge_common_lb_cmd {
+ 	u8 mask;
+ 	u8 enable;
+ 	u8 result;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index e73e10d17222..c65abb2c2b09 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -1845,14 +1845,14 @@ static int hclge_dbg_dump_loopback(struct hclge_dev *hdev, char *buf, int len)
+ {
+ 	struct phy_device *phydev = hdev->hw.mac.phydev;
+ 	struct hclge_config_mac_mode_cmd *req_app;
+-	struct hclge_serdes_lb_cmd *req_serdes;
++	struct hclge_common_lb_cmd *req_common;
+ 	struct hclge_desc desc;
+ 	u8 loopback_en;
+ 	int pos = 0;
+ 	int ret;
+ 
+ 	req_app = (struct hclge_config_mac_mode_cmd *)desc.data;
+-	req_serdes = (struct hclge_serdes_lb_cmd *)desc.data;
++	req_common = (struct hclge_common_lb_cmd *)desc.data;
+ 
+ 	pos += scnprintf(buf + pos, len - pos, "mac id: %u\n",
+ 			 hdev->hw.mac.mac_id);
+@@ -1870,28 +1870,32 @@ static int hclge_dbg_dump_loopback(struct hclge_dev *hdev, char *buf, int len)
+ 	pos += scnprintf(buf + pos, len - pos, "app loopback: %s\n",
+ 			 state_str[loopback_en]);
+ 
+-	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, true);
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, true);
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret) {
+ 		dev_err(&hdev->pdev->dev,
+-			"failed to dump serdes loopback status, ret = %d\n",
++			"failed to dump common loopback status, ret = %d\n",
+ 			ret);
+ 		return ret;
+ 	}
+ 
+-	loopback_en = req_serdes->enable & HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
+-	pos += scnprintf(buf + pos, len - pos, "serdes serial loopback: %s\n",
+-			 state_str[loopback_en]);
++	loopback_en = req_common->enable & HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
++	dev_info(&hdev->pdev->dev, "serdes serial loopback: %s\n",
++		 loopback_en ? "on" : "off");
+ 
+-	loopback_en = req_serdes->enable &
+-			HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B ? 1 : 0;
+-	pos += scnprintf(buf + pos, len - pos, "serdes parallel loopback: %s\n",
+-			 state_str[loopback_en]);
++	loopback_en = req_common->enable &
++			HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
++	dev_info(&hdev->pdev->dev, "serdes parallel loopback: %s\n",
++		 loopback_en ? "on" : "off");
+ 
+ 	if (phydev) {
+-		loopback_en = phydev->loopback_enabled;
+-		pos += scnprintf(buf + pos, len - pos, "phy loopback: %s\n",
+-				 state_str[loopback_en]);
++		dev_info(&hdev->pdev->dev, "phy loopback: %s\n",
++			 phydev->loopback_enabled ? "on" : "off");
++	} else if (hnae3_dev_phy_imp_supported(hdev)) {
++		loopback_en = req_common->enable &
++			      HCLGE_CMD_GE_PHY_INNER_LOOP_B;
++		dev_info(&hdev->pdev->dev, "phy loopback: %s\n",
++			 loopback_en ? "on" : "off");
+ 	}
+ 
+ 	return 0;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index abd79d4bc56d..949dfc433e3e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -752,8 +752,9 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
+ 		handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
+ 		handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
+ 
+-		if (hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv &&
+-		    hdev->hw.mac.phydev->drv->set_loopback) {
++		if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv &&
++		     hdev->hw.mac.phydev->drv->set_loopback) ||
++		    hnae3_dev_phy_imp_supported(hdev)) {
+ 			count += 1;
+ 			handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK;
+ 		}
+@@ -6863,19 +6864,19 @@ static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
+ 	return ret;
+ }
+ 
+-static int hclge_cfg_serdes_loopback(struct hclge_dev *hdev, bool en,
++static int hclge_cfg_common_loopback(struct hclge_dev *hdev, bool en,
+ 				     enum hnae3_loop loop_mode)
+ {
+-#define HCLGE_SERDES_RETRY_MS	10
+-#define HCLGE_SERDES_RETRY_NUM	100
++#define HCLGE_COMMON_LB_RETRY_MS	10
++#define HCLGE_COMMON_LB_RETRY_NUM	100
+ 
+-	struct hclge_serdes_lb_cmd *req;
++	struct hclge_common_lb_cmd *req;
+ 	struct hclge_desc desc;
+ 	int ret, i = 0;
+ 	u8 loop_mode_b;
+ 
+-	req = (struct hclge_serdes_lb_cmd *)desc.data;
+-	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
++	req = (struct hclge_common_lb_cmd *)desc.data;
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, false);
+ 
+ 	switch (loop_mode) {
+ 	case HNAE3_LOOP_SERIAL_SERDES:
+@@ -6884,9 +6885,12 @@ static int hclge_cfg_serdes_loopback(struct hclge_dev *hdev, bool en,
+ 	case HNAE3_LOOP_PARALLEL_SERDES:
+ 		loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
+ 		break;
++	case HNAE3_LOOP_PHY:
++		loop_mode_b = HCLGE_CMD_GE_PHY_INNER_LOOP_B;
++		break;
+ 	default:
+ 		dev_err(&hdev->pdev->dev,
+-			"unsupported serdes loopback mode %d\n", loop_mode);
++			"unsupported common loopback mode %d\n", loop_mode);
+ 		return -ENOTSUPP;
+ 	}
+ 
+@@ -6900,45 +6904,39 @@ static int hclge_cfg_serdes_loopback(struct hclge_dev *hdev, bool en,
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret) {
+ 		dev_err(&hdev->pdev->dev,
+-			"serdes loopback set fail, ret = %d\n", ret);
++			"common loopback set fail, ret = %d\n", ret);
+ 		return ret;
+ 	}
+ 
+ 	do {
+-		msleep(HCLGE_SERDES_RETRY_MS);
+-		hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
++		msleep(HCLGE_COMMON_LB_RETRY_MS);
++		hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK,
+ 					   true);
+ 		ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 		if (ret) {
+ 			dev_err(&hdev->pdev->dev,
+-				"serdes loopback get, ret = %d\n", ret);
++				"common loopback get, ret = %d\n", ret);
+ 			return ret;
+ 		}
+-	} while (++i < HCLGE_SERDES_RETRY_NUM &&
+-		 !(req->result & HCLGE_CMD_SERDES_DONE_B));
++	} while (++i < HCLGE_COMMON_LB_RETRY_NUM &&
++		 !(req->result & HCLGE_CMD_COMMON_LB_DONE_B));
+ 
+-	if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
+-		dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
++	if (!(req->result & HCLGE_CMD_COMMON_LB_DONE_B)) {
++		dev_err(&hdev->pdev->dev, "common loopback set timeout\n");
+ 		return -EBUSY;
+-	} else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
+-		dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
++	} else if (!(req->result & HCLGE_CMD_COMMON_LB_SUCCESS_B)) {
++		dev_err(&hdev->pdev->dev, "common loopback set failed in fw\n");
+ 		return -EIO;
+ 	}
+ 	return ret;
+ }
+ 
+-static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
++static int hclge_set_common_loopback(struct hclge_dev *hdev, bool en,
+ 				     enum hnae3_loop loop_mode)
+ {
+-	u8 duplex;
+ 	int ret;
+ 
+-	duplex = en ? DUPLEX_FULL : hdev->hw.mac.duplex;
+-	ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, duplex);
+-	if (ret)
+-		return ret;
+-
+-	ret = hclge_cfg_serdes_loopback(hdev, en, loop_mode);
++	ret = hclge_cfg_common_loopback(hdev, en, loop_mode);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -7000,8 +6998,12 @@ static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en)
+ 	u8 duplex;
+ 	int ret;
+ 
+-	if (!phydev)
++	if (!phydev) {
++		if (hnae3_dev_phy_imp_supported(hdev))
++			return hclge_set_common_loopback(hdev, en,
++							 HNAE3_LOOP_PHY);
+ 		return -ENOTSUPP;
++	}
+ 
+ 	duplex = en ? DUPLEX_FULL : hdev->hw.mac.duplex;
+ 	ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, duplex);
+@@ -7086,7 +7088,7 @@ static int hclge_set_loopback(struct hnae3_handle *handle,
+ 		break;
+ 	case HNAE3_LOOP_SERIAL_SERDES:
+ 	case HNAE3_LOOP_PARALLEL_SERDES:
+-		ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
++		ret = hclge_set_common_loopback(hdev, en, loop_mode);
+ 		break;
+ 	case HNAE3_LOOP_PHY:
+ 		ret = hclge_set_phy_loopback(hdev, en);
+@@ -7117,11 +7119,11 @@ static int hclge_set_default_loopback(struct hclge_dev *hdev)
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = hclge_cfg_serdes_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES);
++	ret = hclge_cfg_common_loopback(hdev, false, HNAE3_LOOP_SERIAL_SERDES);
+ 	if (ret)
+ 		return ret;
+ 
+-	return hclge_cfg_serdes_loopback(hdev, false,
++	return hclge_cfg_common_loopback(hdev, false,
+ 					 HNAE3_LOOP_PARALLEL_SERDES);
+ }
+ 
+-- 
+2.34.1
+
diff --git a/patches/0421-net-hns3-add-support-to-query-device-specifications.patch b/patches/0421-net-hns3-add-support-to-query-device-specifications.patch
new file mode 100644
index 0000000..5e23cd7
--- /dev/null
+++ b/patches/0421-net-hns3-add-support-to-query-device-specifications.patch
@@ -0,0 +1,286 @@
+From a5121f5fd129c3af716088c90b4e986466bd27b7 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sun, 27 Sep 2020 15:12:45 +0800
+Subject: [PATCH 060/283] net: hns3: add support to query device specifications
+
+mainline inclusion
+from mainline-v5.10-rc1
+commit af2aedc57277dfd1d9ebe16777cf84dccce8e68d
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=af2aedc57277dfd1d9ebe16777cf84dccce8e68d
+--------------------------------
+
+To improve code maintainability and compatibility, new commands
+HCLGE_OPC_QUERY_DEV_SPECS for PF and HCLGEVF_OPC_QUERY_DEV_SPECS
+for VF are introduced to query device specifications, instead of
+statically defining specifications by checking the hardware version
+or other methods.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   | 11 ++++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  6 +-
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 62 ++++++++++++++++++
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       | 15 +++++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 64 +++++++++++++++++++
+ 5 files changed, 155 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 99fe5603ef1c..6a21c1b0434e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -321,6 +321,16 @@ struct hnae3_ring_chain_node {
+ #define HNAE3_IS_TX_RING(node) \
+ 	(((node)->flag & 1 << HNAE3_RING_TYPE_B) == HNAE3_RING_TYPE_TX)
+ 
++/* device specification info from firmware */
++struct hnae3_dev_specs {
++	u32 mac_entry_num; /* number of mac-vlan table entry */
++	u32 mng_entry_num; /* number of manager table entry */
++	u16 rss_ind_tbl_size;
++	u16 rss_key_size;
++	u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */
++	u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */
++};
++
+ struct hnae3_client_ops {
+ 	int (*init_instance)(struct hnae3_handle *handle);
+ 	void (*uninit_instance)(struct hnae3_handle *handle, bool reset);
+@@ -348,6 +358,7 @@ struct hnae3_ae_dev {
+ 	u32 flag;
+ 	unsigned long hw_err_reset_req;
+ #ifndef __GENKSYMS__
++	struct hnae3_dev_specs dev_specs;
+ 	u32 dev_version;
+ 	unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)];
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 028ff1722614..865316591916 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -116,7 +116,8 @@ enum hclge_opcode_type {
+ 	HCLGE_OPC_DFX_RCB_REG		= 0x004D,
+ 	HCLGE_OPC_DFX_TQP_REG		= 0x004E,
+ 	HCLGE_OPC_DFX_SSU_REG_2		= 0x004F,
+-	HCLGE_OPC_DFX_QUERY_CHIP_CAP	= 0x0050,
++
++	HCLGE_OPC_QUERY_DEV_SPECS	= 0x0050,
+ 
+ 	/* MAC command */
+ 	HCLGE_OPC_CONFIG_MAC_MODE	= 0x0301,
+@@ -1141,8 +1142,7 @@ struct hclge_dev_specs_0_cmd {
+ 	__le16 rss_key_size;
+ 	__le16 int_ql_max;
+ 	u8 max_non_tso_bd_num;
+-	u8 rsv1;
+-	__le32 max_tm_rate;
++	u8 rsv1[5];
+ };
+ 
+ #define HCLGE_DEF_MAX_INT_GL		0x1FE0U
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 949dfc433e3e..67b0279303cd 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1356,6 +1356,61 @@ static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
+ 	return 0;
+ }
+ 
++static void hclge_set_default_dev_specs(struct hclge_dev *hdev)
++{
++#define HCLGE_MAX_NON_TSO_BD_NUM			8U
++
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++
++	ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
++	ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
++	ae_dev->dev_specs.rss_key_size = HCLGE_RSS_KEY_SIZE;
++}
++
++static void hclge_parse_dev_specs(struct hclge_dev *hdev,
++				  struct hclge_desc *desc)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	struct hclge_dev_specs_0_cmd *req0;
++
++	req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data;
++
++	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
++	ae_dev->dev_specs.rss_ind_tbl_size =
++		le16_to_cpu(req0->rss_ind_tbl_size);
++	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
++}
++
++static int hclge_query_dev_specs(struct hclge_dev *hdev)
++{
++	struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM];
++	int ret;
++	int i;
++
++	/* set default specifications as devices lower than version V3 do not
++	 * support querying specifications from firmware.
++	 */
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
++		hclge_set_default_dev_specs(hdev);
++		return 0;
++	}
++
++	for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
++		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS,
++					   true);
++		desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	}
++	hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
++
++	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_QUERY_DEV_SPECS_BD_NUM);
++	if (ret)
++		return ret;
++
++	hclge_parse_dev_specs(hdev, desc);
++
++	return 0;
++}
++
+ static int hclge_get_cap(struct hclge_dev *hdev)
+ {
+ 	int ret;
+@@ -10551,6 +10606,13 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	if (ret)
+ 		goto err_cmd_uninit;
+ 
++	ret = hclge_query_dev_specs(hdev);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to query dev specifications, ret = %d.\n",
++			ret);
++		goto err_cmd_uninit;
++	}
++
+ 	ret = hclge_configure(hdev);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 7d021cb394c5..942a1d7406a0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -92,6 +92,8 @@ enum hclgevf_opcode_type {
+ 	/* Generic command */
+ 	HCLGEVF_OPC_QUERY_FW_VER	= 0x0001,
+ 	HCLGEVF_OPC_QUERY_VF_RSRC	= 0x0024,
++	HCLGEVF_OPC_QUERY_DEV_SPECS	= 0x0050,
++
+ 	/* TQP command */
+ 	HCLGEVF_OPC_QUERY_TX_STATUS	= 0x0B03,
+ 	HCLGEVF_OPC_QUERY_RX_STATUS	= 0x0B13,
+@@ -272,6 +274,19 @@ struct hclgevf_cfg_tx_queue_pointer_cmd {
+ 
+ #define HCLGEVF_RING_BASEADDR_SHIFT   32
+ 
++#define HCLGEVF_QUERY_DEV_SPECS_BD_NUM		4
++
++struct hclgevf_dev_specs_0_cmd {
++	__le32 rsv0;
++	__le32 mac_entry_num;
++	__le32 mng_entry_num;
++	__le16 rss_ind_tbl_size;
++	__le16 rss_key_size;
++	__le16 int_ql_max;
++	u8 max_non_tso_bd_num;
++	u8 rsv1[5];
++};
++
+ static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
+ {
+ 	writel(value, base + reg);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index accec5762d91..eed608ebe0a6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -3038,6 +3038,63 @@ static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
+ 	return 0;
+ }
+ 
++static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)
++{
++#define HCLGEVF_MAX_NON_TSO_BD_NUM			8U
++
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++
++	ae_dev->dev_specs.max_non_tso_bd_num =
++					HCLGEVF_MAX_NON_TSO_BD_NUM;
++	ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
++	ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE;
++}
++
++static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
++				    struct hclgevf_desc *desc)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	struct hclgevf_dev_specs_0_cmd *req0;
++
++	req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;
++
++	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
++	ae_dev->dev_specs.rss_ind_tbl_size =
++					le16_to_cpu(req0->rss_ind_tbl_size);
++	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
++}
++
++static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
++{
++	struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];
++	int ret;
++	int i;
++
++	/* set default specifications as devices lower than version V3 do not
++	 * support querying specifications from firmware.
++	 */
++	if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
++		hclgevf_set_default_dev_specs(hdev);
++		return 0;
++	}
++
++	for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
++		hclgevf_cmd_setup_basic_desc(&desc[i],
++					     HCLGEVF_OPC_QUERY_DEV_SPECS, true);
++		desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT);
++	}
++	hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS,
++				     true);
++
++	ret = hclgevf_cmd_send(&hdev->hw, desc, HCLGEVF_QUERY_DEV_SPECS_BD_NUM);
++	if (ret)
++		return ret;
++
++	hclgevf_parse_dev_specs(hdev, desc);
++
++	return 0;
++}
++
+ static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
+ {
+ 	struct pci_dev *pdev = hdev->pdev;
+@@ -3147,6 +3204,13 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
+ 	if (ret)
+ 		goto err_cmd_init;
+ 
++	ret = hclgevf_query_dev_specs(hdev);
++	if (ret) {
++		dev_err(&pdev->dev,
++			"failed to query dev specifications, ret = %d\n", ret);
++		goto err_cmd_init;
++	}
++
+ 	ret = hclgevf_init_msi(hdev);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
+-- 
+2.34.1
+
diff --git a/patches/0422-net-hns3-remove-unused-code-of-vmdq.patch b/patches/0422-net-hns3-remove-unused-code-of-vmdq.patch
new file mode 100644
index 0000000..af3af58
--- /dev/null
+++ b/patches/0422-net-hns3-remove-unused-code-of-vmdq.patch
@@ -0,0 +1,497 @@
+From ec9d476015ea7b74fc96fb7e6215d1efcf5f542a Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:59 +0800
+Subject: [PATCH 061/283] net: hns3: remove unused code of vmdq
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit 43f8b9333d86d4e3a42e55a6e41c78c249ac0216
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=43f8b9333d86d4e3a42e55a6e41c78c249ac0216
+
+----------------------------------------------------------------------
+
+Vmdq is not supported yet, the num_vmdq_vport is always 0,
+it's a bit confusing when using the num_vport, so remove
+these unused codes of vmdq.
+
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |   2 -
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 247 ++++++++----------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   2 -
+ .../hisilicon/hns3/hns3vf/hclgevf_main.h      |   1 -
+ 4 files changed, 102 insertions(+), 150 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 865316591916..b6498f8ce224 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -500,8 +500,6 @@ struct hclge_pf_res_cmd {
+ #define HCLGE_CFG_RD_LEN_BYTES	16
+ #define HCLGE_CFG_RD_LEN_UNIT	4
+ 
+-#define HCLGE_CFG_VMDQ_S	0
+-#define HCLGE_CFG_VMDQ_M	GENMASK(7, 0)
+ #define HCLGE_CFG_TC_NUM_S	8
+ #define HCLGE_CFG_TC_NUM_M	GENMASK(15, 8)
+ #define HCLGE_CFG_TQP_DESC_N_S	16
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 67b0279303cd..5885e1181517 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1266,9 +1266,6 @@ static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
+ 	req = (struct hclge_cfg_param_cmd *)desc[0].data;
+ 
+ 	/* get the configuration */
+-	cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
+-					      HCLGE_CFG_VMDQ_M,
+-					      HCLGE_CFG_VMDQ_S);
+ 	cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
+ 				      HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
+ 	cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
+@@ -1438,7 +1435,7 @@ static void hclge_init_kdump_kernel_config(struct hclge_dev *hdev)
+ 		 "Running kdump kernel. Using minimal resources\n");
+ 
+ 	/* minimal queue pairs equals to the number of vports */
+-	hdev->num_tqps = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
++	hdev->num_tqps = hdev->num_req_vfs + 1;
+ 	hdev->num_tx_desc = HCLGE_MIN_TX_DESC;
+ 	hdev->num_rx_desc = HCLGE_MIN_RX_DESC;
+ }
+@@ -1455,7 +1452,6 @@ static int hclge_configure(struct hclge_dev *hdev)
+ 	if (ret)
+ 		return ret;
+ 
+-	hdev->num_vmdq_vport = cfg.vmdq_vport_num;
+ 	hdev->base_tqp_pid = 0;
+ 	hdev->rss_size_max = cfg.rss_size_max;
+ 	hdev->rx_buf_len = cfg.rx_buf_len;
+@@ -1697,8 +1693,8 @@ static int hclge_map_tqp(struct hclge_dev *hdev)
+ 	struct hclge_vport *vport = hdev->vport;
+ 	u16 i, num_vport;
+ 
+-	num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
+-	for (i = 0; i < num_vport; i++) {
++	num_vport = hdev->num_req_vfs + 1;
++	for (i = 0; i < num_vport; i++)	{
+ 		int ret;
+ 
+ 		ret = hclge_map_tqp_to_vport(hdev, vport);
+@@ -1739,7 +1735,7 @@ static int hclge_alloc_vport(struct hclge_dev *hdev)
+ 	int ret;
+ 
+ 	/* We need to alloc a vport for main NIC of PF */
+-	num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
++	num_vport = hdev->num_req_vfs + 1;
+ 
+ 	if (hdev->num_tqps < num_vport) {
+ 		dev_err(&hdev->pdev->dev, "tqps(%u) is less than vports(%d)",
+@@ -2825,13 +2821,12 @@ static void hclge_push_link_status(struct hclge_dev *hdev)
+ 
+ static void hclge_update_link_status(struct hclge_dev *hdev)
+ {
++	struct hnae3_handle *rhandle = &hdev->vport[0].roce;
++	struct hnae3_handle *handle = &hdev->vport[0].nic;
+ 	struct hnae3_client *rclient = hdev->roce_client;
+ 	struct hnae3_client *client = hdev->nic_client;
+-	struct hnae3_handle *rhandle;
+-	struct hnae3_handle *handle;
+ 	int state;
+ 	int ret;
+-	int i;
+ 
+ 	if (!client)
+ 		return;
+@@ -2847,15 +2842,10 @@ static void hclge_update_link_status(struct hclge_dev *hdev)
+ 
+ 	if (state != hdev->hw.mac.link) {
+ 		hdev->hw.mac.link = state;
+-		for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
+-			handle = &hdev->vport[i].nic;
+-			client->ops->link_status_change(handle, state);
+-			hclge_config_mac_tnl_int(hdev, state);
+-			rhandle = &hdev->vport[i].roce;
+-			if (rclient && rclient->ops->link_status_change)
+-				rclient->ops->link_status_change(rhandle,
+-								 state);
+-		}
++		client->ops->link_status_change(handle, state);
++		hclge_config_mac_tnl_int(hdev, state);
++		if (rclient && rclient->ops->link_status_change)
++			rclient->ops->link_status_change(rhandle, state);
+ 
+ 		hclge_push_link_status(hdev);
+ 	}
+@@ -3429,8 +3419,9 @@ static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
+ int hclge_notify_client(struct hclge_dev *hdev,
+ 			enum hnae3_reset_notify_type type)
+ {
++	struct hnae3_handle *handle = &hdev->vport[0].nic;
+ 	struct hnae3_client *client = hdev->nic_client;
+-	u16 i;
++	int ret;
+ 
+ 	if (!test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state) || !client)
+ 		return 0;
+@@ -3438,27 +3429,20 @@ int hclge_notify_client(struct hclge_dev *hdev,
+ 	if (!client->ops->reset_notify)
+ 		return -EOPNOTSUPP;
+ 
+-	for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
+-		struct hnae3_handle *handle = &hdev->vport[i].nic;
+-		int ret;
+-
+-		ret = client->ops->reset_notify(handle, type);
+-		if (ret) {
+-			dev_err(&hdev->pdev->dev,
+-				"notify nic client failed %d(%d)\n", type, ret);
+-			return ret;
+-		}
+-	}
++	ret = client->ops->reset_notify(handle, type);
++	if (ret)
++		dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
++			type, ret);
+ 
+-	return 0;
++	return ret;
+ }
+ 
+ static int hclge_notify_roce_client(struct hclge_dev *hdev,
+ 				    enum hnae3_reset_notify_type type)
+ {
++	struct hnae3_handle *handle = &hdev->vport[0].roce;
+ 	struct hnae3_client *client = hdev->roce_client;
+-	int ret = 0;
+-	u16 i;
++	int ret;
+ 
+ 	if (!test_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state) || !client)
+ 		return 0;
+@@ -3466,17 +3450,10 @@ static int hclge_notify_roce_client(struct hclge_dev *hdev,
+ 	if (!client->ops->reset_notify)
+ 		return -EOPNOTSUPP;
+ 
+-	for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
+-		struct hnae3_handle *handle = &hdev->vport[i].roce;
+-
+-		ret = client->ops->reset_notify(handle, type);
+-		if (ret) {
+-			dev_err(&hdev->pdev->dev,
+-				"notify roce client failed %d(%d)",
+-				type, ret);
+-			return ret;
+-		}
+-	}
++	ret = client->ops->reset_notify(handle, type);
++	if (ret)
++		dev_err(&hdev->pdev->dev, "notify roce client failed %d(%d)",
++			type, ret);
+ 
+ 	return ret;
+ }
+@@ -3544,7 +3521,7 @@ static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
+ {
+ 	int i;
+ 
+-	for (i = hdev->num_vmdq_vport + 1; i < hdev->num_alloc_vport; i++) {
++	for (i = HCLGE_VF_VPORT_START_NUM; i < hdev->num_alloc_vport; i++) {
+ 		struct hclge_vport *vport = &hdev->vport[i];
+ 		int ret;
+ 
+@@ -3627,14 +3604,12 @@ void hclge_report_hw_error(struct hclge_dev *hdev,
+ 			   enum hnae3_hw_error_type type)
+ {
+ 	struct hnae3_client *client = hdev->nic_client;
+-	u16 i;
+ 
+ 	if (!client || !client->ops->process_hw_error ||
+ 	    !test_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state))
+ 		return;
+ 
+-	for (i = 0; i < hdev->num_vmdq_vport + 1; i++)
+-		client->ops->process_hw_error(&hdev->vport[i].nic, type);
++	client->ops->process_hw_error(&hdev->vport[0].nic, type);
+ }
+ 
+ static void hclge_handle_imp_error(struct hclge_dev *hdev)
+@@ -4424,7 +4399,7 @@ static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
+ 	return 0;
+ }
+ 
+-static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
++static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u16 *indir)
+ {
+ 	struct hclge_rss_indirection_table_cmd *req;
+ 	struct hclge_desc desc;
+@@ -4843,7 +4818,7 @@ static int hclge_init_rss_tc_mode(struct hclge_dev *hdev)
+ int hclge_rss_init_hw(struct hclge_dev *hdev)
+ {
+ 	struct hclge_vport *vport = hdev->vport;
+-	u8 *rss_indir = vport[0].rss_indirection_tbl;
++	u16 *rss_indir = vport[0].rss_indirection_tbl;
+ 	u8 *key = vport[0].rss_hash_key;
+ 	u8 hfunc = vport[0].rss_algo;
+ 	int ret;
+@@ -4865,49 +4840,48 @@ int hclge_rss_init_hw(struct hclge_dev *hdev)
+ 
+ void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
+ {
+-	struct hclge_vport *vport = hdev->vport;
+-	int i, j;
++	struct hclge_vport *vport = &hdev->vport[0];
++	int i;
+ 
+-	for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
+-		for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
+-			vport[j].rss_indirection_tbl[i] =
+-				i % vport[j].alloc_rss_size;
+-	}
++	for (i = 0; i < hdev->ae_dev->dev_specs.rss_ind_tbl_size; i++)
++		vport->rss_indirection_tbl[i] = i % vport->alloc_rss_size;
+ }
+ 
+-static void hclge_rss_init_cfg(struct hclge_dev *hdev)
++static int hclge_rss_init_cfg(struct hclge_dev *hdev)
+ {
+-	int i, rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
+-	struct hclge_vport *vport = hdev->vport;
++	u16 rss_ind_tbl_size = hdev->ae_dev->dev_specs.rss_ind_tbl_size;
++	int rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
++	struct hclge_vport *vport = &hdev->vport[0];
++	u16 *rss_ind_tbl;
+ 
+ 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+ 		rss_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
+ 
+-	for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
+-		vport[i].rss_tuple_sets.ipv4_tcp_en =
+-			HCLGE_RSS_INPUT_TUPLE_OTHER;
+-		vport[i].rss_tuple_sets.ipv4_udp_en =
+-			HCLGE_RSS_INPUT_TUPLE_OTHER;
+-		vport[i].rss_tuple_sets.ipv4_sctp_en =
+-			HCLGE_RSS_INPUT_TUPLE_SCTP4;
+-		vport[i].rss_tuple_sets.ipv4_fragment_en =
+-			HCLGE_RSS_INPUT_TUPLE_OTHER;
+-		vport[i].rss_tuple_sets.ipv6_tcp_en =
+-			HCLGE_RSS_INPUT_TUPLE_OTHER;
+-		vport[i].rss_tuple_sets.ipv6_udp_en =
+-			HCLGE_RSS_INPUT_TUPLE_OTHER;
+-		vport[i].rss_tuple_sets.ipv6_sctp_en =
+-			HCLGE_RSS_INPUT_TUPLE_SCTP6;
+-		vport[i].rss_tuple_sets.ipv6_fragment_en =
+-			HCLGE_RSS_INPUT_TUPLE_OTHER;
+-
+-		vport[i].rss_algo = rss_algo;
+-
+-		memcpy(vport[i].rss_hash_key, hclge_hash_key,
+-		       HCLGE_RSS_KEY_SIZE);
+-	}
++	vport->rss_tuple_sets.ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
++	vport->rss_tuple_sets.ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
++	vport->rss_tuple_sets.ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP4;
++	vport->rss_tuple_sets.ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
++	vport->rss_tuple_sets.ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
++	vport->rss_tuple_sets.ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
++	vport->rss_tuple_sets.ipv6_sctp_en =
++		hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2 ?
++		HCLGE_RSS_INPUT_TUPLE_SCTP6 :
++		HCLGE_RSS_INPUT_TUPLE_SCTP4;
++	vport->rss_tuple_sets.ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
++
++	vport->rss_algo = rss_algo;
++
++	rss_ind_tbl = devm_kcalloc(&hdev->pdev->dev, rss_ind_tbl_size,
++				   sizeof(*rss_ind_tbl), GFP_KERNEL);
++	if (!rss_ind_tbl)
++		return -ENOMEM;
++
++	vport->rss_indirection_tbl = rss_ind_tbl;
++	memcpy(vport->rss_hash_key, hclge_hash_key, HCLGE_RSS_KEY_SIZE);
+ 
+ 	hclge_rss_indir_init_cfg(hdev);
++
++	return 0;
+ }
+ 
+ int hclge_bind_ring_with_vector(struct hclge_vport *vport,
+@@ -10186,7 +10160,6 @@ static void hclge_info_show(struct hclge_dev *hdev)
+ 	dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
+ 	dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
+ 	dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
+-	dev_info(dev, "Numbers of vmdp vports: %u\n", hdev->num_vmdq_vport);
+ 	dev_info(dev, "Numbers of VF for this PF: %u\n", hdev->num_req_vfs);
+ 	dev_info(dev, "HW tc map: %u\n", hdev->hw_tc_map);
+ 	dev_info(dev, "Total buffer size for TX/RX: %u\n", hdev->pkt_buf_size);
+@@ -10306,39 +10279,35 @@ static int hclge_init_client_instance(struct hnae3_client *client,
+ 				      struct hnae3_ae_dev *ae_dev)
+ {
+ 	struct hclge_dev *hdev = ae_dev->priv;
+-	struct hclge_vport *vport;
+-	int i, ret;
+-
+-	for (i = 0; i <  hdev->num_vmdq_vport + 1; i++) {
+-		vport = &hdev->vport[i];
++	struct hclge_vport *vport = &hdev->vport[0];
++	int ret;
+ 
+-		switch (client->type) {
+-		case HNAE3_CLIENT_KNIC:
+-			hdev->nic_client = client;
+-			vport->nic.client = client;
+-			ret = hclge_init_nic_client_instance(ae_dev, vport);
+-			if (ret)
+-				goto clear_nic;
++	switch (client->type) {
++	case HNAE3_CLIENT_KNIC:
++		hdev->nic_client = client;
++		vport->nic.client = client;
++		ret = hclge_init_nic_client_instance(ae_dev, vport);
++		if (ret)
++			goto clear_nic;
+ 
+-			ret = hclge_init_roce_client_instance(ae_dev, vport);
+-			if (ret)
+-				goto clear_roce;
++		ret = hclge_init_roce_client_instance(ae_dev, vport);
++		if (ret)
++			goto clear_roce;
+ 
+-			break;
+-		case HNAE3_CLIENT_ROCE:
+-			if (hnae3_dev_roce_supported(hdev)) {
+-				hdev->roce_client = client;
+-				vport->roce.client = client;
+-			}
++		break;
++	case HNAE3_CLIENT_ROCE:
++		if (hnae3_dev_roce_supported(hdev)) {
++			hdev->roce_client = client;
++			vport->roce.client = client;
++		}
+ 
+-			ret = hclge_init_roce_client_instance(ae_dev, vport);
+-			if (ret)
+-				goto clear_roce;
++		ret = hclge_init_roce_client_instance(ae_dev, vport);
++		if (ret)
++			goto clear_roce;
+ 
+-			break;
+-		default:
+-			return -EINVAL;
+-		}
++		break;
++	default:
++		return -EINVAL;
+ 	}
+ 
+ 	return 0;
+@@ -10357,39 +10326,27 @@ static void hclge_uninit_client_instance(struct hnae3_client *client,
+ 					 struct hnae3_ae_dev *ae_dev)
+ {
+ 	struct hclge_dev *hdev = ae_dev->priv;
+-	struct hclge_vport *vport;
+-	int i;
++	struct hclge_vport *vport = &hdev->vport[0];
+ 
+-#ifdef CONFIG_HNS3_TEST
+-	if (ae_dev->ops->ext_uninit) {
+-		vport = &hdev->vport[0];
+-		ae_dev->ops->ext_uninit(&vport->nic);
+-	}
+-#endif
++	if (hdev->roce_client) {
++		clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
++		while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
++			msleep(HCLGE_WAIT_RESET_DONE);
+ 
+-	for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
+-		vport = &hdev->vport[i];
+-		if (hdev->roce_client) {
+-			clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
+-			while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
+-				msleep(HCLGE_WAIT_RESET_DONE);
+-
+-			hdev->roce_client->ops->uninit_instance(&vport->roce,
+-								0);
+-			hdev->roce_client = NULL;
+-			vport->roce.client = NULL;
+-		}
+-		if (client->type == HNAE3_CLIENT_ROCE)
+-			return;
+-		if (hdev->nic_client && client->ops->uninit_instance) {
+-			clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
+-			while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
+-				msleep(HCLGE_WAIT_RESET_DONE);
+-
+-			client->ops->uninit_instance(&vport->nic, 0);
+-			hdev->nic_client = NULL;
+-			vport->nic.client = NULL;
+-		}
++		hdev->roce_client->ops->uninit_instance(&vport->roce, 0);
++		hdev->roce_client = NULL;
++		vport->roce.client = NULL;
++	}
++	if (client->type == HNAE3_CLIENT_ROCE)
++		return;
++	if (hdev->nic_client && client->ops->uninit_instance) {
++		clear_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state);
++		while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
++			msleep(HCLGE_WAIT_RESET_DONE);
++
++		client->ops->uninit_instance(&vport->nic, 0);
++		hdev->nic_client = NULL;
++		vport->nic.client = NULL;
+ 	}
+ }
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 138358b3b16b..ac88f2dd9f3b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -361,7 +361,6 @@ struct hclge_tc_info {
+ };
+ 
+ struct hclge_cfg {
+-	u8 vmdq_vport_num;
+ 	u8 tc_num;
+ 	u8 vlan_fliter_cap;
+ 	u16 tqp_desc_num;
+@@ -772,7 +771,6 @@ struct hclge_dev {
+ 	struct semaphore reset_sem;	/* protect reset process */
+ 	u32 reset_fail_cnt;
+ 	u32 fw_version;
+-	u16 num_vmdq_vport;		/* Num vmdq vport this PF has set up */
+ 	u16 num_tqps;			/* Num task queue pairs of this PF */
+ 	u16 num_req_vfs;		/* Num VFs requested for this PF */
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index fe0c87a9e2ff..a35bbfd93384 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -191,7 +191,6 @@ struct hclgevf_tqp {
+ };
+ 
+ struct hclgevf_cfg {
+-	u8 vmdq_vport_num;
+ 	u8 tc_num;
+ 	u16 tqp_desc_num;
+ 	u16 rx_buf_len;
+-- 
+2.34.1
+
diff --git a/patches/0423-net-hns3-remove-redundant-blank-lines.patch b/patches/0423-net-hns3-remove-redundant-blank-lines.patch
new file mode 100644
index 0000000..5c259ae
--- /dev/null
+++ b/patches/0423-net-hns3-remove-redundant-blank-lines.patch
@@ -0,0 +1,206 @@
+From b0653457f736251682d9068068c758eeb967b7d4 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Sat, 24 Jul 2021 15:44:00 +0800
+Subject: [PATCH 062/283] net: hns3: remove redundant blank lines
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit c0127115ee2329dd57a65dceb139ec7cc39f48c7
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c0127115ee2329dd57a65dceb139ec7cc39f48c7
+
+----------------------------------------------------------------------
+
+Remove some redundant blank lines.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c           | 5 -----
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c    | 1 -
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c    | 2 --
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c   | 5 -----
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h   | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c  | 1 -
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 2 --
+ 7 files changed, 1 insertion(+), 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index d2284ce2c250..b78f2fe7f39c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -1234,7 +1234,6 @@ static unsigned int hns3_tx_bd_num(struct sk_buff *skb, unsigned int *bd_size,
+ 		return UINT_MAX;
+ 
+ 	bd_num = hns3_skb_bd_num(skb, bd_size, bd_num);
+-
+ 	if (!skb_has_frag_list(skb) || bd_num > HNS3_MAX_TSO_BD_NUM)
+ 		return bd_num;
+ 
+@@ -2940,7 +2939,6 @@ static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
+ 					  HNS3_RXD_L3ID_S);
+ 		l4_type = hnae3_get_field(l234info, HNS3_RXD_L4ID_M,
+ 					  HNS3_RXD_L4ID_S);
+-
+ 		/* Can checksum ipv4 or ipv6 + UDP/TCP/SCTP packets */
+ 		if ((l3_type == HNS3_L3_TYPE_IPV4 ||
+ 		     l3_type == HNS3_L3_TYPE_IPV6) &&
+@@ -3282,7 +3280,6 @@ static int hns3_handle_rx_bd(struct hns3_enet_ring *ring)
+ 
+ 	if (!skb) {
+ 		bd_base_info = le32_to_cpu(desc->rx.bd_base_info);
+-
+ 		/* Check valid BD */
+ 		if (unlikely(!(bd_base_info & BIT(HNS3_RXD_VLD_B))))
+ 			return -ENXIO;
+@@ -3547,7 +3544,6 @@ static int hns3_nic_common_poll(struct napi_struct *napi, int budget)
+ 	hns3_for_each_ring(ring, tqp_vector->rx_group) {
+ 		int rx_cleaned = hns3_clean_rx_ring(ring, rx_budget,
+ 						    hns3_rx_skb);
+-
+ 		if (rx_cleaned >= rx_budget)
+ 			clean_complete = false;
+ 
+@@ -4021,7 +4017,6 @@ static void hns3_init_ring_hw(struct hns3_enet_ring *ring)
+ 			       hns3_buf_size2type(ring->buf_size));
+ 		hns3_write_dev(q, HNS3_RING_RX_RING_BD_NUM_REG,
+ 			       ring->desc_num / 8 - 1);
+-
+ 	} else {
+ 		hns3_write_dev(q, HNS3_RING_TX_RING_BASEADDR_L_REG,
+ 			       (u32)dma);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index c4d30bcc8fa3..7646e510c0e7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -379,7 +379,6 @@ static void hclge_parse_capability(struct hclge_dev *hdev,
+ 	u32 caps;
+ 
+ 	caps = __le32_to_cpu(cmd->caps[0]);
+-
+ 	if (hnae3_get_bit(caps, HCLGE_CAP_UDP_GSO_B))
+ 		set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
+ 	if (hnae3_get_bit(caps, HCLGE_CAP_PTP_B))
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 9265243fbb84..7d72e30d0d16 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -1498,7 +1498,6 @@ hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev)
+ 	}
+ 
+ 	status = le32_to_cpu(desc[0].data[0]);
+-
+ 	if (status & HCLGE_ROCEE_AXI_ERR_INT_MASK) {
+ 		if (status & HCLGE_ROCEE_RERR_INT_MASK)
+ 			dev_err(dev, "ROCEE RAS AXI rresp error\n");
+@@ -1651,7 +1650,6 @@ pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev)
+ 	}
+ 
+ 	status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG);
+-
+ 	if (status & HCLGE_RAS_REG_NFE_MASK ||
+ 	    status & HCLGE_RAS_REG_ROCEE_ERR_MASK)
+ 		ae_dev->hw_err_reset_req = 0;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 5885e1181517..6c2960df62a6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -527,7 +527,6 @@ int hclge_mac_update_stats(struct hclge_dev *hdev)
+ 	int ret;
+ 
+ 	ret = hclge_mac_query_reg_num(hdev, &desc_num);
+-
+ 	/* The firmware supports the new statistics acquisition method */
+ 	if (!ret)
+ 		ret = hclge_mac_update_stats_complete(hdev, desc_num);
+@@ -758,7 +757,6 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
+ 			count += 1;
+ 			handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK;
+ 		}
+-
+ 	} else if (stringset == ETH_SS_STATS) {
+ 		count = ARRAY_SIZE(g_mac_stats_string) +
+ 			hclge_tqps_get_sset_count(handle, stringset);
+@@ -2113,7 +2111,6 @@ static int hclge_only_alloc_priv_buff(struct hclge_dev *hdev,
+ 			COMPENSATE_HALF_MPS_NUM * half_mps;
+ 	min_rx_priv = round_up(min_rx_priv, HCLGE_BUF_SIZE_UNIT);
+ 	rx_priv = round_down(rx_priv, HCLGE_BUF_SIZE_UNIT);
+-
+ 	if (rx_priv < min_rx_priv)
+ 		return false;
+ 
+@@ -7860,7 +7857,6 @@ int hclge_add_mc_addr_common(struct hclge_vport *vport,
+ 	if (status)
+ 		return status;
+ 	status = hclge_add_mac_vlan_tbl(vport, &req, desc);
+-
+ 	/* if already overflow, not to print each time */
+ 	if (status == -ENOSPC &&
+ 	    !(vport->overflow_promisc_flags & HNAE3_OVERFLOW_MPE)) {
+@@ -7912,7 +7908,6 @@ int hclge_rm_mc_addr_common(struct hclge_vport *vport,
+ 		else
+ 			/* Not all the vfid is zero, update the vfid */
+ 			status = hclge_add_mac_vlan_tbl(vport, &req, desc);
+-
+ 	} else if (status == -ENOENT) {
+ 		status = 0;
+ 	}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index ac88f2dd9f3b..56a7c6a3e1d9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -946,7 +946,7 @@ struct hclge_vport {
+ 
+ 	u8  rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
+ 	/* User configured lookup table entries */
+-	u8  rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
++	u16 *rss_indirection_tbl;
+ 	int rss_algo;		/* User configured hash algorithm */
+ 	/* User configured rss tuple sets */
+ 	struct hclge_rss_tuple_cfg rss_tuple_sets;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 9430334e1c22..67d44d21814e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -365,7 +365,6 @@ static void hclgevf_parse_capability(struct hclgevf_dev *hdev,
+ 	u32 caps;
+ 
+ 	caps = __le32_to_cpu(cmd->caps[0]);
+-
+ 	if (hnae3_get_bit(caps, HCLGEVF_CAP_UDP_GSO_B))
+ 		set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
+ 	if (hnae3_get_bit(caps, HCLGEVF_CAP_INT_QL_B))
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index eed608ebe0a6..9368e6ab8310 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -487,7 +487,6 @@ void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
+ 
+ 	link_state =
+ 		test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
+-
+ 	if (link_state != hdev->hw.mac.link) {
+ 		hdev->hw.mac.link = link_state;
+ 		client->ops->link_status_change(handle, !!link_state);
+@@ -2352,7 +2351,6 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
+ 	/* fetch the events from their corresponding regs */
+ 	cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
+ 					 HCLGEVF_VECTOR0_CMDQ_STATE_REG);
+-
+ 	if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
+ 		rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
+ 		dev_info(&hdev->pdev->dev,
+-- 
+2.34.1
+
diff --git a/patches/0424-net-hns3-remove-redundant-query-in-hclge_config_tm_h.patch b/patches/0424-net-hns3-remove-redundant-query-in-hclge_config_tm_h.patch
new file mode 100644
index 0000000..e83a1e1
--- /dev/null
+++ b/patches/0424-net-hns3-remove-redundant-query-in-hclge_config_tm_h.patch
@@ -0,0 +1,53 @@
+From 4ee2e9ca379a23b990b6e46bcc68b94eb6fd09c6 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Sat, 24 Jul 2021 15:44:01 +0800
+Subject: [PATCH 063/283] net: hns3: remove redundant query in
+ hclge_config_tm_hw_err_int()
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit d914971df022e7abdb5f8fdfd901a655c9786c05
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d914971df022e7abdb5f8fdfd901a655c9786c05
+
+----------------------------------------------------------------------
+
+According to the HW manual, the query operation is unnecessary
+when the TM QCN error event is enabled, so remove it.
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 8 +-------
+ 1 file changed, 1 insertion(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 7d72e30d0d16..494498629317 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -866,13 +866,7 @@ static int hclge_config_tm_hw_err_int(struct hclge_dev *hdev, bool en)
+ 	}
+ 
+ 	/* configure TM QCN hw errors */
+-	ret = hclge_cmd_query_error(hdev, &desc, HCLGE_TM_QCN_MEM_INT_CFG, 0);
+-	if (ret) {
+-		dev_err(dev, "fail(%d) to read TM QCN CFG status\n", ret);
+-		return ret;
+-	}
+-
+-	hclge_cmd_reuse_desc(&desc, false);
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_QCN_MEM_INT_CFG, false);
+ 	if (en)
+ 		desc.data[1] = cpu_to_le32(HCLGE_TM_QCN_MEM_ERR_INT_EN);
+ 
+-- 
+2.34.1
+
diff --git a/patches/0425-net-hns3-split-function-hclge_reset_rebuild.patch b/patches/0425-net-hns3-split-function-hclge_reset_rebuild.patch
new file mode 100644
index 0000000..26381c8
--- /dev/null
+++ b/patches/0425-net-hns3-split-function-hclge_reset_rebuild.patch
@@ -0,0 +1,91 @@
+From e5abebab275bf375c2c8f2a44e6a5587192857d7 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Sat, 24 Jul 2021 15:44:06 +0800
+Subject: [PATCH 064/283] net: hns3: split function hclge_reset_rebuild()
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit 74d439b74ad3e05780d4cf3ab047345b443f7e67
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=74d439b74ad3e05780d4cf3ab047345b443f7e67
+
+----------------------------------------------------------------------
+
+hclge_reset_rebuild() is a bit too long. So add a new function
+hclge_update_reset_level() to improve readability.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 30 ++++++++++---------
+ 1 file changed, 16 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 6c2960df62a6..69ab9c00af4a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3866,6 +3866,21 @@ static bool hclge_reset_err_handle(struct hclge_dev *hdev)
+ 	return false;
+ }
+ 
++static void hclge_update_reset_level(struct hclge_dev *hdev)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	enum hnae3_reset_type reset_level;
++
++	/* if default_reset_request has a higher level reset request,
++	 * it should be handled as soon as possible. since some errors
++	 * need this kind of reset to fix.
++	 */
++	reset_level = hclge_get_reset_level(ae_dev,
++					    &hdev->default_reset_request);
++	if (reset_level != HNAE3_NONE_RESET)
++		set_bit(reset_level, &hdev->reset_request);
++}
++
+ static int hclge_set_rst_done(struct hclge_dev *hdev)
+ {
+ 	struct hclge_pf_rst_done_cmd *req;
+@@ -3955,9 +3970,6 @@ static int hclge_reset_prepare(struct hclge_dev *hdev)
+ 
+ static int hclge_reset_rebuild(struct hclge_dev *hdev)
+ {
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+-	struct hnae3_handle *handle = &hdev->vport[0].nic;
+-	enum hnae3_reset_type reset_level;
+ 	int ret;
+ 
+ 	hdev->rst_stats.hw_reset_done_cnt++;
+@@ -4001,17 +4013,7 @@ static int hclge_reset_rebuild(struct hclge_dev *hdev)
+ 	hdev->rst_stats.reset_done_cnt++;
+ 	clear_bit(HCLGE_STATE_RST_FAIL, &hdev->state);
+ 
+-	/* if default_reset_request has a higher level reset request,
+-	 * it should be handled as soon as possible. since some errors
+-	 * need this kind of reset to fix.
+-	 */
+-	reset_level = hclge_get_reset_level(ae_dev,
+-					    &hdev->default_reset_request);
+-	if (reset_level != HNAE3_NONE_RESET)
+-		set_bit(reset_level, &hdev->reset_request);
+-
+-	if (handle && handle->ae_algo->ops->reset_end)
+-		handle->ae_algo->ops->reset_end(handle, true);
++	hclge_update_reset_level(hdev);
+ 
+ 	return 0;
+ }
+-- 
+2.34.1
+
diff --git a/patches/0426-net-hns3-split-out-hclge_tm_vport_tc_info_update.patch b/patches/0426-net-hns3-split-out-hclge_tm_vport_tc_info_update.patch
new file mode 100644
index 0000000..d02e74e
--- /dev/null
+++ b/patches/0426-net-hns3-split-out-hclge_tm_vport_tc_info_update.patch
@@ -0,0 +1,67 @@
+From 090f4c65c7addfe624049fb1d8ba3ed1be7340a7 Mon Sep 17 00:00:00 2001
+From: Guojia Liao <liaoguojia@huawei.com>
+Date: Sat, 24 Jul 2021 15:44:07 +0800
+Subject: [PATCH 065/283] net: hns3: split out hclge_tm_vport_tc_info_update()
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit b1261897b0902d870c483fb006a9443723a3d58b
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b1261897b0902d870c483fb006a9443723a3d58b
+
+----------------------------------------------------------------------
+
+hclge_tm_vport_tc_info_update() is bloated, so split it into
+separate functions for readability and maintainability.
+
+Signed-off-by: Guojia Liao <liaoguojia@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index be641288651f..c92d084bb798 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -597,12 +597,11 @@ static u16 hclge_vport_get_tqp_num(struct hclge_vport *vport)
+ 	return sum;
+ }
+ 
+-static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
++static void hclge_tm_update_kinfo_rss_size(struct hclge_vport *vport)
+ {
+ 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
+ 	struct hclge_dev *hdev = vport->back;
+ 	u16 max_rss_size;
+-	u8 i;
+ 
+ 	/* TC configuration is shared by PF/VF in one port, only allow
+ 	 * one tc for VF for simplicity. VF's vport_id is non zero.
+@@ -626,7 +625,15 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
+ 		/* Set to the maximum specification value (max_rss_size). */
+ 		kinfo->rss_size = max_rss_size;
+ 	}
++}
++
++static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
++{
++	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
++	struct hclge_dev *hdev = vport->back;
++	u8 i;
+ 
++	hclge_tm_update_kinfo_rss_size(vport);
+ 	kinfo->num_tqps = hclge_vport_get_tqp_num(vport);
+ 	vport->dwrr = 100;  /* 100 percent as init */
+ 	vport->alloc_rss_size = kinfo->rss_size;
+-- 
+2.34.1
+
diff --git a/patches/0427-net-hns3-Trivial-spell-fix-in-hns3-driver.patch b/patches/0427-net-hns3-Trivial-spell-fix-in-hns3-driver.patch
new file mode 100644
index 0000000..b4c2284
--- /dev/null
+++ b/patches/0427-net-hns3-Trivial-spell-fix-in-hns3-driver.patch
@@ -0,0 +1,69 @@
+From 053856ded21ec0f1a60e12926dfc9f5a7b271f12 Mon Sep 17 00:00:00 2001
+From: Salil Mehta <salil.mehta@huawei.com>
+Date: Sat, 24 Jul 2021 15:44:20 +0800
+Subject: [PATCH 066/283] net: hns3: Trivial spell fix in hns3 driver
+
+mainline inclusion
+from mainline-v5.12-rc7
+commit cd7e963d2f0875789ddb5c3746b628716bd0a8c9
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cd7e963d2f0875789ddb5c3746b628716bd0a8c9
+
+----------------------------------------------------------------------
+
+Some trivial spelling mistakes which caught my eye during the
+review of the code.
+
+Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
+Link: https://lore.kernel.org/r/20210409074223.32480-1-salil.mehta@huawei.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c   | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 4 ++--
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 69ab9c00af4a..0f5bb93927f7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -11168,7 +11168,7 @@ static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
+ 	if (ret)
+ 		return ret;
+ 
+-	/* RSS indirection table has been configuared by user */
++	/* RSS indirection table has been configured by user */
+ 	if (rxfh_configured)
+ 		goto out;
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 9368e6ab8310..ea1313a8e9da 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -2187,7 +2187,7 @@ static void hclgevf_reset_service_task(struct hclgevf_dev *hdev)
+ 
+ 	if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
+ 			       &hdev->reset_state)) {
+-		/* PF has initmated that it is about to reset the hardware.
++		/* PF has intimated that it is about to reset the hardware.
+ 		 * We now have to poll & check if hardware has actually
+ 		 * completed the reset sequence. On hardware reset completion,
+ 		 * VF needs to reset the client and ae device.
+@@ -3424,7 +3424,7 @@ static int hclgevf_set_channels(struct hnae3_handle *handle, u32 new_tqps_num,
+ 	if (ret)
+ 		return ret;
+ 
+-	/* RSS indirection table has been configuared by user */
++	/* RSS indirection table has been configured by user */
+ 	if (rxfh_configured)
+ 		goto out;
+ 
+-- 
+2.34.1
+
diff --git a/patches/0428-net-hns3-cleanup-inappropriate-spaces-in-struct-hlcg.patch b/patches/0428-net-hns3-cleanup-inappropriate-spaces-in-struct-hlcg.patch
new file mode 100644
index 0000000..783fcaf
--- /dev/null
+++ b/patches/0428-net-hns3-cleanup-inappropriate-spaces-in-struct-hlcg.patch
@@ -0,0 +1,49 @@
+From 1c9929559bc4d9566052be19536581979167f2a3 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 24 Jul 2021 15:44:25 +0800
+Subject: [PATCH 067/283] net: hns3: cleanup inappropriate spaces in struct
+ hlcgevf_tqp_stats
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit 8ed64dbe0bdf39479772896b2b4e5cbbdf89f086
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8ed64dbe0bdf39479772896b2b4e5cbbdf89f086
+
+----------------------------------------------------------------------
+
+Modify some inappropriate spaces in comments of struct
+hlcgevf_tqp_stats.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index a35bbfd93384..e75e1b437585 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -175,9 +175,9 @@ struct hclgevf_hw {
+ 
+ /* TQP stats */
+ struct hlcgevf_tqp_stats {
+-	/* query_tqp_tx_queue_statistics ,opcode id:  0x0B03 */
++	/* query_tqp_tx_queue_statistics, opcode id: 0x0B03 */
+ 	u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
+-	/* query_tqp_rx_queue_statistics ,opcode id:  0x0B13 */
++	/* query_tqp_rx_queue_statistics, opcode id: 0x0B13 */
+ 	u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
+ };
+ 
+-- 
+2.34.1
+
diff --git a/patches/0429-net-hns3-clear-unnecessary-reset-request-in-hclge_re.patch b/patches/0429-net-hns3-clear-unnecessary-reset-request-in-hclge_re.patch
new file mode 100644
index 0000000..8c09b46
--- /dev/null
+++ b/patches/0429-net-hns3-clear-unnecessary-reset-request-in-hclge_re.patch
@@ -0,0 +1,55 @@
+From 44d9658f603e15947345c1ea3732fe504a3f7843 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Sat, 24 Jul 2021 15:44:27 +0800
+Subject: [PATCH 068/283] net: hns3: clear unnecessary reset request in
+ hclge_reset_rebuild
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit 8c9200e387721c597baabb319b4bd1cdf1155e35
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8c9200e387721c597baabb319b4bd1cdf1155e35
+
+----------------------------------------------------------------------
+
+HW error and global reset are reported through MSIX interrupts.
+The same error may be reported to different functions at the
+same time. When global reset begins, the pending reset request
+set by this error is unnecessary. So clear the pending reset
+request after the reset is complete to avoid the repeated reset.
+
+Fixes: f6162d44126c ("net: hns3: add handling of hw errors reported through MSIX")
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 0f5bb93927f7..bc70eb4fae64 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3871,6 +3871,12 @@ static void hclge_update_reset_level(struct hclge_dev *hdev)
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	enum hnae3_reset_type reset_level;
+ 
++	/* reset request will not be set during reset, so clear
++	 * pending reset request to avoid unnecessary reset
++	 * caused by the same reason.
++	 */
++	hclge_get_reset_level(ae_dev, &hdev->reset_request);
++
+ 	/* if default_reset_request has a higher level reset request,
+ 	 * it should be handled as soon as possible. since some errors
+ 	 * need this kind of reset to fix.
+-- 
+2.34.1
+
diff --git a/patches/0430-net-hns3-add-support-for-configuring-interrupt-quant.patch b/patches/0430-net-hns3-add-support-for-configuring-interrupt-quant.patch
new file mode 100644
index 0000000..a84f100
--- /dev/null
+++ b/patches/0430-net-hns3-add-support-for-configuring-interrupt-quant.patch
@@ -0,0 +1,297 @@
+From 70a8b68f854337fc619fdfd150a037b3352563ee Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Wed, 14 Jul 2021 20:55:24 +0800
+Subject: [PATCH 069/283] net: hns3: add support for configuring interrupt
+ quantity limiting
+
+mainline inclusion
+from mainline-v5.11-rc1
+commit 91bfae25eedd981b384339c7b12bef9eeaba0f34
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMQV
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=91bfae25eedd981b384339c7b12bef9eeaba0f34
+
+----------------------------------------------------------------------
+
+QL(quantity limiting) means that hardware supports the interrupt
+coalesce based on the frame quantity.  QL can be configured when
+int_ql_max in device's specification is non-zero, so add support
+to configure it. Also, rename two coalesce init function to fit
+their purpose.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: li yongxin <liyongxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 65 ++++++++++++++-----
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   | 13 +++-
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 43 +++++++++++-
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  1 +
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |  1 +
+ 5 files changed, 105 insertions(+), 18 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index b78f2fe7f39c..dcf65dce1240 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -239,35 +239,68 @@ void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
+ 	writel(tx_gl_reg, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET);
+ }
+ 
+-static void hns3_vector_gl_rl_init(struct hns3_enet_tqp_vector *tqp_vector,
+-				   struct hns3_nic_priv *priv)
++void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
++				    u32 ql_value)
+ {
++	writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET);
++}
++
++void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
++				    u32 ql_value)
++{
++	writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET);
++}
++
++static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
++				      struct hns3_nic_priv *priv)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
++	struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
++	struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
++
+ 	/* initialize the configuration for interrupt coalescing.
+ 	 * 1. GL (Interrupt Gap Limiter)
+ 	 * 2. RL (Interrupt Rate Limiter)
++	 * 3. QL (Interrupt Quantity Limiter)
+ 	 *
+ 	 * Default: enable interrupt coalescing self-adaptive and GL
+ 	 */
+-	tqp_vector->tx_group.coal.gl_adapt_enable = 1;
+-	tqp_vector->rx_group.coal.gl_adapt_enable = 1;
++	tx_coal->gl_adapt_enable = 1;
++	rx_coal->gl_adapt_enable = 1;
++
++	tx_coal->int_gl = HNS3_INT_GL_50K;
++	rx_coal->int_gl = HNS3_INT_GL_50K;
+ 
+-	tqp_vector->tx_group.coal.int_gl = HNS3_INT_GL_50K;
+-	tqp_vector->rx_group.coal.int_gl = HNS3_INT_GL_50K;
++	rx_coal->flow_level = HNS3_FLOW_LOW;
++	tx_coal->flow_level = HNS3_FLOW_LOW;
+ 
+-	tqp_vector->rx_group.coal.flow_level = HNS3_FLOW_LOW;
+-	tqp_vector->tx_group.coal.flow_level = HNS3_FLOW_LOW;
++	if (ae_dev->dev_specs.int_ql_max) {
++		tx_coal->ql_enable = 1;
++		rx_coal->ql_enable = 1;
++		tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
++		rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
++		tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
++		rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
++	}
+ }
+ 
+-static void hns3_vector_gl_rl_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
+-				      struct hns3_nic_priv *priv)
++static void
++hns3_vector_coalesce_init_hw(struct hns3_enet_tqp_vector *tqp_vector,
++			     struct hns3_nic_priv *priv)
+ {
++	struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
++	struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
+ 	struct hnae3_handle *h = priv->ae_handle;
+ 
+-	hns3_set_vector_coalesce_tx_gl(tqp_vector,
+-				       tqp_vector->tx_group.coal.int_gl);
+-	hns3_set_vector_coalesce_rx_gl(tqp_vector,
+-				       tqp_vector->rx_group.coal.int_gl);
++	hns3_set_vector_coalesce_tx_gl(tqp_vector, tx_coal->int_gl);
++	hns3_set_vector_coalesce_rx_gl(tqp_vector, rx_coal->int_gl);
+ 	hns3_set_vector_coalesce_rl(tqp_vector, h->kinfo.int_rl_setting);
++
++	if (tx_coal->ql_enable)
++		hns3_set_vector_coalesce_tx_ql(tqp_vector, tx_coal->int_ql);
++
++	if (rx_coal->ql_enable)
++		hns3_set_vector_coalesce_rx_ql(tqp_vector, rx_coal->int_ql);
+ }
+ 
+ static int hns3_nic_set_real_num_queue(struct net_device *netdev)
+@@ -3702,7 +3735,7 @@ static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
+ 
+ 	for (i = 0; i < priv->vector_num; i++) {
+ 		tqp_vector = &priv->tqp_vector[i];
+-		hns3_vector_gl_rl_init_hw(tqp_vector, priv);
++		hns3_vector_coalesce_init_hw(tqp_vector, priv);
+ 		tqp_vector->num_tqps = 0;
+ 	}
+ 
+@@ -3798,7 +3831,7 @@ static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
+ 		tqp_vector->idx = i;
+ 		tqp_vector->mask_addr = vector[i].io_addr;
+ 		tqp_vector->vector_irq = vector[i].vector;
+-		hns3_vector_gl_rl_init(tqp_vector, priv);
++		hns3_vector_coalesce_init(tqp_vector, priv);
+ 	}
+ 
+ out:
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index c337e4dbe2c6..0d9d46be1415 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -193,6 +193,8 @@ enum hns3_nic_state {
+ #define HNS3_VECTOR_GL2_OFFSET			0x300
+ #define HNS3_VECTOR_RL_OFFSET			0x900
+ #define HNS3_VECTOR_RL_EN_B			6
++#define HNS3_VECTOR_TX_QL_OFFSET		0xe00
++#define HNS3_VECTOR_RX_QL_OFFSET		0xf00
+ 
+ #define HNS3_RING_EN_B				0
+ 
+@@ -447,9 +449,14 @@ enum hns3_flow_level_range {
+ #define HNS3_INT_RL_MAX			0x00EC
+ #define HNS3_INT_RL_ENABLE_MASK		0x40
+ 
++#define HNS3_INT_QL_DEFAULT_CFG		0x20
++
+ struct hns3_enet_coalesce {
+ 	u16 int_gl;
+-	u8 gl_adapt_enable;
++	u16 int_ql;
++	u16 int_ql_max;
++	u8 gl_adapt_enable:1;
++	u8 ql_enable:1;
+ 	enum hns3_flow_level_range flow_level;
+ };
+ 
+@@ -621,6 +628,10 @@ void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
+ 				    u32 gl_value);
+ void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
+ 				 u32 rl_value);
++void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
++				    u32 ql_value);
++void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
++				    u32 ql_value);
+ 
+ void hns3_request_update_promisc_mode(struct hnae3_handle *handle);
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 3bad65d1a49d..7ed5f9a2ae38 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1144,6 +1144,9 @@ static int hns3_get_coalesce_per_queue(struct net_device *netdev, u32 queue,
+ 	cmd->tx_coalesce_usecs_high = h->kinfo.int_rl_setting;
+ 	cmd->rx_coalesce_usecs_high = h->kinfo.int_rl_setting;
+ 
++	cmd->tx_max_coalesced_frames = tx_vector->tx_group.coal.int_ql;
++	cmd->rx_max_coalesced_frames = rx_vector->rx_group.coal.int_ql;
++
+ 	return 0;
+ }
+ 
+@@ -1217,6 +1220,29 @@ static int hns3_check_rl_coalesce_para(struct net_device *netdev,
+ 	return 0;
+ }
+ 
++static int hns3_check_ql_coalesce_param(struct net_device *netdev,
++					struct ethtool_coalesce *cmd)
++{
++	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
++
++	if ((cmd->tx_max_coalesced_frames || cmd->rx_max_coalesced_frames) &&
++	    !ae_dev->dev_specs.int_ql_max) {
++		netdev_err(netdev, "coalesced frames is not supported\n");
++		return -EOPNOTSUPP;
++	}
++
++	if (cmd->tx_max_coalesced_frames > ae_dev->dev_specs.int_ql_max ||
++	    cmd->rx_max_coalesced_frames > ae_dev->dev_specs.int_ql_max) {
++		netdev_err(netdev,
++			   "invalid coalesced_frames value, range is 0-%u\n",
++			   ae_dev->dev_specs.int_ql_max);
++		return -ERANGE;
++	}
++
++	return 0;
++}
++
+ static int hns3_check_coalesce_para(struct net_device *netdev,
+ 				    struct ethtool_coalesce *cmd)
+ {
+@@ -1236,6 +1262,10 @@ static int hns3_check_coalesce_para(struct net_device *netdev,
+ 		return ret;
+ 	}
+ 
++	ret = hns3_check_ql_coalesce_param(netdev, cmd);
++	if (ret)
++		return ret;
++
+ 	if (cmd->use_adaptive_tx_coalesce == 1 ||
+ 	    cmd->use_adaptive_rx_coalesce == 1) {
+ 		netdev_info(netdev,
+@@ -1267,6 +1297,9 @@ static void hns3_set_coalesce_per_queue(struct net_device *netdev,
+ 	tx_vector->tx_group.coal.int_gl = cmd->tx_coalesce_usecs;
+ 	rx_vector->rx_group.coal.int_gl = cmd->rx_coalesce_usecs;
+ 
++	tx_vector->tx_group.coal.int_ql = cmd->tx_max_coalesced_frames;
++	rx_vector->rx_group.coal.int_ql = cmd->rx_max_coalesced_frames;
++
+ 	hns3_set_vector_coalesce_tx_gl(tx_vector,
+ 				       tx_vector->tx_group.coal.int_gl);
+ 	hns3_set_vector_coalesce_rx_gl(rx_vector,
+@@ -1274,6 +1307,13 @@ static void hns3_set_coalesce_per_queue(struct net_device *netdev,
+ 
+ 	hns3_set_vector_coalesce_rl(tx_vector, h->kinfo.int_rl_setting);
+ 	hns3_set_vector_coalesce_rl(rx_vector, h->kinfo.int_rl_setting);
++
++	if (tx_vector->tx_group.coal.ql_enable)
++		hns3_set_vector_coalesce_tx_ql(tx_vector,
++					       tx_vector->tx_group.coal.int_ql);
++	if (rx_vector->rx_group.coal.ql_enable)
++		hns3_set_vector_coalesce_rx_ql(rx_vector,
++					       rx_vector->rx_group.coal.int_ql);
+ }
+ 
+ static int hns3_set_coalesce(struct net_device *netdev,
+@@ -1501,7 +1541,8 @@ static int hns3_get_module_eeprom(struct net_device *netdev,
+ #define HNS3_ETHTOOL_COALESCE	(ETHTOOL_COALESCE_USECS |		\
+ 				 ETHTOOL_COALESCE_USE_ADAPTIVE |	\
+ 				 ETHTOOL_COALESCE_RX_USECS_HIGH |	\
+-				 ETHTOOL_COALESCE_TX_USECS_HIGH)
++				 ETHTOOL_COALESCE_TX_USECS_HIGH |	\
++				 ETHTOOL_COALESCE_MAX_FRAMES)
+ 
+ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ 	.supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index bc70eb4fae64..3b4b1c8be8a3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1373,6 +1373,7 @@ static void hclge_parse_dev_specs(struct hclge_dev *hdev,
+ 	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
+ 	ae_dev->dev_specs.rss_ind_tbl_size =
+ 		le16_to_cpu(req0->rss_ind_tbl_size);
++	ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
+ 	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
+ }
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index ea1313a8e9da..b9a1b8032c5c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -3059,6 +3059,7 @@ static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
+ 	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
+ 	ae_dev->dev_specs.rss_ind_tbl_size =
+ 					le16_to_cpu(req0->rss_ind_tbl_size);
++	ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
+ 	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
+ }
+ 
+-- 
+2.34.1
+
diff --git a/patches/0431-net-hns3-fix-user-s-coalesce-configuration-lost-issu.patch b/patches/0431-net-hns3-fix-user-s-coalesce-configuration-lost-issu.patch
new file mode 100644
index 0000000..7a04028
--- /dev/null
+++ b/patches/0431-net-hns3-fix-user-s-coalesce-configuration-lost-issu.patch
@@ -0,0 +1,352 @@
+From 928e13b775e8d61b7ba04900551ef54c0fd82a97 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 24 Jul 2021 15:44:40 +0800
+Subject: [PATCH 070/283] net: hns3: fix user's coalesce configuration lost
+ issue
+
+mainline inclusion
+from mainline-v5.13-rc4
+commit 73a13d8dbe33e53a12400f2be0f5af169816c67f
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=73a13d8dbe33e53a12400f2be0f5af169816c67f
+
+----------------------------------------------------------------------
+
+Currently, when adaptive is on, the user's coalesce configuration
+may be overwritten by the dynamic one. The reason is that user's
+configurations are saved in struct hns3_enet_tqp_vector whose
+value maybe changed by the dynamic algorithm. To fix it, use
+struct hns3_nic_priv instead of struct hns3_enet_tqp_vector to
+save and get the user's configuration.
+
+BTW, operations of storing and restoring coalesce info in the reset
+process are unnecessary now, so remove them as well.
+
+Fixes: 434776a5fae2 ("net: hns3: add ethtool_ops.set_coalesce support to PF")
+Fixes: 7e96adc46633 ("net: hns3: add ethtool_ops.get_coalesce support to PF")
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 92 +++++++++----------
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  2 +-
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 68 +++++---------
+ 3 files changed, 70 insertions(+), 92 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index dcf65dce1240..6d9be3895f5a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -213,8 +213,8 @@ void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
+ 	 * GL and RL(Rate Limiter) are 2 ways to acheive interrupt coalescing
+ 	 */
+ 
+-	if (rl_reg > 0 && !tqp_vector->tx_group.coal.gl_adapt_enable &&
+-	    !tqp_vector->rx_group.coal.gl_adapt_enable)
++	if (rl_reg > 0 && !tqp_vector->tx_group.coal.adapt_enable &&
++	    !tqp_vector->rx_group.coal.adapt_enable)
+ 		/* According to the hardware, the range of rl_reg is
+ 		 * 0-59 and the unit is 4.
+ 		 */
+@@ -257,30 +257,25 @@ static void hns3_vector_coalesce_init(struct hns3_enet_tqp_vector *tqp_vector,
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
+ 	struct hns3_enet_coalesce *tx_coal = &tqp_vector->tx_group.coal;
+ 	struct hns3_enet_coalesce *rx_coal = &tqp_vector->rx_group.coal;
++	struct hns3_enet_coalesce *ptx_coal = &priv->tx_coal;
++	struct hns3_enet_coalesce *prx_coal = &priv->rx_coal;
+ 
+-	/* initialize the configuration for interrupt coalescing.
+-	 * 1. GL (Interrupt Gap Limiter)
+-	 * 2. RL (Interrupt Rate Limiter)
+-	 * 3. QL (Interrupt Quantity Limiter)
+-	 *
+-	 * Default: enable interrupt coalescing self-adaptive and GL
+-	 */
+-	tx_coal->gl_adapt_enable = 1;
+-	rx_coal->gl_adapt_enable = 1;
++	tx_coal->adapt_enable = ptx_coal->adapt_enable;
++	rx_coal->adapt_enable = prx_coal->adapt_enable;
+ 
+-	tx_coal->int_gl = HNS3_INT_GL_50K;
+-	rx_coal->int_gl = HNS3_INT_GL_50K;
++	tx_coal->int_gl = ptx_coal->int_gl;
++	rx_coal->int_gl = prx_coal->int_gl;
+ 
+-	rx_coal->flow_level = HNS3_FLOW_LOW;
+-	tx_coal->flow_level = HNS3_FLOW_LOW;
++	rx_coal->flow_level = prx_coal->flow_level;
++	tx_coal->flow_level = ptx_coal->flow_level;
+ 
+ 	if (ae_dev->dev_specs.int_ql_max) {
+ 		tx_coal->ql_enable = 1;
+ 		rx_coal->ql_enable = 1;
+ 		tx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
+ 		rx_coal->int_ql_max = ae_dev->dev_specs.int_ql_max;
+-		tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
+-		rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
++		tx_coal->int_ql = ptx_coal->int_ql;
++		rx_coal->int_ql = prx_coal->int_ql;
+ 	}
+ }
+ 
+@@ -3531,14 +3526,14 @@ static void hns3_update_new_int_gl(struct hns3_enet_tqp_vector *tqp_vector)
+ 			tqp_vector->last_jiffies + msecs_to_jiffies(1000)))
+ 		return;
+ 
+-	if (rx_group->coal.gl_adapt_enable) {
++	if (rx_group->coal.adapt_enable) {
+ 		rx_update = hns3_get_new_int_gl(rx_group);
+ 		if (rx_update)
+ 			hns3_set_vector_coalesce_rx_gl(tqp_vector,
+ 						       rx_group->coal.int_gl);
+ 	}
+ 
+-	if (tx_group->coal.gl_adapt_enable) {
++	if (tx_group->coal.adapt_enable) {
+ 		tx_update = hns3_get_new_int_gl(tx_group);
+ 		if (tx_update)
+ 			hns3_set_vector_coalesce_tx_gl(tqp_vector,
+@@ -3791,6 +3786,34 @@ static int hns3_nic_init_vector_data(struct hns3_nic_priv *priv)
+ 	return ret;
+ }
+ 
++static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(priv->ae_handle->pdev);
++	struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
++	struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
++
++	/* initialize the configuration for interrupt coalescing.
++	 * 1. GL (Interrupt Gap Limiter)
++	 * 2. RL (Interrupt Rate Limiter)
++	 * 3. QL (Interrupt Quantity Limiter)
++	 *
++	 * Default: enable interrupt coalescing self-adaptive and GL
++	 */
++	tx_coal->adapt_enable = 1;
++	rx_coal->adapt_enable = 1;
++
++	tx_coal->int_gl = HNS3_INT_GL_50K;
++	rx_coal->int_gl = HNS3_INT_GL_50K;
++
++	rx_coal->flow_level = HNS3_FLOW_LOW;
++	tx_coal->flow_level = HNS3_FLOW_LOW;
++
++	if (ae_dev->dev_specs.int_ql_max) {
++		tx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
++		rx_coal->int_ql = HNS3_INT_QL_DEFAULT_CFG;
++	}
++}
++
+ static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
+ {
+ #define HNS3_VECTOR_PF_MAX_NUM		64
+@@ -4255,6 +4278,8 @@ static int hns3_client_init(struct hnae3_handle *handle)
+ 		goto out_get_ring_cfg;
+ 	}
+ 
++	hns3_nic_init_coal_cfg(priv);
++
+ 	ret = hns3_nic_alloc_vector_data(priv);
+ 	if (ret) {
+ 		ret = -ENOMEM;
+@@ -4539,31 +4564,6 @@ int hns3_nic_reset_all_ring(struct hnae3_handle *h)
+ 	return 0;
+ }
+ 
+-static void hns3_store_coal(struct hns3_nic_priv *priv)
+-{
+-	/* ethtool only support setting and querying one coal
+-	 * configuration for now, so save the vector 0' coal
+-	 * configuration here in order to restore it.
+-	 */
+-	memcpy(&priv->tx_coal, &priv->tqp_vector[0].tx_group.coal,
+-	       sizeof(struct hns3_enet_coalesce));
+-	memcpy(&priv->rx_coal, &priv->tqp_vector[0].rx_group.coal,
+-	       sizeof(struct hns3_enet_coalesce));
+-}
+-
+-static void hns3_restore_coal(struct hns3_nic_priv *priv)
+-{
+-	u16 vector_num = priv->vector_num;
+-	int i;
+-
+-	for (i = 0; i < vector_num; i++) {
+-		memcpy(&priv->tqp_vector[i].tx_group.coal, &priv->tx_coal,
+-		       sizeof(struct hns3_enet_coalesce));
+-		memcpy(&priv->tqp_vector[i].rx_group.coal, &priv->rx_coal,
+-		       sizeof(struct hns3_enet_coalesce));
+-	}
+-}
+-
+ static int hns3_reset_notify_down_enet(struct hnae3_handle *handle)
+ {
+ 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
+@@ -4622,8 +4622,6 @@ static int hns3_reset_notify_init_enet(struct hnae3_handle *handle)
+ 	if (ret)
+ 		goto err_put_ring;
+ 
+-	hns3_restore_coal(priv);
+-
+ 	ret = hns3_nic_init_vector_data(priv);
+ 	if (ret)
+ 		goto err_dealloc_vector;
+@@ -4690,8 +4688,6 @@ static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
+ 
+ 	hns3_nic_uninit_vector_data(priv);
+ 
+-	hns3_store_coal(priv);
+-
+ 	hns3_nic_dealloc_vector_data(priv);
+ 
+ 	ret = hns3_uninit_all_ring(priv);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 0d9d46be1415..c2b465415e8c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -455,7 +455,7 @@ struct hns3_enet_coalesce {
+ 	u16 int_gl;
+ 	u16 int_ql;
+ 	u16 int_ql_max;
+-	u8 gl_adapt_enable:1;
++	u8 adapt_enable:1;
+ 	u8 ql_enable:1;
+ 	enum hns3_flow_level_range flow_level;
+ };
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 7ed5f9a2ae38..4d982cb80f8b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1112,50 +1112,32 @@ static void hns3_get_channels(struct net_device *netdev,
+ 		h->ae_algo->ops->get_channels(h, ch);
+ }
+ 
+-static int hns3_get_coalesce_per_queue(struct net_device *netdev, u32 queue,
+-				       struct ethtool_coalesce *cmd)
++static int hns3_get_coalesce(struct net_device *netdev,
++			     struct ethtool_coalesce *cmd)
+ {
+-	struct hns3_enet_tqp_vector *tx_vector, *rx_vector;
+ 	struct hns3_nic_priv *priv = netdev_priv(netdev);
++	struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
++	struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
+ 	struct hnae3_handle *h = priv->ae_handle;
+-	u16 queue_num = h->kinfo.num_tqps;
+ 
+ 	if (hns3_nic_resetting(netdev))
+ 		return -EBUSY;
+ 
+-	if (queue >= queue_num) {
+-		netdev_err(netdev,
+-			   "Invalid queue value %u! Queue max id=%u\n",
+-			   queue, queue_num - 1);
+-		return -EINVAL;
+-	}
+-
+-	tx_vector = priv->ring[queue].tqp_vector;
+-	rx_vector = priv->ring[queue_num + queue].tqp_vector;
++	cmd->use_adaptive_tx_coalesce = tx_coal->adapt_enable;
++	cmd->use_adaptive_rx_coalesce = rx_coal->adapt_enable;
+ 
+-	cmd->use_adaptive_tx_coalesce =
+-			tx_vector->tx_group.coal.gl_adapt_enable;
+-	cmd->use_adaptive_rx_coalesce =
+-			rx_vector->rx_group.coal.gl_adapt_enable;
+-
+-	cmd->tx_coalesce_usecs = tx_vector->tx_group.coal.int_gl;
+-	cmd->rx_coalesce_usecs = rx_vector->rx_group.coal.int_gl;
++	cmd->tx_coalesce_usecs = tx_coal->int_gl;
++	cmd->rx_coalesce_usecs = rx_coal->int_gl;
+ 
+ 	cmd->tx_coalesce_usecs_high = h->kinfo.int_rl_setting;
+ 	cmd->rx_coalesce_usecs_high = h->kinfo.int_rl_setting;
+ 
+-	cmd->tx_max_coalesced_frames = tx_vector->tx_group.coal.int_ql;
+-	cmd->rx_max_coalesced_frames = rx_vector->rx_group.coal.int_ql;
++	cmd->tx_max_coalesced_frames = tx_coal->int_ql;
++	cmd->rx_max_coalesced_frames = rx_coal->int_ql;
+ 
+ 	return 0;
+ }
+ 
+-static int hns3_get_coalesce(struct net_device *netdev,
+-			     struct ethtool_coalesce *cmd)
+-{
+-	return hns3_get_coalesce_per_queue(netdev, 0, cmd);
+-}
+-
+ static int hns3_check_gl_coalesce_para(struct net_device *netdev,
+ 				       struct ethtool_coalesce *cmd)
+ {
+@@ -1262,19 +1244,7 @@ static int hns3_check_coalesce_para(struct net_device *netdev,
+ 		return ret;
+ 	}
+ 
+-	ret = hns3_check_ql_coalesce_param(netdev, cmd);
+-	if (ret)
+-		return ret;
+-
+-	if (cmd->use_adaptive_tx_coalesce == 1 ||
+-	    cmd->use_adaptive_rx_coalesce == 1) {
+-		netdev_info(netdev,
+-			    "adaptive-tx=%u and adaptive-rx=%u, tx_usecs or rx_usecs will changed dynamically.\n",
+-			    cmd->use_adaptive_tx_coalesce,
+-			    cmd->use_adaptive_rx_coalesce);
+-	}
+-
+-	return 0;
++	return hns3_check_ql_coalesce_param(netdev, cmd);
+ }
+ 
+ static void hns3_set_coalesce_per_queue(struct net_device *netdev,
+@@ -1289,9 +1259,9 @@ static void hns3_set_coalesce_per_queue(struct net_device *netdev,
+ 	tx_vector = priv->ring[queue].tqp_vector;
+ 	rx_vector = priv->ring[queue_num + queue].tqp_vector;
+ 
+-	tx_vector->tx_group.coal.gl_adapt_enable =
++	tx_vector->tx_group.coal.adapt_enable =
+ 				cmd->use_adaptive_tx_coalesce;
+-	rx_vector->rx_group.coal.gl_adapt_enable =
++	rx_vector->rx_group.coal.adapt_enable =
+ 				cmd->use_adaptive_rx_coalesce;
+ 
+ 	tx_vector->tx_group.coal.int_gl = cmd->tx_coalesce_usecs;
+@@ -1320,6 +1290,9 @@ static int hns3_set_coalesce(struct net_device *netdev,
+ 			     struct ethtool_coalesce *cmd)
+ {
+ 	struct hnae3_handle *h = hns3_get_handle(netdev);
++	struct hns3_nic_priv *priv = netdev_priv(netdev);
++	struct hns3_enet_coalesce *tx_coal = &priv->tx_coal;
++	struct hns3_enet_coalesce *rx_coal = &priv->rx_coal;
+ 	u16 queue_num = h->kinfo.num_tqps;
+ 	int ret;
+ 	int i;
+@@ -1334,6 +1307,15 @@ static int hns3_set_coalesce(struct net_device *netdev,
+ 	h->kinfo.int_rl_setting =
+ 		hns3_rl_round_down(cmd->rx_coalesce_usecs_high);
+ 
++	tx_coal->adapt_enable = cmd->use_adaptive_tx_coalesce;
++	rx_coal->adapt_enable = cmd->use_adaptive_rx_coalesce;
++
++	tx_coal->int_gl = cmd->tx_coalesce_usecs;
++	rx_coal->int_gl = cmd->rx_coalesce_usecs;
++
++	tx_coal->int_ql = cmd->tx_max_coalesced_frames;
++	rx_coal->int_ql = cmd->rx_max_coalesced_frames;
++
+ 	for (i = 0; i < queue_num; i++)
+ 		hns3_set_coalesce_per_queue(netdev, cmd, i);
+ 
+-- 
+2.34.1
+
diff --git a/patches/0432-net-hns3-use-HCLGE_VPORT_STATE_PROMISC_CHANGE-to-rep.patch b/patches/0432-net-hns3-use-HCLGE_VPORT_STATE_PROMISC_CHANGE-to-rep.patch
new file mode 100644
index 0000000..7c4b9d6
--- /dev/null
+++ b/patches/0432-net-hns3-use-HCLGE_VPORT_STATE_PROMISC_CHANGE-to-rep.patch
@@ -0,0 +1,125 @@
+From f3f3f7ffce8d19629e5318531208b5c40cdfb267 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Sat, 24 Jul 2021 15:44:58 +0800
+Subject: [PATCH 071/283] net: hns3: use HCLGE_VPORT_STATE_PROMISC_CHANGE to
+ replace HCLGE_STATE_PROMISC_CHANGED
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 4e2471f7b6ef5a564cd05bc5fb9f3ce71b7b7942
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4e2471f7b6ef5a564cd05bc5fb9f3ce71b7b7942
+
+----------------------------------------------------------------------
+
+Currently, PF is using HCLGE_STATE_PROMISC_CHANGED to indicate
+need synchronize the promisc mode for itself, and using flag
+HCLGE_VPORT_STATE_PROMISC_CHANGE for its VF. To keep consistent,
+remove flag HCLGE_STATE_PROMISC_CHANGED, and use flag
+HCLGE_VPORT_STATE_PROMISC_CHANGE instead.
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 21 ++++++++++---------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  4 +++-
+ 2 files changed, 14 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 3b4b1c8be8a3..9634927949f9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -5077,9 +5077,8 @@ static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
+ static void hclge_request_update_promisc_mode(struct hnae3_handle *handle)
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+-	struct hclge_dev *hdev = vport->back;
+ 
+-	set_bit(HCLGE_STATE_PROMISC_CHANGED, &hdev->state);
++	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
+ }
+ 
+ static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
+@@ -7266,6 +7265,8 @@ int hclge_vport_start(struct hclge_vport *vport)
+ {
+ 	struct hclge_dev *hdev = vport->back;
+ 
++	set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
++	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
+ 	vport->last_active_jiffies = jiffies;
+ 	set_bit(HCLGE_VPORT_STATE_START, &vport->state);
+ 	set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
+@@ -9305,8 +9306,7 @@ static void hclge_restore_hw_table(struct hclge_dev *hdev)
+ 	hclge_restore_mac_table_common(vport);
+ 	hclge_restore_vport_port_base_vlan_config(hdev);
+ 	hclge_restore_vport_vlan_table(vport);
+-	set_bit(HCLGE_STATE_PROMISC_CHANGED, &hdev->state);
+-
++	set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
+ 	hclge_restore_fd_entries(handle);
+ }
+ 
+@@ -11030,7 +11030,7 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 		return ret;
+ 	}
+ 
+-	set_bit(HCLGE_STATE_PROMISC_CHANGED, &hdev->state);
++	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &hdev->state);
+ 
+ 	/* Log and clear the hw errors those already occurred */
+ 	hclge_handle_all_hns_hw_errors(ae_dev);
+@@ -11745,18 +11745,19 @@ static void hclge_sync_promisc_mode(struct hclge_dev *hdev)
+ 	int i;
+ 
+ 	if (vport->last_promisc_flags != vport->overflow_promisc_flags) {
+-		set_bit(HCLGE_STATE_PROMISC_CHANGED, &hdev->state);
++		set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
+ 		vport->last_promisc_flags = vport->overflow_promisc_flags;
+ 	}
+ 
+-	if (test_bit(HCLGE_STATE_PROMISC_CHANGED, &hdev->state)) {
++	if (test_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state)) {
+ 		tmp_flags = handle->netdev_flags | vport->last_promisc_flags;
+ 		ret = hclge_set_promisc_mode(handle, tmp_flags & HNAE3_UPE,
+ 					     tmp_flags & HNAE3_MPE);
+ 		if (!ret) {
+-			clear_bit(HCLGE_STATE_PROMISC_CHANGED, &hdev->state);
+-			set_bit(HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
+-				&vport->state);
++			clear_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE,
++				  &vport->state);
++			hclge_enable_vlan_filter(handle,
++						 tmp_flags & HNAE3_VLAN_FLTR);
+ 		}
+ 	}
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 56a7c6a3e1d9..97916f0fdf50 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -220,8 +220,10 @@ enum HCLGE_DEV_STATE {
+ 	HCLGE_STATE_STATISTICS_UPDATING,
+ 	HCLGE_STATE_CMD_DISABLE,
+ 	HCLGE_STATE_LINK_UPDATING,
+-	HCLGE_STATE_PROMISC_CHANGED,
+ 	HCLGE_STATE_RST_FAIL,
++	HCLGE_STATE_FD_TBL_CHANGED,
++	HCLGE_STATE_FD_CLEAR_ALL,
++	HCLGE_STATE_FD_USER_DEF_CHANGED,
+ 	HCLGE_STATE_MAX
+ };
+ 
+-- 
+2.34.1
+
diff --git a/patches/0433-net-hns3-add-a-separate-error-handling-task.patch b/patches/0433-net-hns3-add-a-separate-error-handling-task.patch
new file mode 100644
index 0000000..83895ee
--- /dev/null
+++ b/patches/0433-net-hns3-add-a-separate-error-handling-task.patch
@@ -0,0 +1,111 @@
+From 06cb892ebf06734ffa1a5d51f0b0efcea5fe00c8 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:08 +0800
+Subject: [PATCH 072/283] net: hns3: add a separate error handling task
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit d991452dd7900cf152ffb43db3b1d385e1a01579
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d991452dd7900cf152ffb43db3b1d385e1a01579
+
+----------------------------------------------------------------------
+
+Error handling and recovery logic are intertwined. Error handling (i.e.
+error identification, clearing error sources and initiation of recovery)
+is done in context of reset task. If certain hardware errors get
+delivered during driver init time, which can cause driver init/loading
+to fail.
+
+Introduce a separate error handling task to ensure below:
+
+1. Reset logic remains independent of the error handling logic.
+2. Add the hclge_errhand_task_schedule to schedule error recovery
+tasks, This will ensure that common misellaneous MSI-X interrupt are
+re-enabled quickly.
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_err.c   |  4 ++--
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c  | 16 ++++++++++++++++
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h  |  1 +
+ 3 files changed, 19 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 494498629317..18c60ea70fc4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -1943,8 +1943,8 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
+ 
+ 	if (!test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state)) {
+ 		dev_err(dev,
+-			"Can't handle - MSIx error reported during dev init\n");
+-		return 0;
++			"failed to handle msix error during dev init\n");
++		return -EAGAIN;
+ 	}
+ 
+ 	return hclge_handle_all_hw_msix_error(hdev, reset_requests);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 9634927949f9..8d69e4568baf 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -2752,6 +2752,14 @@ static void hclge_reset_task_schedule(struct hclge_dev *hdev)
+ 		mod_delayed_work(hclge_wq, &hdev->service_task, 0);
+ }
+ 
++static void hclge_errhand_task_schedule(struct hclge_dev *hdev)
++{
++	if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
++	    !test_and_set_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
++		mod_delayed_work_on(cpumask_first(&hdev->affinity_mask),
++				    hclge_wq, &hdev->service_task, 0);
++}
++
+ void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time)
+ {
+ 	if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
+@@ -4174,6 +4182,14 @@ static void hclge_misc_err_recovery(struct hclge_dev *hdev)
+ 	hclge_enable_vector(&hdev->misc_vector, true);
+ }
+ 
++static void hclge_errhand_service_task(struct hclge_dev *hdev)
++{
++	if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
++		return;
++
++	hclge_misc_err_recovery(hdev);
++}
++
+ static void hclge_reset_service_task(struct hclge_dev *hdev)
+ {
+ 	if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 97916f0fdf50..ffe21f617a63 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -217,6 +217,7 @@ enum HCLGE_DEV_STATE {
+ 	HCLGE_STATE_RST_HANDLING,
+ 	HCLGE_STATE_MBX_SERVICE_SCHED,
+ 	HCLGE_STATE_MBX_HANDLING,
++	HCLGE_STATE_ERR_SERVICE_SCHED,
+ 	HCLGE_STATE_STATISTICS_UPDATING,
+ 	HCLGE_STATE_CMD_DISABLE,
+ 	HCLGE_STATE_LINK_UPDATING,
+-- 
+2.34.1
+
diff --git a/patches/0434-net-hns3-add-scheduling-logic-for-error-handling-tas.patch b/patches/0434-net-hns3-add-scheduling-logic-for-error-handling-tas.patch
new file mode 100644
index 0000000..eca5698
--- /dev/null
+++ b/patches/0434-net-hns3-add-scheduling-logic-for-error-handling-tas.patch
@@ -0,0 +1,85 @@
+From 675855af069cab3fd5d9ef5da1e3459ef83a208a Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:09 +0800
+Subject: [PATCH 073/283] net: hns3: add scheduling logic for error handling
+ task
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit aff399a638da7e56680cdf6fa7544b67e0373a4e
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aff399a638da7e56680cdf6fa7544b67e0373a4e
+
+----------------------------------------------------------------------
+
+Error handling & recovery is done in context of reset task which
+gets scheduled from misc interrupt handler in existing code. But
+since error handling has been moved to new task, it should get
+scheduled instead of the reset task from the interrupt handler.
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 20 ++++++-------------
+ 1 file changed, 6 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 8d69e4568baf..0ec52f603fc5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3311,18 +3311,8 @@ static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
+ 	/* vector 0 interrupt is shared with reset and mailbox source events.*/
+ 	switch (event_cause) {
+ 	case HCLGE_VECTOR0_EVENT_ERR:
+-		/* we do not know what type of reset is required now. This could
+-		 * only be decided after we fetch the type of errors which
+-		 * caused this event. Therefore, we will do below for now:
+-		 * 1. Assert HNAE3_UNKNOWN_RESET type of reset. This means we
+-		 *    have defered type of reset to be used.
+-		 * 2. Schedule the reset serivce task.
+-		 * 3. When service task receives  HNAE3_UNKNOWN_RESET type it
+-		 *    will fetch the correct type of reset.  This would be done
+-		 *    by first decoding the types of errors.
+-		 */
+-		set_bit(HNAE3_UNKNOWN_RESET, &hdev->reset_request);
+-		/* fall through */
++		hclge_errhand_task_schedule(hdev);
++		break;
+ 	case HCLGE_VECTOR0_EVENT_RST:
+ 		hclge_reset_task_schedule(hdev);
+ 		break;
+@@ -4285,14 +4275,16 @@ static void hclge_service_task(struct work_struct *work)
+ 	struct hclge_dev *hdev =
+ 		container_of(work, struct hclge_dev, service_task.work);
+ 
++	hclge_errhand_service_task(hdev);
+ 	hclge_reset_service_task(hdev);
+ 	hclge_mailbox_service_task(hdev);
+ 	hclge_periodic_service_task(hdev);
+ 
+-	/* Handle reset and mbx again in case periodical task delays the
+-	 * handling by calling hclge_task_schedule() in
++	/* Handle error recovery, reset and mbx again in case periodical task
++	 * delays the handling by calling hclge_task_schedule() in
+ 	 * hclge_periodic_service_task().
+ 	 */
++	hclge_errhand_service_task(hdev);
+ 	hclge_reset_service_task(hdev);
+ 	hclge_mailbox_service_task(hdev);
+ }
+-- 
+2.34.1
+
diff --git a/patches/0435-net-hns3-add-log-for-workqueue-scheduled-late.patch b/patches/0435-net-hns3-add-log-for-workqueue-scheduled-late.patch
new file mode 100644
index 0000000..01337ea
--- /dev/null
+++ b/patches/0435-net-hns3-add-log-for-workqueue-scheduled-late.patch
@@ -0,0 +1,143 @@
+From c311d421d90c808afb638faff4d51c2d255854fe Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Wed, 24 Nov 2021 09:06:51 +0800
+Subject: [PATCH 074/283] net: hns3: add log for workqueue scheduled late
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit d9069dab207534d9f6f41993ee78a651733becea
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d9069dab207534d9f6f41993ee78a651733becea
+
+--------------------------------
+
+When the mbx or reset message arrives, the driver is informed
+through an interrupt. This task can be processed only after
+the workqueue is scheduled. In some cases, this workqueue
+scheduling takes a long time. As a result, the mbx or reset
+service task cannot be processed in time. So add some warning
+message to improve debugging efficiency for this case.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../net/ethernet/hisilicon/hns3/hclge_mbx.h   |  3 +++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 25 ++++++++++++++-----
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  2 ++
+ .../hisilicon/hns3/hns3pf/hclge_mbx.c         |  8 ++++++
+ 4 files changed, 32 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
+index 5ab56fd90738..bfd6f19aa65a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
+@@ -81,6 +81,9 @@ enum hclge_mbx_tbl_cfg_subcode {
+ #define HCLGE_MBX_MAX_RESP_DATA_SIZE	8U
+ #define HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM	4
+ 
++#define HCLGE_RESET_SCHED_TIMEOUT	(3 * HZ)
++#define HCLGE_MBX_SCHED_TIMEOUT	(HZ / 2)
++
+ struct hclge_ring_chain_param {
+ 	u8 ring_type;
+ 	u8 tqp_index;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 0ec52f603fc5..062572b2f779 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -2740,16 +2740,20 @@ static int hclge_mac_init(struct hclge_dev *hdev)
+ static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
+ {
+ 	if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
+-	    !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
++	    !test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) {
++		hdev->last_mbx_scheduled = jiffies;
+ 		mod_delayed_work(hclge_wq, &hdev->service_task, 0);
++	}
+ }
+ 
+ static void hclge_reset_task_schedule(struct hclge_dev *hdev)
+ {
+ 	if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
+ 	    test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) &&
+-	    !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
++	    !test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) {
++		hdev->last_rst_scheduled = jiffies;
+ 		mod_delayed_work(hclge_wq, &hdev->service_task, 0);
++	}
+ }
+ 
+ static void hclge_errhand_task_schedule(struct hclge_dev *hdev)
+@@ -3556,6 +3560,13 @@ static void hclge_mailbox_service_task(struct hclge_dev *hdev)
+ 	    test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
+ 		return;
+ 
++	if (time_is_before_jiffies(hdev->last_mbx_scheduled +
++				   HCLGE_MBX_SCHED_TIMEOUT))
++		dev_warn(&hdev->pdev->dev,
++			 "mbx service task is scheduled after %ums on cpu%u!\n",
++			 jiffies_to_msecs(jiffies - hdev->last_mbx_scheduled),
++			 smp_processor_id());
++
+ 	hclge_mbx_handler(hdev);
+ 
+ 	clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
+@@ -4185,10 +4196,12 @@ static void hclge_reset_service_task(struct hclge_dev *hdev)
+ 	if (!test_and_clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
+ 		return;
+ 
+-	if (test_and_clear_bit(HNAE3_UNKNOWN_RESET, &hdev->reset_request)) {
+-		hclge_misc_err_recovery(hdev);
+-		return;
+-	}
++	if (time_is_before_jiffies(hdev->last_rst_scheduled +
++				   HCLGE_RESET_SCHED_TIMEOUT))
++		dev_warn(&hdev->pdev->dev,
++			 "reset service task is scheduled after %ums on cpu%u!\n",
++			 jiffies_to_msecs(jiffies - hdev->last_rst_scheduled),
++			 smp_processor_id());
+ 
+ 	down(&hdev->reset_sem);
+ 	set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index ffe21f617a63..c8eb73b58326 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -858,6 +858,8 @@ struct hclge_dev {
+ 	u16 hclge_fd_rule_num;
+ 	unsigned long serv_processed_cnt;
+ 	unsigned long last_serv_processed;
++	unsigned long last_rst_scheduled;
++	unsigned long last_mbx_scheduled;
+ 	unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
+ 	enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
+ 	u8 fd_en;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+index ff283ac443e5..841c9b0c9fe4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+@@ -951,6 +951,14 @@ void hclge_mbx_handler(struct hclge_dev *hdev)
+ 		if (hnae3_get_bit(req->mbx_need_resp, HCLGE_MBX_NEED_RESP_B) &&
+ 		    req->msg.code < HCLGE_MBX_GET_VF_FLR_STATUS) {
+ 			resp_msg.status = ret;
++			if (time_is_before_jiffies(hdev->last_mbx_scheduled +
++						   HCLGE_MBX_SCHED_TIMEOUT))
++				dev_warn(&hdev->pdev->dev,
++					 "resp vport%u mbx(%u,%u) late\n",
++					 req->mbx_src_vfid,
++					 req->msg.code,
++					 req->msg.subcode);
++
+ 			hclge_gen_resp_to_vf(vport, req, &resp_msg);
+ 		}
+ 
+-- 
+2.34.1
+
diff --git a/patches/0436-net-hns3-remove-now-redundant-logic-related-to-HNAE3.patch b/patches/0436-net-hns3-remove-now-redundant-logic-related-to-HNAE3.patch
new file mode 100644
index 0000000..c736366
--- /dev/null
+++ b/patches/0436-net-hns3-remove-now-redundant-logic-related-to-HNAE3.patch
@@ -0,0 +1,50 @@
+From b91dbf7afeac98f63bca87ee6c37921bb7a925bc Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:10 +0800
+Subject: [PATCH 075/283] net: hns3: remove now redundant logic related to
+ HNAE3_UNKNOWN_RESET
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit e0fe0a38371b6d2d669e231c1fd68ce620dfa6b2
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e0fe0a38371b6d2d669e231c1fd68ce620dfa6b2
+
+----------------------------------------------------------------------
+
+Earlier patches have decoupled the MSI-X conveyed error handling
+and recovery logic. This earlier concept code is no longer required.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 6a21c1b0434e..6a93ea356234 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -234,7 +234,9 @@ enum hnae3_reset_type {
+ 	HNAE3_FUNC_RESET,
+ 	HNAE3_GLOBAL_RESET,
+ 	HNAE3_IMP_RESET,
++#ifdef __GENKSYMS__
+ 	HNAE3_UNKNOWN_RESET,
++#endif
+ 	HNAE3_NONE_RESET,
+ 	HNAE3_MAX_RESET,
+ };
+-- 
+2.34.1
+
diff --git a/patches/0437-net-hns3-add-support-for-handling-all-errors-through.patch b/patches/0437-net-hns3-add-support-for-handling-all-errors-through.patch
new file mode 100644
index 0000000..53cc780
--- /dev/null
+++ b/patches/0437-net-hns3-add-support-for-handling-all-errors-through.patch
@@ -0,0 +1,187 @@
+From 1405375054d9e15c95982cd1eb6608a7dad08de7 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:11 +0800
+Subject: [PATCH 076/283] net: hns3: add support for handling all errors
+ through MSI-X
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 17f59244029bf9c0673725efdd0386ed95e127a7
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=17f59244029bf9c0673725efdd0386ed95e127a7
+
+----------------------------------------------------------------------
+
+Currently, hardware errors can be reported through AER or MSI-X mode.
+However, the AER mode is intended to handle only bus errors, but not
+hardware errors. On the other hand, virtual machines cannot handle
+AER errors. When an AER error is reported, virtual machines will be
+suspended. So add support for handling all these hardware errors
+through MSI-X mode which depends on a newer version of firmware,
+and reserve the handler of the AER mode for compatibility.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_err.c         | 16 +++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 47 ++++++++++---------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  1 +
+ 3 files changed, 41 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 18c60ea70fc4..3855c029829a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -1614,11 +1614,27 @@ static const struct hclge_hw_blk hw_blk[] = {
+ 	{ /* sentinel */ }
+ };
+ 
++static void hclge_config_all_msix_error(struct hclge_dev *hdev, bool enable)
++{
++	u32 reg_val;
++
++	reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
++
++	if (enable)
++		reg_val |= BIT(HCLGE_VECTOR0_ALL_MSIX_ERR_B);
++	else
++		reg_val &= ~BIT(HCLGE_VECTOR0_ALL_MSIX_ERR_B);
++
++	hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
++}
++
+ int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state)
+ {
+ 	const struct hclge_hw_blk *module = hw_blk;
+ 	int ret = 0;
+ 
++	hclge_config_all_msix_error(hdev, state);
++
+ 	while (module->name) {
+ 		if (module->config_err_int) {
+ 			ret = module->config_err_int(hdev, state);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 062572b2f779..f56cc318e2ad 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3220,11 +3220,13 @@ static int hclge_set_vf_link_state(struct hnae3_handle *handle, int vf,
+ 
+ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
+ {
+-	u32 cmdq_src_reg, msix_src_reg;
++	u32 cmdq_src_reg, msix_src_reg, hw_err_src_reg;
+ 
+ 	/* fetch the events from their corresponding regs */
+ 	cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
+ 	msix_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
++	hw_err_src_reg = hclge_read_dev(&hdev->hw,
++					HCLGE_RAS_PF_OTHER_INT_STS_REG);
+ 
+ 	/* Assumption: If by any chance reset and mailbox events are reported
+ 	 * together then we will only process reset event in this go and will
+@@ -3252,11 +3254,11 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
+ 		return HCLGE_VECTOR0_EVENT_RST;
+ 	}
+ 
+-	/* check for vector0 msix event source */
+-	if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK) {
+-		*clearval = msix_src_reg;
++	/* check for vector0 msix event and hardware error event source */
++	if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK ||
++	    hw_err_src_reg & HCLGE_RAS_REG_NFE_MASK ||
++	    hw_err_src_reg & HCLGE_RAS_REG_ROCEE_ERR_MASK)
+ 		return HCLGE_VECTOR0_EVENT_ERR;
+-	}
+ 
+ 	/* check for vector0 mailbox(=CMDQ RX) event source */
+ 	if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
+@@ -3267,9 +3269,8 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
+ 
+ 	/* print other vector0 event source */
+ 	dev_info(&hdev->pdev->dev,
+-		 "CMDQ INT status:0x%x, other INT status:0x%x\n",
+-		 cmdq_src_reg, msix_src_reg);
+-	*clearval = msix_src_reg;
++		 "INT status: CMDQ(%#x) HW errors(%#x) other(%#x)\n",
++		 cmdq_src_reg, hw_err_src_reg, msix_src_reg);
+ 
+ 	return HCLGE_VECTOR0_EVENT_OTHER;
+ }
+@@ -3340,15 +3341,10 @@ static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
+ 
+ 	hclge_clear_event_cause(hdev, event_cause, clearval);
+ 
+-	/* Enable interrupt if it is not cause by reset. And when
+-	 * clearval equal to 0, it means interrupt status may be
+-	 * cleared by hardware before driver reads status register.
+-	 * For this case, vector0 interrupt also should be enabled.
+-	 */
+-	if (!clearval ||
+-	    event_cause == HCLGE_VECTOR0_EVENT_MBX) {
++	/* Enable interrupt if it is not caused by reset event or error event */
++	if (event_cause == HCLGE_VECTOR0_EVENT_MBX ||
++	    event_cause == HCLGE_VECTOR0_EVENT_OTHER)
+ 		hclge_enable_vector(&hdev->misc_vector, true);
+-	}
+ 
+ 	return IRQ_HANDLED;
+ }
+@@ -4165,22 +4161,27 @@ static void hclge_misc_err_recovery(struct hclge_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct device *dev = &hdev->pdev->dev;
++	enum hnae3_reset_type reset_type;
+ 	u32 msix_sts_reg;
+ 
+ 	msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
+-
+ 	if (msix_sts_reg & HCLGE_VECTOR0_REG_MSIX_MASK) {
+-		if (hclge_handle_hw_msix_error(hdev,
+-					       &hdev->default_reset_request))
++		if (hclge_handle_hw_msix_error
++				(hdev, &hdev->default_reset_request))
+ 			dev_info(dev, "received msix interrupt 0x%x\n",
+ 				 msix_sts_reg);
++	}
++	hclge_enable_vector(&hdev->misc_vector, true);
+ 
+-		if (hdev->default_reset_request)
+-			if (ae_dev->ops->reset_event)
+-				ae_dev->ops->reset_event(hdev->pdev, NULL);
++	hclge_handle_hw_ras_error(ae_dev);
++	if (ae_dev->hw_err_reset_req) {
++		reset_type = hclge_get_reset_level(ae_dev,
++						   &ae_dev->hw_err_reset_req);
++		hclge_set_def_reset_request(ae_dev, reset_type);
+ 	}
+ 
+-	hclge_enable_vector(&hdev->misc_vector, true);
++	if (hdev->default_reset_request && ae_dev->ops->reset_event)
++		ae_dev->ops->reset_event(hdev->pdev, NULL);
+ }
+ 
+ static void hclge_errhand_service_task(struct hclge_dev *hdev)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index c8eb73b58326..1a262a247701 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -187,6 +187,7 @@ enum HLCGE_PORT_TYPE {
+ #define HCLGE_VECTOR0_IMP_RESET_INT_B	1
+ #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B	4U
+ #define HCLGE_VECTOR0_IMP_RD_POISON_B	5U
++#define HCLGE_VECTOR0_ALL_MSIX_ERR_B	6U
+ 
+ #define HCLGE_MAC_DEFAULT_FRAME \
+ 	(ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
+-- 
+2.34.1
+
diff --git a/patches/0438-net-hns3-add-the-RAS-compatibility-adaptation-soluti.patch b/patches/0438-net-hns3-add-the-RAS-compatibility-adaptation-soluti.patch
new file mode 100644
index 0000000..1b82d42
--- /dev/null
+++ b/patches/0438-net-hns3-add-the-RAS-compatibility-adaptation-soluti.patch
@@ -0,0 +1,625 @@
+From ff05551bfec7c306b38bdb056f0e1203b8f01980 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:12 +0800
+Subject: [PATCH 077/283] net: hns3: add the RAS compatibility adaptation
+ solution
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 2e2deee7618b062efe3aba9fcb017dadcf148819
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2e2deee7618b062efe3aba9fcb017dadcf148819
+
+----------------------------------------------------------------------
+
+To adapt to hardware modification and ensure that the driver is
+compatible with the original error handling content, we need to add the
+RAS compatibility adaptation solution.
+
+Add a processing branch to the driver during error handling. In the new
+processing branch, NIC fault information is integrated by the IMP. An
+interaction command is added between the driver and IMP to query
+and clear the fault source and interrupt source. The IMP integrates
+error information and reports the highest reset level to the driver.
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         |   3 +-
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |   2 +
+ .../hisilicon/hns3/hns3pf/hclge_err.c         | 324 ++++++++++++++++--
+ .../hisilicon/hns3/hns3pf/hclge_err.h         |  68 ++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  54 ++-
+ 5 files changed, 410 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 7646e510c0e7..e127ca7106b7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -194,7 +194,8 @@ static bool hclge_is_special_opcode(u16 opcode)
+ 			     HCLGE_QUERY_CLEAR_MPF_RAS_INT,
+ 			     HCLGE_QUERY_CLEAR_PF_RAS_INT,
+ 			     HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
+-			     HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT};
++			     HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT,
++			     HCLGE_QUERY_ALL_ERR_INFO};
+ 	int i;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index b6498f8ce224..81b726e557df 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -296,6 +296,8 @@ enum hclge_opcode_type {
+ 	HCLGE_QUERY_MSIX_INT_STS_BD_NUM	= 0x1513,
+ 	HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT	= 0x1514,
+ 	HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT	= 0x1515,
++	HCLGE_QUERY_ALL_ERR_BD_NUM		= 0x1516,
++	HCLGE_QUERY_ALL_ERR_INFO		= 0x1517,
+ 	HCLGE_CONFIG_ROCEE_RAS_INT_EN	= 0x1580,
+ 	HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
+ 	HCLGE_ROCEE_PF_RAS_INT_CMD	= 0x1584,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 3855c029829a..cf4afddad526 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -631,9 +631,101 @@ const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[] = {
+ 	{ /* sentinel */ }
+ };
+ 
++static const struct hclge_hw_module_id hclge_hw_module_id_st[] = {
++	{
++		.module_id = MODULE_NONE,
++		.msg = "MODULE_NONE"
++	}, {
++		.module_id = MODULE_BIOS_COMMON,
++		.msg = "MODULE_BIOS_COMMON"
++	}, {
++		.module_id = MODULE_GE,
++		.msg = "MODULE_GE"
++	}, {
++		.module_id = MODULE_IGU_EGU,
++		.msg = "MODULE_IGU_EGU"
++	}, {
++		.module_id = MODULE_LGE,
++		.msg = "MODULE_LGE"
++	}, {
++		.module_id = MODULE_NCSI,
++		.msg = "MODULE_NCSI"
++	}, {
++		.module_id = MODULE_PPP,
++		.msg = "MODULE_PPP"
++	}, {
++		.module_id = MODULE_QCN,
++		.msg = "MODULE_QCN"
++	}, {
++		.module_id = MODULE_RCB_RX,
++		.msg = "MODULE_RCB_RX"
++	}, {
++		.module_id = MODULE_RTC,
++		.msg = "MODULE_RTC"
++	}, {
++		.module_id = MODULE_SSU,
++		.msg = "MODULE_SSU"
++	}, {
++		.module_id = MODULE_TM,
++		.msg = "MODULE_TM"
++	}, {
++		.module_id = MODULE_RCB_TX,
++		.msg = "MODULE_RCB_TX"
++	}, {
++		.module_id = MODULE_TXDMA,
++		.msg = "MODULE_TXDMA"
++	}, {
++		.module_id = MODULE_MASTER,
++		.msg = "MODULE_MASTER"
++	}
++};
++
++static const struct hclge_hw_type_id hclge_hw_type_id_st[] = {
++	{
++		.type_id = NONE_ERROR,
++		.msg = "none_error"
++	}, {
++		.type_id = FIFO_ERROR,
++		.msg = "fifo_error"
++	}, {
++		.type_id = MEMORY_ERROR,
++		.msg = "memory_error"
++	}, {
++		.type_id = POISON_ERROR,
++		.msg = "poison_error"
++	}, {
++		.type_id = MSIX_ECC_ERROR,
++		.msg = "msix_ecc_error"
++	}, {
++		.type_id = TQP_INT_ECC_ERROR,
++		.msg = "tqp_int_ecc_error"
++	}, {
++		.type_id = PF_ABNORMAL_INT_ERROR,
++		.msg = "pf_abnormal_int_error"
++	}, {
++		.type_id = MPF_ABNORMAL_INT_ERROR,
++		.msg = "mpf_abnormal_int_error"
++	}, {
++		.type_id = COMMON_ERROR,
++		.msg = "common_error"
++	}, {
++		.type_id = PORT_ERROR,
++		.msg = "port_error"
++	}, {
++		.type_id = ETS_ERROR,
++		.msg = "ets_error"
++	}, {
++		.type_id = NCSI_ERROR,
++		.msg = "ncsi_error"
++	}, {
++		.type_id = GLB_ERROR,
++		.msg = "glb_error"
++	}
++};
++
+ void hclge_log_error(struct device *dev, char *reg,
+-		     const struct hclge_hw_error *err,
+-		     u32 err_sts, unsigned long *reset_requests)
++			    const struct hclge_hw_error *err,
++			    u32 err_sts, unsigned long *reset_requests)
+ {
+ 	while (err->msg) {
+ 		if (err->int_msk & err_sts) {
+@@ -1895,11 +1987,8 @@ static int hclge_handle_pf_msix_error(struct hclge_dev *hdev,
+ static int hclge_handle_all_hw_msix_error(struct hclge_dev *hdev,
+ 					  unsigned long *reset_requests)
+ {
+-	struct hclge_mac_tnl_stats mac_tnl_stats;
+-	struct device *dev = &hdev->pdev->dev;
+ 	u32 mpf_bd_num, pf_bd_num, bd_num;
+ 	struct hclge_desc *desc;
+-	u32 status;
+ 	int ret;
+ 
+ 	/* query the number of bds for the MSIx int status */
+@@ -1922,29 +2011,7 @@ static int hclge_handle_all_hw_msix_error(struct hclge_dev *hdev,
+ 	if (ret)
+ 		goto msi_error;
+ 
+-	/* query and clear mac tnl interruptions */
+-	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_MAC_TNL_INT,
+-				   true);
+-	ret = hclge_cmd_send(&hdev->hw, &desc[0], 1);
+-	if (ret) {
+-		dev_err(dev, "query mac tnl int cmd failed (%d)\n", ret);
+-		goto msi_error;
+-	}
+-
+-	status = le32_to_cpu(desc->data[0]);
+-	if (status) {
+-		/* When mac tnl interrupt occurs, we record current time and
+-		 * register status here in a fifo, then clear the status. So
+-		 * that if link status changes suddenly at some time, we can
+-		 * query them by debugfs.
+-		 */
+-		mac_tnl_stats.time = local_clock();
+-		mac_tnl_stats.status = status;
+-		kfifo_put(&hdev->mac_tnl_log, mac_tnl_stats);
+-		ret = hclge_clear_mac_tnl_int(hdev);
+-		if (ret)
+-			dev_err(dev, "clear mac tnl int failed (%d)\n", ret);
+-	}
++	ret = hclge_handle_mac_tnl(hdev);
+ 
+ msi_error:
+ 	kfree(desc);
+@@ -1966,10 +2033,43 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
+ 	return hclge_handle_all_hw_msix_error(hdev, reset_requests);
+ }
+ 
+-void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev)
++int hclge_handle_mac_tnl(struct hclge_dev *hdev)
+ {
+-#define HCLGE_DESC_NO_DATA_LEN 8
++	struct hclge_mac_tnl_stats mac_tnl_stats;
++	struct device *dev = &hdev->pdev->dev;
++	struct hclge_desc desc;
++	u32 status;
++	int ret;
+ 
++	/* query and clear mac tnl interruptions */
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_TNL_INT, true);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(dev, "failed to query mac tnl int, ret = %d.\n", ret);
++		return ret;
++	}
++
++	status = le32_to_cpu(desc.data[0]);
++	if (status) {
++		/* When mac tnl interrupt occurs, we record current time and
++		 * register status here in a fifo, then clear the status. So
++		 * that if link status changes suddenly at some time, we can
++		 * query them by debugfs.
++		 */
++		mac_tnl_stats.time = local_clock();
++		mac_tnl_stats.status = status;
++		kfifo_put(&hdev->mac_tnl_log, mac_tnl_stats);
++		ret = hclge_clear_mac_tnl_int(hdev);
++		if (ret)
++			dev_err(dev, "failed to clear mac tnl int, ret = %d.\n",
++				ret);
++	}
++
++	return ret;
++}
++
++void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev)
++{
+ 	struct hclge_dev *hdev = ae_dev->priv;
+ 	struct device *dev = &hdev->pdev->dev;
+ 	u32 mpf_bd_num, pf_bd_num, bd_num;
+@@ -2018,3 +2118,167 @@ void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev)
+ msi_error:
+ 	kfree(desc);
+ }
++
++static void
++hclge_handle_error_type_reg_log(struct device *dev,
++				struct hclge_mod_err_info *mod_info,
++				struct hclge_type_reg_err_info *type_reg_info)
++{
++#define HCLGE_ERR_TYPE_MASK 0x7F
++#define HCLGE_ERR_TYPE_IS_RAS_OFFSET 7
++
++	u8 mod_id, total_module, type_id, total_type, i, is_ras;
++
++	mod_id = mod_info->mod_id;
++	type_id = type_reg_info->type_id & HCLGE_ERR_TYPE_MASK;
++	is_ras = type_reg_info->type_id >> HCLGE_ERR_TYPE_IS_RAS_OFFSET;
++
++	total_module = ARRAY_SIZE(hclge_hw_module_id_st);
++	total_type = ARRAY_SIZE(hclge_hw_type_id_st);
++
++	if (mod_id < total_module && type_id < total_type)
++		dev_err(dev,
++			"found %s %s, is %s error.\n",
++			hclge_hw_module_id_st[mod_id].msg,
++			hclge_hw_type_id_st[type_id].msg,
++			is_ras ? "ras" : "msix");
++	else
++		dev_err(dev,
++			"unknown module[%u] or type[%u].\n", mod_id, type_id);
++
++	dev_err(dev, "reg_value:\n");
++	for (i = 0; i < type_reg_info->reg_num; i++)
++		dev_err(dev, "0x%08x\n", type_reg_info->hclge_reg[i]);
++}
++
++static void hclge_handle_error_module_log(struct hnae3_ae_dev *ae_dev,
++					  const u32 *buf, u32 buf_size)
++{
++	struct hclge_type_reg_err_info *type_reg_info;
++	struct hclge_dev *hdev = ae_dev->priv;
++	struct device *dev = &hdev->pdev->dev;
++	struct hclge_mod_err_info *mod_info;
++	struct hclge_sum_err_info *sum_info;
++	u8 mod_num, err_num, i;
++	u32 offset = 0;
++
++	sum_info = (struct hclge_sum_err_info *)&buf[offset++];
++	if (sum_info->reset_type &&
++	    sum_info->reset_type != HNAE3_NONE_RESET)
++		set_bit(sum_info->reset_type, &ae_dev->hw_err_reset_req);
++	mod_num = sum_info->mod_num;
++
++	while (mod_num--) {
++		if (offset >= buf_size) {
++			dev_err(dev, "The offset(%u) exceeds buf's size(%u).\n",
++				offset, buf_size);
++			return;
++		}
++		mod_info = (struct hclge_mod_err_info *)&buf[offset++];
++		err_num = mod_info->err_num;
++
++		for (i = 0; i < err_num; i++) {
++			if (offset >= buf_size) {
++				dev_err(dev,
++					"The offset(%u) exceeds buf size(%u).\n",
++					offset, buf_size);
++				return;
++			}
++
++			type_reg_info = (struct hclge_type_reg_err_info *)
++					    &buf[offset++];
++			hclge_handle_error_type_reg_log(dev, mod_info,
++							type_reg_info);
++
++			offset += type_reg_info->reg_num;
++		}
++	}
++}
++
++static int hclge_query_all_err_bd_num(struct hclge_dev *hdev, u32 *bd_num)
++{
++	struct device *dev = &hdev->pdev->dev;
++	struct hclge_desc desc_bd;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc_bd, HCLGE_QUERY_ALL_ERR_BD_NUM, true);
++	ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1);
++	if (ret) {
++		dev_err(dev, "failed to query error bd_num, ret = %d.\n", ret);
++		return ret;
++	}
++
++	*bd_num = le32_to_cpu(desc_bd.data[0]);
++	if (!(*bd_num)) {
++		dev_err(dev, "The value of bd_num is 0!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int hclge_query_all_err_info(struct hclge_dev *hdev,
++				    struct hclge_desc *desc, u32 bd_num)
++{
++	struct device *dev = &hdev->pdev->dev;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(desc, HCLGE_QUERY_ALL_ERR_INFO, true);
++	ret = hclge_cmd_send(&hdev->hw, desc, bd_num);
++	if (ret)
++		dev_err(dev, "failed to query error info, ret = %d.\n", ret);
++
++	return ret;
++}
++
++int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev)
++{
++	u32 bd_num, desc_len, buf_len, buf_size, i;
++	struct hclge_dev *hdev = ae_dev->priv;
++	struct hclge_desc *desc;
++	__le32 *desc_data;
++	u32 *buf;
++	int ret;
++
++	ret = hclge_query_all_err_bd_num(hdev, &bd_num);
++	if (ret)
++		goto out;
++
++	desc_len = bd_num * sizeof(struct hclge_desc);
++	desc = kzalloc(desc_len, GFP_KERNEL);
++	if (!desc) {
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	ret = hclge_query_all_err_info(hdev, desc, bd_num);
++	if (ret)
++		goto err_desc;
++
++	buf_len = bd_num * sizeof(struct hclge_desc) - HCLGE_DESC_NO_DATA_LEN;
++	buf_size = buf_len / sizeof(u32);
++
++	desc_data = kzalloc(buf_len, GFP_KERNEL);
++	if (!desc_data)
++		return -ENOMEM;
++
++	buf = kzalloc(buf_len, GFP_KERNEL);
++	if (!buf) {
++		ret = -ENOMEM;
++		goto err_buf_alloc;
++	}
++
++	memcpy(desc_data, &desc[0].data[0], buf_len);
++	for (i = 0; i < buf_size; i++)
++		buf[i] = le32_to_cpu(desc_data[i]);
++
++	hclge_handle_error_module_log(ae_dev, buf, buf_size);
++	kfree(buf);
++
++err_buf_alloc:
++	kfree(desc_data);
++err_desc:
++	kfree(desc);
++out:
++	return ret;
++}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+index fcaf4f472379..6cc225a5cfbe 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+@@ -110,6 +110,10 @@
+ #define HCLGE_ROCEE_OVF_ERR_INT_MASK		0x10000
+ #define HCLGE_ROCEE_OVF_ERR_TYPE_MASK		0x3F
+ 
++#define HCLGE_DESC_DATA_MAX			8
++#define HCLGE_REG_NUM_MAX			256
++#define HCLGE_DESC_NO_DATA_LEN			8
++
+ enum hclge_err_int_type {
+ 	HCLGE_ERR_INT_MSIX = 0,
+ 	HCLGE_ERR_INT_RAS_CE = 1,
+@@ -117,6 +121,40 @@ enum hclge_err_int_type {
+ 	HCLGE_ERR_INT_RAS_FE = 3,
+ };
+ 
++enum hclge_mod_name_list {
++	MODULE_NONE		= 0,
++	MODULE_BIOS_COMMON	= 1,
++	MODULE_GE		= 2,
++	MODULE_IGU_EGU		= 3,
++	MODULE_LGE		= 4,
++	MODULE_NCSI		= 5,
++	MODULE_PPP		= 6,
++	MODULE_QCN		= 7,
++	MODULE_RCB_RX		= 8,
++	MODULE_RTC		= 9,
++	MODULE_SSU		= 10,
++	MODULE_TM		= 11,
++	MODULE_RCB_TX		= 12,
++	MODULE_TXDMA		= 13,
++	MODULE_MASTER		= 14,
++};
++
++enum hclge_err_type_list {
++	NONE_ERROR		= 0,
++	FIFO_ERROR		= 1,
++	MEMORY_ERROR		= 2,
++	POISON_ERROR		= 3,
++	MSIX_ECC_ERROR		= 4,
++	TQP_INT_ECC_ERROR	= 5,
++	PF_ABNORMAL_INT_ERROR	= 6,
++	MPF_ABNORMAL_INT_ERROR	= 7,
++	COMMON_ERROR		= 8,
++	PORT_ERROR		= 9,
++	ETS_ERROR		= 10,
++	NCSI_ERROR		= 11,
++	GLB_ERROR		= 12,
++};
++
+ struct hclge_hw_blk {
+ 	u32 msk;
+ 	const char *name;
+@@ -153,6 +191,34 @@ extern const struct hclge_hw_error hclge_ssu_fifo_overflow_int[];
+ extern const struct hclge_hw_error hclge_ssu_ets_tcg_int[];
+ extern const struct hclge_hw_error hclge_ssu_port_based_pf_int[];
+ extern const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[];
++struct hclge_hw_module_id {
++	enum hclge_mod_name_list module_id;
++	const char *msg;
++};
++
++struct hclge_hw_type_id {
++	enum hclge_err_type_list type_id;
++	const char *msg;
++};
++
++struct hclge_sum_err_info {
++	u8 reset_type;
++	u8 mod_num;
++	u8 rsv[2];
++};
++
++struct hclge_mod_err_info {
++	u8 mod_id;
++	u8 err_num;
++	u8 rsv[2];
++};
++
++struct hclge_type_reg_err_info {
++	u8 type_id;
++	u8 reg_num;
++	u8 rsv[2];
++	u32 hclge_reg[HCLGE_REG_NUM_MAX];
++};
+ 
+ int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
+ int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
+@@ -166,4 +232,6 @@ int hclge_handle_rocee_ras_error(struct hnae3_ae_dev *ae_dev);
+ void hclge_log_error(struct device *dev, char *reg,
+ 		     const struct hclge_hw_error *err,
+ 		     u32 err_sts, unsigned long *reset_requests);
++int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev);
++int hclge_handle_mac_tnl(struct hclge_dev *hdev);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index f56cc318e2ad..59d81b0f48c5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -4157,11 +4157,49 @@ static void hclge_reset_subtask(struct hclge_dev *hdev)
+ 	hdev->reset_type = HNAE3_NONE_RESET;
+ }
+ 
++static void hclge_handle_err_reset_request(struct hclge_dev *hdev)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	enum hnae3_reset_type reset_type;
++
++	if (ae_dev->hw_err_reset_req) {
++		reset_type = hclge_get_reset_level(ae_dev,
++						   &ae_dev->hw_err_reset_req);
++		hclge_set_def_reset_request(ae_dev, reset_type);
++	}
++
++	if (hdev->default_reset_request && ae_dev->ops->reset_event)
++		ae_dev->ops->reset_event(hdev->pdev, NULL);
++
++	/* enable interrupt after error handling complete */
++	hclge_enable_vector(&hdev->misc_vector, true);
++}
++
++static void hclge_handle_err_recovery(struct hclge_dev *hdev)
++{
++	u32 mask_val = HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK;
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	u32 msix_src_flag, hw_err_src_flag;
++
++	msix_src_flag = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
++			HCLGE_VECTOR0_REG_MSIX_MASK;
++
++	hw_err_src_flag = hclge_read_dev(&hdev->hw,
++					 HCLGE_RAS_PF_OTHER_INT_STS_REG) &
++			  mask_val;
++
++	if (msix_src_flag || hw_err_src_flag) {
++		hclge_handle_error_info_log(ae_dev);
++		hclge_handle_mac_tnl(hdev);
++	}
++
++	hclge_handle_err_reset_request(hdev);
++}
++
+ static void hclge_misc_err_recovery(struct hclge_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct device *dev = &hdev->pdev->dev;
+-	enum hnae3_reset_type reset_type;
+ 	u32 msix_sts_reg;
+ 
+ 	msix_sts_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
+@@ -4171,17 +4209,10 @@ static void hclge_misc_err_recovery(struct hclge_dev *hdev)
+ 			dev_info(dev, "received msix interrupt 0x%x\n",
+ 				 msix_sts_reg);
+ 	}
+-	hclge_enable_vector(&hdev->misc_vector, true);
+ 
+ 	hclge_handle_hw_ras_error(ae_dev);
+-	if (ae_dev->hw_err_reset_req) {
+-		reset_type = hclge_get_reset_level(ae_dev,
+-						   &ae_dev->hw_err_reset_req);
+-		hclge_set_def_reset_request(ae_dev, reset_type);
+-	}
+ 
+-	if (hdev->default_reset_request && ae_dev->ops->reset_event)
+-		ae_dev->ops->reset_event(hdev->pdev, NULL);
++	hclge_handle_err_reset_request(hdev);
+ }
+ 
+ static void hclge_errhand_service_task(struct hclge_dev *hdev)
+@@ -4189,7 +4220,10 @@ static void hclge_errhand_service_task(struct hclge_dev *hdev)
+ 	if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
+ 		return;
+ 
+-	hclge_misc_err_recovery(hdev);
++	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
++		hclge_handle_err_recovery(hdev);
++	else
++		hclge_misc_err_recovery(hdev);
+ }
+ 
+ static void hclge_reset_service_task(struct hclge_dev *hdev)
+-- 
+2.34.1
+
diff --git a/patches/0439-net-hns3-add-support-for-imp-handle-ras-capability.patch b/patches/0439-net-hns3-add-support-for-imp-handle-ras-capability.patch
new file mode 100644
index 0000000..cbb13a5
--- /dev/null
+++ b/patches/0439-net-hns3-add-support-for-imp-handle-ras-capability.patch
@@ -0,0 +1,205 @@
+From cae1920670d4a53a2baca8fa36a2218583cfa9c0 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:13 +0800
+Subject: [PATCH 078/283] net: hns3: add support for imp-handle ras capability
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit e65e9f5c2e4efc17657d016d767eb7010d9dd598
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e65e9f5c2e4efc17657d016d767eb7010d9dd598
+
+----------------------------------------------------------------------
+
+IMP(Intelligent Management Processor) firmware add a new feature to
+handle and consolidate RAS information for new devices, NIC driver
+only needs to query the reported RAS information. NIC driver adds
+support for this feature.
+
+Driver queries device capability to check whether IMP support this
+feature, If yes, execute the new RAS processing branch.
+
+In order to add a method to check whether PF supports imp-handle RAS
+feature, add dumping this info in debugfs.
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  8 +++-
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    | 46 +++++++++++++++++++
+ .../ethernet/hisilicon/hns3/hns3_debugfs.h    |  5 ++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         |  8 ++++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  6 +++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  2 +-
+ 6 files changed, 73 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 6a93ea356234..26286e76877c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -64,7 +64,6 @@
+ #define HNAE3_KNIC_CLIENT_INITED_B		0x3
+ #define HNAE3_UNIC_CLIENT_INITED_B		0x4
+ #define HNAE3_ROCE_CLIENT_INITED_B		0x5
+-#define HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B	0x8
+ #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\
+ 		BIT(HNAE3_DEV_SUPPORT_ROCE_B))
+ 
+@@ -91,6 +90,10 @@ enum HNAE3_DEV_CAP_BITS {
+ 	HNAE3_DEV_SUPPORT_STASH_B,
+ 	HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
+ 	HNAE3_DEV_SUPPORT_PAUSE_B,
++	HNAE3_DEV_SUPPORT_RAS_IMP_B,
++	HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
++	HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
++	HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
+ };
+ 
+ #define hnae3_dev_fd_supported(hdev) \
+@@ -129,6 +132,9 @@ enum HNAE3_DEV_CAP_BITS {
+ #define hnae3_dev_phy_imp_supported(hdev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps)
+ 
++#define hnae3_dev_ras_imp_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, (hdev)->ae_dev->caps)
++
+ #define hnae3_dev_tqp_txrx_indep_supported(hdev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps)
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 59d9dda8f325..1d86debdc09e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -318,6 +318,52 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
+ 	},
+ };
+ 
++static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
++	{
++		.name = "support FD",
++		.cap_bit = HNAE3_DEV_SUPPORT_FD_B,
++	}, {
++		.name = "support GRO",
++		.cap_bit = HNAE3_DEV_SUPPORT_GRO_B,
++	}, {
++		.name = "support FEC",
++		.cap_bit = HNAE3_DEV_SUPPORT_FEC_B,
++	}, {
++		.name = "support UDP GSO",
++		.cap_bit = HNAE3_DEV_SUPPORT_UDP_GSO_B,
++	}, {
++		.name = "support PTP",
++		.cap_bit = HNAE3_DEV_SUPPORT_PTP_B,
++	}, {
++		.name = "support INT QL",
++		.cap_bit = HNAE3_DEV_SUPPORT_INT_QL_B,
++	}, {
++		.name = "support HW TX csum",
++		.cap_bit = HNAE3_DEV_SUPPORT_HW_TX_CSUM_B,
++	}, {
++		.name = "support UDP tunnel csum",
++		.cap_bit = HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B,
++	}, {
++		.name = "support TX push",
++		.cap_bit = HNAE3_DEV_SUPPORT_TX_PUSH_B,
++	}, {
++		.name = "support imp-controlled PHY",
++		.cap_bit = HNAE3_DEV_SUPPORT_PHY_IMP_B,
++	}, {
++		.name = "support imp-controlled RAS",
++		.cap_bit = HNAE3_DEV_SUPPORT_RAS_IMP_B,
++	}, {
++		.name = "support rxd advanced layout",
++		.cap_bit = HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
++	}, {
++		.name = "support port vlan bypass",
++		.cap_bit = HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
++	}, {
++		.name = "support modify vlan filter state",
++		.cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
++	}
++};
++
+ static void hns3_dbg_fill_content(char *content, u16 len,
+ 				  const struct hns3_dbg_item *items,
+ 				  const char **result, u16 size)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h
+index 902e16d99fb7..97578eabb7d8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h
+@@ -58,4 +58,9 @@ struct hns3_dbg_func {
+ 	int (*dbg_dump_bd)(struct hns3_dbg_data *data, char *buf, int len);
+ };
+ 
++struct hns3_dbg_cap_info {
++	const char *name;
++	enum HNAE3_DEV_CAP_BITS cap_bit;
++};
++
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index e127ca7106b7..26e9d03da720 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -392,6 +392,14 @@ static void hclge_parse_capability(struct hclge_dev *hdev,
+ 		set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
+ 	if (hnae3_get_bit(caps, HCLGE_CAP_PHY_IMP_B))
+ 		set_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGE_CAP_RAS_IMP_B))
++		set_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGE_CAP_RXD_ADV_LAYOUT_B))
++		set_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, ae_dev->caps);
++	if (hnae3_get_bit(caps, HCLGE_CAP_PORT_VLAN_BYPASS_B)) {
++		set_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps);
++		set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
++	}
+ }
+ 
+ static enum hclge_cmd_status
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 81b726e557df..022e58235a58 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -388,6 +388,12 @@ enum HCLGE_CAP_BITS {
+ 	HCLGE_CAP_TQP_TXRX_INDEP_B,
+ 	HCLGE_CAP_HW_PAD_B,
+ 	HCLGE_CAP_STASH_B,
++	HCLGE_CAP_UDP_TUNNEL_CSUM_B,
++	HCLGE_CAP_RAS_IMP_B = 12,
++	HCLGE_CAP_FEC_B = 13,
++	HCLGE_CAP_PAUSE_B = 14,
++	HCLGE_CAP_RXD_ADV_LAYOUT_B = 15,
++	HCLGE_CAP_PORT_VLAN_BYPASS_B = 17,
+ };
+ 
+ #define HCLGE_QUERY_CAP_LENGTH		3
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 59d81b0f48c5..46a3bc0a9df3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -4220,7 +4220,7 @@ static void hclge_errhand_service_task(struct hclge_dev *hdev)
+ 	if (!test_and_clear_bit(HCLGE_STATE_ERR_SERVICE_SCHED, &hdev->state))
+ 		return;
+ 
+-	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
++	if (hnae3_dev_ras_imp_supported(hdev))
+ 		hclge_handle_err_recovery(hdev);
+ 	else
+ 		hclge_misc_err_recovery(hdev);
+-- 
+2.34.1
+
diff --git a/patches/0440-net-hns3-update-error-recovery-module-and-type.patch b/patches/0440-net-hns3-update-error-recovery-module-and-type.patch
new file mode 100644
index 0000000..d1a1b31
--- /dev/null
+++ b/patches/0440-net-hns3-update-error-recovery-module-and-type.patch
@@ -0,0 +1,191 @@
+From 20e92bdb92a37e27ce6c102a5338ded5a4962780 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:14 +0800
+Subject: [PATCH 079/283] net: hns3: update error recovery module and type
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 8a95e360fd512f1cb55239645879b15d26bc7e21
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8a95e360fd512f1cb55239645879b15d26bc7e21
+
+----------------------------------------------------------------------
+
+Update error recovery module and type for RoCE.
+
+The enumeration values of module names and error types are not sorted
+in sequence. If use the current printing mode, they cannot be correctly
+printed.
+
+Use the index mode, If mod_id and type_id match the enumerated value,
+display the corresponding information.
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Weihang Li <liweihang@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_err.c         | 58 ++++++++++++++++++-
+ .../hisilicon/hns3/hns3pf/hclge_err.h         | 18 ++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  3 +-
+ 3 files changed, 74 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index cf4afddad526..b303cf2d72bf 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -677,6 +677,36 @@ static const struct hclge_hw_module_id hclge_hw_module_id_st[] = {
+ 	}, {
+ 		.module_id = MODULE_MASTER,
+ 		.msg = "MODULE_MASTER"
++	}, {
++		.module_id = MODULE_ROCEE_TOP,
++		.msg = "MODULE_ROCEE_TOP"
++	}, {
++		.module_id = MODULE_ROCEE_TIMER,
++		.msg = "MODULE_ROCEE_TIMER"
++	}, {
++		.module_id = MODULE_ROCEE_MDB,
++		.msg = "MODULE_ROCEE_MDB"
++	}, {
++		.module_id = MODULE_ROCEE_TSP,
++		.msg = "MODULE_ROCEE_TSP"
++	}, {
++		.module_id = MODULE_ROCEE_TRP,
++		.msg = "MODULE_ROCEE_TRP"
++	}, {
++		.module_id = MODULE_ROCEE_SCC,
++		.msg = "MODULE_ROCEE_SCC"
++	}, {
++		.module_id = MODULE_ROCEE_CAEP,
++		.msg = "MODULE_ROCEE_CAEP"
++	}, {
++		.module_id = MODULE_ROCEE_GEN_AC,
++		.msg = "MODULE_ROCEE_GEN_AC"
++	}, {
++		.module_id = MODULE_ROCEE_QMM,
++		.msg = "MODULE_ROCEE_QMM"
++	}, {
++		.module_id = MODULE_ROCEE_LSAN,
++		.msg = "MODULE_ROCEE_LSAN"
+ 	}
+ };
+ 
+@@ -720,6 +750,12 @@ static const struct hclge_hw_type_id hclge_hw_type_id_st[] = {
+ 	}, {
+ 		.type_id = GLB_ERROR,
+ 		.msg = "glb_error"
++	}, {
++		.type_id = ROCEE_NORMAL_ERR,
++		.msg = "rocee_normal_error"
++	}, {
++		.type_id = ROCEE_OVF_ERR,
++		.msg = "rocee_ovf_error"
+ 	}
+ };
+ 
+@@ -2128,6 +2164,8 @@ hclge_handle_error_type_reg_log(struct device *dev,
+ #define HCLGE_ERR_TYPE_IS_RAS_OFFSET 7
+ 
+ 	u8 mod_id, total_module, type_id, total_type, i, is_ras;
++	u8 index_module = MODULE_NONE;
++	u8 index_type = NONE_ERROR;
+ 
+ 	mod_id = mod_info->mod_id;
+ 	type_id = type_reg_info->type_id & HCLGE_ERR_TYPE_MASK;
+@@ -2136,11 +2174,25 @@ hclge_handle_error_type_reg_log(struct device *dev,
+ 	total_module = ARRAY_SIZE(hclge_hw_module_id_st);
+ 	total_type = ARRAY_SIZE(hclge_hw_type_id_st);
+ 
+-	if (mod_id < total_module && type_id < total_type)
++	for (i = 0; i < total_module; i++) {
++		if (mod_id == hclge_hw_module_id_st[i].module_id) {
++			index_module = i;
++			break;
++		}
++	}
++
++	for (i = 0; i < total_type; i++) {
++		if (type_id == hclge_hw_type_id_st[i].type_id) {
++			index_type = i;
++			break;
++		}
++	}
++
++	if (index_module != MODULE_NONE && index_type != NONE_ERROR)
+ 		dev_err(dev,
+ 			"found %s %s, is %s error.\n",
+-			hclge_hw_module_id_st[mod_id].msg,
+-			hclge_hw_type_id_st[type_id].msg,
++			hclge_hw_module_id_st[index_module].msg,
++			hclge_hw_type_id_st[index_type].msg,
+ 			is_ras ? "ras" : "msix");
+ 	else
+ 		dev_err(dev,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+index 6cc225a5cfbe..aa9bd5a5e7dd 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+@@ -18,6 +18,8 @@
+ 	BIT(HCLGE_VECTOR0_IMP_CMDQ_ERR_B)
+ #define HCLGE_RAS_REG_NFE_MASK   0xFF00
+ #define HCLGE_RAS_REG_ROCEE_ERR_MASK   0x3000000
++#define HCLGE_RAS_REG_ERR_MASK \
++	(HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK)
+ 
+ #define HCLGE_VECTOR0_REG_MSIX_MASK   0x1FF00
+ 
+@@ -137,6 +139,18 @@ enum hclge_mod_name_list {
+ 	MODULE_RCB_TX		= 12,
+ 	MODULE_TXDMA		= 13,
+ 	MODULE_MASTER		= 14,
++	/* add new MODULE NAME for NIC here in order */
++	MODULE_ROCEE_TOP	= 40,
++	MODULE_ROCEE_TIMER	= 41,
++	MODULE_ROCEE_MDB	= 42,
++	MODULE_ROCEE_TSP	= 43,
++	MODULE_ROCEE_TRP	= 44,
++	MODULE_ROCEE_SCC	= 45,
++	MODULE_ROCEE_CAEP	= 46,
++	MODULE_ROCEE_GEN_AC	= 47,
++	MODULE_ROCEE_QMM	= 48,
++	MODULE_ROCEE_LSAN	= 49,
++	/* add new MODULE NAME for RoCEE here in order */
+ };
+ 
+ enum hclge_err_type_list {
+@@ -153,6 +167,10 @@ enum hclge_err_type_list {
+ 	ETS_ERROR		= 10,
+ 	NCSI_ERROR		= 11,
+ 	GLB_ERROR		= 12,
++	/* add new ERROR TYPE for NIC here in order */
++	ROCEE_NORMAL_ERR	= 40,
++	ROCEE_OVF_ERR		= 41,
++	/* add new ERROR TYPE for ROCEE here in order */
+ };
+ 
+ struct hclge_hw_blk {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 46a3bc0a9df3..b7e3b4e399c9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3256,8 +3256,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
+ 
+ 	/* check for vector0 msix event and hardware error event source */
+ 	if (msix_src_reg & HCLGE_VECTOR0_REG_MSIX_MASK ||
+-	    hw_err_src_reg & HCLGE_RAS_REG_NFE_MASK ||
+-	    hw_err_src_reg & HCLGE_RAS_REG_ROCEE_ERR_MASK)
++	    hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK)
+ 		return HCLGE_VECTOR0_EVENT_ERR;
+ 
+ 	/* check for vector0 mailbox(=CMDQ RX) event source */
+-- 
+2.34.1
+
diff --git a/patches/0441-net-hns3-add-error-handling-compatibility-during-ini.patch b/patches/0441-net-hns3-add-error-handling-compatibility-during-ini.patch
new file mode 100644
index 0000000..2b5c5f2
--- /dev/null
+++ b/patches/0441-net-hns3-add-error-handling-compatibility-during-ini.patch
@@ -0,0 +1,134 @@
+From a396cef35ddf1a20786e8bd5e08396af11906316 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:15 +0800
+Subject: [PATCH 080/283] net: hns3: add error handling compatibility during
+ initialization
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 1c360a4a077fc0f74a350fe2ef267cbe8a9388e3
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1c360a4a077fc0f74a350fe2ef267cbe8a9388e3
+
+----------------------------------------------------------------------
+
+During initialization, the driver logs and clears the hw errors that
+already occurred. For device supports imp-handle ras capability, it
+needs handle different error status, otherwise it may cause wrong reset.
+
+So fix it by adding a new processing branch.
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_err.c         | 22 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_err.h         |  2 ++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 21 +++++++++---------
+ 3 files changed, 34 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index b303cf2d72bf..a4e9aa9c5d6f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -2155,6 +2155,28 @@ void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev)
+ 	kfree(desc);
+ }
+ 
++bool hclge_find_error_source(struct hclge_dev *hdev)
++{
++	u32 msix_src_flag, hw_err_src_flag;
++
++	msix_src_flag = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
++			HCLGE_VECTOR0_REG_MSIX_MASK;
++
++	hw_err_src_flag = hclge_read_dev(&hdev->hw,
++					 HCLGE_RAS_PF_OTHER_INT_STS_REG) &
++			  HCLGE_RAS_REG_ERR_MASK;
++
++	return msix_src_flag || hw_err_src_flag;
++}
++
++void hclge_handle_occurred_error(struct hclge_dev *hdev)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++
++	if (hclge_find_error_source(hdev))
++		hclge_handle_error_info_log(ae_dev);
++}
++
+ static void
+ hclge_handle_error_type_reg_log(struct device *dev,
+ 				struct hclge_mod_err_info *mod_info,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+index aa9bd5a5e7dd..a53781491473 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+@@ -242,6 +242,8 @@ int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
+ int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
+ int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
+ void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);
++bool hclge_find_error_source(struct hclge_dev *hdev);
++void hclge_handle_occurred_error(struct hclge_dev *hdev);
+ pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
+ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
+ 			       unsigned long *reset_requests);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index b7e3b4e399c9..f81c6f8bb030 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -4176,18 +4176,11 @@ static void hclge_handle_err_reset_request(struct hclge_dev *hdev)
+ 
+ static void hclge_handle_err_recovery(struct hclge_dev *hdev)
+ {
+-	u32 mask_val = HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK;
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+-	u32 msix_src_flag, hw_err_src_flag;
+ 
+-	msix_src_flag = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
+-			HCLGE_VECTOR0_REG_MSIX_MASK;
++	ae_dev->hw_err_reset_req = 0;
+ 
+-	hw_err_src_flag = hclge_read_dev(&hdev->hw,
+-					 HCLGE_RAS_PF_OTHER_INT_STS_REG) &
+-			  mask_val;
+-
+-	if (msix_src_flag || hw_err_src_flag) {
++	if (hclge_find_error_source(hdev)) {
+ 		hclge_handle_error_info_log(ae_dev);
+ 		hclge_handle_mac_tnl(hdev);
+ 	}
+@@ -10734,7 +10727,10 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	hclge_clear_resetting_state(hdev);
+ 
+ 	/* Log and clear the hw errors those already occurred */
+-	hclge_handle_all_hns_hw_errors(ae_dev);
++	if (hnae3_dev_ras_imp_supported(hdev))
++		hclge_handle_occurred_error(hdev);
++	else
++		hclge_handle_all_hns_hw_errors(ae_dev);
+ 
+ 	/* request delayed reset for the error recovery because an immediate
+ 	 * global reset on a PF affecting pending initialization of other PFs
+@@ -11088,7 +11084,10 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &hdev->state);
+ 
+ 	/* Log and clear the hw errors those already occurred */
+-	hclge_handle_all_hns_hw_errors(ae_dev);
++	if (hnae3_dev_ras_imp_supported(hdev))
++		hclge_handle_occurred_error(hdev);
++	else
++		hclge_handle_all_hns_hw_errors(ae_dev);
+ 
+ 	/* Re-enable the hw error interrupts because
+ 	 * the interrupts get disabled on global reset.
+-- 
+2.34.1
+
diff --git a/patches/0442-net-hns3-use-list_move_tail-instead-of-list_del-list.patch b/patches/0442-net-hns3-use-list_move_tail-instead-of-list_del-list.patch
new file mode 100644
index 0000000..b8eb7de
--- /dev/null
+++ b/patches/0442-net-hns3-use-list_move_tail-instead-of-list_del-list.patch
@@ -0,0 +1,67 @@
+From abf30a8ed22d235661b84b3c7fbfc3f9beabbfca Mon Sep 17 00:00:00 2001
+From: Baokun Li <libaokun1@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:16 +0800
+Subject: [PATCH 081/283] net: hns3: use list_move_tail instead of
+ list_del/list_add_tail in hclgevf_main.c
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 49768ce98c2c1766619dfd6d157dd87826738fa7
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=49768ce98c2c1766619dfd6d157dd87826738fa7
+
+----------------------------------------------------------------------
+
+Using list_move_tail() instead of list_del() + list_add_tail() in hclgevf_main.c.
+
+Reported-by: Hulk Robot <hulkci@huawei.com>
+Signed-off-by: Baokun Li <libaokun1@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c    | 9 +++------
+ 1 file changed, 3 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index b9a1b8032c5c..74d2aef34315 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -1515,8 +1515,7 @@ static void hclgevf_sync_from_add_list(struct list_head *add_list,
+ 			kfree(mac_node);
+ 		} else if (mac_node->state == HCLGEVF_MAC_ACTIVE) {
+ 			mac_node->state = HCLGEVF_MAC_TO_DEL;
+-			list_del(&mac_node->node);
+-			list_add_tail(&mac_node->node, mac_list);
++			list_move_tail(&mac_node->node, mac_list);
+ 		} else {
+ 			list_del(&mac_node->node);
+ 			kfree(mac_node);
+@@ -1541,8 +1540,7 @@ static void hclgevf_sync_from_del_list(struct list_head *del_list,
+ 			list_del(&mac_node->node);
+ 			kfree(mac_node);
+ 		} else {
+-			list_del(&mac_node->node);
+-			list_add_tail(&mac_node->node, mac_list);
++			list_move_tail(&mac_node->node, mac_list);
+ 		}
+ 	}
+ }
+@@ -1578,8 +1576,7 @@ static void hclgevf_sync_mac_list(struct hclgevf_dev *hdev,
+ 	list_for_each_entry_safe(mac_node, tmp, list, node) {
+ 		switch (mac_node->state) {
+ 		case HCLGEVF_MAC_TO_DEL:
+-			list_del(&mac_node->node);
+-			list_add_tail(&mac_node->node, &tmp_del_list);
++			list_move_tail(&mac_node->node, &tmp_del_list);
+ 			break;
+ 		case HCLGEVF_MAC_TO_ADD:
+ 			new_node = kzalloc(sizeof(*new_node), GFP_ATOMIC);
+-- 
+2.34.1
+
diff --git a/patches/0443-net-hns3-refactor-dev-capability-and-dev-spec-of-deb.patch b/patches/0443-net-hns3-refactor-dev-capability-and-dev-spec-of-deb.patch
new file mode 100644
index 0000000..72d1f8e
--- /dev/null
+++ b/patches/0443-net-hns3-refactor-dev-capability-and-dev-spec-of-deb.patch
@@ -0,0 +1,697 @@
+From c1ae2604ddee1c0aab234155abcf65a3ca50ab62 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Sat, 24 Jul 2021 15:44:31 +0800
+Subject: [PATCH 082/283] net: hns3: refactor dev capability and dev spec of
+ debugfs
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit c929bc2ac36efa9344e6c8b8f55f6b8eeebb4393
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c929bc2ac36efa9344e6c8b8f55f6b8eeebb4393
+
+----------------------------------------------------------------------
+
+Currently, the debugfs command for dev capability and dev spec
+are implemented by "echo xxxx > cmd", and record the information
+in dmesg. It's unnecessary and heavy. To improve it, create a
+single file "dev_info" for them, and query them by command
+"cat dev_info", return the result to userspace, rather than
+record in dmesg.
+
+The display style is below:
+$cat dev_info
+dev capability:
+support FD: yes
+support GRO: yes
+support FEC: yes
+support UDP GSO: no
+support PTP: no
+support INT QL: no
+support HW TX csum: no
+support UDP tunnel csum: no
+support TX push: no
+support imp-controlled PHY: no
+support rxd advanced layout: no
+
+dev spec:
+MAC entry num: 0
+MNG entry num: 0
+MAX non tso bd num: 8
+RSS ind tbl size: 512
+RSS key size: 40
+RSS size: 1
+Allocated RSS size: 0
+Task queue pairs numbers: 1
+RX buffer length: 2048
+Desc num per TX queue: 1024
+Desc num per RX queue: 1024
+Total number of enabled TCs: 1
+MAX INT QL: 0
+MAX INT GL: 8160
+MAX TM RATE: 100000
+MAX QSET number: 1024
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   | 11 +++
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    | 92 +++++++++++++++++--
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  1 -
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 14 +--
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  3 +-
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     | 70 +++++++-------
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  8 ++
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  2 +
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 27 +++---
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.h |  2 +
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       |  8 ++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |  4 +
+ 12 files changed, 180 insertions(+), 62 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 26286e76877c..6b2969e1346a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -255,6 +255,7 @@ enum hnae3_port_base_vlan_state {
+ };
+ 
+ enum hnae3_dbg_cmd {
++	HNAE3_DBG_CMD_TM_NODES,
+ 	HNAE3_DBG_CMD_TM_PRI,
+ 	HNAE3_DBG_CMD_TM_QSET,
+ 	HNAE3_DBG_CMD_TM_MAP,
+@@ -263,7 +264,9 @@ enum hnae3_dbg_cmd {
+ 	HNAE3_DBG_CMD_TC_SCH_INFO,
+ 	HNAE3_DBG_CMD_QOS_PAUSE_CFG,
+ 	HNAE3_DBG_CMD_QOS_PRI_MAP,
++	HNAE3_DBG_CMD_QOS_DSCP_MAP,
+ 	HNAE3_DBG_CMD_QOS_BUF_CFG,
++	HNAE3_DBG_CMD_DEV_INFO,
+ 	HNAE3_DBG_CMD_TX_BD,
+ 	HNAE3_DBG_CMD_RX_BD,
+ 	HNAE3_DBG_CMD_MAC_UC,
+@@ -271,6 +274,7 @@ enum hnae3_dbg_cmd {
+ 	HNAE3_DBG_CMD_MAC_TBL,
+ 	HNAE3_DBG_CMD_MNG_TBL,
+ 	HNAE3_DBG_CMD_LOOPBACK,
++	HNAE3_DBG_CMD_PTP_INFO,
+ 	HNAE3_DBG_CMD_INTERRUPT_INFO,
+ 	HNAE3_DBG_CMD_RESET_INFO,
+ 	HNAE3_DBG_CMD_IMP_INFO,
+@@ -291,9 +295,13 @@ enum hnae3_dbg_cmd {
+ 	HNAE3_DBG_CMD_RX_QUEUE_INFO,
+ 	HNAE3_DBG_CMD_TX_QUEUE_INFO,
+ 	HNAE3_DBG_CMD_FD_TCAM,
++	HNAE3_DBG_CMD_FD_COUNTER,
+ 	HNAE3_DBG_CMD_MAC_TNL_STATUS,
+ 	HNAE3_DBG_CMD_SERV_INFO,
+ 	HNAE3_DBG_CMD_UMV_INFO,
++	HNAE3_DBG_CMD_PAGE_POOL_INFO,
++	HNAE3_DBG_CMD_COAL_INFO,
++	HNAE3_DBG_CMD_WOL_INFO,
+ 	HNAE3_DBG_CMD_UNKNOWN,
+ };
+ 
+@@ -333,10 +341,13 @@ struct hnae3_ring_chain_node {
+ struct hnae3_dev_specs {
+ 	u32 mac_entry_num; /* number of mac-vlan table entry */
+ 	u32 mng_entry_num; /* number of manager table entry */
++	u32 max_tm_rate;
+ 	u16 rss_ind_tbl_size;
+ 	u16 rss_key_size;
+ 	u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */
++	u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */
+ 	u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */
++	u16 max_qset_num;
+ };
+ 
+ struct hnae3_client_ops {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 1d86debdc09e..ad7015b3ec80 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -134,13 +134,6 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
+ 		.buf_len = HNS3_DBG_READ_LEN,
+ 		.init = hns3_dbg_common_file_init,
+ 	},
+-	{
+-		.name = "mac_tbl",
+-		.cmd = HNAE3_DBG_CMD_MAC_TBL,
+-		.dentry = HNS3_DBG_DENTRY_COMMON,
+-		.buf_len = HNS3_DBG_READ_LEN_1MB,
+-		.init = hns3_dbg_common_file_init,
+-	},
+ 	{
+ 		.name = "mng_tbl",
+ 		.cmd = HNAE3_DBG_CMD_MNG_TBL,
+@@ -316,6 +309,13 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
+ 		.buf_len = HNS3_DBG_READ_LEN,
+ 		.init = hns3_dbg_common_file_init,
+ 	},
++	{
++		.name = "dev_info",
++		.cmd = HNAE3_DBG_CMD_DEV_INFO,
++		.dentry = HNS3_DBG_DENTRY_COMMON,
++		.buf_len = HNS3_DBG_READ_LEN,
++		.init = hns3_dbg_common_file_init,
++	},
+ };
+ 
+ static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
+@@ -659,6 +659,80 @@ static void hns3_dump_rx_bd_info(struct hns3_nic_priv *priv,
+ 	sprintf(result[j++], "NA");
+ }
+ 
++static void
++hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
++	static const char * const str[] = {"no", "yes"};
++	unsigned long *caps = ae_dev->caps;
++	u32 i, state;
++
++	*pos += scnprintf(buf + *pos, len - *pos, "dev capability:\n");
++
++	for (i = 0; i < ARRAY_SIZE(hns3_dbg_cap); i++) {
++		state = test_bit(hns3_dbg_cap[i].cap_bit, caps);
++		*pos += scnprintf(buf + *pos, len - *pos, "%s: %s\n",
++				  hns3_dbg_cap[i].name, str[state]);
++	}
++
++	*pos += scnprintf(buf + *pos, len - *pos, "\n");
++}
++
++static void
++hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
++	struct hnae3_dev_specs *dev_specs = &ae_dev->dev_specs;
++	struct hnae3_knic_private_info *kinfo = &h->kinfo;
++
++	*pos += scnprintf(buf + *pos, len - *pos, "dev_spec:\n");
++	*pos += scnprintf(buf + *pos, len - *pos, "MAC entry num: %u\n",
++			  dev_specs->mac_entry_num);
++	*pos += scnprintf(buf + *pos, len - *pos, "MNG entry num: %u\n",
++			  dev_specs->mng_entry_num);
++	*pos += scnprintf(buf + *pos, len - *pos, "MAX non tso bd num: %u\n",
++			  dev_specs->max_non_tso_bd_num);
++	*pos += scnprintf(buf + *pos, len - *pos, "RSS ind tbl size: %u\n",
++			  dev_specs->rss_ind_tbl_size);
++	*pos += scnprintf(buf + *pos, len - *pos, "RSS key size: %u\n",
++			  dev_specs->rss_key_size);
++	*pos += scnprintf(buf + *pos, len - *pos, "RSS size: %u\n",
++			  kinfo->rss_size);
++	*pos += scnprintf(buf + *pos, len - *pos, "Allocated RSS size: %u\n",
++			  kinfo->req_rss_size);
++	*pos += scnprintf(buf + *pos, len - *pos,
++			  "Task queue pairs numbers: %u\n",
++			  kinfo->num_tqps);
++	*pos += scnprintf(buf + *pos, len - *pos, "RX buffer length: %u\n",
++			  kinfo->rx_buf_len);
++	*pos += scnprintf(buf + *pos, len - *pos, "Desc num per TX queue: %u\n",
++			  kinfo->num_tx_desc);
++	*pos += scnprintf(buf + *pos, len - *pos, "Desc num per RX queue: %u\n",
++			  kinfo->num_rx_desc);
++	*pos += scnprintf(buf + *pos, len - *pos,
++			  "Total number of enabled TCs: %u\n",
++			  kinfo->tc_info.num_tc);
++	*pos += scnprintf(buf + *pos, len - *pos, "MAX INT QL: %u\n",
++			  dev_specs->int_ql_max);
++	*pos += scnprintf(buf + *pos, len - *pos, "MAX INT GL: %u\n",
++			  dev_specs->max_int_gl);
++	*pos += scnprintf(buf + *pos, len - *pos, "MAX TM RATE: %u\n",
++			  dev_specs->max_tm_rate);
++	*pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n",
++			  dev_specs->max_qset_num);
++}
++
++static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len)
++{
++	int pos = 0;
++
++	hns3_dbg_dev_caps(h, buf, len, &pos);
++
++	hns3_dbg_dev_specs(h, buf, len, &pos);
++
++	return 0;
++}
++
+ static int hns3_dbg_rx_bd_info(struct hns3_dbg_data *d, char *buf, int len)
+ {
+ 	char data_str[ARRAY_SIZE(rx_bd_info_items)][HNS3_DBG_DATA_STR_LEN];
+@@ -810,6 +884,10 @@ static const struct hns3_dbg_func hns3_dbg_cmd_func[] = {
+ 		.cmd = HNAE3_DBG_CMD_TX_QUEUE_INFO,
+ 		.dbg_dump = hns3_dbg_tx_queue_info,
+ 	},
++	{
++		.cmd = HNAE3_DBG_CMD_DEV_INFO,
++		.dbg_dump = hns3_dbg_dev_info,
++	},
+ };
+ 
+ static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index c2b465415e8c..85002d1c1fb7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -440,7 +440,6 @@ enum hns3_flow_level_range {
+ 	HNS3_FLOW_ULTRA = 3,
+ };
+ 
+-#define HNS3_INT_GL_MAX			0x1FE0
+ #define HNS3_INT_GL_50K			0x0014
+ #define HNS3_INT_GL_20K			0x0032
+ #define HNS3_INT_GL_18K			0x0036
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 4d982cb80f8b..ea26a3fce66b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1141,19 +1141,21 @@ static int hns3_get_coalesce(struct net_device *netdev,
+ static int hns3_check_gl_coalesce_para(struct net_device *netdev,
+ 				       struct ethtool_coalesce *cmd)
+ {
++	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+ 	u32 rx_gl, tx_gl;
+ 
+-	if (cmd->rx_coalesce_usecs > HNS3_INT_GL_MAX) {
++	if (cmd->rx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) {
+ 		netdev_err(netdev,
+-			   "Invalid rx-usecs value, rx-usecs range is 0-%d\n",
+-			   HNS3_INT_GL_MAX);
++			   "invalid rx-usecs value, rx-usecs range is 0-%u\n",
++			   ae_dev->dev_specs.max_int_gl);
+ 		return -EINVAL;
+ 	}
+ 
+-	if (cmd->tx_coalesce_usecs > HNS3_INT_GL_MAX) {
++	if (cmd->tx_coalesce_usecs > ae_dev->dev_specs.max_int_gl) {
+ 		netdev_err(netdev,
+-			   "Invalid tx-usecs value, tx-usecs range is 0-%d\n",
+-			   HNS3_INT_GL_MAX);
++			   "invalid tx-usecs value, tx-usecs range is 0-%u\n",
++			   ae_dev->dev_specs.max_int_gl);
+ 		return -EINVAL;
+ 	}
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 022e58235a58..d28546b5af0b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -1148,7 +1148,8 @@ struct hclge_dev_specs_0_cmd {
+ 	__le16 rss_key_size;
+ 	__le16 int_ql_max;
+ 	u8 max_non_tso_bd_num;
+-	u8 rsv1[5];
++	u8 rsv1;
++	__le32 max_tm_rate;
+ };
+ 
+ #define HCLGE_DEF_MAX_INT_GL		0x1FE0U
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index c65abb2c2b09..0517dedae55f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -1324,16 +1324,16 @@ static int hclge_dbg_dump_mac_table(struct hclge_dev *hdev, char *buf, int len)
+ 	int j;
+ 
+ 	mc_tbl_len = sizeof(struct hclge_mac_vlan_idx_rd_mc) *
+-		     HCLGE_DBG_MAC_TBL_MAX;
++						HCLGE_DBG_MAC_TBL_MAX;
+ 	mc_mac_tbl = kzalloc(mc_tbl_len, GFP_KERNEL);
+ 	if (!mc_mac_tbl)
+ 		return -ENOMEM;
+ 
+ 	pos += scnprintf(buf + pos, len - pos, "Unicast tab:\n");
+ 	pos += scnprintf(buf + pos, len - pos,
+-			 " index  mac_addr            vlan_id  VMDq1  ");
++					 " index  mac_addr            vlan_id  VMDq1  ");
+ 	pos += scnprintf(buf + pos, len - pos,
+-			 "U_M  mac_en  in_port  E_type  E_Port\n");
++					 "U_M  mac_en  in_port  E_type  E_Port\n");
+ 
+ 	mc_tbl_idx = 0;
+ 	for (i = 0; i < HCLGE_DBG_MAC_TBL_MAX; i++) {
+@@ -1342,13 +1342,13 @@ static int hclge_dbg_dump_mac_table(struct hclge_dev *hdev, char *buf, int len)
+ 			msleep(HCLGE_DBG_PAUSE_TIME);
+ 
+ 		hclge_cmd_setup_basic_desc(&desc[0], HCLGE_PPP_MAC_VLAN_IDX_RD,
+-					   true);
++								true);
+ 		desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
+ 		hclge_cmd_setup_basic_desc(&desc[1], HCLGE_PPP_MAC_VLAN_IDX_RD,
+-					   true);
++								   true);
+ 		desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
+ 		hclge_cmd_setup_basic_desc(&desc[2], HCLGE_PPP_MAC_VLAN_IDX_RD,
+-					   true);
++								   true);
+ 
+ 		mac_rd_cmd = (struct hclge_mac_vlan_idx_rd_cmd *)desc[0].data;
+ 
+@@ -1356,7 +1356,7 @@ static int hclge_dbg_dump_mac_table(struct hclge_dev *hdev, char *buf, int len)
+ 		ret = hclge_cmd_send(&hdev->hw, desc, 3);
+ 		if (ret) {
+ 			dev_err(&hdev->pdev->dev,
+-				"failed to dump mac table, ret = %d\n", ret);
++				    "failed to dump mac table, ret = %d\n", ret);
+ 			kfree(mc_mac_tbl);
+ 			return ret;
+ 		}
+@@ -1367,58 +1367,58 @@ static int hclge_dbg_dump_mac_table(struct hclge_dev *hdev, char *buf, int len)
+ 		if (mac_rd_cmd->entry_type == HCLGE_DBG_MAC_MC_TBL) {
+ 			mc_mac_tbl[mc_tbl_idx].index = i;
+ 			memcpy(mc_mac_tbl[mc_tbl_idx].mac_addr,
+-			       mac_rd_cmd->mac_addr, ETH_ALEN);
++				   mac_rd_cmd->mac_addr, ETH_ALEN);
+ 			memcpy(mc_mac_tbl[mc_tbl_idx].mg_vf_mb,
+-			       desc[1].data, 24);
++				   desc[1].data, 24);
+ 			memcpy(&mc_mac_tbl[mc_tbl_idx].mg_vf_mb[24],
+-			       desc[2].data, 8);
++				   desc[2].data, 8);
+ 			mc_tbl_idx++;
+ 
+ 			continue;
+ 		}
+ 
+ 		pos += scnprintf(buf + pos, len - pos, " %04u   %pM  ",
+-				 i, mac_rd_cmd->mac_addr);
++						 i, mac_rd_cmd->mac_addr);
+ 
+ 		pos += scnprintf(buf + pos, len - pos,
+-				 " %04u     %u      %u    %u       %u        ",
+-				 le16_to_cpu(mac_rd_cmd->vlan_tag),
+-				 mac_rd_cmd->entry_type &
+-				 HCLGE_DBG_MAC_TBL_EN_TYPE,
+-				 mac_rd_cmd->entry_type &
+-				 HCLGE_DBG_MAC_TBL_MC_TYPE,
+-				 mac_rd_cmd->mc_mac_en &
+-				 HCLGE_DBG_MAC_TBL_MAC_EN,
+-				 le16_to_cpu(mac_rd_cmd->port) &
+-				 HCLGE_DBG_MAC_TBL_IN_PORT);
++						 " %04u     %u      %u    %u       %u        ",
++						 le16_to_cpu(mac_rd_cmd->vlan_tag),
++						 mac_rd_cmd->entry_type &
++						 HCLGE_DBG_MAC_TBL_EN_TYPE,
++						 mac_rd_cmd->entry_type &
++						 HCLGE_DBG_MAC_TBL_MC_TYPE,
++						 mac_rd_cmd->mc_mac_en &
++						 HCLGE_DBG_MAC_TBL_MAC_EN,
++						 le16_to_cpu(mac_rd_cmd->port) &
++						 HCLGE_DBG_MAC_TBL_IN_PORT);
+ 
+ 		pos += scnprintf(buf + pos, len - pos,
+-				 "%lu       %04x\n",
+-				 le16_to_cpu(mac_rd_cmd->egress_port) &
+-				 HCLGE_DBG_MAC_TBL_E_PORT_B,
+-				 le16_to_cpu(mac_rd_cmd->egress_port) &
+-				 HCLGE_DBG_MAC_TBL_E_PORT);
++						 "%lu       %04x\n",
++						 le16_to_cpu(mac_rd_cmd->egress_port) &
++						 HCLGE_DBG_MAC_TBL_E_PORT_B,
++						 le16_to_cpu(mac_rd_cmd->egress_port) &
++						 HCLGE_DBG_MAC_TBL_E_PORT);
+ 	}
+ 
+ 	if (mc_tbl_idx > 0) {
+ 		pos += scnprintf(buf + pos, len - pos,
+-				 "Multicast tab: entry number = %u\n",
+-				 mc_tbl_idx);
++						 "Multicast tab: entry number = %u\n",
++						 mc_tbl_idx);
+ 		pos += scnprintf(buf + pos, len - pos,
+-				 " index  mac_addr           UM_MC_RDATA\n");
++						 " index  mac_addr           UM_MC_RDATA\n");
+ 	}
+ 
+ 	for (i = 0; i < mc_tbl_idx; i++) {
+ 		pos += scnprintf(buf + pos, len - pos, " %04u   %pM  ",
+-				 mc_mac_tbl[i].index, mc_mac_tbl[i].mac_addr);
++						 mc_mac_tbl[i].index, mc_mac_tbl[i].mac_addr);
+ 
+ 		for (j = 31; j >= 3; j -= 4)
+ 			pos += scnprintf(buf + pos, len - pos,
+-					 "%02x%02x%02x%02x ",
+-					 mc_mac_tbl[i].mg_vf_mb[j],
+-					 mc_mac_tbl[i].mg_vf_mb[j - 1],
+-					 mc_mac_tbl[i].mg_vf_mb[j - 2],
+-					 mc_mac_tbl[i].mg_vf_mb[j - 3]);
++							 "%02x%02x%02x%02x ",
++							 mc_mac_tbl[i].mg_vf_mb[j],
++							 mc_mac_tbl[i].mg_vf_mb[j - 1],
++							 mc_mac_tbl[i].mg_vf_mb[j - 2],
++							 mc_mac_tbl[i].mg_vf_mb[j - 3]);
+ 
+ 		pos += scnprintf(buf + pos, len - pos, "\n");
+ 	}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index f81c6f8bb030..358d41ab9bfc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1360,6 +1360,9 @@ static void hclge_set_default_dev_specs(struct hclge_dev *hdev)
+ 	ae_dev->dev_specs.max_non_tso_bd_num = HCLGE_MAX_NON_TSO_BD_NUM;
+ 	ae_dev->dev_specs.rss_ind_tbl_size = HCLGE_RSS_IND_TBL_SIZE;
+ 	ae_dev->dev_specs.rss_key_size = HCLGE_RSS_KEY_SIZE;
++	ae_dev->dev_specs.max_qset_num = HCLGE_MAX_QSET_NUM;
++	ae_dev->dev_specs.max_tm_rate = HCLGE_ETHER_MAX_RATE;
++	ae_dev->dev_specs.max_int_gl = HCLGE_DEF_MAX_INT_GL;
+ }
+ 
+ static void hclge_parse_dev_specs(struct hclge_dev *hdev,
+@@ -1367,14 +1370,19 @@ static void hclge_parse_dev_specs(struct hclge_dev *hdev,
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct hclge_dev_specs_0_cmd *req0;
++	struct hclge_dev_specs_1_cmd *req1;
+ 
+ 	req0 = (struct hclge_dev_specs_0_cmd *)desc[0].data;
++	req1 = (struct hclge_dev_specs_1_cmd *)desc[1].data;
+ 
+ 	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
+ 	ae_dev->dev_specs.rss_ind_tbl_size =
+ 		le16_to_cpu(req0->rss_ind_tbl_size);
++	ae_dev->dev_specs.max_qset_num = le16_to_cpu(req1->max_qset_num);
+ 	ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
+ 	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
++	ae_dev->dev_specs.max_tm_rate = le32_to_cpu(req0->max_tm_rate);
++	ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
+ }
+ 
+ static int hclge_query_dev_specs(struct hclge_dev *hdev)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 1a262a247701..081f03e8eae5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -145,6 +145,8 @@
+ /* Factor used to calculate offset and bitmap of VF num */
+ #define HCLGE_VF_NUM_PER_CMD           64
+ 
++#define HCLGE_MAX_QSET_NUM             1024
++
+ #define HCLGE_DBG_RESET_INFO_LEN	1024
+ 
+ enum HLCGE_PORT_TYPE {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index c92d084bb798..434e6dfca032 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -23,8 +23,6 @@ enum hclge_shaper_level {
+ #define HCLGE_SHAPER_BS_U_DEF	5
+ #define HCLGE_SHAPER_BS_S_DEF	20
+ 
+-#define HCLGE_ETHER_MAX_RATE	100000
+-
+ /* hclge_shaper_para_calc: calculate ir parameter for the shaper
+  * @ir: Rate to be config, its unit is Mbps
+  * @shaper_level: the shaper level. eg: port, pg, priority, queueset
+@@ -40,7 +38,8 @@ enum hclge_shaper_level {
+  * @return: 0: calculate sucessful, negative: fail
+  */
+ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
+-				  struct hclge_shaper_ir_para *ir_para)
++				  struct hclge_shaper_ir_para *ir_para,
++				  u32 max_tm_rate)
+ {
+ #define DEFAULT_SHAPER_IR_B	126
+ #define DIVISOR_CLK		(1000 * 8)
+@@ -59,7 +58,7 @@ static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
+ 
+ 	/* Calc tick */
+ 	if (shaper_level >= HCLGE_SHAPER_LVL_CNT ||
+-	    ir > HCLGE_ETHER_MAX_RATE)
++	    ir > max_tm_rate)
+ 		return -EINVAL;
+ 
+ 	tick = tick_array[shaper_level];
+@@ -408,7 +407,7 @@ static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
+ 	int ret;
+ 
+ 	ret = hclge_shaper_para_calc(hdev->hw.mac.speed, HCLGE_SHAPER_LVL_PORT,
+-					&ir_para);
++					&ir_para, hdev->ae_dev->dev_specs.max_tm_rate);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -524,10 +523,10 @@ int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate)
+ 	int ret, i;
+ 
+ 	if (!max_tx_rate)
+-		max_tx_rate = HCLGE_ETHER_MAX_RATE;
++		max_tx_rate = hdev->ae_dev->dev_specs.max_tm_rate;
+ 
+ 	ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET,
+-				     &ir_para);
++				     &ir_para, hdev->ae_dev->dev_specs.max_tm_rate);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -701,7 +700,8 @@ static void hclge_tm_pg_info_init(struct hclge_dev *hdev)
+ 		hdev->tm_info.pg_info[i].pg_id = i;
+ 		hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR;
+ 
+-		hdev->tm_info.pg_info[i].bw_limit = HCLGE_ETHER_MAX_RATE;
++		hdev->tm_info.pg_info[i].bw_limit =
++					 hdev->ae_dev->dev_specs.max_tm_rate;
+ 
+ 		if (i != 0)
+ 			continue;
+@@ -764,6 +764,7 @@ static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev)
+ 
+ static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
+ {
++	u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
+ 	struct hclge_shaper_ir_para ir_para;
+ 	u32 shaper_para;
+ 	int ret;
+@@ -779,7 +780,7 @@ static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
+ 		ret = hclge_shaper_para_calc(
+ 					hdev->tm_info.pg_info[i].bw_limit,
+ 					HCLGE_SHAPER_LVL_PG,
+-					&ir_para);
++					&ir_para, max_tm_rate);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -897,6 +898,7 @@ static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)
+ 
+ static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
+ {
++	u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
+ 	struct hclge_shaper_ir_para ir_para;
+ 	u32 shaper_para;
+ 	int ret;
+@@ -906,7 +908,7 @@ static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
+ 		ret = hclge_shaper_para_calc(
+ 					hdev->tm_info.tc_info[i].bw_limit,
+ 					HCLGE_SHAPER_LVL_PRI,
+-					&ir_para);
++					&ir_para, max_tm_rate);
+ 		if (ret)
+ 			return ret;
+ 
+@@ -940,7 +942,7 @@ static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport)
+ 	int ret;
+ 
+ 	ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF,
+-				     &ir_para);
++				     &ir_para, hdev->ae_dev->dev_specs.max_tm_rate);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -969,6 +971,7 @@ static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport)
+ 	struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
+ 	struct hclge_dev *hdev = vport->back;
+ 	struct hclge_shaper_ir_para ir_para;
++	u32 max_tm_rate = hdev->ae_dev->dev_specs.max_tm_rate;
+ 	u32 i;
+ 	int ret;
+ 
+@@ -976,7 +979,7 @@ static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport)
+ 		ret = hclge_shaper_para_calc(
+ 					hdev->tm_info.tc_info[i].bw_limit,
+ 					HCLGE_SHAPER_LVL_QSET,
+-					&ir_para);
++					&ir_para, max_tm_rate);
+ 		if (ret)
+ 			return ret;
+ 	}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+index f4fb9c7e9c5f..8abb89beaae1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+@@ -19,6 +19,8 @@
+ #define HCLGE_TM_TX_SCHD_DWRR_MSK	BIT(0)
+ #define HCLGE_TM_TX_SCHD_SP_MSK		0xFE
+ 
++#define HCLGE_ETHER_MAX_RATE   100000
++
+ #define HCLGE_TM_PF_MAX_PRI_NUM		8
+ #define HCLGE_TM_PF_MAX_QSET_NUM	8
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 942a1d7406a0..2e857063a6b1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -287,6 +287,14 @@ struct hclgevf_dev_specs_0_cmd {
+ 	u8 rsv1[5];
+ };
+ 
++#define HCLGEVF_DEF_MAX_INT_GL         0x1FE0U
++
++struct hclgevf_dev_specs_1_cmd {
++       __le32 rsv0;
++       __le16 max_int_gl;
++       u8 rsv1[18];
++};
++
+ static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
+ {
+ 	writel(value, base + reg);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 74d2aef34315..db292ca270b8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -3043,6 +3043,7 @@ static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)
+ 					HCLGEVF_MAX_NON_TSO_BD_NUM;
+ 	ae_dev->dev_specs.rss_ind_tbl_size = HCLGEVF_RSS_IND_TBL_SIZE;
+ 	ae_dev->dev_specs.rss_key_size = HCLGEVF_RSS_KEY_SIZE;
++	ae_dev->dev_specs.max_int_gl = HCLGEVF_DEF_MAX_INT_GL;
+ }
+ 
+ static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
+@@ -3050,14 +3051,17 @@ static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct hclgevf_dev_specs_0_cmd *req0;
++	struct hclgevf_dev_specs_1_cmd *req1;
+ 
+ 	req0 = (struct hclgevf_dev_specs_0_cmd *)desc[0].data;
++	req1 = (struct hclgevf_dev_specs_1_cmd *)desc[1].data;
+ 
+ 	ae_dev->dev_specs.max_non_tso_bd_num = req0->max_non_tso_bd_num;
+ 	ae_dev->dev_specs.rss_ind_tbl_size =
+ 					le16_to_cpu(req0->rss_ind_tbl_size);
+ 	ae_dev->dev_specs.int_ql_max = le16_to_cpu(req0->int_ql_max);
+ 	ae_dev->dev_specs.rss_key_size = le16_to_cpu(req0->rss_key_size);
++	ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
+ }
+ 
+ static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
+-- 
+2.34.1
+
diff --git a/patches/0444-net-hns3-add-support-for-PTP.patch b/patches/0444-net-hns3-add-support-for-PTP.patch
new file mode 100644
index 0000000..8e09e71
--- /dev/null
+++ b/patches/0444-net-hns3-add-support-for-PTP.patch
@@ -0,0 +1,1167 @@
+From f10be9f9b028d04c6f7460837dbf8b57ba3af9c3 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:18 +0800
+Subject: [PATCH 083/283] net: hns3: add support for PTP
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 0bf5eb788512187b744ef7f79de835e6cbe85b9c
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0bf5eb788512187b744ef7f79de835e6cbe85b9c
+
+----------------------------------------------------------------------
+
+Adds PTP support for HNS3 ethernet driver.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/Kconfig
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+---
+ drivers/net/ethernet/hisilicon/Kconfig        |   1 +
+ drivers/net/ethernet/hisilicon/hns3/Makefile  |   3 +-
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  20 +
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  27 +
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  14 +-
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  12 +
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |   4 +
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  61 +-
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   7 +
+ .../hisilicon/hns3/hns3pf/hclge_ptp.c         | 544 ++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ptp.h         | 134 +++++
+ include/linux/ptp_clock_kernel.h              |  13 +
+ 12 files changed, 832 insertions(+), 8 deletions(-)
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
+
+diff --git a/drivers/net/ethernet/hisilicon/Kconfig b/drivers/net/ethernet/hisilicon/Kconfig
+index 397ce4088b53..2b8d32d02049 100644
+--- a/drivers/net/ethernet/hisilicon/Kconfig
++++ b/drivers/net/ethernet/hisilicon/Kconfig
+@@ -91,6 +91,7 @@ config HNS3_HCLGE
+ 	tristate "Hisilicon HNS3 HCLGE Acceleration Engine & Compatibility Layer Support"
+ 	default m
+ 	depends on PCI_MSI
++	imply PTP_1588_CLOCK
+ 	---help---
+ 	  This selects the HNS3_HCLGE network acceleration engine & its hardware
+ 	  compatibility layer. The engine would be used in Hisilicon hip08 family of
+diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile
+index 5bec09bb6e9e..c012979b86be 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/Makefile
+@@ -35,7 +35,8 @@ HCLGE_OBJ = 	hns3pf/hclge_main.o \
+ 			hns3pf/hclge_debugfs.o \
+ 			hns3pf/hclge_tm.o \
+ 			hns3pf/hclge_mbx.o \
+-			hns3pf/hclge_err.o
++			hns3pf/hclge_err.o \
++			hns3pf/hclge_ptp.o
+ 
+ 
+ HCLGE_OBJ_IT_MAIN	=	hns3_extension/hns3pf/hclge_main_it.o \
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 6b2969e1346a..9e5a62a4f549 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -530,6 +530,20 @@ struct hnae3_ae_dev {
+  *   Configure the default MAC for specified VF
+  * get_module_eeprom
+  *   Get the optical module eeprom info.
++ * add_cls_flower
++ *   Add clsflower rule
++ * del_cls_flower
++ *   Delete clsflower rule
++ * cls_flower_active
++ *   Check if any cls flower rule exist
++ * dbg_read_cmd
++ *   Execute debugfs read command.
++ * set_tx_hwts_info
++ *   Save information for 1588 tx packet
++ * get_rx_hwts
++ *   Get 1588 rx hwstamp
++ * get_ts_info
++ *   Get phc info
+  */
+ struct hnae3_ae_ops {
+ 	int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
+@@ -716,6 +730,12 @@ struct hnae3_ae_ops {
+ 				      struct ethtool_link_ksettings *cmd);
+ 	int (*set_phy_link_ksettings)(struct hnae3_handle *handle,
+ 				      const struct ethtool_link_ksettings *cmd);
++	bool (*set_tx_hwts_info)(struct hnae3_handle *handle,
++				 struct sk_buff *skb);
++	void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb,
++			    u32 nsec, u32 sec);
++	int (*get_ts_info)(struct hnae3_handle *handle,
++			   struct ethtool_ts_info *info);
+ /* Notice! If the function is not for test, the definition must before
+  * CONFIG_HNS3_TEST! Because RoCE will use this head file, and it won't
+  * set CONFIG_HNS3_TEST, that may cause RoCE calling the wrong function.
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 6d9be3895f5a..ddf8644e9111 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -1510,6 +1510,18 @@ static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
+ 	ring->pending_buf = 0;
+ }
+ 
++static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
++		      struct hns3_desc *desc)
++{
++	struct hnae3_handle *h = hns3_get_handle(netdev);
++
++	if (!(h->ae_algo->ops->set_tx_hwts_info &&
++	      h->ae_algo->ops->set_tx_hwts_info(h, skb)))
++		return;
++
++	desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
++}
++
+ netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
+ {
+ 	struct hns3_nic_priv *priv = netdev_priv(netdev);
+@@ -1561,9 +1573,15 @@ netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
+ 
+ 	pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
+ 					(ring->desc_num - 1);
++
++	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
++		hns3_tsyn(netdev, skb, &ring->desc[pre_ntu]);
++
+ 	ring->desc[pre_ntu].tx.bdtp_fe_sc_vld_ra_ri |=
+ 				cpu_to_le16(BIT(HNS3_TXD_FE_B));
+ 
++	skb_tx_timestamp(skb);
++
+ 	/* Complete translate all packets */
+ 	dev_queue = netdev_get_tx_queue(netdev, ring->queue_index);
+ 	if (!netdev_xmit_more()) {
+@@ -3234,6 +3252,15 @@ static int hns3_handle_bdinfo(struct hns3_enet_ring *ring, struct sk_buff *skb)
+ 	l234info = le32_to_cpu(desc->rx.l234_info);
+ 	ol_info = le32_to_cpu(desc->rx.ol_info);
+ 
++	if (unlikely(bd_base_info & BIT(HNS3_RXD_TS_VLD_B))) {
++		struct hnae3_handle *h = hns3_get_handle(netdev);
++		u32 nsec = le32_to_cpu(desc->ts_nsec);
++		u32 sec = le32_to_cpu(desc->ts_sec);
++
++		if (h->ae_algo->ops->get_rx_hwts)
++			h->ae_algo->ops->get_rx_hwts(h, skb, nsec, sec);
++	}
++
+ 	/* Based on hw strategy, the tag offloaded will be stored at
+ 	 * ot_vlan_tag in two layer tag case, and stored at vlan_tag
+ 	 * in one layer tag case.
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 85002d1c1fb7..70662c84cb57 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -121,8 +121,9 @@ enum hns3_nic_state {
+ #define HNS3_RXD_LUM_B				9
+ #define HNS3_RXD_CRCP_B				10
+ #define HNS3_RXD_L3L4P_B			11
+-#define HNS3_RXD_TSIND_S			12
+-#define HNS3_RXD_TSIND_M			(0x7 << HNS3_RXD_TSIND_S)
++#define HNS3_RXD_TSIDX_S			12
++#define HNS3_RXD_TSIDX_M			(0x3 << HNS3_RXD_TSIDX_S)
++#define HNS3_RXD_TS_VLD_B			14
+ #define HNS3_RXD_LKBK_B				15
+ #define HNS3_RXD_GRO_SIZE_S			16
+ #define HNS3_RXD_GRO_SIZE_M			(0x3fff << HNS3_RXD_GRO_SIZE_S)
+@@ -235,7 +236,14 @@ enum hns3_pkt_tun_type {
+ 
+ /* hardware spec ring buffer format */
+ struct __packed hns3_desc {
+-	__le64 addr;
++	union {
++		__le64 addr;
++		__le16 csum;
++		struct {
++			__le32 ts_nsec;
++			__le32 ts_sec;
++		};
++	};
+ 	union {
+ 		struct {
+ 			__le16 vlan_tag;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index ea26a3fce66b..c42c6163ac80 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1528,6 +1528,17 @@ static int hns3_get_module_eeprom(struct net_device *netdev,
+ 				 ETHTOOL_COALESCE_TX_USECS_HIGH |	\
+ 				 ETHTOOL_COALESCE_MAX_FRAMES)
+ 
++static int hns3_get_ts_info(struct net_device *netdev,
++			    struct ethtool_ts_info *info)
++{
++	struct hnae3_handle *handle = hns3_get_handle(netdev);
++
++	if (handle->ae_algo->ops->get_ts_info)
++		return handle->ae_algo->ops->get_ts_info(handle, info);
++
++	return ethtool_op_get_ts_info(netdev, info);
++}
++
+ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ 	.supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
+ 	.get_drvinfo = hns3_get_drvinfo,
+@@ -1588,6 +1599,7 @@ static const struct ethtool_ops hns3_ethtool_ops = {
+ 	.set_fecparam = hns3_set_fecparam,
+ 	.get_module_info = hns3_get_module_info,
+ 	.get_module_eeprom = hns3_get_module_eeprom,
++	.get_ts_info = hns3_get_ts_info,
+ };
+ 
+ void hns3_ethtool_set_ops(struct net_device *netdev)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index d28546b5af0b..4d89efaf4aed 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -133,6 +133,10 @@ enum hclge_opcode_type {
+ 	/* check sum command */
+ 	HCLGE_OPC_CFG_CHECKSUM_EN       = 0x0601,
+ 
++	/* PTP commands */
++	HCLGE_OPC_PTP_INT_EN		= 0x0501,
++	HCLGE_OPC_PTP_MODE_CFG		= 0x0507,
++
+ 	/* PFC/Pause commands */
+ 	HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
+ 	HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 358d41ab9bfc..d4db7a84f279 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3267,6 +3267,12 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
+ 	    hw_err_src_reg & HCLGE_RAS_REG_ERR_MASK)
+ 		return HCLGE_VECTOR0_EVENT_ERR;
+ 
++	/* check for vector0 ptp event source */
++	if (BIT(HCLGE_VECTOR0_REG_PTP_INT_B) & msix_src_reg) {
++		*clearval = msix_src_reg;
++		return HCLGE_VECTOR0_EVENT_PTP;
++	}
++
+ 	/* check for vector0 mailbox(=CMDQ RX) event source */
+ 	if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
+ 		cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
+@@ -3286,6 +3292,7 @@ static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
+ 				    u32 regclr)
+ {
+ 	switch (event_type) {
++	case HCLGE_VECTOR0_EVENT_PTP:
+ 	case HCLGE_VECTOR0_EVENT_RST:
+ 		hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
+ 		break;
+@@ -3314,6 +3321,7 @@ static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
+ static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
+ {
+ 	struct hclge_dev *hdev = data;
++	unsigned long flags;
+ 	u32 clearval = 0;
+ 	u32 event_cause;
+ 
+@@ -3328,6 +3336,11 @@ static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
+ 	case HCLGE_VECTOR0_EVENT_RST:
+ 		hclge_reset_task_schedule(hdev);
+ 		break;
++	case HCLGE_VECTOR0_EVENT_PTP:
++		spin_lock_irqsave(&hdev->ptp->lock, flags);
++		hclge_ptp_clean_tx_hwts(hdev);
++		spin_unlock_irqrestore(&hdev->ptp->lock, flags);
++		break;
+ 	case HCLGE_VECTOR0_EVENT_MBX:
+ 		/* If we are here then,
+ 		 * 1. Either we are not handling any mbx task and we are not
+@@ -3349,7 +3362,8 @@ static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
+ 	hclge_clear_event_cause(hdev, event_cause, clearval);
+ 
+ 	/* Enable interrupt if it is not caused by reset event or error event */
+-	if (event_cause == HCLGE_VECTOR0_EVENT_MBX ||
++	if (event_cause == HCLGE_VECTOR0_EVENT_PTP ||
++	    event_cause == HCLGE_VECTOR0_EVENT_MBX ||
+ 	    event_cause == HCLGE_VECTOR0_EVENT_OTHER)
+ 		hclge_enable_vector(&hdev->misc_vector, true);
+ 
+@@ -4318,6 +4332,27 @@ static void hclge_periodic_service_task(struct hclge_dev *hdev)
+ 	hclge_task_schedule(hdev, delta);
+ }
+ 
++static void hclge_ptp_service_task(struct hclge_dev *hdev)
++{
++	unsigned long flags;
++
++	if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state) ||
++	    !test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state) ||
++	    !time_is_before_jiffies(hdev->ptp->tx_start + HZ))
++		return;
++
++	/* to prevent concurrence with the irq handler */
++	spin_lock_irqsave(&hdev->ptp->lock, flags);
++
++	/* check HCLGE_STATE_PTP_TX_HANDLING here again, since the irq
++	 * handler may handle it just before spin_lock_irqsave().
++	 */
++	if (test_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state))
++		hclge_ptp_clean_tx_hwts(hdev);
++
++	spin_unlock_irqrestore(&hdev->ptp->lock, flags);
++}
++
+ static void hclge_service_task(struct work_struct *work)
+ {
+ 	struct hclge_dev *hdev =
+@@ -4325,6 +4360,7 @@ static void hclge_service_task(struct work_struct *work)
+ 
+ 	hclge_errhand_service_task(hdev);
+ 	hclge_reset_service_task(hdev);
++	hclge_ptp_service_task(hdev);
+ 	hclge_mailbox_service_task(hdev);
+ 	hclge_periodic_service_task(hdev);
+ 
+@@ -8579,8 +8615,15 @@ static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+ 
+-	if (!hdev->hw.mac.phydev)
+-		return hclge_mii_ioctl(hdev, ifr, cmd);
++	switch (cmd) {
++	case SIOCGHWTSTAMP:
++		return hclge_ptp_get_cfg(hdev, ifr);
++	case SIOCSHWTSTAMP:
++		return hclge_ptp_set_cfg(hdev, ifr);
++	default:
++		if (!hdev->hw.mac.phydev)
++			return hclge_mii_ioctl(hdev, ifr, cmd);
++	}
+ 
+ 	return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
+ }
+@@ -10719,6 +10762,10 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 		goto err_mdiobus_unreg;
+ 	}
+ 
++	ret = hclge_ptp_init(hdev);
++	if (ret)
++		goto err_mdiobus_unreg;
++
+ 	INIT_KFIFO(hdev->mac_tnl_log);
+ 
+ 	hclge_dcb_ops_set(hdev);
+@@ -11089,7 +11136,9 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 		return ret;
+ 	}
+ 
+-	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &hdev->state);
++	ret = hclge_ptp_init(hdev);
++	if (ret)
++		return ret;
+ 
+ 	/* Log and clear the hw errors those already occurred */
+ 	if (hnae3_dev_ras_imp_supported(hdev))
+@@ -11147,6 +11196,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	hclge_clear_vf_vlan(hdev);
+ 	hclge_misc_affinity_teardown(hdev);
+ 	hclge_state_uninit(hdev);
++	hclge_ptp_uninit(hdev);
+ 	hclge_uninit_vport_mac_table(hdev);
+ 
+ 	if (mac->phydev)
+@@ -12049,6 +12099,9 @@ struct hnae3_ae_ops hclge_ops = {
+ 	.get_cmdq_stat = hclge_get_cmdq_stat,
+ 	.get_phy_link_ksettings = hclge_get_phy_link_ksettings,
+ 	.set_phy_link_ksettings = hclge_set_phy_link_ksettings,
++	.set_tx_hwts_info = hclge_ptp_set_tx_info,
++	.get_rx_hwts = hclge_ptp_get_rx_hwts,
++	.get_ts_info = hclge_ptp_get_ts_info,
+ };
+ 
+ static struct hnae3_ae_algo ae_algo = {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 081f03e8eae5..660201b8bd11 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -10,6 +10,7 @@
+ #include <linux/kfifo.h>
+ 
+ #include "hclge_cmd.h"
++#include "hclge_ptp.h"
+ #include "hnae3.h"
+ 
+ #define HCLGE_MOD_VERSION "23.7.1"
+@@ -177,6 +178,7 @@ enum HLCGE_PORT_TYPE {
+ #define HCLGE_FUN_RST_ING_B		0
+ 
+ /* Vector0 register bits define */
++#define HCLGE_VECTOR0_REG_PTP_INT_B	0
+ #define HCLGE_VECTOR0_GLOBALRESET_INT_B	5
+ #define HCLGE_VECTOR0_CORERESET_INT_B	6
+ #define HCLGE_VECTOR0_IMPRESET_INT_B	7
+@@ -228,6 +230,8 @@ enum HCLGE_DEV_STATE {
+ 	HCLGE_STATE_FD_TBL_CHANGED,
+ 	HCLGE_STATE_FD_CLEAR_ALL,
+ 	HCLGE_STATE_FD_USER_DEF_CHANGED,
++	HCLGE_STATE_PTP_EN,
++	HCLGE_STATE_PTP_TX_HANDLING,
+ 	HCLGE_STATE_MAX
+ };
+ 
+@@ -235,6 +239,7 @@ enum hclge_evt_cause {
+ 	HCLGE_VECTOR0_EVENT_RST,
+ 	HCLGE_VECTOR0_EVENT_MBX,
+ 	HCLGE_VECTOR0_EVENT_ERR,
++	HCLGE_VECTOR0_EVENT_PTP,
+ 	HCLGE_VECTOR0_EVENT_OTHER,
+ };
+ 
+@@ -880,6 +885,8 @@ struct hclge_dev {
+ 
+ 	/* affinity mask and notify for misc interrupt */
+ 	cpumask_t affinity_mask;
++	struct irq_affinity_notify affinity_notify;
++	struct hclge_ptp *ptp;
+ };
+ 
+ /* VPort level vlan tag configuration for TX direction */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+new file mode 100644
+index 000000000000..b3eb8f109dbb
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+@@ -0,0 +1,544 @@
++// SPDX-License-Identifier: GPL-2.0+
++// Copyright (c) 2021 Hisilicon Limited.
++
++#include <linux/skbuff.h>
++#include "hclge_main.h"
++#include "hnae3.h"
++
++static int hclge_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
++{
++	struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp);
++	u64 adj_val, adj_base, diff;
++	unsigned long flags;
++	bool is_neg = false;
++	u32 quo, numerator;
++
++	if (ppb < 0) {
++		ppb = -ppb;
++		is_neg = true;
++	}
++
++	adj_base = HCLGE_PTP_CYCLE_ADJ_BASE * HCLGE_PTP_CYCLE_ADJ_UNIT;
++	adj_val = adj_base * ppb;
++	diff = div_u64(adj_val, 1000000000ULL);
++
++	if (is_neg)
++		adj_val = adj_base - diff;
++	else
++		adj_val = adj_base + diff;
++
++	/* This clock cycle is defined by three part: quotient, numerator
++	 * and denominator. For example, 2.5ns, the quotient is 2,
++	 * denominator is fixed to HCLGE_PTP_CYCLE_ADJ_UNIT, and numerator
++	 * is 0.5 * HCLGE_PTP_CYCLE_ADJ_UNIT.
++	 */
++	quo = div_u64_rem(adj_val, HCLGE_PTP_CYCLE_ADJ_UNIT, &numerator);
++
++	spin_lock_irqsave(&hdev->ptp->lock, flags);
++	writel(quo, hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG);
++	writel(numerator, hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG);
++	writel(HCLGE_PTP_CYCLE_ADJ_UNIT,
++	       hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG);
++	writel(HCLGE_PTP_CYCLE_ADJ_EN,
++	       hdev->ptp->io_base + HCLGE_PTP_CYCLE_CFG_REG);
++	spin_unlock_irqrestore(&hdev->ptp->lock, flags);
++
++	return 0;
++}
++
++bool hclge_ptp_set_tx_info(struct hnae3_handle *handle, struct sk_buff *skb)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_dev *hdev = vport->back;
++	struct hclge_ptp *ptp = hdev->ptp;
++
++	if (!test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) ||
++	    test_and_set_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state)) {
++		ptp->tx_skipped++;
++		return false;
++	}
++
++	ptp->tx_start = jiffies;
++	ptp->tx_skb = skb_get(skb);
++	ptp->tx_cnt++;
++
++	return true;
++}
++
++void hclge_ptp_clean_tx_hwts(struct hclge_dev *hdev)
++{
++	struct sk_buff *skb = hdev->ptp->tx_skb;
++	struct skb_shared_hwtstamps hwts;
++	u32 hi, lo;
++	u64 ns;
++
++	ns = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_NSEC_REG) &
++	     HCLGE_PTP_TX_TS_NSEC_MASK;
++	lo = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_SEC_L_REG);
++	hi = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_SEC_H_REG) &
++	     HCLGE_PTP_TX_TS_SEC_H_MASK;
++	hdev->ptp->last_tx_seqid = readl(hdev->ptp->io_base +
++		HCLGE_PTP_TX_TS_SEQID_REG);
++
++	if (skb) {
++		hdev->ptp->tx_skb = NULL;
++		hdev->ptp->tx_cleaned++;
++
++		ns += (((u64)hi) << 32 | lo) * NSEC_PER_SEC;
++		hwts.hwtstamp = ns_to_ktime(ns);
++		skb_tstamp_tx(skb, &hwts);
++		dev_kfree_skb_any(skb);
++	}
++
++	clear_bit(HCLGE_STATE_PTP_TX_HANDLING, &hdev->state);
++}
++
++void hclge_ptp_get_rx_hwts(struct hnae3_handle *handle, struct sk_buff *skb,
++			   u32 nsec, u32 sec)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_dev *hdev = vport->back;
++	unsigned long flags;
++	u64 ns = nsec;
++	u32 sec_h;
++
++	if (!test_bit(HCLGE_PTP_FLAG_RX_EN, &hdev->ptp->flags))
++		return;
++
++	/* Since the BD does not have enough space for the higher 16 bits of
++	 * second, and this part will not change frequently, so read it
++	 * from register.
++	 */
++	spin_lock_irqsave(&hdev->ptp->lock, flags);
++	sec_h = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_SEC_H_REG);
++	spin_unlock_irqrestore(&hdev->ptp->lock, flags);
++
++	ns += (((u64)sec_h) << HCLGE_PTP_SEC_H_OFFSET | sec) * NSEC_PER_SEC;
++	skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
++	hdev->ptp->last_rx = jiffies;
++	hdev->ptp->rx_cnt++;
++}
++
++static int hclge_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
++			      struct ptp_system_timestamp *sts)
++{
++	struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp);
++	unsigned long flags;
++	u32 hi, lo;
++	u64 ns;
++
++	spin_lock_irqsave(&hdev->ptp->lock, flags);
++	ns = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_NSEC_REG);
++	hi = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_SEC_H_REG);
++	lo = readl(hdev->ptp->io_base + HCLGE_PTP_CUR_TIME_SEC_L_REG);
++	spin_unlock_irqrestore(&hdev->ptp->lock, flags);
++
++	ns += (((u64)hi) << HCLGE_PTP_SEC_H_OFFSET | lo) * NSEC_PER_SEC;
++	*ts = ns_to_timespec64(ns);
++
++	return 0;
++}
++
++static int hclge_ptp_settime(struct ptp_clock_info *ptp,
++			     const struct timespec64 *ts)
++{
++	struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp);
++	unsigned long flags;
++
++	spin_lock_irqsave(&hdev->ptp->lock, flags);
++	writel(ts->tv_nsec, hdev->ptp->io_base + HCLGE_PTP_TIME_NSEC_REG);
++	writel(ts->tv_sec >> HCLGE_PTP_SEC_H_OFFSET,
++	       hdev->ptp->io_base + HCLGE_PTP_TIME_SEC_H_REG);
++	writel(ts->tv_sec & HCLGE_PTP_SEC_L_MASK,
++	       hdev->ptp->io_base + HCLGE_PTP_TIME_SEC_L_REG);
++	/* synchronize the time of phc */
++	writel(HCLGE_PTP_TIME_SYNC_EN,
++	       hdev->ptp->io_base + HCLGE_PTP_TIME_SYNC_REG);
++	spin_unlock_irqrestore(&hdev->ptp->lock, flags);
++
++	return 0;
++}
++
++static int hclge_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
++{
++	struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp);
++	unsigned long flags;
++	bool is_neg = false;
++	u32 adj_val = 0;
++
++	if (delta < 0) {
++		adj_val |= HCLGE_PTP_TIME_NSEC_NEG;
++		delta = -delta;
++		is_neg = true;
++	}
++
++	if (delta > HCLGE_PTP_TIME_NSEC_MASK) {
++		struct timespec64 ts;
++		s64 ns;
++
++		hclge_ptp_gettimex(ptp, &ts, NULL);
++		ns = timespec64_to_ns(&ts);
++		ns = is_neg ? ns - delta : ns + delta;
++		ts = ns_to_timespec64(ns);
++		return hclge_ptp_settime(ptp, &ts);
++	}
++
++	adj_val |= delta & HCLGE_PTP_TIME_NSEC_MASK;
++
++	spin_lock_irqsave(&hdev->ptp->lock, flags);
++	writel(adj_val, hdev->ptp->io_base + HCLGE_PTP_TIME_NSEC_REG);
++	writel(HCLGE_PTP_TIME_ADJ_EN,
++	       hdev->ptp->io_base + HCLGE_PTP_TIME_ADJ_REG);
++	spin_unlock_irqrestore(&hdev->ptp->lock, flags);
++
++	return 0;
++}
++
++int hclge_ptp_get_cfg(struct hclge_dev *hdev, struct ifreq *ifr)
++{
++	if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state))
++		return -EOPNOTSUPP;
++
++	return copy_to_user(ifr->ifr_data, &hdev->ptp->ts_cfg,
++		sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
++}
++
++static int hclge_ptp_int_en(struct hclge_dev *hdev, bool en)
++{
++	struct hclge_ptp_int_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	req = (struct hclge_ptp_int_cmd *)desc.data;
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PTP_INT_EN, false);
++	req->int_en = en ? 1 : 0;
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to %s ptp interrupt, ret = %d\n",
++			en ? "enable" : "disable", ret);
++
++	return ret;
++}
++
++int hclge_ptp_cfg_qry(struct hclge_dev *hdev, u32 *cfg)
++{
++	struct hclge_ptp_cfg_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	req = (struct hclge_ptp_cfg_cmd *)desc.data;
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PTP_MODE_CFG, true);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to query ptp config, ret = %d\n", ret);
++		return ret;
++	}
++
++	*cfg = le32_to_cpu(req->cfg);
++
++	return 0;
++}
++
++static int hclge_ptp_cfg(struct hclge_dev *hdev, u32 cfg)
++{
++	struct hclge_ptp_cfg_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	req = (struct hclge_ptp_cfg_cmd *)desc.data;
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PTP_MODE_CFG, false);
++	req->cfg = cpu_to_le32(cfg);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to config ptp, ret = %d\n", ret);
++
++	return ret;
++}
++
++static int hclge_ptp_set_tx_mode(struct hwtstamp_config *cfg,
++				 unsigned long *flags, u32 *ptp_cfg)
++{
++	switch (cfg->tx_type) {
++	case HWTSTAMP_TX_OFF:
++		clear_bit(HCLGE_PTP_FLAG_TX_EN, flags);
++		break;
++	case HWTSTAMP_TX_ON:
++		set_bit(HCLGE_PTP_FLAG_TX_EN, flags);
++		*ptp_cfg |= HCLGE_PTP_TX_EN_B;
++		break;
++	default:
++		return -ERANGE;
++	}
++
++	return 0;
++}
++
++static int hclge_ptp_set_rx_mode(struct hwtstamp_config *cfg,
++				 unsigned long *flags, u32 *ptp_cfg)
++{
++	int rx_filter = cfg->rx_filter;
++
++	switch (cfg->rx_filter) {
++	case HWTSTAMP_FILTER_NONE:
++		clear_bit(HCLGE_PTP_FLAG_RX_EN, flags);
++		break;
++	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
++	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
++	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
++		set_bit(HCLGE_PTP_FLAG_RX_EN, flags);
++		*ptp_cfg |= HCLGE_PTP_RX_EN_B;
++		*ptp_cfg |= HCLGE_PTP_UDP_FULL_TYPE << HCLGE_PTP_UDP_EN_SHIFT;
++		rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
++		break;
++	case HWTSTAMP_FILTER_PTP_V2_EVENT:
++	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
++	case HWTSTAMP_FILTER_PTP_V2_SYNC:
++	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
++	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
++	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
++	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
++	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
++	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
++		set_bit(HCLGE_PTP_FLAG_RX_EN, flags);
++		*ptp_cfg |= HCLGE_PTP_RX_EN_B;
++		*ptp_cfg |= HCLGE_PTP_UDP_FULL_TYPE << HCLGE_PTP_UDP_EN_SHIFT;
++		*ptp_cfg |= HCLGE_PTP_MSG1_V2_DEFAULT << HCLGE_PTP_MSG1_SHIFT;
++		*ptp_cfg |= HCLGE_PTP_MSG0_V2_EVENT << HCLGE_PTP_MSG0_SHIFT;
++		*ptp_cfg |= HCLGE_PTP_MSG_TYPE_V2 << HCLGE_PTP_MSG_TYPE_SHIFT;
++		rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
++		break;
++	case HWTSTAMP_FILTER_ALL:
++	default:
++		return -ERANGE;
++	}
++
++	cfg->rx_filter = rx_filter;
++
++	return 0;
++}
++
++static int hclge_ptp_set_ts_mode(struct hclge_dev *hdev,
++				 struct hwtstamp_config *cfg)
++{
++	unsigned long flags = hdev->ptp->flags;
++	u32 ptp_cfg = 0;
++	int ret;
++
++	if (test_bit(HCLGE_PTP_FLAG_EN, &hdev->ptp->flags))
++		ptp_cfg |= HCLGE_PTP_EN_B;
++
++	ret = hclge_ptp_set_tx_mode(cfg, &flags, &ptp_cfg);
++	if (ret)
++		return ret;
++
++	ret = hclge_ptp_set_rx_mode(cfg, &flags, &ptp_cfg);
++	if (ret)
++		return ret;
++
++	ret = hclge_ptp_cfg(hdev, ptp_cfg);
++	if (ret)
++		return ret;
++
++	hdev->ptp->flags = flags;
++	hdev->ptp->ptp_cfg = ptp_cfg;
++
++	return 0;
++}
++
++int hclge_ptp_set_cfg(struct hclge_dev *hdev, struct ifreq *ifr)
++{
++	struct hwtstamp_config cfg;
++	int ret;
++
++	if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state)) {
++		dev_err(&hdev->pdev->dev, "phc is unsupported\n");
++		return -EOPNOTSUPP;
++	}
++
++	if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
++		return -EFAULT;
++
++	ret = hclge_ptp_set_ts_mode(hdev, &cfg);
++	if (ret)
++		return ret;
++
++	hdev->ptp->ts_cfg = cfg;
++
++	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
++}
++
++int hclge_ptp_get_ts_info(struct hnae3_handle *handle,
++			  struct ethtool_ts_info *info)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_dev *hdev = vport->back;
++
++	if (!test_bit(HCLGE_STATE_PTP_EN, &hdev->state)) {
++		dev_err(&hdev->pdev->dev, "phc is unsupported\n");
++		return -EOPNOTSUPP;
++	}
++
++	info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
++				SOF_TIMESTAMPING_RX_SOFTWARE |
++				SOF_TIMESTAMPING_SOFTWARE |
++				SOF_TIMESTAMPING_TX_HARDWARE |
++				SOF_TIMESTAMPING_RX_HARDWARE |
++				SOF_TIMESTAMPING_RAW_HARDWARE;
++
++	if (hdev->ptp->clock)
++		info->phc_index = ptp_clock_index(hdev->ptp->clock);
++	else
++		info->phc_index = -1;
++
++	info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
++
++	info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
++			   BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
++			   BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
++			   BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ);
++
++	info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
++			    BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
++			    BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
++			    BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
++			    BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
++			    BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
++			    BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
++			    BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ);
++
++	return 0;
++}
++
++static int hclge_ptp_create_clock(struct hclge_dev *hdev)
++{
++#define HCLGE_PTP_NAME_LEN	32
++
++	struct hclge_ptp *ptp;
++
++	ptp = devm_kzalloc(&hdev->pdev->dev, sizeof(*ptp), GFP_KERNEL);
++	if (!ptp)
++		return -ENOMEM;
++
++	ptp->hdev = hdev;
++	snprintf(ptp->info.name, HCLGE_PTP_NAME_LEN, "%s",
++		 HCLGE_DRIVER_NAME);
++	ptp->info.owner = THIS_MODULE;
++	ptp->info.max_adj = HCLGE_PTP_CYCLE_ADJ_MAX;
++	ptp->info.n_ext_ts = 0;
++	ptp->info.pps = 0;
++	ptp->info.adjfreq = hclge_ptp_adjfreq;
++	ptp->info.adjtime = hclge_ptp_adjtime;
++	ptp->info.gettimex64 = hclge_ptp_gettimex;
++	ptp->info.settime64 = hclge_ptp_settime;
++
++	ptp->info.n_alarm = 0;
++	ptp->clock = ptp_clock_register(&ptp->info, &hdev->pdev->dev);
++	if (IS_ERR(ptp->clock)) {
++		dev_err(&hdev->pdev->dev,
++			"%d failed to register ptp clock, ret = %ld\n",
++			ptp->info.n_alarm, PTR_ERR(ptp->clock));
++		return -ENODEV;
++	} else if (!ptp->clock) {
++		dev_err(&hdev->pdev->dev, "failed to register ptp clock\n");
++		return -ENODEV;
++	}
++
++	spin_lock_init(&ptp->lock);
++	ptp->io_base = hdev->hw.io_base + HCLGE_PTP_REG_OFFSET;
++	ptp->ts_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
++	ptp->ts_cfg.tx_type = HWTSTAMP_TX_OFF;
++	hdev->ptp = ptp;
++
++	return 0;
++}
++
++static void hclge_ptp_destroy_clock(struct hclge_dev *hdev)
++{
++	ptp_clock_unregister(hdev->ptp->clock);
++	hdev->ptp->clock = NULL;
++	devm_kfree(&hdev->pdev->dev, hdev->ptp);
++	hdev->ptp = NULL;
++}
++
++int hclge_ptp_init(struct hclge_dev *hdev)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	struct timespec64 ts;
++	int ret;
++
++	if (!test_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps))
++		return 0;
++
++	if (!hdev->ptp) {
++		ret = hclge_ptp_create_clock(hdev);
++		if (ret)
++			return ret;
++	}
++
++	ret = hclge_ptp_int_en(hdev, true);
++	if (ret)
++		goto out;
++
++	set_bit(HCLGE_PTP_FLAG_EN, &hdev->ptp->flags);
++	ret = hclge_ptp_adjfreq(&hdev->ptp->info, 0);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to init freq, ret = %d\n", ret);
++		goto out;
++	}
++
++	ret = hclge_ptp_set_ts_mode(hdev, &hdev->ptp->ts_cfg);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to init ts mode, ret = %d\n", ret);
++		goto out;
++	}
++
++	ktime_get_real_ts64(&ts);
++	ret = hclge_ptp_settime(&hdev->ptp->info, &ts);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to init ts time, ret = %d\n", ret);
++		goto out;
++	}
++
++	set_bit(HCLGE_STATE_PTP_EN, &hdev->state);
++	dev_info(&hdev->pdev->dev, "phc initializes ok!\n");
++
++	return 0;
++
++out:
++	hclge_ptp_destroy_clock(hdev);
++
++	return ret;
++}
++
++void hclge_ptp_uninit(struct hclge_dev *hdev)
++{
++	struct hclge_ptp *ptp = hdev->ptp;
++
++	if (!ptp)
++		return;
++
++	hclge_ptp_int_en(hdev, false);
++	clear_bit(HCLGE_STATE_PTP_EN, &hdev->state);
++	clear_bit(HCLGE_PTP_FLAG_EN, &ptp->flags);
++	ptp->ts_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
++	ptp->ts_cfg.tx_type = HWTSTAMP_TX_OFF;
++
++	if (hclge_ptp_set_ts_mode(hdev, &ptp->ts_cfg))
++		dev_err(&hdev->pdev->dev, "failed to disable phc\n");
++
++	if (ptp->tx_skb) {
++		struct sk_buff *skb = ptp->tx_skb;
++
++		ptp->tx_skb = NULL;
++		dev_kfree_skb_any(skb);
++	}
++
++	hclge_ptp_destroy_clock(hdev);
++}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
+new file mode 100644
+index 000000000000..b3ca7afdaaa6
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
+@@ -0,0 +1,134 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++// Copyright (c) 2021 Hisilicon Limited.
++
++#ifndef __HCLGE_PTP_H
++#define __HCLGE_PTP_H
++
++#include <linux/ptp_clock_kernel.h>
++#include <linux/net_tstamp.h>
++#include <linux/types.h>
++
++#define HCLGE_PTP_REG_OFFSET	0x29000
++
++#define HCLGE_PTP_TX_TS_SEQID_REG	0x0
++#define HCLGE_PTP_TX_TS_NSEC_REG	0x4
++#define HCLGE_PTP_TX_TS_NSEC_MASK	GENMASK(29, 0)
++#define HCLGE_PTP_TX_TS_SEC_L_REG	0x8
++#define HCLGE_PTP_TX_TS_SEC_H_REG	0xC
++#define HCLGE_PTP_TX_TS_SEC_H_MASK	GENMASK(15, 0)
++#define HCLGE_PTP_TX_TS_CNT_REG		0x30
++
++#define HCLGE_PTP_TIME_SEC_H_REG	0x50
++#define HCLGE_PTP_TIME_SEC_H_MASK	GENMASK(15, 0)
++#define HCLGE_PTP_TIME_SEC_L_REG	0x54
++#define HCLGE_PTP_TIME_NSEC_REG		0x58
++#define HCLGE_PTP_TIME_NSEC_MASK	GENMASK(29, 0)
++#define HCLGE_PTP_TIME_NSEC_NEG		BIT(31)
++#define HCLGE_PTP_TIME_SYNC_REG		0x5C
++#define HCLGE_PTP_TIME_SYNC_EN		BIT(0)
++#define HCLGE_PTP_TIME_ADJ_REG		0x60
++#define HCLGE_PTP_TIME_ADJ_EN		BIT(0)
++#define HCLGE_PTP_CYCLE_QUO_REG		0x64
++#define HCLGE_PTP_CYCLE_DEN_REG		0x68
++#define HCLGE_PTP_CYCLE_NUM_REG		0x6C
++#define HCLGE_PTP_CYCLE_CFG_REG		0x70
++#define HCLGE_PTP_CYCLE_ADJ_EN		BIT(0)
++#define HCLGE_PTP_CUR_TIME_SEC_H_REG	0x74
++#define HCLGE_PTP_CUR_TIME_SEC_L_REG	0x78
++#define HCLGE_PTP_CUR_TIME_NSEC_REG	0x7C
++
++#define HCLGE_PTP_CYCLE_ADJ_BASE	2
++#define HCLGE_PTP_CYCLE_ADJ_MAX		500000000
++#define HCLGE_PTP_CYCLE_ADJ_UNIT	100000000
++#define HCLGE_PTP_SEC_H_OFFSET		32u
++#define HCLGE_PTP_SEC_L_MASK		GENMASK(31, 0)
++
++#define HCLGE_PTP_FLAG_EN		BIT(0)
++#define HCLGE_PTP_FLAG_TX_EN		BIT(1)
++#define HCLGE_PTP_FLAG_RX_EN		BIT(2)
++
++struct hclge_ptp {
++	struct hclge_dev *hdev;
++	struct ptp_clock *clock;
++	struct sk_buff *tx_skb;
++	unsigned long flags;
++	void __iomem *io_base;
++	struct ptp_clock_info info;
++	struct hwtstamp_config ts_cfg;
++	spinlock_t lock;	/* protects ptp registers */
++	u32 ptp_cfg;
++	u32 last_tx_seqid;
++	unsigned long tx_start;
++	unsigned long tx_cnt;
++	unsigned long tx_skipped;
++	unsigned long tx_cleaned;
++	unsigned long last_rx;
++	unsigned long rx_cnt;
++	unsigned long tx_timeout;
++};
++
++struct hclge_ptp_int_cmd {
++#define HCLGE_PTP_INT_EN_B	BIT(0)
++
++	u8 int_en;
++	u8 rsvd[23];
++};
++
++enum hclge_ptp_udp_type {
++	HCLGE_PTP_UDP_NOT_TYPE,
++	HCLGE_PTP_UDP_P13F_TYPE,
++	HCLGE_PTP_UDP_P140_TYPE,
++	HCLGE_PTP_UDP_FULL_TYPE,
++};
++
++enum hclge_ptp_msg_type {
++	HCLGE_PTP_MSG_TYPE_V2_L2,
++	HCLGE_PTP_MSG_TYPE_V2,
++	HCLGE_PTP_MSG_TYPE_V2_EVENT,
++};
++
++enum hclge_ptp_msg0_type {
++	HCLGE_PTP_MSG0_V2_DELAY_REQ = 1,
++	HCLGE_PTP_MSG0_V2_PDELAY_REQ,
++	HCLGE_PTP_MSG0_V2_DELAY_RESP,
++	HCLGE_PTP_MSG0_V2_EVENT = 0xF,
++};
++
++#define HCLGE_PTP_MSG1_V2_DEFAULT	1
++
++struct hclge_ptp_cfg_cmd {
++#define HCLGE_PTP_EN_B			BIT(0)
++#define HCLGE_PTP_TX_EN_B		BIT(1)
++#define HCLGE_PTP_RX_EN_B		BIT(2)
++#define HCLGE_PTP_UDP_EN_SHIFT		3
++#define HCLGE_PTP_UDP_EN_MASK		GENMASK(4, 3)
++#define HCLGE_PTP_MSG_TYPE_SHIFT	8
++#define HCLGE_PTP_MSG_TYPE_MASK		GENMASK(9, 8)
++#define HCLGE_PTP_MSG1_SHIFT		16
++#define HCLGE_PTP_MSG1_MASK		GENMASK(19, 16)
++#define HCLGE_PTP_MSG0_SHIFT		24
++#define HCLGE_PTP_MSG0_MASK		GENMASK(27, 24)
++
++	__le32 cfg;
++	u8 rsvd[20];
++};
++
++static inline struct hclge_dev *hclge_ptp_get_hdev(struct ptp_clock_info *info)
++{
++	struct hclge_ptp *ptp = container_of(info, struct hclge_ptp, info);
++
++	return ptp->hdev;
++}
++
++bool hclge_ptp_set_tx_info(struct hnae3_handle *handle, struct sk_buff *skb);
++void hclge_ptp_clean_tx_hwts(struct hclge_dev *dev);
++void hclge_ptp_get_rx_hwts(struct hnae3_handle *handle, struct sk_buff *skb,
++			   u32 nsec, u32 sec);
++int hclge_ptp_get_cfg(struct hclge_dev *hdev, struct ifreq *ifr);
++int hclge_ptp_set_cfg(struct hclge_dev *hdev, struct ifreq *ifr);
++int hclge_ptp_init(struct hclge_dev *hdev);
++void hclge_ptp_uninit(struct hclge_dev *hdev);
++int hclge_ptp_get_ts_info(struct hnae3_handle *handle,
++			  struct ethtool_ts_info *info);
++int hclge_ptp_cfg_qry(struct hclge_dev *hdev, u32 *cfg);
++#endif
+diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h
+index 51349d124ee5..cd0570c2b501 100644
+--- a/include/linux/ptp_clock_kernel.h
++++ b/include/linux/ptp_clock_kernel.h
+@@ -39,6 +39,15 @@ struct ptp_clock_request {
+ };
+ 
+ struct system_device_crosststamp;
++
++/**
++ * struct ptp_system_timestamp - system time corresponding to a PHC timestamp
++ */
++struct ptp_system_timestamp {
++	struct timespec64 pre_ts;
++	struct timespec64 post_ts;
++};
++
+ /**
+  * struct ptp_clock_info - decribes a PTP hardware clock
+  *
+@@ -123,6 +132,10 @@ struct ptp_clock_info {
+ 	int (*adjfine)(struct ptp_clock_info *ptp, long scaled_ppm);
+ 	int (*adjfreq)(struct ptp_clock_info *ptp, s32 delta);
+ 	int (*adjtime)(struct ptp_clock_info *ptp, s64 delta);
++#ifndef __GENKSYMS__
++	int (*gettimex64)(struct ptp_clock_info *ptp, struct timespec64 *ts,
++			  struct ptp_system_timestamp *sts);
++#endif
+ 	int (*gettime64)(struct ptp_clock_info *ptp, struct timespec64 *ts);
+ 	int (*getcrosststamp)(struct ptp_clock_info *ptp,
+ 			      struct system_device_crosststamp *cts);
+-- 
+2.34.1
+
diff --git a/patches/0445-net-hns3-fix-a-double-shift-bug.patch b/patches/0445-net-hns3-fix-a-double-shift-bug.patch
new file mode 100644
index 0000000..08086fc
--- /dev/null
+++ b/patches/0445-net-hns3-fix-a-double-shift-bug.patch
@@ -0,0 +1,56 @@
+From 0c48a7c9c98be4713a7bd1628773c2b8a09d56e9 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Sat, 24 Jul 2021 15:45:20 +0800
+Subject: [PATCH 084/283] net: hns3: fix a double shift bug
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 956c3ae411b2746c5018e0454909eb8c662b31ef
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=956c3ae411b2746c5018e0454909eb8c662b31ef
+
+----------------------------------------------------------------------
+
+These flags are used to set and test bits like this:
+
+	if (!test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) ||
+
+The issue is that test_bit() takes a bit number like 1, but we are
+passing BIT(1) instead and it's testing BIT(BIT(1)).  This does not
+cause a problem because it is always done consistently and the bit
+values are very small.
+
+Fixes: 0bf5eb788512 ("net: hns3: add support for PTP")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
+index b3ca7afdaaa6..5a202b775471 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
+@@ -43,9 +43,9 @@
+ #define HCLGE_PTP_SEC_H_OFFSET		32u
+ #define HCLGE_PTP_SEC_L_MASK		GENMASK(31, 0)
+ 
+-#define HCLGE_PTP_FLAG_EN		BIT(0)
+-#define HCLGE_PTP_FLAG_TX_EN		BIT(1)
+-#define HCLGE_PTP_FLAG_RX_EN		BIT(2)
++#define HCLGE_PTP_FLAG_EN		0
++#define HCLGE_PTP_FLAG_TX_EN		1
++#define HCLGE_PTP_FLAG_RX_EN		2
+ 
+ struct hclge_ptp {
+ 	struct hclge_dev *hdev;
+-- 
+2.34.1
+
diff --git a/patches/0446-net-hns3-minor-refactor-related-to-desc_cb-handling.patch b/patches/0446-net-hns3-minor-refactor-related-to-desc_cb-handling.patch
new file mode 100644
index 0000000..0343cc1
--- /dev/null
+++ b/patches/0446-net-hns3-minor-refactor-related-to-desc_cb-handling.patch
@@ -0,0 +1,180 @@
+From e5560ec3d352948a28a8f0e0c5f773421b429fe8 Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:21 +0800
+Subject: [PATCH 085/283] net: hns3: minor refactor related to desc_cb handling
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 26f1ccdf609a9fb087f49a3782fdc2ade23cde82
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=26f1ccdf609a9fb087f49a3782fdc2ade23cde82
+
+----------------------------------------------------------------------
+
+desc_cb is used to store mapping and freeing info for the
+corresponding desc, which is used in the cleaning process.
+There will be more desc_cb type coming up when supporting the
+tx bounce buffer, change desc_cb type to bit-wise value in order
+to reduce the desc_cb type checking operation in the data path.
+
+Also move the desc_cb type definition to hns3_enet.h because it
+is only used in hns3_enet.c, and declare a local variable desc_cb
+in hns3_clear_desc() to reduce lines of code.
+
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  7 ----
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 40 +++++++++----------
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  7 ++++
+ 3 files changed, 25 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 9e5a62a4f549..5c38c7a02912 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -152,13 +152,6 @@ enum HNAE3_PF_CAP_BITS {
+ #define ring_ptr_move_bw(ring, p) \
+ 	((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num)
+ 
+-enum hns_desc_type {
+-	DESC_TYPE_UNKNOWN,
+-	DESC_TYPE_SKB,
+-	DESC_TYPE_FRAGLIST_SKB,
+-	DESC_TYPE_PAGE,
+-};
+-
+ struct hnae3_handle;
+ 
+ struct hnae3_queue {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index ddf8644e9111..6f3465df40ca 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -1132,7 +1132,7 @@ static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
+ }
+ 
+ static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
+-			  unsigned int size, enum hns_desc_type type)
++			  unsigned int size, unsigned int type)
+ {
+ #define HNS3_LIKELY_BD_NUM	1
+ 
+@@ -1144,8 +1144,7 @@ static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
+ 	int k, sizeoflast;
+ 	dma_addr_t dma;
+ 
+-	if (type == DESC_TYPE_FRAGLIST_SKB ||
+-	    type == DESC_TYPE_SKB) {
++	if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
+ 		struct sk_buff *skb = (struct sk_buff *)priv;
+ 
+ 		dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
+@@ -1411,6 +1410,7 @@ static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
+ 
+ 	for (i = 0; i < ring->desc_num; i++) {
+ 		struct hns3_desc *desc = &ring->desc[ring->next_to_use];
++		struct hns3_desc_cb *desc_cb;
+ 
+ 		memset(desc, 0, sizeof(*desc));
+ 
+@@ -1421,31 +1421,27 @@ static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
+ 		/* rollback one */
+ 		ring_ptr_move_bw(ring, next_to_use);
+ 
+-		if (!ring->desc_cb[ring->next_to_use].dma)
++		desc_cb = &ring->desc_cb[ring->next_to_use];
++
++		if (!desc_cb->dma)
+ 			continue;
+ 
+ 		/* unmap the descriptor dma address */
+-		if (ring->desc_cb[ring->next_to_use].type == DESC_TYPE_SKB ||
+-		    ring->desc_cb[ring->next_to_use].type ==
+-		    DESC_TYPE_FRAGLIST_SKB)
+-			dma_unmap_single(dev,
+-					 ring->desc_cb[ring->next_to_use].dma,
+-					ring->desc_cb[ring->next_to_use].length,
+-					DMA_TO_DEVICE);
+-		else if (ring->desc_cb[ring->next_to_use].length)
+-			dma_unmap_page(dev,
+-				       ring->desc_cb[ring->next_to_use].dma,
+-				       ring->desc_cb[ring->next_to_use].length,
++		if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
++			dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
++					 DMA_TO_DEVICE);
++		else if (desc_cb->length)
++			dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
+ 				       DMA_TO_DEVICE);
+ 
+-		ring->desc_cb[ring->next_to_use].length = 0;
+-		ring->desc_cb[ring->next_to_use].dma = 0;
+-		ring->desc_cb[ring->next_to_use].type = DESC_TYPE_UNKNOWN;
++		desc_cb->length = 0;
++		desc_cb->dma = 0;
++		desc_cb->type = DESC_TYPE_UNKNOWN;
+ 	}
+ }
+ 
+ static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
+-				 struct sk_buff *skb, enum hns_desc_type type)
++				 struct sk_buff *skb, unsigned int type)
+ {
+ 	unsigned int size = skb_headlen(skb);
+ 	struct sk_buff *frag_skb;
+@@ -2547,7 +2543,7 @@ static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
+ static void hns3_free_buffer(struct hns3_enet_ring *ring,
+ 			     struct hns3_desc_cb *cb, int budget)
+ {
+-	if (cb->type == DESC_TYPE_SKB)
++	if (cb->type & DESC_TYPE_SKB)
+ 		napi_consume_skb(cb->priv, budget);
+ 	else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias)
+ 		__page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
+@@ -2568,7 +2564,7 @@ static int hns3_map_buffer(struct hns3_enet_ring *ring, struct hns3_desc_cb *cb)
+ static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
+ 			      struct hns3_desc_cb *cb)
+ {
+-	if (cb->type == DESC_TYPE_SKB || cb->type == DESC_TYPE_FRAGLIST_SKB)
++	if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
+ 		dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
+ 				 ring_to_dma_dir(ring));
+ 	else if (cb->length)
+@@ -2724,7 +2720,7 @@ static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
+ 
+ 		desc_cb = &ring->desc_cb[ntc];
+ 
+-		if (desc_cb->type == DESC_TYPE_SKB) {
++		if (desc_cb->type & DESC_TYPE_SKB) {
+ 			(*pkts)++;
+ 			(*bytes) += desc_cb->send_bytes;
+ 		}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 70662c84cb57..4b035c458a58 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -297,6 +297,13 @@ struct __packed hns3_desc {
+ 	};
+ };
+ 
++enum hns3_desc_type {
++	DESC_TYPE_UNKNOWN		= 0,
++	DESC_TYPE_SKB			= 1 << 0,
++	DESC_TYPE_FRAGLIST_SKB		= 1 << 1,
++	DESC_TYPE_PAGE			= 1 << 2,
++};
++
+ struct hns3_desc_cb {
+ 	dma_addr_t dma; /* dma address of this desc */
+ 	void *buf;      /* cpu addr for a desc */
+-- 
+2.34.1
+
diff --git a/patches/0447-net-hns3-refactor-for-hns3_fill_desc-function.patch b/patches/0447-net-hns3-refactor-for-hns3_fill_desc-function.patch
new file mode 100644
index 0000000..a147288
--- /dev/null
+++ b/patches/0447-net-hns3-refactor-for-hns3_fill_desc-function.patch
@@ -0,0 +1,159 @@
+From c142070dd4b17fc1d4a60214f12d6300c6d5fb94 Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:22 +0800
+Subject: [PATCH 086/283] net: hns3: refactor for hns3_fill_desc() function
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 8677d78c3d860c156ccd335e2b97728298c2cbb1
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8677d78c3d860c156ccd335e2b97728298c2cbb1
+
+----------------------------------------------------------------------
+
+Factor out hns3_fill_desc() so that it can be reused in the
+tx bounce supporting.
+
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 87 ++++++++++---------
+ 1 file changed, 48 insertions(+), 39 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 6f3465df40ca..3ca646e15345 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -1131,39 +1131,14 @@ static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
+ 	return 0;
+ }
+ 
+-static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
+-			  unsigned int size, unsigned int type)
++static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
++			  unsigned int size)
+ {
+ #define HNS3_LIKELY_BD_NUM	1
+ 
+-	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
+ 	struct hns3_desc *desc = &ring->desc[ring->next_to_use];
+-	struct device *dev = ring_to_dev(ring);
+-	struct skb_frag_struct *frag;
+ 	unsigned int frag_buf_num;
+ 	int k, sizeoflast;
+-	dma_addr_t dma;
+-
+-	if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
+-		struct sk_buff *skb = (struct sk_buff *)priv;
+-
+-		dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
+-	} else {
+-		frag = (struct skb_frag_struct *)priv;
+-		dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
+-	}
+-
+-	if (unlikely(dma_mapping_error(dev, dma))) {
+-		u64_stats_update_begin(&ring->syncp);
+-		ring->stats.sw_err_cnt++;
+-		u64_stats_update_end(&ring->syncp);
+-		return -ENOMEM;
+-	}
+-
+-	desc_cb->priv = priv;
+-	desc_cb->length = size;
+-	desc_cb->dma = dma;
+-	desc_cb->type = type;
+ 
+ 	if (likely(size <= HNS3_MAX_BD_SIZE)) {
+ 		desc->addr = cpu_to_le64(dma);
+@@ -1199,6 +1174,47 @@ static int hns3_fill_desc(struct hns3_enet_ring *ring, void *priv,
+ 	return frag_buf_num;
+ }
+ 
++static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
++				  unsigned int type)
++{
++	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
++	struct device *dev = ring_to_dev(ring);
++	unsigned int size;
++	dma_addr_t dma;
++
++	if (type & (DESC_TYPE_FRAGLIST_SKB | DESC_TYPE_SKB)) {
++		struct sk_buff *skb = (struct sk_buff *)priv;
++
++		size = skb_headlen(skb);
++		if (!size)
++			return 0;
++
++		dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
++	} else {
++		struct skb_frag_struct *frag = (struct skb_frag_struct *)priv;
++
++		size = skb_frag_size(frag);
++		if (!size)
++			return 0;
++
++		dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
++	}
++
++	if (unlikely(dma_mapping_error(dev, dma))) {
++		u64_stats_update_begin(&ring->syncp);
++		ring->stats.sw_err_cnt++;
++		u64_stats_update_end(&ring->syncp);
++		return -ENOMEM;
++	}
++
++	desc_cb->priv = priv;
++	desc_cb->length = size;
++	desc_cb->dma = dma;
++	desc_cb->type = type;
++
++	return hns3_fill_desc(ring, dma, size);
++}
++
+ static unsigned int hns3_skb_bd_num(struct sk_buff *skb, unsigned int *bd_size,
+ 				    unsigned int bd_num)
+ {
+@@ -1443,26 +1459,19 @@ static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
+ static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
+ 				 struct sk_buff *skb, unsigned int type)
+ {
+-	unsigned int size = skb_headlen(skb);
+ 	struct sk_buff *frag_skb;
+ 	int i, ret, bd_num = 0;
+ 
+-	if (size) {
+-		ret = hns3_fill_desc(ring, skb, size, type);
+-		if (unlikely(ret < 0))
+-			return ret;
++	ret = hns3_map_and_fill_desc(ring, skb, type);
++	if (unlikely(ret < 0))
++		return ret;
+ 
+-		bd_num += ret;
+-	}
++	bd_num += ret;
+ 
+ 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+ 		struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
+ 
+-		size = skb_frag_size(frag);
+-		if (!size)
+-			continue;
+-
+-		ret = hns3_fill_desc(ring, frag, size, DESC_TYPE_PAGE);
++		ret = hns3_map_and_fill_desc(ring, frag, DESC_TYPE_PAGE);
+ 		if (unlikely(ret < 0))
+ 			return ret;
+ 
+-- 
+2.34.1
+
diff --git a/patches/0448-net-hns3-add-priv-flags-support-to-switch-limit-prom.patch b/patches/0448-net-hns3-add-priv-flags-support-to-switch-limit-prom.patch
new file mode 100644
index 0000000..d954550
--- /dev/null
+++ b/patches/0448-net-hns3-add-priv-flags-support-to-switch-limit-prom.patch
@@ -0,0 +1,382 @@
+From f4b6431fab7c7162824b541cb194b476e5f7bfe6 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Sun, 6 Dec 2020 12:06:14 +0800
+Subject: [PATCH 087/283] net: hns3: add priv flags support to switch limit
+ promisc mode
+
+mainline inclusion
+from mainline-v5.11-rc1
+commit 5e7414cdf1abea7e2fc19a3190aa7b0d0b1e629d
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5e7414cdf1abea7e2fc19a3190aa7b0d0b1e629d
+
+--------------------------------
+
+Currently, the tx unicast promisc is always enabled when promisc
+mode on. If tx unicast promisc on, a function will receive all
+unicast packet from other functions belong to the same port.
+Add a ethtool private flag to control whether enable tx
+unicast promisc. Then the function is able to filter the
+unknown unicast packets from other function.
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+---
+ .../net/ethernet/hisilicon/hns3/hclge_mbx.h   |  1 +
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   | 10 +++
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  3 +
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 86 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         | 17 ++--
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 10 +--
+ .../hisilicon/hns3/hns3pf/hclge_mbx.c         |  6 ++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |  7 ++
+ 8 files changed, 127 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
+index bfd6f19aa65a..5a13eea2742d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
+@@ -122,6 +122,7 @@ struct hclge_vf_to_pf_msg {
+ 			u8 en_bc;
+ 			u8 en_uc;
+ 			u8 en_mc;
++			u8 en_limit_promisc;
+ 		};
+ 		struct {
+ 			u8 vector_id;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 5c38c7a02912..738baccf5a8a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -853,6 +853,11 @@ struct hnae3_unic_private_info {
+ #define HNAE3_MPE		(HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE)
+ #define HNAE3_OVERFLOW_UMPE	(HNAE3_OVERFLOW_UPE | HNAE3_OVERFLOW_MPE)
+ 
++enum hnae3_pflag {
++	HNAE3_PFLAG_LIMIT_PROMISC,
++	HNAE3_PFLAG_MAX
++};
++
+ struct hnae3_handle {
+ 	struct hnae3_client *client;
+ 	struct pci_dev *pdev;
+@@ -885,6 +890,11 @@ struct hnae3_handle {
+ 	/* for sysfs */
+ 	struct kobject *kobj;
+ #endif
++
++#ifndef __GENKSYMS__
++	unsigned long supported_pflags;
++	unsigned long priv_flags;
++#endif
+ };
+ 
+ #define hnae3_set_field(origin, mask, shift, val) \
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 3ca646e15345..7600a2e4a645 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -4371,6 +4371,9 @@ static int hns3_client_init(struct hnae3_handle *handle)
+ 
+ 	set_bit(HNS3_NIC_STATE_INITED, &priv->state);
+ 
++	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
++		set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
++
+ 	ret = register_netdev(netdev);
+ 	if (ret) {
+ 		dev_err(priv->dev, "probe register netdev fail!\n");
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index c42c6163ac80..ae22adfe5740 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -22,6 +22,11 @@ struct hns3_sfp_type {
+ 	u8 ext_type;
+ };
+ 
++struct hns3_pflag_desc {
++	char name[ETH_GSTRING_LEN];
++	void (*handler)(struct net_device *netdev, bool enable);
++};
++
+ /* tqp related stats */
+ #define HNS3_TQP_STAT(_string, _member)	{			\
+ 	.stats_string = _string,				\
+@@ -65,6 +70,8 @@ static const struct hns3_stats hns3_rxq_stats[] = {
+ 	HNS3_TQP_STAT("non_reuse_pg", non_reuse_pg),
+ };
+ 
++#define HNS3_PRIV_FLAGS_LEN ARRAY_SIZE(hns3_priv_flags)
++
+ #define HNS3_RXQ_STATS_COUNT ARRAY_SIZE(hns3_rxq_stats)
+ 
+ #define HNS3_TQP_STATS_COUNT (HNS3_TXQ_STATS_COUNT + HNS3_RXQ_STATS_COUNT)
+@@ -408,6 +415,23 @@ static void hns3_self_test(struct net_device *ndev,
+ 		netdev_info(ndev, "self test end\n");
+ }
+ 
++static void hns3_update_limit_promisc_mode(struct net_device *netdev,
++					   bool enable)
++{
++	struct hnae3_handle *handle = hns3_get_handle(netdev);
++
++	if (enable)
++		set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags);
++	else
++		clear_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags);
++
++	hns3_request_update_promisc_mode(handle);
++}
++
++static const struct hns3_pflag_desc hns3_priv_flags[HNAE3_PFLAG_MAX] = {
++	{ "limit_promisc",	hns3_update_limit_promisc_mode }
++};
++
+ static int hns3_get_sset_count(struct net_device *netdev, int stringset)
+ {
+ 	struct hnae3_handle *h = hns3_get_handle(netdev);
+@@ -424,6 +448,9 @@ static int hns3_get_sset_count(struct net_device *netdev, int stringset)
+ 	case ETH_SS_TEST:
+ 		return ops->get_sset_count(h, stringset);
+ 
++	case ETH_SS_PRIV_FLAGS:
++		return HNAE3_PFLAG_MAX;
++
+ 	default:
+ 		return -EOPNOTSUPP;
+ 	}
+@@ -477,6 +504,7 @@ static void hns3_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
+ 	struct hnae3_handle *h = hns3_get_handle(netdev);
+ 	const struct hnae3_ae_ops *ops = h->ae_algo->ops;
+ 	char *buff = (char *)data;
++	int i;
+ 
+ 	if (!ops->get_strings)
+ 		return;
+@@ -489,6 +517,13 @@ static void hns3_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
+ 	case ETH_SS_TEST:
+ 		ops->get_strings(h, stringset, data);
+ 		break;
++	case ETH_SS_PRIV_FLAGS:
++		for (i = 0; i < HNS3_PRIV_FLAGS_LEN; i++) {
++			snprintf(buff, ETH_GSTRING_LEN, "%s",
++				 hns3_priv_flags[i].name);
++			buff += ETH_GSTRING_LEN;
++		}
++		break;
+ 	default:
+ 		break;
+ 	}
+@@ -1522,6 +1557,53 @@ static int hns3_get_module_eeprom(struct net_device *netdev,
+ 	return ops->get_module_eeprom(handle, ee->offset, ee->len, data);
+ }
+ 
++static u32 hns3_get_priv_flags(struct net_device *netdev)
++{
++	struct hnae3_handle *handle = hns3_get_handle(netdev);
++
++	return handle->priv_flags;
++}
++
++static int hns3_check_priv_flags(struct hnae3_handle *h, u32 changed)
++{
++	u32 i;
++
++	for (i = 0; i < HNAE3_PFLAG_MAX; i++)
++		if ((changed & BIT(i)) && !test_bit(i, &h->supported_pflags)) {
++			netdev_err(h->netdev, "%s is unsupported\n",
++				   hns3_priv_flags[i].name);
++			return -EOPNOTSUPP;
++		}
++
++	return 0;
++}
++
++static int hns3_set_priv_flags(struct net_device *netdev, u32 pflags)
++{
++	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	u32 changed = pflags ^ handle->priv_flags;
++	int ret;
++	u32 i;
++
++	ret = hns3_check_priv_flags(handle, changed);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < HNAE3_PFLAG_MAX; i++) {
++		if (changed & BIT(i)) {
++			bool enable = !(handle->priv_flags & BIT(i));
++
++			if (enable)
++				handle->priv_flags |= BIT(i);
++			else
++				handle->priv_flags &= ~BIT(i);
++			hns3_priv_flags[i].handler(netdev, enable);
++		}
++	}
++
++	return 0;
++}
++
+ #define HNS3_ETHTOOL_COALESCE	(ETHTOOL_COALESCE_USECS |		\
+ 				 ETHTOOL_COALESCE_USE_ADAPTIVE |	\
+ 				 ETHTOOL_COALESCE_RX_USECS_HIGH |	\
+@@ -1563,6 +1645,8 @@ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ 	.get_link = hns3_get_link,
+ 	.get_msglevel = hns3_get_msglevel,
+ 	.set_msglevel = hns3_set_msglevel,
++	.get_priv_flags = hns3_get_priv_flags,
++	.set_priv_flags = hns3_set_priv_flags,
+ };
+ 
+ static const struct ethtool_ops hns3_ethtool_ops = {
+@@ -1599,6 +1683,8 @@ static const struct ethtool_ops hns3_ethtool_ops = {
+ 	.set_fecparam = hns3_set_fecparam,
+ 	.get_module_info = hns3_get_module_info,
+ 	.get_module_eeprom = hns3_get_module_eeprom,
++	.get_priv_flags = hns3_get_priv_flags,
++	.set_priv_flags = hns3_set_priv_flags,
+ 	.get_ts_info = hns3_get_ts_info,
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 4d89efaf4aed..ba10e18ddb7e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -599,23 +599,24 @@ struct hclge_link_status_cmd {
+ 	u8 rsv[23];
+ };
+ 
++#define HCLGE_PROMISC_TX_EN_B	BIT(4)
++#define HCLGE_PROMISC_RX_EN_B	BIT(5)
++#define HCLGE_PROMISC_EN_B	1
++#define HCLGE_PROMISC_EN_ALL   0x7
++#define HCLGE_PROMISC_EN_UC    0x1
++#define HCLGE_PROMISC_EN_MC    0x2
++#define HCLGE_PROMISC_EN_BC    0x4
++
+ struct hclge_promisc_param {
+ 	u8 vf_id;
+ 	u8 enable;
+ };
+ 
+-#define HCLGE_PROMISC_TX_EN_B	BIT(4)
+-#define HCLGE_PROMISC_RX_EN_B	BIT(5)
+-#define HCLGE_PROMISC_EN_B	1
+-#define HCLGE_PROMISC_EN_ALL	0x7
+-#define HCLGE_PROMISC_EN_UC	0x1
+-#define HCLGE_PROMISC_EN_MC	0x2
+-#define HCLGE_PROMISC_EN_BC	0x4
+ struct hclge_promisc_cfg_cmd {
+ 	u8 flag;
+ 	u8 vf_id;
+ 	__le16 rsv0;
+-	u8 rsv1[20];
++	u8 rsv1[21];
+ };
+ 
+ enum hclge_promisc_type {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index d4db7a84f279..d46a1d31c701 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -5109,20 +5109,20 @@ static int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
+ 	 * send command to fireware in revision(0x20).
+ 	 */
+ 	req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
+-		HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
++		    HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret)
+ 		dev_err(&hdev->pdev->dev,
+-			"Set vport %d promisc mode fail, ret = %d.\n",
+-			param->vf_id, ret);
++		       "failed to set vport %d promisc mode, ret = %d.\n",
++		       param->vf_id, ret);
+ 
+ 	return ret;
+ }
+ 
+ static void hclge_promisc_param_init(struct hclge_promisc_param *param,
+-				     bool en_uc, bool en_mc, bool en_bc,
+-				     int vport_id)
++				    bool en_uc, bool en_mc, bool en_bc,
++				    int vport_id)
+ {
+ 	if (!param)
+ 		return;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+index 841c9b0c9fe4..a9dd7d0601ab 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+@@ -327,11 +327,17 @@ static void hclge_set_vf_promisc_mode(struct hclge_vport *vport,
+ 				      struct hclge_mbx_vf_to_pf_cmd *req)
+ {
+ 	struct hclge_dev *hdev = vport->back;
++	struct hnae3_handle *handle = &vport->nic;
+ 
+ 	vport->vf_info.request_uc_en = req->msg.en_uc;
+ 	vport->vf_info.request_mc_en = req->msg.en_mc;
+ 	vport->vf_info.request_bc_en = req->msg.en_bc;
+ 
++	if (req->msg.en_limit_promisc)
++		set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags);
++	else
++		clear_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->priv_flags);
++
+ 	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
+ 	hclge_task_schedule(hdev, 0);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index db292ca270b8..d58b4e4780a8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -15,6 +15,9 @@
+ #define HCLGEVF_RESET_MAX_FAIL_CNT	5
+ 
+ static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
++static void hclgevf_task_schedule(struct hclgevf_dev *hdev,
++				  unsigned long delay);
++
+ static struct hnae3_ae_algo ae_algovf;
+ 
+ static struct workqueue_struct *hclgevf_wq;
+@@ -1177,6 +1180,7 @@ static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
+ 					bool en_uc_pmc, bool en_mc_pmc,
+ 					bool en_bc_pmc)
+ {
++	struct hnae3_handle *handle = &hdev->nic;
+ 	struct hclge_vf_to_pf_msg send_msg;
+ 	int ret;
+ 
+@@ -1185,6 +1189,8 @@ static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
+ 	send_msg.en_bc = en_bc_pmc ? 1 : 0;
+ 	send_msg.en_uc = en_uc_pmc ? 1 : 0;
+ 	send_msg.en_mc = en_mc_pmc ? 1 : 0;
++	send_msg.en_limit_promisc = test_bit(HNAE3_PFLAG_LIMIT_PROMISC,
++					     &handle->priv_flags) ? 1 : 0;
+ 
+ 	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
+ 	if (ret)
+@@ -1211,6 +1217,7 @@ static void hclgevf_request_update_promisc_mode(struct hnae3_handle *handle)
+ 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
+ 
+ 	set_bit(HCLGEVF_STATE_PROMISC_CHANGED, &hdev->state);
++	hclgevf_task_schedule(hdev, 0);
+ }
+ 
+ static void hclgevf_sync_promisc_mode(struct hclgevf_dev *hdev)
+-- 
+2.34.1
+
diff --git a/patches/0449-net-hns3-use-tx-bounce-buffer-for-small-packets.patch b/patches/0449-net-hns3-use-tx-bounce-buffer-for-small-packets.patch
new file mode 100644
index 0000000..e6b5905
--- /dev/null
+++ b/patches/0449-net-hns3-use-tx-bounce-buffer-for-small-packets.patch
@@ -0,0 +1,719 @@
+From 576d5899a183853648fdf5e9bfd9fd50951153b9 Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:23 +0800
+Subject: [PATCH 088/283] net: hns3: use tx bounce buffer for small packets
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 907676b130711fd1f627824559e92259db2061d1
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=907676b130711fd1f627824559e92259db2061d1
+
+----------------------------------------------------------------------
+
+when the packet or frag size is small, it causes both security and
+performance issue. As dma can't map sub-page, this means some extra
+kernel data is visible to devices. On the other hand, the overhead
+of dma map and unmap is huge when IOMMU is on.
+
+So add a queue based tx shared bounce buffer to memcpy the small
+packet when the len of the xmitted skb is below tx_copybreak.
+Add tx_spare_buf_size module param to set the size of tx spare
+buffer, and add set/get_tunable to set or query the tx_copybreak.
+
+The throughtput improves from 30 Gbps to 90+ Gbps when running 16
+netperf threads with 32KB UDP message size when IOMMU is in the
+strict mode(tx_copybreak = 2000 and mtu = 1500).
+
+Suggested-by: Barry Song <song.bao.hua@hisilicon.com>
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    |  54 +++-
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 294 +++++++++++++++++-
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  43 ++-
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  51 +++
+ 4 files changed, 423 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index ad7015b3ec80..6b2179516fff 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -385,6 +385,56 @@ static void hns3_dbg_fill_content(char *content, u16 len,
+ 	*pos++ = '\0';
+ }
+ 
++static const struct hns3_dbg_item tx_spare_info_items[] = {
++	{ "QUEUE_ID", 2 },
++	{ "COPYBREAK", 2 },
++	{ "LEN", 7 },
++	{ "NTU", 4 },
++	{ "NTC", 4 },
++	{ "LTC", 4 },
++	{ "DMA", 17 },
++};
++
++static void hns3_dbg_tx_spare_info(struct hns3_enet_ring *ring, char *buf,
++				   int len, u32 ring_num, int *pos)
++{
++	char data_str[ARRAY_SIZE(tx_spare_info_items)][HNS3_DBG_DATA_STR_LEN];
++	struct hns3_tx_spare *tx_spare = ring->tx_spare;
++	char *result[ARRAY_SIZE(tx_spare_info_items)];
++	char content[HNS3_DBG_INFO_LEN];
++	u32 i, j;
++
++	if (!tx_spare) {
++		*pos += scnprintf(buf + *pos, len - *pos,
++				  "tx spare buffer is not enabled\n");
++		return;
++	}
++
++	for (i = 0; i < ARRAY_SIZE(tx_spare_info_items); i++)
++		result[i] = &data_str[i][0];
++
++	*pos += scnprintf(buf + *pos, len - *pos, "tx spare buffer info\n");
++	hns3_dbg_fill_content(content, sizeof(content), tx_spare_info_items,
++			      NULL, ARRAY_SIZE(tx_spare_info_items));
++	*pos += scnprintf(buf + *pos, len - *pos, "%s", content);
++
++	for (i = 0; i < ring_num; i++) {
++		j = 0;
++		sprintf(result[j++], "%8u", i);
++		sprintf(result[j++], "%9u", ring->tx_copybreak);
++		sprintf(result[j++], "%3u", tx_spare->len);
++		sprintf(result[j++], "%3u", tx_spare->next_to_use);
++		sprintf(result[j++], "%3u", tx_spare->next_to_clean);
++		sprintf(result[j++], "%3u", tx_spare->last_to_clean);
++		sprintf(result[j++], "%pad", &tx_spare->dma);
++		hns3_dbg_fill_content(content, sizeof(content),
++				      tx_spare_info_items,
++				      (const char **)result,
++				      ARRAY_SIZE(tx_spare_info_items));
++		*pos += scnprintf(buf + *pos, len - *pos, "%s", content);
++	}
++}
++
+ static const struct hns3_dbg_item rx_queue_info_items[] = {
+ 	{ "QUEUE_ID", 2 },
+ 	{ "BD_NUM", 2 },
+@@ -544,7 +594,7 @@ static int hns3_dbg_tx_queue_info(struct hnae3_handle *h,
+ 	char *result[ARRAY_SIZE(tx_queue_info_items)];
+ 	struct hns3_nic_priv *priv = h->priv;
+ 	char content[HNS3_DBG_INFO_LEN];
+-	struct hns3_enet_ring *ring;
++	struct hns3_enet_ring *ring = NULL;
+ 	int pos = 0;
+ 	u32 i;
+ 
+@@ -578,6 +628,8 @@ static int hns3_dbg_tx_queue_info(struct hnae3_handle *h,
+ 		pos += scnprintf(buf + pos, len - pos, "%s", content);
+ 	}
+ 
++	hns3_dbg_tx_spare_info(ring, buf, len, h->kinfo.num_tqps, &pos);
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 7600a2e4a645..fd800aa35f3e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -52,6 +52,10 @@ static int debug = -1;
+ module_param(debug, int, 0);
+ MODULE_PARM_DESC(debug, " Network interface message level setting");
+ 
++static unsigned int tx_spare_buf_size;
++module_param(tx_spare_buf_size, uint, 0400);
++MODULE_PARM_DESC(tx_spare_buf_size, "Size used to allocate tx spare buffer");
++
+ #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
+ 			   NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
+ 
+@@ -645,7 +649,178 @@ void hns3_request_update_promisc_mode(struct hnae3_handle *handle)
+ 		ops->request_update_promisc_mode(handle);
+ }
+ 
+-static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
++static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
++{
++	struct hns3_tx_spare *tx_spare = ring->tx_spare;
++	u32 ntc, ntu;
++
++	/* This smp_load_acquire() pairs with smp_store_release() in
++	 * hns3_tx_spare_update() called in tx desc cleaning process.
++	 */
++	ntc = smp_load_acquire(&tx_spare->last_to_clean);
++	ntu = tx_spare->next_to_use;
++
++	if (ntc > ntu)
++		return ntc - ntu - 1;
++
++	/* The free tx buffer is divided into two part, so pick the
++	 * larger one.
++	 */
++	return (ntc > (tx_spare->len - ntu) ? ntc :
++			(tx_spare->len - ntu)) - 1;
++}
++
++static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
++{
++	struct hns3_tx_spare *tx_spare = ring->tx_spare;
++
++	if (!tx_spare ||
++	    tx_spare->last_to_clean == tx_spare->next_to_clean)
++		return;
++
++	/* This smp_store_release() pairs with smp_load_acquire() in
++	 * hns3_tx_spare_space() called in xmit process.
++	 */
++	smp_store_release(&tx_spare->last_to_clean,
++			  tx_spare->next_to_clean);
++}
++
++static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
++				   struct sk_buff *skb,
++				   u32 space)
++{
++	u32 len = skb->len <= ring->tx_copybreak ? skb->len :
++				skb_headlen(skb);
++
++	if (len > ring->tx_copybreak)
++		return false;
++
++	if (ALIGN(len, dma_get_cache_alignment()) > space) {
++		u64_stats_update_begin(&ring->syncp);
++		ring->stats.tx_spare_full++;
++		u64_stats_update_end(&ring->syncp);
++		return false;
++	}
++
++	return true;
++}
++
++static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
++{
++	struct hns3_tx_spare *tx_spare;
++	struct page *page;
++	dma_addr_t dma;
++	int order;
++
++	if (!tx_spare_buf_size)
++		return;
++
++	order = get_order(tx_spare_buf_size);
++	tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
++				GFP_KERNEL);
++	if (!tx_spare) {
++		/* The driver still work without the tx spare buffer */
++		dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
++		return;
++	}
++
++	page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
++				GFP_KERNEL, order);
++	if (!page) {
++		dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
++		devm_kfree(ring_to_dev(ring), tx_spare);
++		return;
++	}
++
++	dma = dma_map_page(ring_to_dev(ring), page, 0,
++			   PAGE_SIZE << order, DMA_TO_DEVICE);
++	if (dma_mapping_error(ring_to_dev(ring), dma)) {
++		dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
++		put_page(page);
++		devm_kfree(ring_to_dev(ring), tx_spare);
++		return;
++	}
++
++	tx_spare->dma = dma;
++	tx_spare->buf = page_address(page);
++	tx_spare->len = PAGE_SIZE << order;
++	ring->tx_spare = tx_spare;
++}
++
++/* Use hns3_tx_spare_space() to make sure there is enough buffer
++ * before calling below function to allocate tx buffer.
++ */
++static void *hns3_tx_spare_alloc(struct hns3_enet_ring *ring,
++				 unsigned int size, dma_addr_t *dma,
++				 u32 *cb_len)
++{
++	struct hns3_tx_spare *tx_spare = ring->tx_spare;
++	u32 ntu = tx_spare->next_to_use;
++
++	size = ALIGN(size, dma_get_cache_alignment());
++	*cb_len = size;
++
++	/* Tx spare buffer wraps back here because the end of
++	 * freed tx buffer is not enough.
++	 */
++	if (ntu + size > tx_spare->len) {
++		*cb_len += (tx_spare->len - ntu);
++		ntu = 0;
++	}
++
++	tx_spare->next_to_use = ntu + size;
++	if (tx_spare->next_to_use == tx_spare->len)
++		tx_spare->next_to_use = 0;
++
++	*dma = tx_spare->dma + ntu;
++
++	return tx_spare->buf + ntu;
++}
++
++static void hns3_tx_spare_rollback(struct hns3_enet_ring *ring, u32 len)
++{
++	struct hns3_tx_spare *tx_spare = ring->tx_spare;
++
++	if (len > tx_spare->next_to_use) {
++		len -= tx_spare->next_to_use;
++		tx_spare->next_to_use = tx_spare->len - len;
++	} else {
++		tx_spare->next_to_use -= len;
++	}
++}
++
++static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
++				     struct hns3_desc_cb *cb)
++{
++	struct hns3_tx_spare *tx_spare = ring->tx_spare;
++	u32 ntc = tx_spare->next_to_clean;
++	u32 len = cb->length;
++
++	tx_spare->next_to_clean += len;
++
++	if (tx_spare->next_to_clean >= tx_spare->len) {
++		tx_spare->next_to_clean -= tx_spare->len;
++
++		if (tx_spare->next_to_clean) {
++			ntc = 0;
++			len = tx_spare->next_to_clean;
++		}
++	}
++
++	/* This tx spare buffer is only really reclaimed after calling
++	 * hns3_tx_spare_update(), so it is still safe to use the info in
++	 * the tx buffer to do the dma sync after tx_spare->next_to_clean
++	 * is moved forword.
++	 */
++	if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
++		dma_addr_t dma = tx_spare->dma + ntc;
++
++		dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
++					DMA_TO_DEVICE);
++	}
++}
++
++static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
+ 			u16 *mss, u32 *type_cs_vlan_tso, u32 *send_bytes)
+ {
+ 	u32 l4_offset, hdr_len;
+@@ -719,7 +894,7 @@ static int hns3_set_tso(struct sk_buff *skb, u32 *paylen,
+ 	*send_bytes = (skb_shinfo(skb)->gso_segs - 1) * hdr_len + skb->len;
+ 
+ 	/* find the txbd field values */
+-	*paylen = skb->len - hdr_len;
++	*paylen_fdop_ol4cs = skb->len - hdr_len;
+ 	hns3_set_field(*type_cs_vlan_tso, HNS3_TXD_TSO_B, 1);
+ 
+ 	/* get MSS for TSO */
+@@ -1190,6 +1365,11 @@ static int hns3_map_and_fill_desc(struct hns3_enet_ring *ring, void *priv,
+ 			return 0;
+ 
+ 		dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
++	} else if (type & DESC_TYPE_BOUNCE_HEAD) {
++		/* Head data has been filled in hns3_handle_tx_bounce(),
++		 * just return 0 here.
++		 */
++		return 0;
+ 	} else {
+ 		struct skb_frag_struct *frag = (struct skb_frag_struct *)priv;
+ 
+@@ -1446,6 +1626,9 @@ static void hns3_clear_desc(struct hns3_enet_ring *ring, int next_to_use_orig)
+ 		if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
+ 			dma_unmap_single(dev, desc_cb->dma, desc_cb->length,
+ 					 DMA_TO_DEVICE);
++		else if (desc_cb->type &
++			 (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL))
++			hns3_tx_spare_rollback(ring, desc_cb->length);
+ 		else if (desc_cb->length)
+ 			dma_unmap_page(dev, desc_cb->dma, desc_cb->length,
+ 				       DMA_TO_DEVICE);
+@@ -1527,6 +1710,79 @@ static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
+ 	desc->tx.bdtp_fe_sc_vld_ra_ri |= cpu_to_le16(BIT(HNS3_TXD_TSYN_B));
+ }
+ 
++static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
++				 struct sk_buff *skb)
++{
++	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
++	unsigned int type = DESC_TYPE_BOUNCE_HEAD;
++	unsigned int size = skb_headlen(skb);
++	dma_addr_t dma;
++	int bd_num = 0;
++	u32 cb_len;
++	void *buf;
++	int ret;
++
++	if (skb->len <= ring->tx_copybreak) {
++		size = skb->len;
++		type = DESC_TYPE_BOUNCE_ALL;
++	}
++
++	/* hns3_can_use_tx_bounce() is called to ensure the below
++	 * function can always return the tx buffer.
++	 */
++	buf = hns3_tx_spare_alloc(ring, size, &dma, &cb_len);
++
++	ret = skb_copy_bits(skb, 0, buf, size);
++	if (unlikely(ret < 0)) {
++		hns3_tx_spare_rollback(ring, cb_len);
++		u64_stats_update_begin(&ring->syncp);
++		ring->stats.copy_bits_err++;
++		u64_stats_update_end(&ring->syncp);
++		return ret;
++	}
++
++	desc_cb->priv = skb;
++	desc_cb->length = cb_len;
++	desc_cb->dma = dma;
++	desc_cb->type = type;
++
++	bd_num += hns3_fill_desc(ring, dma, size);
++
++	if (type == DESC_TYPE_BOUNCE_HEAD) {
++		ret = hns3_fill_skb_to_desc(ring, skb,
++					    DESC_TYPE_BOUNCE_HEAD);
++		if (unlikely(ret < 0))
++			return ret;
++
++		bd_num += ret;
++	}
++
++	dma_sync_single_for_device(ring_to_dev(ring), dma, size,
++				   DMA_TO_DEVICE);
++
++	u64_stats_update_begin(&ring->syncp);
++	ring->stats.tx_bounce++;
++	u64_stats_update_end(&ring->syncp);
++	return bd_num;
++}
++
++static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
++				    struct sk_buff *skb)
++{
++	u32 space;
++
++	if (!ring->tx_spare)
++		goto out;
++
++	space = hns3_tx_spare_space(ring);
++
++	if (hns3_can_use_tx_bounce(ring, skb, space))
++		return hns3_handle_tx_bounce(ring, skb);
++
++out:
++	return hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
++}
++
+ netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
+ {
+ 	struct hns3_nic_priv *priv = netdev_priv(netdev);
+@@ -1572,7 +1828,7 @@ netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
+ 	 * zero, which is unlikely, and 'ret > 0' means how many tx desc
+ 	 * need to be notified to the hw.
+ 	 */
+-	ret = hns3_fill_skb_to_desc(ring, skb, DESC_TYPE_SKB);
++	ret = hns3_handle_desc_filling(ring, skb);
+ 	if (unlikely(ret <= 0))
+ 		goto fill_err;
+ 
+@@ -1778,6 +2034,7 @@ static struct rtnl_link_stats64 *hns3_nic_get_stats64(struct net_device *netdev,
+ 			tx_drop += ring->stats.tx_tso_err;
+ 			tx_drop += ring->stats.over_max_recursion;
+ 			tx_drop += ring->stats.hw_limitation;
++			tx_drop += ring->stats.copy_bits_err;
+ 			tx_errors += ring->stats.sw_err_cnt;
+ 			tx_errors += ring->stats.tx_vlan_err;
+ 			tx_errors += ring->stats.tx_l4_proto_err;
+@@ -1785,6 +2042,7 @@ static struct rtnl_link_stats64 *hns3_nic_get_stats64(struct net_device *netdev,
+ 			tx_errors += ring->stats.tx_tso_err;
+ 			tx_errors += ring->stats.over_max_recursion;
+ 			tx_errors += ring->stats.hw_limitation;
++			tx_errors += ring->stats.copy_bits_err;
+ 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
+ 
+ 		/* fetch the rx stats */
+@@ -2552,7 +2810,8 @@ static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
+ static void hns3_free_buffer(struct hns3_enet_ring *ring,
+ 			     struct hns3_desc_cb *cb, int budget)
+ {
+-	if (cb->type & DESC_TYPE_SKB)
++	if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
++			DESC_TYPE_BOUNCE_ALL))
+ 		napi_consume_skb(cb->priv, budget);
+ 	else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias)
+ 		__page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
+@@ -2576,9 +2835,11 @@ static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
+ 	if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_FRAGLIST_SKB))
+ 		dma_unmap_single(ring_to_dev(ring), cb->dma, cb->length,
+ 				 ring_to_dma_dir(ring));
+-	else if (cb->length)
++	else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
+ 		dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
+ 			       ring_to_dma_dir(ring));
++	else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD))
++		hns3_tx_spare_reclaim_cb(ring, cb);
+ }
+ 
+ static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
+@@ -2729,7 +2990,8 @@ static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
+ 
+ 		desc_cb = &ring->desc_cb[ntc];
+ 
+-		if (desc_cb->type & DESC_TYPE_SKB) {
++		if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
++				     DESC_TYPE_BOUNCE_HEAD)) {
+ 			(*pkts)++;
+ 			(*bytes) += desc_cb->send_bytes;
+ 		}
+@@ -2752,6 +3014,9 @@ static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
+ 	 * ring_space called by hns3_nic_net_xmit.
+ 	 */
+ 	smp_store_release(&ring->next_to_clean, ntc);
++
++	hns3_tx_spare_update(ring);
++
+ 	return true;
+ }
+ 
+@@ -3960,7 +4225,8 @@ static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
+ 		ring = &priv->ring[q->tqp_index];
+ 		desc_num = priv->ae_handle->kinfo.num_tx_desc;
+ 		ring->queue_index = q->tqp_index;
+-		ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
++		ring->tx_copybreak = priv->tx_copybreak;
++		ring->last_to_use = 0;
+ 	} else {
+ 		ring = &priv->ring[q->tqp_index + queue_num];
+ 		desc_num = priv->ae_handle->kinfo.num_rx_desc;
+@@ -3979,7 +4245,6 @@ static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
+ 	ring->desc_num = desc_num;
+ 	ring->next_to_use = 0;
+ 	ring->next_to_clean = 0;
+-	ring->last_to_use = 0;
+ }
+ 
+ static void hns3_queue_to_ring(struct hnae3_queue *tqp,
+@@ -4039,6 +4304,8 @@ static int hns3_alloc_ring_memory(struct hns3_enet_ring *ring)
+ 		ret = hns3_alloc_ring_buffers(ring);
+ 		if (ret)
+ 			goto out_with_desc;
++	} else {
++		hns3_init_tx_spare_buffer(ring);
+ 	}
+ 
+ 	return 0;
+@@ -4061,9 +4328,18 @@ void hns3_fini_ring(struct hns3_enet_ring *ring)
+ 	ring->next_to_use = 0;
+ 	ring->last_to_use = 0;
+ 	ring->pending_buf = 0;
+-	if (ring->skb) {
++	if (!HNAE3_IS_TX_RING(ring) && ring->skb) {
+ 		dev_kfree_skb_any(ring->skb);
+ 		ring->skb = NULL;
++	} else if (HNAE3_IS_TX_RING(ring) && ring->tx_spare) {
++		struct hns3_tx_spare *tx_spare = ring->tx_spare;
++
++		dma_unmap_page(ring_to_dev(ring), tx_spare->dma, tx_spare->len,
++			       DMA_TO_DEVICE);
++		free_pages((unsigned long)tx_spare->buf,
++			   get_order(tx_spare->len));
++		devm_kfree(ring_to_dev(ring), tx_spare);
++		ring->tx_spare = NULL;
+ 	}
+ }
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 4b035c458a58..7d0d9c3eb53c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -302,6 +302,8 @@ enum hns3_desc_type {
+ 	DESC_TYPE_SKB			= 1 << 0,
+ 	DESC_TYPE_FRAGLIST_SKB		= 1 << 1,
+ 	DESC_TYPE_PAGE			= 1 << 2,
++	DESC_TYPE_BOUNCE_ALL		= 1 << 3,
++	DESC_TYPE_BOUNCE_HEAD		= 1 << 4,
+ };
+ 
+ struct hns3_desc_cb {
+@@ -395,6 +397,9 @@ struct ring_stats {
+ 			u64 tx_tso_err;
+ 			u64 over_max_recursion;
+ 			u64 hw_limitation;
++			u64 tx_bounce;
++			u64 tx_spare_full;
++			u64 copy_bits_err;
+ 		};
+ 		struct {
+ 			u64 rx_pkts;
+@@ -411,6 +416,15 @@ struct ring_stats {
+ 	};
+ };
+ 
++struct hns3_tx_spare {
++	dma_addr_t dma;
++	void *buf;
++	u32 next_to_use;
++	u32 next_to_clean;
++	u32 last_to_clean;
++	u32 len;
++};
++
+ struct hns3_enet_ring {
+ 	u8 __iomem *io_base; /* base io address for the ring */
+ 	struct hns3_desc *desc; /* dma map address space */
+@@ -434,18 +448,28 @@ struct hns3_enet_ring {
+ 	 * next_to_use
+ 	 */
+ 	int next_to_clean;
+-	union {
+-		int last_to_use;	/* last idx used by xmit */
+-		u32 pull_len;		/* memcpy len for current rx packet */
+-	};
+-	u32 frag_num;
+-	void *va; /* first buffer address for current packet */
+-
+ 	u32 flag;          /* ring attribute */
+ 
+ 	int pending_buf;
+-	struct sk_buff *skb;
+-	struct sk_buff *tail_skb;
++	union {
++		/* for Tx ring */
++		struct {
++			u32 fd_qb_tx_sample;
++			int last_to_use;        /* last idx used by xmit */
++			u32 tx_copybreak;
++			struct hns3_tx_spare *tx_spare;
++		};
++
++		/* for Rx ring */
++		struct {
++			u32 pull_len;   /* memcpy len for current rx packet */
++			u32 frag_num;
++			/* first buffer address for current packet */
++			unsigned char *va;
++			struct sk_buff *skb;
++			struct sk_buff *tail_skb;
++		};
++	};
+ } ____cacheline_internodealigned_in_smp;
+ 
+ enum hns3_flow_level_range {
+@@ -524,6 +548,7 @@ struct hns3_nic_priv {
+ 
+ 	struct hns3_enet_coalesce tx_coal;
+ 	struct hns3_enet_coalesce rx_coal;
++	u32 tx_copybreak;
+ };
+ 
+ union l3_hdr_info {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index ae22adfe5740..5b5780a59d3e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -50,6 +50,9 @@ static const struct hns3_stats hns3_txq_stats[] = {
+ 	HNS3_TQP_STAT("tso_err", tx_tso_err),
+ 	HNS3_TQP_STAT("over_max_recursion", over_max_recursion),
+ 	HNS3_TQP_STAT("hw_limitation", hw_limitation),
++	HNS3_TQP_STAT("bounce", tx_bounce),
++	HNS3_TQP_STAT("spare_full", tx_spare_full),
++	HNS3_TQP_STAT("copy_bits_err", copy_bits_err),
+ };
+ 
+ #define HNS3_TXQ_STATS_COUNT ARRAY_SIZE(hns3_txq_stats)
+@@ -1604,6 +1607,50 @@ static int hns3_set_priv_flags(struct net_device *netdev, u32 pflags)
+ 	return 0;
+ }
+ 
++static int hns3_get_tunable(struct net_device *netdev,
++			    const struct ethtool_tunable *tuna,
++			    void *data)
++{
++	struct hns3_nic_priv *priv = netdev_priv(netdev);
++	int ret = 0;
++
++	switch (tuna->id) {
++	case ETHTOOL_TX_COPYBREAK:
++		/* all the tx rings have the same tx_copybreak */
++		*(u32 *)data = priv->tx_copybreak;
++		break;
++	default:
++		ret = -EOPNOTSUPP;
++		break;
++	}
++
++	return ret;
++}
++
++static int hns3_set_tunable(struct net_device *netdev,
++			    const struct ethtool_tunable *tuna,
++			    const void *data)
++{
++	struct hns3_nic_priv *priv = netdev_priv(netdev);
++	struct hnae3_handle *h = priv->ae_handle;
++	int i, ret = 0;
++
++	switch (tuna->id) {
++	case ETHTOOL_TX_COPYBREAK:
++		priv->tx_copybreak = *(u32 *)data;
++
++		for (i = 0; i < h->kinfo.num_tqps; i++)
++			priv->ring[i].tx_copybreak = priv->tx_copybreak;
++
++		break;
++	default:
++		ret = -EOPNOTSUPP;
++		break;
++	}
++
++	return ret;
++}
++
+ #define HNS3_ETHTOOL_COALESCE	(ETHTOOL_COALESCE_USECS |		\
+ 				 ETHTOOL_COALESCE_USE_ADAPTIVE |	\
+ 				 ETHTOOL_COALESCE_RX_USECS_HIGH |	\
+@@ -1647,6 +1694,8 @@ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ 	.set_msglevel = hns3_set_msglevel,
+ 	.get_priv_flags = hns3_get_priv_flags,
+ 	.set_priv_flags = hns3_set_priv_flags,
++	.get_tunable = hns3_get_tunable,
++	.set_tunable = hns3_set_tunable,
+ };
+ 
+ static const struct ethtool_ops hns3_ethtool_ops = {
+@@ -1686,6 +1735,8 @@ static const struct ethtool_ops hns3_ethtool_ops = {
+ 	.get_priv_flags = hns3_get_priv_flags,
+ 	.set_priv_flags = hns3_set_priv_flags,
+ 	.get_ts_info = hns3_get_ts_info,
++	.get_tunable = hns3_get_tunable,
++	.set_tunable = hns3_set_tunable,
+ };
+ 
+ void hns3_ethtool_set_ops(struct net_device *netdev)
+-- 
+2.34.1
+
diff --git a/patches/0450-net-hns3-add-support-to-query-tx-spare-buffer-size-f.patch b/patches/0450-net-hns3-add-support-to-query-tx-spare-buffer-size-f.patch
new file mode 100644
index 0000000..f8c1380
--- /dev/null
+++ b/patches/0450-net-hns3-add-support-to-query-tx-spare-buffer-size-f.patch
@@ -0,0 +1,172 @@
+From 246537a68b01bb2e12a9251437731d92eaa32905 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:24 +0800
+Subject: [PATCH 089/283] net: hns3: add support to query tx spare buffer size
+ for pf
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 1a00197b7d2fe57f0be93037d5090e19a9b178c8
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1a00197b7d2fe57f0be93037d5090e19a9b178c8
+
+----------------------------------------------------------------------
+
+Add support to query tx spare buffer size from configuration
+file, and use this info to do spare buffer initialization when
+the module parameter 'tx_spare_buf_size' is not specified.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h       |  3 +++
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c   |  7 +++++--
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h    |  4 ++++
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c   | 15 +++++++++++++++
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h   |  4 ++++
+ 5 files changed, 31 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 738baccf5a8a..58022716456d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -801,6 +801,9 @@ struct hnae3_knic_private_info {
+ 	u16 rx_buf_len;
+ 	u16 num_tx_desc;
+ 	u16 num_rx_desc;
++#ifndef __GENKSYMS__
++	u32 tx_spare_buf_size;
++#endif
+ 
+ 	struct hnae3_tc_info tc_info;
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index fd800aa35f3e..6fbc211facbb 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -709,13 +709,16 @@ static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
+ {
+ 	struct hns3_tx_spare *tx_spare;
+ 	struct page *page;
++	u32 alloc_size;
+ 	dma_addr_t dma;
+ 	int order;
+ 
+-	if (!tx_spare_buf_size)
++	alloc_size = tx_spare_buf_size ? tx_spare_buf_size :
++		     ring->tqp->handle->kinfo.tx_spare_buf_size;
++	if (!alloc_size)
+ 		return;
+ 
+-	order = get_order(tx_spare_buf_size);
++	order = get_order(alloc_size);
+ 	tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
+ 				GFP_KERNEL);
+ 	if (!tx_spare) {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index ba10e18ddb7e..08e02c1c6eb2 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -534,6 +534,10 @@ struct hclge_pf_res_cmd {
+ #define HCLGE_CFG_VLAN_FLTR_CAP_M	GENMASK(9, 8)
+ #define HCLGE_CFG_UMV_TBL_SPACE_S	16
+ #define HCLGE_CFG_UMV_TBL_SPACE_M	GENMASK(31, 16)
++#define HCLGE_CFG_PF_RSS_SIZE_S		0
++#define HCLGE_CFG_PF_RSS_SIZE_M		GENMASK(3, 0)
++#define HCLGE_CFG_TX_SPARE_BUF_SIZE_S	4
++#define HCLGE_CFG_TX_SPARE_BUF_SIZE_M	GENMASK(15, 4)
+ 
+ #define HCLGE_CFG_CMD_CNT		4
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index d46a1d31c701..047423fd4084 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1256,6 +1256,8 @@ static u32 hclge_get_max_speed(u8 speed_ability)
+ 
+ static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
+ {
++#define HCLGE_TX_SPARE_SIZE_UNIT		4096
++
+ 	struct hclge_cfg_param_cmd *req;
+ 	u64 mac_addr_tmp_high;
+ 	u64 mac_addr_tmp;
+@@ -1313,6 +1315,15 @@ static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
+ 					 HCLGE_CFG_UMV_TBL_SPACE_S);
+ 	if (!cfg->umv_space)
+ 		cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
++
++	/* The unit of the tx spare buffer size queried from configuration
++	 * file is HCLGE_TX_SPARE_SIZE_UNIT(4096) bytes, so a conversion is
++	 * needed here.
++	 */
++	cfg->tx_spare_buf_size = hnae3_get_field(__le32_to_cpu(req->param[2]),
++						 HCLGE_CFG_TX_SPARE_BUF_SIZE_M,
++						 HCLGE_CFG_TX_SPARE_BUF_SIZE_S);
++	cfg->tx_spare_buf_size *= HCLGE_TX_SPARE_SIZE_UNIT;
+ }
+ 
+ /* hclge_get_cfg: query the static parameter from flash
+@@ -1471,6 +1482,7 @@ static int hclge_configure(struct hclge_dev *hdev)
+ 	hdev->tc_max = cfg.tc_num;
+ 	hdev->tm_info.hw_pfc_map = 0;
+ 	hdev->wanted_umv_size = cfg.umv_space;
++	hdev->tx_spare_buf_size = cfg.tx_spare_buf_size;
+ 	if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF)
+ 		hnae3_set_bit(ae_dev->flag,
+ 			      HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 1);
+@@ -1658,6 +1670,7 @@ static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps,
+ 	kinfo->num_rx_desc = num_rx_desc;
+ 
+ 	kinfo->rx_buf_len = hdev->rx_buf_len;
++	kinfo->tx_spare_buf_size = hdev->tx_spare_buf_size;
+ 
+ 	kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, num_tqps,
+ 				  sizeof(struct hnae3_queue *), GFP_KERNEL);
+@@ -10274,6 +10287,8 @@ static void hclge_info_show(struct hclge_dev *hdev)
+ 		 hdev->flag & HCLGE_FLAG_DCB_ENABLE ? "enable" : "disable");
+ 	dev_info(dev, "MQPRIO %s\n",
+ 		 hdev->flag & HCLGE_FLAG_MQPRIO_ENABLE ? "enable" : "disable");
++	dev_info(dev, "Default tx spare buffer size: %u\n",
++		 hdev->tx_spare_buf_size);
+ 
+ 	dev_info(dev, "PF info end.\n");
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 660201b8bd11..07a1e7ed734b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -382,6 +382,7 @@ struct hclge_cfg {
+ 	u8 mac_addr[ETH_ALEN];
+ 	u8 default_speed;
+ 	u32 numa_node_map;
++	u32 tx_spare_buf_size;
+ 	u8 speed_ability;
+ 	u16 umv_space;
+ };
+@@ -788,6 +789,9 @@ struct hclge_dev {
+ 	u16 base_tqp_pid;	/* Base task tqp physical id of this PF */
+ 	u16 alloc_rss_size;		/* Allocated RSS task queue */
+ 	u16 rss_size_max;		/* HW defined max RSS task queue */
++	u16 vf_rss_size_max;		/* HW defined VF max RSS task queue */
++	u16 pf_rss_size_max;		/* HW defined PF max RSS task queue */
++	u32 tx_spare_buf_size;		/* HW defined TX spare buffer size */
+ 
+ 	u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
+ 	u16 num_alloc_vport;		/* Num vports this driver supports */
+-- 
+2.34.1
+
diff --git a/patches/0451-net-hns3-support-dma_map_sg-for-multi-frags-skb.patch b/patches/0451-net-hns3-support-dma_map_sg-for-multi-frags-skb.patch
new file mode 100644
index 0000000..01a76d8
--- /dev/null
+++ b/patches/0451-net-hns3-support-dma_map_sg-for-multi-frags-skb.patch
@@ -0,0 +1,276 @@
+From 1f7cc1d8d8904beb52079cf0fc7ae819161bb0ed Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:25 +0800
+Subject: [PATCH 090/283] net: hns3: support dma_map_sg() for multi frags skb
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 7459775e9f658a2d5f3ff9d4d087e86f4d4e5b83
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7459775e9f658a2d5f3ff9d4d087e86f4d4e5b83
+
+----------------------------------------------------------------------
+
+Using the queue based tx buffer, it is also possible to allocate a
+sgl buffer, and use skb_to_sgvec() to convert the skb to the sgvec
+in order to support the dma_map_sg() to decreases the overhead of
+IOMMU mapping and unmapping.
+
+Firstly, it reduces the number of buffers. For example, a tcp skb
+may have a 66-byte header and 3 fragments of 4328, 32768, and 28064
+bytes. With this patch, dma_map_sg() will combine them into two
+buffers, 66-bytes header and one 65160-bytes fragment by using IOMMU.
+
+Secondly, it reduces the number of dma mapping and unmapping. All the
+original 4 buffers are mapped only once rather than 4 times.
+
+The throughput improves above 10% when running single thread of iperf
+using TCP when IOMMU is in strict mode.
+
+Suggested-by: Barry Song <song.bao.hua@hisilicon.com>
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 111 +++++++++++++++++-
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |   4 +
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |   3 +
+ 3 files changed, 113 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 6fbc211facbb..5bb5b8a5e5a0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -56,6 +56,15 @@ static unsigned int tx_spare_buf_size;
+ module_param(tx_spare_buf_size, uint, 0400);
+ MODULE_PARM_DESC(tx_spare_buf_size, "Size used to allocate tx spare buffer");
+ 
++static unsigned int tx_sgl = 1;
++module_param(tx_sgl, uint, 0600);
++MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
++
++#define HNS3_SGL_SIZE(nfrag)	(sizeof(struct scatterlist) * (nfrag) +	\
++				 sizeof(struct sg_table))
++#define HNS3_MAX_SGL_SIZE	ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM),\
++				      dma_get_cache_alignment())
++
+ #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
+ 			   NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
+ 
+@@ -705,6 +714,25 @@ static bool hns3_can_use_tx_bounce(struct hns3_enet_ring *ring,
+ 	return true;
+ }
+ 
++static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
++				struct sk_buff *skb,
++				u32 space)
++{
++	if (skb->len <= ring->tx_copybreak || !tx_sgl ||
++	    (!skb_has_frag_list(skb) &&
++	     skb_shinfo(skb)->nr_frags < tx_sgl))
++		return false;
++
++	if (space < HNS3_MAX_SGL_SIZE) {
++		u64_stats_update_begin(&ring->syncp);
++		ring->stats.tx_spare_full++;
++		u64_stats_update_end(&ring->syncp);
++		return false;
++	}
++
++	return true;
++}
++
+ static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
+ {
+ 	struct hns3_tx_spare *tx_spare;
+@@ -812,14 +840,19 @@ static void hns3_tx_spare_reclaim_cb(struct hns3_enet_ring *ring,
+ 
+ 	/* This tx spare buffer is only really reclaimed after calling
+ 	 * hns3_tx_spare_update(), so it is still safe to use the info in
+-	 * the tx buffer to do the dma sync after tx_spare->next_to_clean
+-	 * is moved forword.
++	 * the tx buffer to do the dma sync or sg unmapping after
++	 * tx_spare->next_to_clean is moved forword.
+ 	 */
+ 	if (cb->type & (DESC_TYPE_BOUNCE_HEAD | DESC_TYPE_BOUNCE_ALL)) {
+ 		dma_addr_t dma = tx_spare->dma + ntc;
+ 
+ 		dma_sync_single_for_cpu(ring_to_dev(ring), dma, len,
+ 					DMA_TO_DEVICE);
++	} else {
++		struct sg_table *sgt = tx_spare->buf + ntc;
++
++		dma_unmap_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
++			     DMA_TO_DEVICE);
+ 	}
+ }
+ 
+@@ -1769,6 +1802,65 @@ static int hns3_handle_tx_bounce(struct hns3_enet_ring *ring,
+ 	return bd_num;
+ }
+ 
++static int hns3_handle_tx_sgl(struct hns3_enet_ring *ring,
++			      struct sk_buff *skb)
++{
++	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
++	u32 nfrag = skb_shinfo(skb)->nr_frags + 1;
++	struct sg_table *sgt;
++	int i, bd_num = 0;
++	dma_addr_t dma;
++	u32 cb_len;
++	int nents;
++
++	if (skb_has_frag_list(skb))
++		nfrag = HNS3_MAX_TSO_BD_NUM;
++
++	/* hns3_can_use_tx_sgl() is called to ensure the below
++	 * function can always return the tx buffer.
++	 */
++	sgt = hns3_tx_spare_alloc(ring, HNS3_SGL_SIZE(nfrag),
++				  &dma, &cb_len);
++
++	/* scatterlist follows by the sg table */
++	sgt->sgl = (struct scatterlist *)(sgt + 1);
++	sg_init_table(sgt->sgl, nfrag);
++	nents = skb_to_sgvec(skb, sgt->sgl, 0, skb->len);
++	if (unlikely(nents < 0)) {
++		hns3_tx_spare_rollback(ring, cb_len);
++		u64_stats_update_begin(&ring->syncp);
++		ring->stats.skb2sgl_err++;
++		u64_stats_update_end(&ring->syncp);
++		return -ENOMEM;
++	}
++
++	sgt->orig_nents = nents;
++	sgt->nents = dma_map_sg(ring_to_dev(ring), sgt->sgl, sgt->orig_nents,
++				DMA_TO_DEVICE);
++	if (unlikely(!sgt->nents)) {
++		hns3_tx_spare_rollback(ring, cb_len);
++		u64_stats_update_begin(&ring->syncp);
++		ring->stats.map_sg_err++;
++		u64_stats_update_end(&ring->syncp);
++		return -ENOMEM;
++	}
++
++	desc_cb->priv = skb;
++	desc_cb->length = cb_len;
++	desc_cb->dma = dma;
++	desc_cb->type = DESC_TYPE_SGL_SKB;
++
++	for (i = 0; i < sgt->nents; i++)
++		bd_num += hns3_fill_desc(ring, sg_dma_address(sgt->sgl + i),
++					 sg_dma_len(sgt->sgl + i));
++
++	u64_stats_update_begin(&ring->syncp);
++	ring->stats.tx_sgl++;
++	u64_stats_update_end(&ring->syncp);
++
++	return bd_num;
++}
++
+ static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
+ 				    struct sk_buff *skb)
+ {
+@@ -1779,6 +1871,9 @@ static int hns3_handle_desc_filling(struct hns3_enet_ring *ring,
+ 
+ 	space = hns3_tx_spare_space(ring);
+ 
++	if (hns3_can_use_tx_sgl(ring, skb, space))
++		return hns3_handle_tx_sgl(ring, skb);
++
+ 	if (hns3_can_use_tx_bounce(ring, skb, space))
+ 		return hns3_handle_tx_bounce(ring, skb);
+ 
+@@ -2038,6 +2133,8 @@ static struct rtnl_link_stats64 *hns3_nic_get_stats64(struct net_device *netdev,
+ 			tx_drop += ring->stats.over_max_recursion;
+ 			tx_drop += ring->stats.hw_limitation;
+ 			tx_drop += ring->stats.copy_bits_err;
++			tx_drop += ring->stats.skb2sgl_err;
++			tx_drop += ring->stats.map_sg_err;
+ 			tx_errors += ring->stats.sw_err_cnt;
+ 			tx_errors += ring->stats.tx_vlan_err;
+ 			tx_errors += ring->stats.tx_l4_proto_err;
+@@ -2046,6 +2143,8 @@ static struct rtnl_link_stats64 *hns3_nic_get_stats64(struct net_device *netdev,
+ 			tx_errors += ring->stats.over_max_recursion;
+ 			tx_errors += ring->stats.hw_limitation;
+ 			tx_errors += ring->stats.copy_bits_err;
++			tx_errors += ring->stats.skb2sgl_err;
++			tx_errors += ring->stats.map_sg_err;
+ 		} while (u64_stats_fetch_retry_irq(&ring->syncp, start));
+ 
+ 		/* fetch the rx stats */
+@@ -2814,7 +2913,7 @@ static void hns3_free_buffer(struct hns3_enet_ring *ring,
+ 			     struct hns3_desc_cb *cb, int budget)
+ {
+ 	if (cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_HEAD |
+-			DESC_TYPE_BOUNCE_ALL))
++			DESC_TYPE_BOUNCE_ALL | DESC_TYPE_SGL_SKB))
+ 		napi_consume_skb(cb->priv, budget);
+ 	else if (!HNAE3_IS_TX_RING(ring) && cb->pagecnt_bias)
+ 		__page_frag_cache_drain(cb->priv, cb->pagecnt_bias);
+@@ -2841,7 +2940,8 @@ static void hns3_unmap_buffer(struct hns3_enet_ring *ring,
+ 	else if ((cb->type & DESC_TYPE_PAGE) && cb->length)
+ 		dma_unmap_page(ring_to_dev(ring), cb->dma, cb->length,
+ 			       ring_to_dma_dir(ring));
+-	else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD))
++	else if (cb->type & (DESC_TYPE_BOUNCE_ALL | DESC_TYPE_BOUNCE_HEAD |
++			     DESC_TYPE_SGL_SKB))
+ 		hns3_tx_spare_reclaim_cb(ring, cb);
+ }
+ 
+@@ -2994,7 +3094,8 @@ static bool hns3_nic_reclaim_desc(struct hns3_enet_ring *ring,
+ 		desc_cb = &ring->desc_cb[ntc];
+ 
+ 		if (desc_cb->type & (DESC_TYPE_SKB | DESC_TYPE_BOUNCE_ALL |
+-				     DESC_TYPE_BOUNCE_HEAD)) {
++				     DESC_TYPE_BOUNCE_HEAD |
++				     DESC_TYPE_SGL_SKB)) {
+ 			(*pkts)++;
+ 			(*bytes) += desc_cb->send_bytes;
+ 		}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 7d0d9c3eb53c..d9a0fa3e8308 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -304,6 +304,7 @@ enum hns3_desc_type {
+ 	DESC_TYPE_PAGE			= 1 << 2,
+ 	DESC_TYPE_BOUNCE_ALL		= 1 << 3,
+ 	DESC_TYPE_BOUNCE_HEAD		= 1 << 4,
++	DESC_TYPE_SGL_SKB		= 1 << 5,
+ };
+ 
+ struct hns3_desc_cb {
+@@ -400,6 +401,9 @@ struct ring_stats {
+ 			u64 tx_bounce;
+ 			u64 tx_spare_full;
+ 			u64 copy_bits_err;
++			u64 tx_sgl;
++			u64 skb2sgl_err;
++			u64 map_sg_err;
+ 		};
+ 		struct {
+ 			u64 rx_pkts;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 5b5780a59d3e..18627c510617 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -53,6 +53,9 @@ static const struct hns3_stats hns3_txq_stats[] = {
+ 	HNS3_TQP_STAT("bounce", tx_bounce),
+ 	HNS3_TQP_STAT("spare_full", tx_spare_full),
+ 	HNS3_TQP_STAT("copy_bits_err", copy_bits_err),
++	HNS3_TQP_STAT("sgl", tx_sgl),
++	HNS3_TQP_STAT("skb2sgl_err", skb2sgl_err),
++	HNS3_TQP_STAT("map_sg_err", map_sg_err),
+ };
+ 
+ #define HNS3_TXQ_STATS_COUNT ARRAY_SIZE(hns3_txq_stats)
+-- 
+2.34.1
+
diff --git a/patches/0452-net-hns3-use-bounce-buffer-when-rx-page-can-not-be-r.patch b/patches/0452-net-hns3-use-bounce-buffer-when-rx-page-can-not-be-r.patch
new file mode 100644
index 0000000..7b7c834
--- /dev/null
+++ b/patches/0452-net-hns3-use-bounce-buffer-when-rx-page-can-not-be-r.patch
@@ -0,0 +1,245 @@
+From 1f3e5811640bf5e354b7d19adf5a98c52b4ea81c Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:27 +0800
+Subject: [PATCH 091/283] net: hns3: use bounce buffer when rx page can not be
+ reused
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 99f6b5fb5f63cf69c6e56bba8e5492c98c521a63
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=99f6b5fb5f63cf69c6e56bba8e5492c98c521a63
+
+----------------------------------------------------------------------
+
+Currently rx page will be reused to receive future packet when
+the stack releases the previous skb quickly. If the old page
+can not be reused, a new page will be allocated and mapped,
+which comsumes a lot of cpu when IOMMU is in the strict mode,
+especially when the application and irq/NAPI happens to run on
+the same cpu.
+
+So allocate a new frag to memcpy the data to avoid the costly
+IOMMU unmapping/mapping operation, and add "frag_alloc_err"
+and "frag_alloc" stats in "ethtool -S ethX" cmd.
+
+The throughput improves above 50% when running single thread of
+iperf using TCP when IOMMU is in strict mode and iperf shares the
+same cpu with irq/NAPI(rx_copybreak = 2048 and mtu = 1500).
+
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    |  4 +-
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 67 ++++++++++++++-----
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  4 ++
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 12 ++++
+ 4 files changed, 71 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 6b2179516fff..91a063ec9105 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -442,7 +442,8 @@ static const struct hns3_dbg_item rx_queue_info_items[] = {
+ 	{ "TAIL", 2 },
+ 	{ "HEAD", 2 },
+ 	{ "FBDNUM", 2 },
+-	{ "PKTNUM", 5 },
++	{ "PKTNUM", 2 },
++	{ "COPYBREAK", 2 },
+ 	{ "RING_EN", 2 },
+ 	{ "RX_RING_EN", 2 },
+ 	{ "BASE_ADDR", 10 },
+@@ -474,6 +475,7 @@ static void hns3_dump_rx_queue_info(struct hns3_enet_ring *ring,
+ 
+ 	sprintf(result[j++], "%6u", readl_relaxed(ring->tqp->io_base +
+ 		HNS3_RING_RX_RING_PKTNUM_RECORD_REG));
++	sprintf(result[j++], "%9u", ring->rx_copybreak);
+ 
+ 	sprintf(result[j++], "%7s", readl_relaxed(ring->tqp->io_base +
+ 		HNS3_RING_EN_REG) ? "on" : "off");
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 5bb5b8a5e5a0..046c696df091 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -3226,39 +3226,76 @@ static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
+ 				struct hns3_desc_cb *desc_cb)
+ {
+ 	struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
++	u32 frag_offset = desc_cb->page_offset + pull_len;
+ 	int size = le16_to_cpu(desc->rx.size);
+ 	u32 truesize = hns3_buf_size(ring);
++	u32 frag_size = size - pull_len;
++	bool reused;
+ 
+-	desc_cb->pagecnt_bias--;
+-	skb_add_rx_frag(skb, i, desc_cb->priv, desc_cb->page_offset + pull_len,
+-			size - pull_len, truesize);
+-
+-	/* Avoid re-using remote pages, or the stack is still using the page
+-	 * when page_offset rollback to zero, flag default unreuse
+-	 */
+ 	if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
+ 	    (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) {
+ 		__page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
+ 		return;
+ 	}
+ 
+-	/* Move offset up to the next cache line */
+-	desc_cb->page_offset += truesize;
++	reused = hns3_can_reuse_page(desc_cb);
+ 
+-	if (desc_cb->page_offset + truesize <= hns3_page_size(ring)) {
+-		desc_cb->reuse_flag = 1;
+-	} else if (hns3_can_reuse_page(desc_cb)) {
++	/* Rx page can be reused when:
++	 * 1. Rx page is only owned by the driver when page_offset
++	 *    is zero, which means 0 @ truesize will be used by
++	 *    stack after skb_add_rx_frag() is called, and the rest
++	 *    of rx page can be reused by driver.
++	 * Or
++	 * 2. Rx page is only owned by the driver when page_offset
++	 *    is non-zero, which means page_offset @ truesize will
++	 *    be used by stack after skb_add_rx_frag() is called,
++	 *    and 0 @ truesize can be reused by driver.
++	 */
++	if ((!desc_cb->page_offset && reused) ||
++	    ((desc_cb->page_offset + truesize + truesize) <=
++	     hns3_page_size(ring) && desc_cb->page_offset)) {
++		desc_cb->page_offset += truesize;
+ 		desc_cb->reuse_flag = 1;
++	} else if (desc_cb->page_offset && reused) {
+ 		desc_cb->page_offset = 0;
+-	} else if (desc_cb->pagecnt_bias) {
+-		__page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
++		desc_cb->reuse_flag = 1;
++	} else if (frag_size <= ring->rx_copybreak) {
++		void *frag = napi_alloc_frag(frag_size);
++
++		if (unlikely(!frag)) {
++			u64_stats_update_begin(&ring->syncp);
++			ring->stats.frag_alloc_err++;
++			u64_stats_update_end(&ring->syncp);
++
++			hns3_rl_err(ring_to_netdev(ring),
++				    "failed to allocate rx frag\n");
++			goto out;
++		}
++
++		desc_cb->reuse_flag = 1;
++		memcpy(frag, desc_cb->buf + frag_offset, frag_size);
++		skb_add_rx_frag(skb, i, virt_to_page(frag),
++				offset_in_page(frag), frag_size, frag_size);
++
++		u64_stats_update_begin(&ring->syncp);
++		ring->stats.frag_alloc++;
++		u64_stats_update_end(&ring->syncp);
+ 		return;
+ 	}
+ 
++out:
++	desc_cb->pagecnt_bias--;
++
+ 	if (unlikely(!desc_cb->pagecnt_bias)) {
+ 		page_ref_add(desc_cb->priv, USHRT_MAX);
+ 		desc_cb->pagecnt_bias = USHRT_MAX;
+ 	}
++
++	skb_add_rx_frag(skb, i, desc_cb->priv, frag_offset,
++			frag_size, truesize);
++
++	if (unlikely(!desc_cb->reuse_flag))
++		__page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
+ }
+ 
+ static int hns3_gro_complete(struct sk_buff *skb, u32 l234info)
+@@ -4335,7 +4372,7 @@ static void hns3_ring_get_cfg(struct hnae3_queue *q, struct hns3_nic_priv *priv,
+ 		ring = &priv->ring[q->tqp_index + queue_num];
+ 		desc_num = priv->ae_handle->kinfo.num_rx_desc;
+ 		ring->queue_index = q->tqp_index;
+-		ring->io_base = q->io_base;
++		ring->rx_copybreak = priv->rx_copybreak;
+ 	}
+ 
+ 	hnae3_set_bit(ring->flag, HNAE3_RING_TYPE_B, ring_type);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index d9a0fa3e8308..d7238d0744f3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -416,6 +416,8 @@ struct ring_stats {
+ 			u64 l3l4_csum_err;
+ 			u64 rx_multicast;
+ 			u64 non_reuse_pg;
++			u64 frag_alloc_err;
++			u64 frag_alloc;
+ 		};
+ 	};
+ };
+@@ -467,6 +469,7 @@ struct hns3_enet_ring {
+ 		/* for Rx ring */
+ 		struct {
+ 			u32 pull_len;   /* memcpy len for current rx packet */
++			u32 rx_copybreak;
+ 			u32 frag_num;
+ 			/* first buffer address for current packet */
+ 			unsigned char *va;
+@@ -553,6 +556,7 @@ struct hns3_nic_priv {
+ 	struct hns3_enet_coalesce tx_coal;
+ 	struct hns3_enet_coalesce rx_coal;
+ 	u32 tx_copybreak;
++	u32 rx_copybreak;
+ };
+ 
+ union l3_hdr_info {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 18627c510617..8d73f15be8d6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -74,6 +74,8 @@ static const struct hns3_stats hns3_rxq_stats[] = {
+ 	HNS3_TQP_STAT("l3l4_csum_err", l3l4_csum_err),
+ 	HNS3_TQP_STAT("multicast", rx_multicast),
+ 	HNS3_TQP_STAT("non_reuse_pg", non_reuse_pg),
++	HNS3_TQP_STAT("frag_alloc_err", frag_alloc_err),
++	HNS3_TQP_STAT("frag_alloc", frag_alloc),
+ };
+ 
+ #define HNS3_PRIV_FLAGS_LEN ARRAY_SIZE(hns3_priv_flags)
+@@ -1622,6 +1624,9 @@ static int hns3_get_tunable(struct net_device *netdev,
+ 		/* all the tx rings have the same tx_copybreak */
+ 		*(u32 *)data = priv->tx_copybreak;
+ 		break;
++	case ETHTOOL_RX_COPYBREAK:
++		*(u32 *)data = priv->rx_copybreak;
++		break;
+ 	default:
+ 		ret = -EOPNOTSUPP;
+ 		break;
+@@ -1645,6 +1650,13 @@ static int hns3_set_tunable(struct net_device *netdev,
+ 		for (i = 0; i < h->kinfo.num_tqps; i++)
+ 			priv->ring[i].tx_copybreak = priv->tx_copybreak;
+ 
++		break;
++	case ETHTOOL_RX_COPYBREAK:
++		priv->rx_copybreak = *(u32 *)data;
++
++		for (i = h->kinfo.num_tqps; i < h->kinfo.num_tqps * 2; i++)
++			priv->ring[i].rx_copybreak = priv->rx_copybreak;
++
+ 		break;
+ 	default:
+ 		ret = -EOPNOTSUPP;
+-- 
+2.34.1
+
diff --git a/patches/0453-net-hns3-fix-different-snprintf-limit.patch b/patches/0453-net-hns3-fix-different-snprintf-limit.patch
new file mode 100644
index 0000000..15f0ef1
--- /dev/null
+++ b/patches/0453-net-hns3-fix-different-snprintf-limit.patch
@@ -0,0 +1,58 @@
+From 524cc5fcd2276d672246471272e57fe85f68cde0 Mon Sep 17 00:00:00 2001
+From: Dan Carpenter <dan.carpenter@oracle.com>
+Date: Sat, 24 Jul 2021 15:45:29 +0800
+Subject: [PATCH 092/283] net: hns3: fix different snprintf() limit
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit faebad853455b7126450c1690f7c31e048213543
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=faebad853455b7126450c1690f7c31e048213543
+
+----------------------------------------------------------------------
+
+This patch doesn't affect runtime at all, it's just a correctness issue.
+
+The ptp->info.name[] buffer has 16 characters but the snprintf() limit
+was capped at 32 characters.  Fortunately, HCLGE_DRIVER_NAME is "hclge"
+which isn't close to 16 characters so we're fine.
+
+Fixes: 0bf5eb788512 ("net: hns3: add support for PTP")
+Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+index b3eb8f109dbb..3b1f84502e36 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+@@ -415,8 +415,6 @@ int hclge_ptp_get_ts_info(struct hnae3_handle *handle,
+ 
+ static int hclge_ptp_create_clock(struct hclge_dev *hdev)
+ {
+-#define HCLGE_PTP_NAME_LEN	32
+-
+ 	struct hclge_ptp *ptp;
+ 
+ 	ptp = devm_kzalloc(&hdev->pdev->dev, sizeof(*ptp), GFP_KERNEL);
+@@ -424,7 +422,7 @@ static int hclge_ptp_create_clock(struct hclge_dev *hdev)
+ 		return -ENOMEM;
+ 
+ 	ptp->hdev = hdev;
+-	snprintf(ptp->info.name, HCLGE_PTP_NAME_LEN, "%s",
++	snprintf(ptp->info.name, sizeof(ptp->info.name), "%s",
+ 		 HCLGE_DRIVER_NAME);
+ 	ptp->info.owner = THIS_MODULE;
+ 	ptp->info.max_adj = HCLGE_PTP_CYCLE_ADJ_MAX;
+-- 
+2.34.1
+
diff --git a/patches/0454-net-hns3-Fix-a-memory-leak-in-an-error-handling-path.patch b/patches/0454-net-hns3-Fix-a-memory-leak-in-an-error-handling-path.patch
new file mode 100644
index 0000000..c5da4df
--- /dev/null
+++ b/patches/0454-net-hns3-Fix-a-memory-leak-in-an-error-handling-path.patch
@@ -0,0 +1,52 @@
+From 3e89e60f27d5085eac6cfbaedbc209c781b486f7 Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Sat, 24 Jul 2021 15:45:30 +0800
+Subject: [PATCH 093/283] net: hns3: Fix a memory leak in an error handling
+ path in 'hclge_handle_error_info_log()'
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit b40d7af798a0a459d65bd95f34e3dff004eb554a
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b40d7af798a0a459d65bd95f34e3dff004eb554a
+
+----------------------------------------------------------------------
+
+If this 'kzalloc()' fails we must free some resources as in all the other
+error handling paths of this function.
+
+Fixes: 2e2deee7618b ("net: hns3: add the RAS compatibility adaptation solution")
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Reviewed-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index a4e9aa9c5d6f..3d3057fed4bb 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -2333,8 +2333,10 @@ int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev)
+ 	buf_size = buf_len / sizeof(u32);
+ 
+ 	desc_data = kzalloc(buf_len, GFP_KERNEL);
+-	if (!desc_data)
+-		return -ENOMEM;
++	if (!desc_data) {
++		ret = -ENOMEM;
++		goto err_desc;
++	}
+ 
+ 	buf = kzalloc(buf_len, GFP_KERNEL);
+ 	if (!buf) {
+-- 
+2.34.1
+
diff --git a/patches/0455-net-hns3-add-support-for-FD-counter-in-debugfs.patch b/patches/0455-net-hns3-add-support-for-FD-counter-in-debugfs.patch
new file mode 100644
index 0000000..0069004
--- /dev/null
+++ b/patches/0455-net-hns3-add-support-for-FD-counter-in-debugfs.patch
@@ -0,0 +1,184 @@
+From 878e201d94598190fdece0eb9df35c2fab61a0e0 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:31 +0800
+Subject: [PATCH 094/283] net: hns3: add support for FD counter in debugfs
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit 03a92fe8cedb6f619df416d38d0b57fd55070cd7
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=03a92fe8cedb6f619df416d38d0b57fd55070cd7
+
+----------------------------------------------------------------------
+
+Previously, the flow director counter is not enabled. To improve the
+maintainability for chechking whether flow director hit or not, enable
+flow director counter for each function, and add debugfs query inerface
+to query the counters for each function.
+
+The debugfs command is below:
+cat fd_counter
+func_id    hit_times
+pf         0
+vf0        0
+vf1        0
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+---
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    |  7 ++++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         | 23 ++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     | 37 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 10 ++++-
+ 4 files changed, 75 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 91a063ec9105..6c2decba5ac4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -316,6 +316,13 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
+ 		.buf_len = HNS3_DBG_READ_LEN,
+ 		.init = hns3_dbg_common_file_init,
+ 	},
++	{
++		.name = "fd_counter",
++		.cmd = HNAE3_DBG_CMD_FD_COUNTER,
++		.dentry = HNS3_DBG_DENTRY_FD,
++		.buf_len = HNS3_DBG_READ_LEN,
++		.init = hns3_dbg_common_file_init,
++	},
+ };
+ 
+ static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 08e02c1c6eb2..75cf58c5f0b3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -249,6 +249,8 @@ enum hclge_opcode_type {
+ 	HCLGE_OPC_FD_KEY_CONFIG		= 0x1202,
+ 	HCLGE_OPC_FD_TCAM_OP		= 0x1203,
+ 	HCLGE_OPC_FD_AD_OP		= 0x1204,
++	HCLGE_OPC_FD_CNT_OP		= 0x1205,
++	HCLGE_OPC_FD_USER_DEF_OP	= 0x1207,
+ 
+ 	/* MDIO command */
+ 	HCLGE_OPC_MDIO_CONFIG		= 0x1900,
+@@ -1107,6 +1109,27 @@ struct hclge_fd_ad_config_cmd {
+ 	u8 rsv2[8];
+ };
+ 
++struct hclge_fd_ad_cnt_read_cmd {
++	u8 rsv0[4];
++	__le16 index;
++	u8 rsv1[2];
++	__le64 cnt;
++	u8 rsv2[8];
++};
++
++#define HCLGE_FD_USER_DEF_OFT_S		0
++#define HCLGE_FD_USER_DEF_OFT_M		GENMASK(14, 0)
++#define HCLGE_FD_USER_DEF_EN_B		15
++struct hclge_fd_user_def_cfg_cmd {
++	__le16 ol2_cfg;
++	__le16 l2_cfg;
++	__le16 ol3_cfg;
++	__le16 l3_cfg;
++	__le16 ol4_cfg;
++	__le16 l4_cfg;
++	u8 rsv[12];
++};
++
+ struct hclge_get_imp_bd_cmd {
+ 	__le32 bd_num;
+ 	u8 rsv[20];
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index 0517dedae55f..6350ad7353d1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -1629,6 +1629,39 @@ static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len)
+ 	return ret;
+ }
+ 
++static int hclge_dbg_dump_fd_counter(struct hclge_dev *hdev, char *buf, int len)
++{
++	u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */
++	struct hclge_fd_ad_cnt_read_cmd *req;
++	char str_id[HCLGE_DBG_ID_LEN];
++	struct hclge_desc desc;
++	int pos = 0;
++	int ret;
++	u64 cnt;
++	u8 i;
++
++	pos += scnprintf(buf + pos, len - pos,
++			 "func_id\thit_times\n");
++
++	for (i = 0; i < func_num; i++) {
++		hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_CNT_OP, true);
++		req = (struct hclge_fd_ad_cnt_read_cmd *)desc.data;
++		req->index = cpu_to_le16(i);
++		ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++		if (ret) {
++			dev_err(&hdev->pdev->dev, "failed to get fd counter, ret = %d\n",
++				ret);
++			return ret;
++		}
++		cnt = le64_to_cpu(req->cnt);
++		hclge_dbg_get_func_id_str(str_id, i);
++		pos += scnprintf(buf + pos, len - pos,
++				 "%s\t%llu\n", str_id, cnt);
++	}
++
++	return 0;
++}
++
+ int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len)
+ {
+ 	int pos = 0;
+@@ -2392,6 +2425,10 @@ static const struct hclge_dbg_func hclge_dbg_cmd_func[] = {
+ 		.cmd = HNAE3_DBG_CMD_VLAN_CONFIG,
+ 		.dbg_dump = hclge_dbg_dump_vlan_config,
+ 	},
++	{
++		.cmd = HNAE3_DBG_CMD_FD_COUNTER,
++		.dbg_dump = hclge_dbg_dump_fd_counter,
++	},
+ };
+ 
+ int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 047423fd4084..7196dd27e230 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -5641,8 +5641,14 @@ static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
+ 		ad_data.queue_id = rule->queue_id;
+ 	}
+ 
+-	ad_data.use_counter = false;
+-	ad_data.counter_id = 0;
++	if (hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1]) {
++		ad_data.use_counter = true;
++		ad_data.counter_id = rule->vf_id %
++				     hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1];
++	} else {
++		ad_data.use_counter = false;
++		ad_data.counter_id = 0;
++	}
+ 
+ 	ad_data.use_next_stage = false;
+ 	ad_data.next_input_key = 0;
+-- 
+2.34.1
+
diff --git a/patches/0456-net-hns3-fix-rx-VLAN-offload-state-inconsistent-issu.patch b/patches/0456-net-hns3-fix-rx-VLAN-offload-state-inconsistent-issu.patch
new file mode 100644
index 0000000..455aef5
--- /dev/null
+++ b/patches/0456-net-hns3-fix-rx-VLAN-offload-state-inconsistent-issu.patch
@@ -0,0 +1,61 @@
+From a0b1a84acf061473902e6fa2abf848e2ff537513 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Tue, 27 Jul 2021 15:10:37 +0800
+Subject: [PATCH 095/283] net: hns3: fix rx VLAN offload state inconsistent
+ issue
+
+mainline inclusion
+from mainline-v5.14-rc3
+commit bbfd4506f962e7e6fff8f37f017154a3c3791264
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bbfd4506f962e7e6fff8f37f017154a3c3791264
+
+----------------------------------------------------------------------
+
+Currently, VF doesn't enable rx VLAN offload when initializating,
+and PF does it for VFs. If user disable the rx VLAN offload for
+VF with ethtool -K, and reload the VF driver, it may cause the
+rx VLAN offload state being inconsistent between hardware and
+software.
+
+Fixes it by enabling rx VLAN offload when VF initializing.
+
+Fixes: e2cb1dec9779 ("net: hns3: Add HNS3 VF HCL(Hardware Compatibility Layer) Support")
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c  | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index d58b4e4780a8..4cab9c19031a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -2569,6 +2569,16 @@ static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
+ 
+ static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
+ {
++	struct hnae3_handle *nic = &hdev->nic;
++	int ret;
++
++	ret = hclgevf_en_hw_strip_rxvtag(nic, true);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to enable rx vlan offload, ret = %d\n", ret);
++		return ret;
++	}
++
+ 	return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
+ 				       false);
+ }
+-- 
+2.34.1
+
diff --git a/patches/0457-net-hns3-change-the-method-of-obtaining-default-ptp-.patch b/patches/0457-net-hns3-change-the-method-of-obtaining-default-ptp-.patch
new file mode 100644
index 0000000..332d05b
--- /dev/null
+++ b/patches/0457-net-hns3-change-the-method-of-obtaining-default-ptp-.patch
@@ -0,0 +1,156 @@
+From 97e76592c5f727ec2475f6052a56bde969232d16 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Fri, 30 Jul 2021 15:43:57 +0800
+Subject: [PATCH 096/283] net: hns3: change the method of obtaining default ptp
+ cycle
+
+mainline inclusion
+from mainline-v5.14-rc4
+commit 8373cd38a8888549ace7c7617163a2e826970a92
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMUR
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8373cd38a8888549ace7c7617163a2e826970a92
+
+----------------------------------------------------------------------
+
+The ptp cycle is related to the hardware, so it may cause compatibility
+issues if a fixed value is used in driver. Therefore, the method of
+obtaining this value is changed to read from the register rather than
+use a fixed value in driver.
+
+Fixes: 0bf5eb788512 ("net: hns3: add support for PTP")
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_ptp.c         | 36 +++++++++++++++----
+ .../hisilicon/hns3/hns3pf/hclge_ptp.h         | 10 ++++--
+ 2 files changed, 37 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+index 3b1f84502e36..befa9bcc2f2f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+@@ -5,9 +5,27 @@
+ #include "hclge_main.h"
+ #include "hnae3.h"
+ 
++static int hclge_ptp_get_cycle(struct hclge_dev *hdev)
++{
++	struct hclge_ptp *ptp = hdev->ptp;
++
++	ptp->cycle.quo = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG) &
++			 HCLGE_PTP_CYCLE_QUO_MASK;
++	ptp->cycle.numer = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG);
++	ptp->cycle.den = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG);
++
++	if (ptp->cycle.den == 0) {
++		dev_err(&hdev->pdev->dev, "invalid ptp cycle denominator!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
+ static int hclge_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+ {
+ 	struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp);
++	struct hclge_ptp_cycle *cycle = &hdev->ptp->cycle;
+ 	u64 adj_val, adj_base, diff;
+ 	unsigned long flags;
+ 	bool is_neg = false;
+@@ -18,7 +36,7 @@ static int hclge_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+ 		is_neg = true;
+ 	}
+ 
+-	adj_base = HCLGE_PTP_CYCLE_ADJ_BASE * HCLGE_PTP_CYCLE_ADJ_UNIT;
++	adj_base = (u64)cycle->quo * (u64)cycle->den + (u64)cycle->numer;
+ 	adj_val = adj_base * ppb;
+ 	diff = div_u64(adj_val, 1000000000ULL);
+ 
+@@ -29,16 +47,16 @@ static int hclge_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+ 
+ 	/* This clock cycle is defined by three part: quotient, numerator
+ 	 * and denominator. For example, 2.5ns, the quotient is 2,
+-	 * denominator is fixed to HCLGE_PTP_CYCLE_ADJ_UNIT, and numerator
+-	 * is 0.5 * HCLGE_PTP_CYCLE_ADJ_UNIT.
++	 * denominator is fixed to ptp->cycle.den, and numerator
++	 * is 0.5 * ptp->cycle.den.
+ 	 */
+-	quo = div_u64_rem(adj_val, HCLGE_PTP_CYCLE_ADJ_UNIT, &numerator);
++	quo = div_u64_rem(adj_val, cycle->den, &numerator);
+ 
+ 	spin_lock_irqsave(&hdev->ptp->lock, flags);
+-	writel(quo, hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG);
++	writel(quo & HCLGE_PTP_CYCLE_QUO_MASK,
++	       hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG);
+ 	writel(numerator, hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG);
+-	writel(HCLGE_PTP_CYCLE_ADJ_UNIT,
+-	       hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG);
++	writel(cycle->den, hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG);
+ 	writel(HCLGE_PTP_CYCLE_ADJ_EN,
+ 	       hdev->ptp->io_base + HCLGE_PTP_CYCLE_CFG_REG);
+ 	spin_unlock_irqrestore(&hdev->ptp->lock, flags);
+@@ -475,6 +493,10 @@ int hclge_ptp_init(struct hclge_dev *hdev)
+ 		ret = hclge_ptp_create_clock(hdev);
+ 		if (ret)
+ 			return ret;
++
++		ret = hclge_ptp_get_cycle(hdev);
++		if (ret)
++			return ret;
+ 	}
+ 
+ 	ret = hclge_ptp_int_en(hdev, true);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
+index 5a202b775471..dbf5f4c08019 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
+@@ -29,6 +29,7 @@
+ #define HCLGE_PTP_TIME_ADJ_REG		0x60
+ #define HCLGE_PTP_TIME_ADJ_EN		BIT(0)
+ #define HCLGE_PTP_CYCLE_QUO_REG		0x64
++#define HCLGE_PTP_CYCLE_QUO_MASK	GENMASK(7, 0)
+ #define HCLGE_PTP_CYCLE_DEN_REG		0x68
+ #define HCLGE_PTP_CYCLE_NUM_REG		0x6C
+ #define HCLGE_PTP_CYCLE_CFG_REG		0x70
+@@ -37,9 +38,7 @@
+ #define HCLGE_PTP_CUR_TIME_SEC_L_REG	0x78
+ #define HCLGE_PTP_CUR_TIME_NSEC_REG	0x7C
+ 
+-#define HCLGE_PTP_CYCLE_ADJ_BASE	2
+ #define HCLGE_PTP_CYCLE_ADJ_MAX		500000000
+-#define HCLGE_PTP_CYCLE_ADJ_UNIT	100000000
+ #define HCLGE_PTP_SEC_H_OFFSET		32u
+ #define HCLGE_PTP_SEC_L_MASK		GENMASK(31, 0)
+ 
+@@ -47,6 +46,12 @@
+ #define HCLGE_PTP_FLAG_TX_EN		1
+ #define HCLGE_PTP_FLAG_RX_EN		2
+ 
++struct hclge_ptp_cycle {
++	u32 quo;
++	u32 numer;
++	u32 den;
++};
++
+ struct hclge_ptp {
+ 	struct hclge_dev *hdev;
+ 	struct ptp_clock *clock;
+@@ -58,6 +63,7 @@ struct hclge_ptp {
+ 	spinlock_t lock;	/* protects ptp registers */
+ 	u32 ptp_cfg;
+ 	u32 last_tx_seqid;
++	struct hclge_ptp_cycle cycle;
+ 	unsigned long tx_start;
+ 	unsigned long tx_cnt;
+ 	unsigned long tx_skipped;
+-- 
+2.34.1
+
diff --git a/patches/0458-net-hns3-add-support-for-triggering-reset-by-ethtool.patch b/patches/0458-net-hns3-add-support-for-triggering-reset-by-ethtool.patch
new file mode 100644
index 0000000..82619f8
--- /dev/null
+++ b/patches/0458-net-hns3-add-support-for-triggering-reset-by-ethtool.patch
@@ -0,0 +1,171 @@
+From a239416d71310c1163a9ea05016aabcb6d8cdd25 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Sat, 21 Aug 2021 17:00:37 +0800
+Subject: [PATCH 097/283] net: hns3: add support for triggering reset by
+ ethtool
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit ddccc5e368a33daeb6862192d4dca8e59af9234a
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ddccc5e368a33daeb6862192d4dca8e59af9234a
+
+----------------------------------------------------------------------
+
+Currently, four reset types are supported for the HNS3 ethernet
+driver: IMP reset, global reset, function reset, and FLR. Only
+FLR can now be triggered by the user. To restore the device when
+an exception occurs, add support for triggering reset by ethtool.
+
+Run the "ethtool --reset DEVNAME mgmt | all | dedicated" to
+trigger the IMP | global | function reset manually.
+
+In addition, VF can only trigger function reset.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Link: https://lore.kernel.org/r/1628602128-15640-1-git-send-email-huangguangbin2@huawei.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  5 ++
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 56 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  6 ++
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  1 +
+ 4 files changed, 68 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index d7238d0744f3..416c0c44b11d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -577,6 +577,11 @@ struct hns3_hw_error_info {
+ 	const char *msg;
+ };
+ 
++struct hns3_reset_type_map {
++	enum ethtool_reset_flags rst_flags;
++	enum hnae3_reset_type rst_type;
++};
++
+ static inline int ring_space(struct hns3_enet_ring *ring)
+ {
+ 	/* This smp_load_acquire() pairs with smp_store_release() in
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 8d73f15be8d6..4197d40471f4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -965,6 +965,60 @@ static int hns3_get_rxnfc(struct net_device *netdev,
+ 	}
+ }
+ 
++static const struct hns3_reset_type_map hns3_reset_type[] = {
++	{ETH_RESET_MGMT, HNAE3_IMP_RESET},
++	{ETH_RESET_ALL, HNAE3_GLOBAL_RESET},
++	{ETH_RESET_DEDICATED, HNAE3_FUNC_RESET},
++};
++
++static const struct hns3_reset_type_map hns3vf_reset_type[] = {
++	{ETH_RESET_DEDICATED, HNAE3_VF_FUNC_RESET},
++};
++
++static int hns3_set_reset(struct net_device *netdev, u32 *flags)
++{
++	enum hnae3_reset_type rst_type = HNAE3_NONE_RESET;
++	struct hnae3_handle *h = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
++	const struct hnae3_ae_ops *ops = h->ae_algo->ops;
++	const struct hns3_reset_type_map *rst_type_map;
++	u32 i, size;
++
++	if (ops->ae_dev_resetting && ops->ae_dev_resetting(h))
++		return -EBUSY;
++
++	if (!ops->set_default_reset_request || !ops->reset_event)
++		return -EOPNOTSUPP;
++
++	if (h->flags & HNAE3_SUPPORT_VF) {
++		rst_type_map = hns3vf_reset_type;
++		size = ARRAY_SIZE(hns3vf_reset_type);
++	} else {
++		rst_type_map = hns3_reset_type;
++		size = ARRAY_SIZE(hns3_reset_type);
++	}
++
++	for (i = 0; i < size; i++) {
++		if (rst_type_map[i].rst_flags == *flags) {
++			rst_type = rst_type_map[i].rst_type;
++			break;
++		}
++	}
++
++	if (rst_type == HNAE3_NONE_RESET ||
++	    (rst_type == HNAE3_IMP_RESET &&
++	     ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2))
++		return -EOPNOTSUPP;
++
++	netdev_info(netdev, "Setting reset type %d\n", rst_type);
++
++	ops->set_default_reset_request(ae_dev, rst_type);
++
++	ops->reset_event(h->pdev, h);
++
++	return 0;
++}
++
+ static void hns3_change_all_ring_bd_num(struct hns3_nic_priv *priv,
+ 					u32 tx_desc_num, u32 rx_desc_num)
+ {
+@@ -1711,6 +1765,7 @@ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ 	.set_priv_flags = hns3_set_priv_flags,
+ 	.get_tunable = hns3_get_tunable,
+ 	.set_tunable = hns3_set_tunable,
++	.reset = hns3_set_reset,
+ };
+ 
+ static const struct ethtool_ops hns3_ethtool_ops = {
+@@ -1752,6 +1807,7 @@ static const struct ethtool_ops hns3_ethtool_ops = {
+ 	.get_ts_info = hns3_get_ts_info,
+ 	.get_tunable = hns3_get_tunable,
+ 	.set_tunable = hns3_set_tunable,
++	.reset = hns3_set_reset,
+ };
+ 
+ void hns3_ethtool_set_ops(struct net_device *netdev)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 7196dd27e230..359c6fc4ca1d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3700,6 +3700,12 @@ static void hclge_do_reset(struct hclge_dev *hdev)
+ 	}
+ 
+ 	switch (hdev->reset_type) {
++	case HNAE3_IMP_RESET:
++		dev_info(&pdev->dev, "IMP reset requested\n");
++		val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
++		hnae3_set_bit(val, HCLGE_TRIGGER_IMP_RESET_B, 1);
++		hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, val);
++		break;
+ 	case HNAE3_GLOBAL_RESET:
+ 		dev_info(&pdev->dev, "global reset requested\n");
+ 		val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 07a1e7ed734b..e04488bb7278 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -192,6 +192,7 @@ enum HLCGE_PORT_TYPE {
+ #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B	4U
+ #define HCLGE_VECTOR0_IMP_RD_POISON_B	5U
+ #define HCLGE_VECTOR0_ALL_MSIX_ERR_B	6U
++#define HCLGE_TRIGGER_IMP_RESET_B	7U
+ 
+ #define HCLGE_MAC_DEFAULT_FRAME \
+ 	(ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
+-- 
+2.34.1
+
diff --git a/patches/0459-docs-ethtool-Add-two-link-extended-substates-of-bad-.patch b/patches/0459-docs-ethtool-Add-two-link-extended-substates-of-bad-.patch
new file mode 100644
index 0000000..c09b4aa
--- /dev/null
+++ b/patches/0459-docs-ethtool-Add-two-link-extended-substates-of-bad-.patch
@@ -0,0 +1,1432 @@
+From 218242a0d5c4f6c0eb1b933e8af7d61ab109dd2f Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sat, 21 Aug 2021 17:00:38 +0800
+Subject: [PATCH 098/283] docs: ethtool: Add two link extended substates of bad
+ signal integrity
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 958ab281eb3e0543a995457fd2d9cb4504cde4b8
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=958ab281eb3e0543a995457fd2d9cb4504cde4b8
+
+----------------------------------------------------------------------
+
+Add documentation for two bad signal integrity substates:
+ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST
+ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	Documentation/networking/ethtool-netlink.rst
+---
+ Documentation/networking/ethtool-netlink.rst | 1388 ++++++++++++++++++
+ 1 file changed, 1388 insertions(+)
+ create mode 100644 Documentation/networking/ethtool-netlink.rst
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+new file mode 100644
+index 000000000000..f7b88ee9227d
+--- /dev/null
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -0,0 +1,1388 @@
++=============================
++Netlink interface for ethtool
++=============================
++
++
++Basic information
++=================
++
++Netlink interface for ethtool uses generic netlink family ``ethtool``
++(userspace application should use macros ``ETHTOOL_GENL_NAME`` and
++``ETHTOOL_GENL_VERSION`` defined in ``<linux/ethtool_netlink.h>`` uapi
++header). This family does not use a specific header, all information in
++requests and replies is passed using netlink attributes.
++
++The ethtool netlink interface uses extended ACK for error and warning
++reporting, userspace application developers are encouraged to make these
++messages available to user in a suitable way.
++
++Requests can be divided into three categories: "get" (retrieving information),
++"set" (setting parameters) and "action" (invoking an action).
++
++All "set" and "action" type requests require admin privileges
++(``CAP_NET_ADMIN`` in the namespace). Most "get" type requests are allowed for
++anyone but there are exceptions (where the response contains sensitive
++information). In some cases, the request as such is allowed for anyone but
++unprivileged users have attributes with sensitive information (e.g.
++wake-on-lan password) omitted.
++
++
++Conventions
++===========
++
++Attributes which represent a boolean value usually use NLA_U8 type so that we
++can distinguish three states: "on", "off" and "not present" (meaning the
++information is not available in "get" requests or value is not to be changed
++in "set" requests). For these attributes, the "true" value should be passed as
++number 1 but any non-zero value should be understood as "true" by recipient.
++In the tables below, "bool" denotes NLA_U8 attributes interpreted in this way.
++
++In the message structure descriptions below, if an attribute name is suffixed
++with "+", parent nest can contain multiple attributes of the same type. This
++implements an array of entries.
++
++
++Request header
++==============
++
++Each request or reply message contains a nested attribute with common header.
++Structure of this header is
++
++  ==============================  ======  =============================
++  ``ETHTOOL_A_HEADER_DEV_INDEX``  u32     device ifindex
++  ``ETHTOOL_A_HEADER_DEV_NAME``   string  device name
++  ``ETHTOOL_A_HEADER_FLAGS``      u32     flags common for all requests
++  ==============================  ======  =============================
++
++``ETHTOOL_A_HEADER_DEV_INDEX`` and ``ETHTOOL_A_HEADER_DEV_NAME`` identify the
++device message relates to. One of them is sufficient in requests, if both are
++used, they must identify the same device. Some requests, e.g. global string
++sets, do not require device identification. Most ``GET`` requests also allow
++dump requests without device identification to query the same information for
++all devices providing it (each device in a separate message).
++
++``ETHTOOL_A_HEADER_FLAGS`` is a bitmap of request flags common for all request
++types. The interpretation of these flags is the same for all request types but
++the flags may not apply to requests. Recognized flags are:
++
++  =================================  ===================================
++  ``ETHTOOL_FLAG_COMPACT_BITSETS``   use compact format bitsets in reply
++  ``ETHTOOL_FLAG_OMIT_REPLY``        omit optional reply (_SET and _ACT)
++  ``ETHTOOL_FLAG_STATS``             include optional device statistics
++  =================================  ===================================
++
++New request flags should follow the general idea that if the flag is not set,
++the behaviour is backward compatible, i.e. requests from old clients not aware
++of the flag should be interpreted the way the client expects. A client must
++not set flags it does not understand.
++
++
++Bit sets
++========
++
++For short bitmaps of (reasonably) fixed length, standard ``NLA_BITFIELD32``
++type is used. For arbitrary length bitmaps, ethtool netlink uses a nested
++attribute with contents of one of two forms: compact (two binary bitmaps
++representing bit values and mask of affected bits) and bit-by-bit (list of
++bits identified by either index or name).
++
++Verbose (bit-by-bit) bitsets allow sending symbolic names for bits together
++with their values which saves a round trip (when the bitset is passed in a
++request) or at least a second request (when the bitset is in a reply). This is
++useful for one shot applications like traditional ethtool command. On the
++other hand, long running applications like ethtool monitor (displaying
++notifications) or network management daemons may prefer fetching the names
++only once and using compact form to save message size. Notifications from
++ethtool netlink interface always use compact form for bitsets.
++
++A bitset can represent either a value/mask pair (``ETHTOOL_A_BITSET_NOMASK``
++not set) or a single bitmap (``ETHTOOL_A_BITSET_NOMASK`` set). In requests
++modifying a bitmap, the former changes the bit set in mask to values set in
++value and preserves the rest; the latter sets the bits set in the bitmap and
++clears the rest.
++
++Compact form: nested (bitset) atrribute contents:
++
++  ============================  ======  ============================
++  ``ETHTOOL_A_BITSET_NOMASK``   flag    no mask, only a list
++  ``ETHTOOL_A_BITSET_SIZE``     u32     number of significant bits
++  ``ETHTOOL_A_BITSET_VALUE``    binary  bitmap of bit values
++  ``ETHTOOL_A_BITSET_MASK``     binary  bitmap of valid bits
++  ============================  ======  ============================
++
++Value and mask must have length at least ``ETHTOOL_A_BITSET_SIZE`` bits
++rounded up to a multiple of 32 bits. They consist of 32-bit words in host byte
++order, words ordered from least significant to most significant (i.e. the same
++way as bitmaps are passed with ioctl interface).
++
++For compact form, ``ETHTOOL_A_BITSET_SIZE`` and ``ETHTOOL_A_BITSET_VALUE`` are
++mandatory. ``ETHTOOL_A_BITSET_MASK`` attribute is mandatory if
++``ETHTOOL_A_BITSET_NOMASK`` is not set (bitset represents a value/mask pair);
++if ``ETHTOOL_A_BITSET_NOMASK`` is not set, ``ETHTOOL_A_BITSET_MASK`` is not
++allowed (bitset represents a single bitmap.
++
++Kernel bit set length may differ from userspace length if older application is
++used on newer kernel or vice versa. If userspace bitmap is longer, an error is
++issued only if the request actually tries to set values of some bits not
++recognized by kernel.
++
++Bit-by-bit form: nested (bitset) attribute contents:
++
++ +------------------------------------+--------+-----------------------------+
++ | ``ETHTOOL_A_BITSET_NOMASK``        | flag   | no mask, only a list        |
++ +------------------------------------+--------+-----------------------------+
++ | ``ETHTOOL_A_BITSET_SIZE``          | u32    | number of significant bits  |
++ +------------------------------------+--------+-----------------------------+
++ | ``ETHTOOL_A_BITSET_BITS``          | nested | array of bits               |
++ +-+----------------------------------+--------+-----------------------------+
++ | | ``ETHTOOL_A_BITSET_BITS_BIT+``   | nested | one bit                     |
++ +-+-+--------------------------------+--------+-----------------------------+
++ | | | ``ETHTOOL_A_BITSET_BIT_INDEX`` | u32    | bit index (0 for LSB)       |
++ +-+-+--------------------------------+--------+-----------------------------+
++ | | | ``ETHTOOL_A_BITSET_BIT_NAME``  | string | bit name                    |
++ +-+-+--------------------------------+--------+-----------------------------+
++ | | | ``ETHTOOL_A_BITSET_BIT_VALUE`` | flag   | present if bit is set       |
++ +-+-+--------------------------------+--------+-----------------------------+
++
++Bit size is optional for bit-by-bit form. ``ETHTOOL_A_BITSET_BITS`` nest can
++only contain ``ETHTOOL_A_BITSET_BITS_BIT`` attributes but there can be an
++arbitrary number of them.  A bit may be identified by its index or by its
++name. When used in requests, listed bits are set to 0 or 1 according to
++``ETHTOOL_A_BITSET_BIT_VALUE``, the rest is preserved. A request fails if
++index exceeds kernel bit length or if name is not recognized.
++
++When ``ETHTOOL_A_BITSET_NOMASK`` flag is present, bitset is interpreted as
++a simple bitmap. ``ETHTOOL_A_BITSET_BIT_VALUE`` attributes are not used in
++such case. Such bitset represents a bitmap with listed bits set and the rest
++zero.
++
++In requests, application can use either form. Form used by kernel in reply is
++determined by ``ETHTOOL_FLAG_COMPACT_BITSETS`` flag in flags field of request
++header. Semantics of value and mask depends on the attribute.
++
++
++List of message types
++=====================
++
++All constants identifying message types use ``ETHTOOL_CMD_`` prefix and suffix
++according to message purpose:
++
++  ==============    ======================================
++  ``_GET``          userspace request to retrieve data
++  ``_SET``          userspace request to set data
++  ``_ACT``          userspace request to perform an action
++  ``_GET_REPLY``    kernel reply to a ``GET`` request
++  ``_SET_REPLY``    kernel reply to a ``SET`` request
++  ``_ACT_REPLY``    kernel reply to an ``ACT`` request
++  ``_NTF``          kernel notification
++  ==============    ======================================
++
++Userspace to kernel:
++
++  ===================================== ================================
++  ``ETHTOOL_MSG_STRSET_GET``            get string set
++  ``ETHTOOL_MSG_LINKINFO_GET``          get link settings
++  ``ETHTOOL_MSG_LINKINFO_SET``          set link settings
++  ``ETHTOOL_MSG_LINKMODES_GET``         get link modes info
++  ``ETHTOOL_MSG_LINKMODES_SET``         set link modes info
++  ``ETHTOOL_MSG_LINKSTATE_GET``         get link state
++  ``ETHTOOL_MSG_DEBUG_GET``             get debugging settings
++  ``ETHTOOL_MSG_DEBUG_SET``             set debugging settings
++  ``ETHTOOL_MSG_WOL_GET``               get wake-on-lan settings
++  ``ETHTOOL_MSG_WOL_SET``               set wake-on-lan settings
++  ``ETHTOOL_MSG_FEATURES_GET``          get device features
++  ``ETHTOOL_MSG_FEATURES_SET``          set device features
++  ``ETHTOOL_MSG_PRIVFLAGS_GET``         get private flags
++  ``ETHTOOL_MSG_PRIVFLAGS_SET``         set private flags
++  ``ETHTOOL_MSG_RINGS_GET``             get ring sizes
++  ``ETHTOOL_MSG_RINGS_SET``             set ring sizes
++  ``ETHTOOL_MSG_CHANNELS_GET``          get channel counts
++  ``ETHTOOL_MSG_CHANNELS_SET``          set channel counts
++  ``ETHTOOL_MSG_COALESCE_GET``          get coalescing parameters
++  ``ETHTOOL_MSG_COALESCE_SET``          set coalescing parameters
++  ``ETHTOOL_MSG_PAUSE_GET``             get pause parameters
++  ``ETHTOOL_MSG_PAUSE_SET``             set pause parameters
++  ``ETHTOOL_MSG_EEE_GET``               get EEE settings
++  ``ETHTOOL_MSG_EEE_SET``               set EEE settings
++  ``ETHTOOL_MSG_TSINFO_GET``		get timestamping info
++  ``ETHTOOL_MSG_CABLE_TEST_ACT``        action start cable test
++  ``ETHTOOL_MSG_CABLE_TEST_TDR_ACT``    action start raw TDR cable test
++  ``ETHTOOL_MSG_TUNNEL_INFO_GET``       get tunnel offload info
++  ===================================== ================================
++
++Kernel to userspace:
++
++  ===================================== =================================
++  ``ETHTOOL_MSG_STRSET_GET_REPLY``      string set contents
++  ``ETHTOOL_MSG_LINKINFO_GET_REPLY``    link settings
++  ``ETHTOOL_MSG_LINKINFO_NTF``          link settings notification
++  ``ETHTOOL_MSG_LINKMODES_GET_REPLY``   link modes info
++  ``ETHTOOL_MSG_LINKMODES_NTF``         link modes notification
++  ``ETHTOOL_MSG_LINKSTATE_GET_REPLY``   link state info
++  ``ETHTOOL_MSG_DEBUG_GET_REPLY``       debugging settings
++  ``ETHTOOL_MSG_DEBUG_NTF``             debugging settings notification
++  ``ETHTOOL_MSG_WOL_GET_REPLY``         wake-on-lan settings
++  ``ETHTOOL_MSG_WOL_NTF``               wake-on-lan settings notification
++  ``ETHTOOL_MSG_FEATURES_GET_REPLY``    device features
++  ``ETHTOOL_MSG_FEATURES_SET_REPLY``    optional reply to FEATURES_SET
++  ``ETHTOOL_MSG_FEATURES_NTF``          netdev features notification
++  ``ETHTOOL_MSG_PRIVFLAGS_GET_REPLY``   private flags
++  ``ETHTOOL_MSG_PRIVFLAGS_NTF``         private flags
++  ``ETHTOOL_MSG_RINGS_GET_REPLY``       ring sizes
++  ``ETHTOOL_MSG_RINGS_NTF``             ring sizes
++  ``ETHTOOL_MSG_CHANNELS_GET_REPLY``    channel counts
++  ``ETHTOOL_MSG_CHANNELS_NTF``          channel counts
++  ``ETHTOOL_MSG_COALESCE_GET_REPLY``    coalescing parameters
++  ``ETHTOOL_MSG_COALESCE_NTF``          coalescing parameters
++  ``ETHTOOL_MSG_PAUSE_GET_REPLY``       pause parameters
++  ``ETHTOOL_MSG_PAUSE_NTF``             pause parameters
++  ``ETHTOOL_MSG_EEE_GET_REPLY``         EEE settings
++  ``ETHTOOL_MSG_EEE_NTF``               EEE settings
++  ``ETHTOOL_MSG_TSINFO_GET_REPLY``	timestamping info
++  ``ETHTOOL_MSG_CABLE_TEST_NTF``        Cable test results
++  ``ETHTOOL_MSG_CABLE_TEST_TDR_NTF``    Cable test TDR results
++  ``ETHTOOL_MSG_TUNNEL_INFO_GET_REPLY`` tunnel offload info
++  ===================================== =================================
++
++``GET`` requests are sent by userspace applications to retrieve device
++information. They usually do not contain any message specific attributes.
++Kernel replies with corresponding "GET_REPLY" message. For most types, ``GET``
++request with ``NLM_F_DUMP`` and no device identification can be used to query
++the information for all devices supporting the request.
++
++If the data can be also modified, corresponding ``SET`` message with the same
++layout as corresponding ``GET_REPLY`` is used to request changes. Only
++attributes where a change is requested are included in such request (also, not
++all attributes may be changed). Replies to most ``SET`` request consist only
++of error code and extack; if kernel provides additional data, it is sent in
++the form of corresponding ``SET_REPLY`` message which can be suppressed by
++setting ``ETHTOOL_FLAG_OMIT_REPLY`` flag in request header.
++
++Data modification also triggers sending a ``NTF`` message with a notification.
++These usually bear only a subset of attributes which was affected by the
++change. The same notification is issued if the data is modified using other
++means (mostly ioctl ethtool interface). Unlike notifications from ethtool
++netlink code which are only sent if something actually changed, notifications
++triggered by ioctl interface may be sent even if the request did not actually
++change any data.
++
++``ACT`` messages request kernel (driver) to perform a specific action. If some
++information is reported by kernel (which can be suppressed by setting
++``ETHTOOL_FLAG_OMIT_REPLY`` flag in request header), the reply takes form of
++an ``ACT_REPLY`` message. Performing an action also triggers a notification
++(``NTF`` message).
++
++Later sections describe the format and semantics of these messages.
++
++
++STRSET_GET
++==========
++
++Requests contents of a string set as provided by ioctl commands
++``ETHTOOL_GSSET_INFO`` and ``ETHTOOL_GSTRINGS.`` String sets are not user
++writeable so that the corresponding ``STRSET_SET`` message is only used in
++kernel replies. There are two types of string sets: global (independent of
++a device, e.g. device feature names) and device specific (e.g. device private
++flags).
++
++Request contents:
++
++ +---------------------------------------+--------+------------------------+
++ | ``ETHTOOL_A_STRSET_HEADER``           | nested | request header         |
++ +---------------------------------------+--------+------------------------+
++ | ``ETHTOOL_A_STRSET_STRINGSETS``       | nested | string set to request  |
++ +-+-------------------------------------+--------+------------------------+
++ | | ``ETHTOOL_A_STRINGSETS_STRINGSET+`` | nested | one string set         |
++ +-+-+-----------------------------------+--------+------------------------+
++ | | | ``ETHTOOL_A_STRINGSET_ID``        | u32    | set id                 |
++ +-+-+-----------------------------------+--------+------------------------+
++
++Kernel response contents:
++
++ +---------------------------------------+--------+-----------------------+
++ | ``ETHTOOL_A_STRSET_HEADER``           | nested | reply header          |
++ +---------------------------------------+--------+-----------------------+
++ | ``ETHTOOL_A_STRSET_STRINGSETS``       | nested | array of string sets  |
++ +-+-------------------------------------+--------+-----------------------+
++ | | ``ETHTOOL_A_STRINGSETS_STRINGSET+`` | nested | one string set        |
++ +-+-+-----------------------------------+--------+-----------------------+
++ | | | ``ETHTOOL_A_STRINGSET_ID``        | u32    | set id                |
++ +-+-+-----------------------------------+--------+-----------------------+
++ | | | ``ETHTOOL_A_STRINGSET_COUNT``     | u32    | number of strings     |
++ +-+-+-----------------------------------+--------+-----------------------+
++ | | | ``ETHTOOL_A_STRINGSET_STRINGS``   | nested | array of strings      |
++ +-+-+-+---------------------------------+--------+-----------------------+
++ | | | | ``ETHTOOL_A_STRINGS_STRING+``   | nested | one string            |
++ +-+-+-+-+-------------------------------+--------+-----------------------+
++ | | | | | ``ETHTOOL_A_STRING_INDEX``    | u32    | string index          |
++ +-+-+-+-+-------------------------------+--------+-----------------------+
++ | | | | | ``ETHTOOL_A_STRING_VALUE``    | string | string value          |
++ +-+-+-+-+-------------------------------+--------+-----------------------+
++ | ``ETHTOOL_A_STRSET_COUNTS_ONLY``      | flag   | return only counts    |
++ +---------------------------------------+--------+-----------------------+
++
++Device identification in request header is optional. Depending on its presence
++a and ``NLM_F_DUMP`` flag, there are three type of ``STRSET_GET`` requests:
++
++ - no ``NLM_F_DUMP,`` no device: get "global" stringsets
++ - no ``NLM_F_DUMP``, with device: get string sets related to the device
++ - ``NLM_F_DUMP``, no device: get device related string sets for all devices
++
++If there is no ``ETHTOOL_A_STRSET_STRINGSETS`` array, all string sets of
++requested type are returned, otherwise only those specified in the request.
++Flag ``ETHTOOL_A_STRSET_COUNTS_ONLY`` tells kernel to only return string
++counts of the sets, not the actual strings.
++
++
++LINKINFO_GET
++============
++
++Requests link settings as provided by ``ETHTOOL_GLINKSETTINGS`` except for
++link modes and autonegotiation related information. The request does not use
++any attributes.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_LINKINFO_HEADER``         nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_LINKINFO_HEADER``         nested  reply header
++  ``ETHTOOL_A_LINKINFO_PORT``           u8      physical port
++  ``ETHTOOL_A_LINKINFO_PHYADDR``        u8      phy MDIO address
++  ``ETHTOOL_A_LINKINFO_TP_MDIX``        u8      MDI(-X) status
++  ``ETHTOOL_A_LINKINFO_TP_MDIX_CTRL``   u8      MDI(-X) control
++  ``ETHTOOL_A_LINKINFO_TRANSCEIVER``    u8      transceiver
++  ====================================  ======  ==========================
++
++Attributes and their values have the same meaning as matching members of the
++corresponding ioctl structures.
++
++``LINKINFO_GET`` allows dump requests (kernel returns reply message for all
++devices supporting the request).
++
++
++LINKINFO_SET
++============
++
++``LINKINFO_SET`` request allows setting some of the attributes reported by
++``LINKINFO_GET``.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_LINKINFO_HEADER``         nested  request header
++  ``ETHTOOL_A_LINKINFO_PORT``           u8      physical port
++  ``ETHTOOL_A_LINKINFO_PHYADDR``        u8      phy MDIO address
++  ``ETHTOOL_A_LINKINFO_TP_MDIX_CTRL``   u8      MDI(-X) control
++  ====================================  ======  ==========================
++
++MDI(-X) status and transceiver cannot be set, request with the corresponding
++attributes is rejected.
++
++
++LINKMODES_GET
++=============
++
++Requests link modes (supported, advertised and peer advertised) and related
++information (autonegotiation status, link speed and duplex) as provided by
++``ETHTOOL_GLINKSETTINGS``. The request does not use any attributes.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_LINKMODES_HEADER``        nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ==========================================  ======  ==========================
++  ``ETHTOOL_A_LINKMODES_HEADER``              nested  reply header
++  ``ETHTOOL_A_LINKMODES_AUTONEG``             u8      autonegotiation status
++  ``ETHTOOL_A_LINKMODES_OURS``                bitset  advertised link modes
++  ``ETHTOOL_A_LINKMODES_PEER``                bitset  partner link modes
++  ``ETHTOOL_A_LINKMODES_SPEED``               u32     link speed (Mb/s)
++  ``ETHTOOL_A_LINKMODES_DUPLEX``              u8      duplex mode
++  ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG``    u8      Master/slave port mode
++  ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE``  u8      Master/slave port state
++  ==========================================  ======  ==========================
++
++For ``ETHTOOL_A_LINKMODES_OURS``, value represents advertised modes and mask
++represents supported modes. ``ETHTOOL_A_LINKMODES_PEER`` in the reply is a bit
++list.
++
++``LINKMODES_GET`` allows dump requests (kernel returns reply messages for all
++devices supporting the request).
++
++
++LINKMODES_SET
++=============
++
++Request contents:
++
++  ==========================================  ======  ==========================
++  ``ETHTOOL_A_LINKMODES_HEADER``              nested  request header
++  ``ETHTOOL_A_LINKMODES_AUTONEG``             u8      autonegotiation status
++  ``ETHTOOL_A_LINKMODES_OURS``                bitset  advertised link modes
++  ``ETHTOOL_A_LINKMODES_PEER``                bitset  partner link modes
++  ``ETHTOOL_A_LINKMODES_SPEED``               u32     link speed (Mb/s)
++  ``ETHTOOL_A_LINKMODES_DUPLEX``              u8      duplex mode
++  ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG``    u8      Master/slave port mode
++  ==========================================  ======  ==========================
++
++``ETHTOOL_A_LINKMODES_OURS`` bit set allows setting advertised link modes. If
++autonegotiation is on (either set now or kept from before), advertised modes
++are not changed (no ``ETHTOOL_A_LINKMODES_OURS`` attribute) and at least one
++of speed and duplex is specified, kernel adjusts advertised modes to all
++supported modes matching speed, duplex or both (whatever is specified). This
++autoselection is done on ethtool side with ioctl interface, netlink interface
++is supposed to allow requesting changes without knowing what exactly kernel
++supports.
++
++
++LINKSTATE_GET
++=============
++
++Requests link state information. Link up/down flag (as provided by
++``ETHTOOL_GLINK`` ioctl command) is provided. Optionally, extended state might
++be provided as well. In general, extended state describes reasons for why a port
++is down, or why it operates in some non-obvious mode. This request does not have
++any attributes.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_LINKSTATE_HEADER``        nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ====================================  ======  ============================
++  ``ETHTOOL_A_LINKSTATE_HEADER``        nested  reply header
++  ``ETHTOOL_A_LINKSTATE_LINK``          bool    link state (up/down)
++  ``ETHTOOL_A_LINKSTATE_SQI``           u32     Current Signal Quality Index
++  ``ETHTOOL_A_LINKSTATE_SQI_MAX``       u32     Max support SQI value
++  ``ETHTOOL_A_LINKSTATE_EXT_STATE``     u8      link extended state
++  ``ETHTOOL_A_LINKSTATE_EXT_SUBSTATE``  u8      link extended substate
++  ====================================  ======  ============================
++
++For most NIC drivers, the value of ``ETHTOOL_A_LINKSTATE_LINK`` returns
++carrier flag provided by ``netif_carrier_ok()`` but there are drivers which
++define their own handler.
++
++``ETHTOOL_A_LINKSTATE_EXT_STATE`` and ``ETHTOOL_A_LINKSTATE_EXT_SUBSTATE`` are
++optional values. ethtool core can provide either both
++``ETHTOOL_A_LINKSTATE_EXT_STATE`` and ``ETHTOOL_A_LINKSTATE_EXT_SUBSTATE``,
++or only ``ETHTOOL_A_LINKSTATE_EXT_STATE``, or none of them.
++
++``LINKSTATE_GET`` allows dump requests (kernel returns reply messages for all
++devices supporting the request).
++
++
++Link extended states:
++
++  ================================================      ============================================
++  ``ETHTOOL_LINK_EXT_STATE_AUTONEG``                    States relating to the autonegotiation or
++                                                        issues therein
++
++  ``ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE``      Failure during link training
++
++  ``ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH``      Logical mismatch in physical coding sublayer
++                                                        or forward error correction sublayer
++
++  ``ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY``       Signal integrity issues
++
++  ``ETHTOOL_LINK_EXT_STATE_NO_CABLE``                   No cable connected
++
++  ``ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE``                Failure is related to cable,
++                                                        e.g., unsupported cable
++
++  ``ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE``               Failure is related to EEPROM, e.g., failure
++                                                        during reading or parsing the data
++
++  ``ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE``        Failure during calibration algorithm
++
++  ``ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED``      The hardware is not able to provide the
++                                                        power required from cable or module
++
++  ``ETHTOOL_LINK_EXT_STATE_OVERHEAT``                   The module is overheated
++  ================================================      ============================================
++
++Link extended substates:
++
++  Autoneg substates:
++
++  ===============================================================   ================================
++  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED``              Peer side is down
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED``                 Ack not received from peer side
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED``        Next page exchange failed
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE``   Peer side is down during force
++                                                                    mode or there is no agreement of
++                                                                    speed
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE``     Forward error correction modes
++                                                                    in both sides are mismatched
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD``                           No Highest Common Denominator
++  ===============================================================   ================================
++
++  Link training substates:
++
++  ===========================================================================   ====================
++  ``ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED``                    Frames were not
++                                                                                 recognized, the
++                                                                                 lock failed
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT``                       The lock did not
++                                                                                 occur before
++                                                                                 timeout
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY``    Peer side did not
++                                                                                 send ready signal
++                                                                                 after training
++                                                                                 process
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT``                                  Remote side is not
++                                                                                 ready yet
++  ===========================================================================   ====================
++
++  Link logical mismatch substates:
++
++  ================================================================   ===============================
++  ``ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK``   Physical coding sublayer was
++                                                                     not locked in first phase -
++                                                                     block lock
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK``      Physical coding sublayer was
++                                                                     not locked in second phase -
++                                                                     alignment markers lock
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS``     Physical coding sublayer did
++                                                                     not get align status
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED``             FC forward error correction is
++                                                                     not locked
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED``             RS forward error correction is
++                                                                     not locked
++  ================================================================   ===============================
++
++  Bad signal integrity substates:
++
++  =================================================================    =============================
++  ``ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS``    Large number of physical
++                                                                       errors
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE``                   The system attempted to
++                                                                       operate the cable at a rate
++                                                                       that is not formally
++                                                                       supported, which led to
++                                                                       signal integrity issues
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST``        The external clock signal for
++                                                                       SerDes is too weak or
++                                                                       unavailable.
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS``                        The received signal for
++                                                                       SerDes is too weak because
++                                                                       analog loss of signal.
++  =================================================================    =============================
++
++  Cable issue substates:
++
++  ===================================================   ============================================
++  ``ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE``    Unsupported cable
++
++  ``ETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE``   Cable test failure
++  ===================================================   ============================================
++
++DEBUG_GET
++=========
++
++Requests debugging settings of a device. At the moment, only message mask is
++provided.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_DEBUG_HEADER``            nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_DEBUG_HEADER``            nested  reply header
++  ``ETHTOOL_A_DEBUG_MSGMASK``           bitset  message mask
++  ====================================  ======  ==========================
++
++The message mask (``ETHTOOL_A_DEBUG_MSGMASK``) is equal to message level as
++provided by ``ETHTOOL_GMSGLVL`` and set by ``ETHTOOL_SMSGLVL`` in ioctl
++interface. While it is called message level there for historical reasons, most
++drivers and almost all newer drivers use it as a mask of enabled message
++classes (represented by ``NETIF_MSG_*`` constants); therefore netlink
++interface follows its actual use in practice.
++
++``DEBUG_GET`` allows dump requests (kernel returns reply messages for all
++devices supporting the request).
++
++
++DEBUG_SET
++=========
++
++Set or update debugging settings of a device. At the moment, only message mask
++is supported.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_DEBUG_HEADER``            nested  request header
++  ``ETHTOOL_A_DEBUG_MSGMASK``           bitset  message mask
++  ====================================  ======  ==========================
++
++``ETHTOOL_A_DEBUG_MSGMASK`` bit set allows setting or modifying mask of
++enabled debugging message types for the device.
++
++
++WOL_GET
++=======
++
++Query device wake-on-lan settings. Unlike most "GET" type requests,
++``ETHTOOL_MSG_WOL_GET`` requires (netns) ``CAP_NET_ADMIN`` privileges as it
++(potentially) provides SecureOn(tm) password which is confidential.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_WOL_HEADER``              nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_WOL_HEADER``              nested  reply header
++  ``ETHTOOL_A_WOL_MODES``               bitset  mask of enabled WoL modes
++  ``ETHTOOL_A_WOL_SOPASS``              binary  SecureOn(tm) password
++  ====================================  ======  ==========================
++
++In reply, ``ETHTOOL_A_WOL_MODES`` mask consists of modes supported by the
++device, value of modes which are enabled. ``ETHTOOL_A_WOL_SOPASS`` is only
++included in reply if ``WAKE_MAGICSECURE`` mode is supported.
++
++
++WOL_SET
++=======
++
++Set or update wake-on-lan settings.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_WOL_HEADER``              nested  request header
++  ``ETHTOOL_A_WOL_MODES``               bitset  enabled WoL modes
++  ``ETHTOOL_A_WOL_SOPASS``              binary  SecureOn(tm) password
++  ====================================  ======  ==========================
++
++``ETHTOOL_A_WOL_SOPASS`` is only allowed for devices supporting
++``WAKE_MAGICSECURE`` mode.
++
++
++FEATURES_GET
++============
++
++Gets netdev features like ``ETHTOOL_GFEATURES`` ioctl request.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_FEATURES_HEADER``         nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_FEATURES_HEADER``         nested  reply header
++  ``ETHTOOL_A_FEATURES_HW``             bitset  dev->hw_features
++  ``ETHTOOL_A_FEATURES_WANTED``         bitset  dev->wanted_features
++  ``ETHTOOL_A_FEATURES_ACTIVE``         bitset  dev->features
++  ``ETHTOOL_A_FEATURES_NOCHANGE``       bitset  NETIF_F_NEVER_CHANGE
++  ====================================  ======  ==========================
++
++Bitmaps in kernel response have the same meaning as bitmaps used in ioctl
++interference but attribute names are different (they are based on
++corresponding members of struct net_device). Legacy "flags" are not provided,
++if userspace needs them (most likely only ethtool for backward compatibility),
++it can calculate their values from related feature bits itself.
++ETHA_FEATURES_HW uses mask consisting of all features recognized by kernel (to
++provide all names when using verbose bitmap format), the other three use no
++mask (simple bit lists).
++
++
++FEATURES_SET
++============
++
++Request to set netdev features like ``ETHTOOL_SFEATURES`` ioctl request.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_FEATURES_HEADER``         nested  request header
++  ``ETHTOOL_A_FEATURES_WANTED``         bitset  requested features
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_FEATURES_HEADER``         nested  reply header
++  ``ETHTOOL_A_FEATURES_WANTED``         bitset  diff wanted vs. result
++  ``ETHTOOL_A_FEATURES_ACTIVE``         bitset  diff old vs. new active
++  ====================================  ======  ==========================
++
++Request constains only one bitset which can be either value/mask pair (request
++to change specific feature bits and leave the rest) or only a value (request
++to set all features to specified set).
++
++As request is subject to netdev_change_features() sanity checks, optional
++kernel reply (can be suppressed by ``ETHTOOL_FLAG_OMIT_REPLY`` flag in request
++header) informs client about the actual result. ``ETHTOOL_A_FEATURES_WANTED``
++reports the difference between client request and actual result: mask consists
++of bits which differ between requested features and result (dev->features
++after the operation), value consists of values of these bits in the request
++(i.e. negated values from resulting features). ``ETHTOOL_A_FEATURES_ACTIVE``
++reports the difference between old and new dev->features: mask consists of
++bits which have changed, values are their values in new dev->features (after
++the operation).
++
++``ETHTOOL_MSG_FEATURES_NTF`` notification is sent not only if device features
++are modified using ``ETHTOOL_MSG_FEATURES_SET`` request or on of ethtool ioctl
++request but also each time features are modified with netdev_update_features()
++or netdev_change_features().
++
++
++PRIVFLAGS_GET
++=============
++
++Gets private flags like ``ETHTOOL_GPFLAGS`` ioctl request.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_PRIVFLAGS_HEADER``        nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_PRIVFLAGS_HEADER``        nested  reply header
++  ``ETHTOOL_A_PRIVFLAGS_FLAGS``         bitset  private flags
++  ====================================  ======  ==========================
++
++``ETHTOOL_A_PRIVFLAGS_FLAGS`` is a bitset with values of device private flags.
++These flags are defined by driver, their number and names (and also meaning)
++are device dependent. For compact bitset format, names can be retrieved as
++``ETH_SS_PRIV_FLAGS`` string set. If verbose bitset format is requested,
++response uses all private flags supported by the device as mask so that client
++gets the full information without having to fetch the string set with names.
++
++
++PRIVFLAGS_SET
++=============
++
++Sets or modifies values of device private flags like ``ETHTOOL_SPFLAGS``
++ioctl request.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_PRIVFLAGS_HEADER``        nested  request header
++  ``ETHTOOL_A_PRIVFLAGS_FLAGS``         bitset  private flags
++  ====================================  ======  ==========================
++
++``ETHTOOL_A_PRIVFLAGS_FLAGS`` can either set the whole set of private flags or
++modify only values of some of them.
++
++
++RINGS_GET
++=========
++
++Gets ring sizes like ``ETHTOOL_GRINGPARAM`` ioctl request.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_RINGS_HEADER``            nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_RINGS_HEADER``            nested  reply header
++  ``ETHTOOL_A_RINGS_RX_MAX``            u32     max size of RX ring
++  ``ETHTOOL_A_RINGS_RX_MINI_MAX``       u32     max size of RX mini ring
++  ``ETHTOOL_A_RINGS_RX_JUMBO_MAX``      u32     max size of RX jumbo ring
++  ``ETHTOOL_A_RINGS_TX_MAX``            u32     max size of TX ring
++  ``ETHTOOL_A_RINGS_RX``                u32     size of RX ring
++  ``ETHTOOL_A_RINGS_RX_MINI``           u32     size of RX mini ring
++  ``ETHTOOL_A_RINGS_RX_JUMBO``          u32     size of RX jumbo ring
++  ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
++  ====================================  ======  ==========================
++
++
++RINGS_SET
++=========
++
++Sets ring sizes like ``ETHTOOL_SRINGPARAM`` ioctl request.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_RINGS_HEADER``            nested  reply header
++  ``ETHTOOL_A_RINGS_RX``                u32     size of RX ring
++  ``ETHTOOL_A_RINGS_RX_MINI``           u32     size of RX mini ring
++  ``ETHTOOL_A_RINGS_RX_JUMBO``          u32     size of RX jumbo ring
++  ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
++  ====================================  ======  ==========================
++
++Kernel checks that requested ring sizes do not exceed limits reported by
++driver. Driver may impose additional constraints and may not suspport all
++attributes.
++
++
++CHANNELS_GET
++============
++
++Gets channel counts like ``ETHTOOL_GCHANNELS`` ioctl request.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_CHANNELS_HEADER``         nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_CHANNELS_HEADER``          nested  reply header
++  ``ETHTOOL_A_CHANNELS_RX_MAX``          u32     max receive channels
++  ``ETHTOOL_A_CHANNELS_TX_MAX``          u32     max transmit channels
++  ``ETHTOOL_A_CHANNELS_OTHER_MAX``       u32     max other channels
++  ``ETHTOOL_A_CHANNELS_COMBINED_MAX``    u32     max combined channels
++  ``ETHTOOL_A_CHANNELS_RX_COUNT``        u32     receive channel count
++  ``ETHTOOL_A_CHANNELS_TX_COUNT``        u32     transmit channel count
++  ``ETHTOOL_A_CHANNELS_OTHER_COUNT``     u32     other channel count
++  ``ETHTOOL_A_CHANNELS_COMBINED_COUNT``  u32     combined channel count
++  =====================================  ======  ==========================
++
++
++CHANNELS_SET
++============
++
++Sets channel counts like ``ETHTOOL_SCHANNELS`` ioctl request.
++
++Request contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_CHANNELS_HEADER``          nested  request header
++  ``ETHTOOL_A_CHANNELS_RX_COUNT``        u32     receive channel count
++  ``ETHTOOL_A_CHANNELS_TX_COUNT``        u32     transmit channel count
++  ``ETHTOOL_A_CHANNELS_OTHER_COUNT``     u32     other channel count
++  ``ETHTOOL_A_CHANNELS_COMBINED_COUNT``  u32     combined channel count
++  =====================================  ======  ==========================
++
++Kernel checks that requested channel counts do not exceed limits reported by
++driver. Driver may impose additional constraints and may not suspport all
++attributes.
++
++
++COALESCE_GET
++============
++
++Gets coalescing parameters like ``ETHTOOL_GCOALESCE`` ioctl request.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_COALESCE_HEADER``         nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ===========================================  ======  =======================
++  ``ETHTOOL_A_COALESCE_HEADER``                nested  reply header
++  ``ETHTOOL_A_COALESCE_RX_USECS``              u32     delay (us), normal Rx
++  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES``         u32     max packets, normal Rx
++  ``ETHTOOL_A_COALESCE_RX_USECS_IRQ``          u32     delay (us), Rx in IRQ
++  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ``     u32     max packets, Rx in IRQ
++  ``ETHTOOL_A_COALESCE_TX_USECS``              u32     delay (us), normal Tx
++  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES``         u32     max packets, normal Tx
++  ``ETHTOOL_A_COALESCE_TX_USECS_IRQ``          u32     delay (us), Tx in IRQ
++  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ``     u32     IRQ packets, Tx in IRQ
++  ``ETHTOOL_A_COALESCE_STATS_BLOCK_USECS``     u32     delay of stats update
++  ``ETHTOOL_A_COALESCE_USE_ADAPTIVE_RX``       bool    adaptive Rx coalesce
++  ``ETHTOOL_A_COALESCE_USE_ADAPTIVE_TX``       bool    adaptive Tx coalesce
++  ``ETHTOOL_A_COALESCE_PKT_RATE_LOW``          u32     threshold for low rate
++  ``ETHTOOL_A_COALESCE_RX_USECS_LOW``          u32     delay (us), low Rx
++  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW``     u32     max packets, low Rx
++  ``ETHTOOL_A_COALESCE_TX_USECS_LOW``          u32     delay (us), low Tx
++  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW``     u32     max packets, low Tx
++  ``ETHTOOL_A_COALESCE_PKT_RATE_HIGH``         u32     threshold for high rate
++  ``ETHTOOL_A_COALESCE_RX_USECS_HIGH``         u32     delay (us), high Rx
++  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH``    u32     max packets, high Rx
++  ``ETHTOOL_A_COALESCE_TX_USECS_HIGH``         u32     delay (us), high Tx
++  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH``    u32     max packets, high Tx
++  ``ETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL``  u32     rate sampling interval
++  ===========================================  ======  =======================
++
++Attributes are only included in reply if their value is not zero or the
++corresponding bit in ``ethtool_ops::supported_coalesce_params`` is set (i.e.
++they are declared as supported by driver).
++
++
++COALESCE_SET
++============
++
++Sets coalescing parameters like ``ETHTOOL_SCOALESCE`` ioctl request.
++
++Request contents:
++
++  ===========================================  ======  =======================
++  ``ETHTOOL_A_COALESCE_HEADER``                nested  request header
++  ``ETHTOOL_A_COALESCE_RX_USECS``              u32     delay (us), normal Rx
++  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES``         u32     max packets, normal Rx
++  ``ETHTOOL_A_COALESCE_RX_USECS_IRQ``          u32     delay (us), Rx in IRQ
++  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ``     u32     max packets, Rx in IRQ
++  ``ETHTOOL_A_COALESCE_TX_USECS``              u32     delay (us), normal Tx
++  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES``         u32     max packets, normal Tx
++  ``ETHTOOL_A_COALESCE_TX_USECS_IRQ``          u32     delay (us), Tx in IRQ
++  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ``     u32     IRQ packets, Tx in IRQ
++  ``ETHTOOL_A_COALESCE_STATS_BLOCK_USECS``     u32     delay of stats update
++  ``ETHTOOL_A_COALESCE_USE_ADAPTIVE_RX``       bool    adaptive Rx coalesce
++  ``ETHTOOL_A_COALESCE_USE_ADAPTIVE_TX``       bool    adaptive Tx coalesce
++  ``ETHTOOL_A_COALESCE_PKT_RATE_LOW``          u32     threshold for low rate
++  ``ETHTOOL_A_COALESCE_RX_USECS_LOW``          u32     delay (us), low Rx
++  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW``     u32     max packets, low Rx
++  ``ETHTOOL_A_COALESCE_TX_USECS_LOW``          u32     delay (us), low Tx
++  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW``     u32     max packets, low Tx
++  ``ETHTOOL_A_COALESCE_PKT_RATE_HIGH``         u32     threshold for high rate
++  ``ETHTOOL_A_COALESCE_RX_USECS_HIGH``         u32     delay (us), high Rx
++  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH``    u32     max packets, high Rx
++  ``ETHTOOL_A_COALESCE_TX_USECS_HIGH``         u32     delay (us), high Tx
++  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH``    u32     max packets, high Tx
++  ``ETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL``  u32     rate sampling interval
++  ===========================================  ======  =======================
++
++Request is rejected if it attributes declared as unsupported by driver (i.e.
++such that the corresponding bit in ``ethtool_ops::supported_coalesce_params``
++is not set), regardless of their values. Driver may impose additional
++constraints on coalescing parameters and their values.
++
++
++PAUSE_GET
++============
++
++Gets channel counts like ``ETHTOOL_GPAUSE`` ioctl request.
++
++Request contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_PAUSE_HEADER``             nested  request header
++  =====================================  ======  ==========================
++
++Kernel response contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_PAUSE_HEADER``             nested  request header
++  ``ETHTOOL_A_PAUSE_AUTONEG``            bool    pause autonegotiation
++  ``ETHTOOL_A_PAUSE_RX``                 bool    receive pause frames
++  ``ETHTOOL_A_PAUSE_TX``                 bool    transmit pause frames
++  ``ETHTOOL_A_PAUSE_STATS``              nested  pause statistics
++  =====================================  ======  ==========================
++
++``ETHTOOL_A_PAUSE_STATS`` are reported if ``ETHTOOL_FLAG_STATS`` was set
++in ``ETHTOOL_A_HEADER_FLAGS``.
++It will be empty if driver did not report any statistics. Drivers fill in
++the statistics in the following structure:
++
++.. kernel-doc:: include/linux/ethtool.h
++    :identifiers: ethtool_pause_stats
++
++Each member has a corresponding attribute defined.
++
++PAUSE_SET
++============
++
++Sets pause parameters like ``ETHTOOL_GPAUSEPARAM`` ioctl request.
++
++Request contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_PAUSE_HEADER``             nested  request header
++  ``ETHTOOL_A_PAUSE_AUTONEG``            bool    pause autonegotiation
++  ``ETHTOOL_A_PAUSE_RX``                 bool    receive pause frames
++  ``ETHTOOL_A_PAUSE_TX``                 bool    transmit pause frames
++  =====================================  ======  ==========================
++
++
++EEE_GET
++=======
++
++Gets channel counts like ``ETHTOOL_GEEE`` ioctl request.
++
++Request contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_EEE_HEADER``               nested  request header
++  =====================================  ======  ==========================
++
++Kernel response contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_EEE_HEADER``               nested  request header
++  ``ETHTOOL_A_EEE_MODES_OURS``           bool    supported/advertised modes
++  ``ETHTOOL_A_EEE_MODES_PEER``           bool    peer advertised link modes
++  ``ETHTOOL_A_EEE_ACTIVE``               bool    EEE is actively used
++  ``ETHTOOL_A_EEE_ENABLED``              bool    EEE is enabled
++  ``ETHTOOL_A_EEE_TX_LPI_ENABLED``       bool    Tx lpi enabled
++  ``ETHTOOL_A_EEE_TX_LPI_TIMER``         u32     Tx lpi timeout (in us)
++  =====================================  ======  ==========================
++
++In ``ETHTOOL_A_EEE_MODES_OURS``, mask consists of link modes for which EEE is
++enabled, value of link modes for which EEE is advertised. Link modes for which
++peer advertises EEE are listed in ``ETHTOOL_A_EEE_MODES_PEER`` (no mask). The
++netlink interface allows reporting EEE status for all link modes but only
++first 32 are provided by the ``ethtool_ops`` callback.
++
++
++EEE_SET
++=======
++
++Sets pause parameters like ``ETHTOOL_GEEEPARAM`` ioctl request.
++
++Request contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_EEE_HEADER``               nested  request header
++  ``ETHTOOL_A_EEE_MODES_OURS``           bool    advertised modes
++  ``ETHTOOL_A_EEE_ENABLED``              bool    EEE is enabled
++  ``ETHTOOL_A_EEE_TX_LPI_ENABLED``       bool    Tx lpi enabled
++  ``ETHTOOL_A_EEE_TX_LPI_TIMER``         u32     Tx lpi timeout (in us)
++  =====================================  ======  ==========================
++
++``ETHTOOL_A_EEE_MODES_OURS`` is used to either list link modes to advertise
++EEE for (if there is no mask) or specify changes to the list (if there is
++a mask). The netlink interface allows reporting EEE status for all link modes
++but only first 32 can be set at the moment as that is what the ``ethtool_ops``
++callback supports.
++
++
++TSINFO_GET
++==========
++
++Gets timestamping information like ``ETHTOOL_GET_TS_INFO`` ioctl request.
++
++Request contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_TSINFO_HEADER``            nested  request header
++  =====================================  ======  ==========================
++
++Kernel response contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_TSINFO_HEADER``            nested  request header
++  ``ETHTOOL_A_TSINFO_TIMESTAMPING``      bitset  SO_TIMESTAMPING flags
++  ``ETHTOOL_A_TSINFO_TX_TYPES``          bitset  supported Tx types
++  ``ETHTOOL_A_TSINFO_RX_FILTERS``        bitset  supported Rx filters
++  ``ETHTOOL_A_TSINFO_PHC_INDEX``         u32     PTP hw clock index
++  =====================================  ======  ==========================
++
++``ETHTOOL_A_TSINFO_PHC_INDEX`` is absent if there is no associated PHC (there
++is no special value for this case). The bitset attributes are omitted if they
++would be empty (no bit set).
++
++CABLE_TEST
++==========
++
++Start a cable test.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_CABLE_TEST_HEADER``       nested  request header
++  ====================================  ======  ==========================
++
++Notification contents:
++
++An Ethernet cable typically contains 1, 2 or 4 pairs. The length of
++the pair can only be measured when there is a fault in the pair and
++hence a reflection. Information about the fault may not be available,
++depending on the specific hardware. Hence the contents of the notify
++message are mostly optional. The attributes can be repeated an
++arbitrary number of times, in an arbitrary order, for an arbitrary
++number of pairs.
++
++The example shows the notification sent when the test is completed for
++a T2 cable, i.e. two pairs. One pair is OK and hence has no length
++information. The second pair has a fault and does have length
++information.
++
++ +---------------------------------------------+--------+---------------------+
++ | ``ETHTOOL_A_CABLE_TEST_HEADER``             | nested | reply header        |
++ +---------------------------------------------+--------+---------------------+
++ | ``ETHTOOL_A_CABLE_TEST_STATUS``             | u8     | completed           |
++ +---------------------------------------------+--------+---------------------+
++ | ``ETHTOOL_A_CABLE_TEST_NTF_NEST``           | nested | all the results     |
++ +-+-------------------------------------------+--------+---------------------+
++ | | ``ETHTOOL_A_CABLE_NEST_RESULT``           | nested | cable test result   |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | | ``ETHTOOL_A_CABLE_RESULTS_PAIR``        | u8     | pair number         |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | | ``ETHTOOL_A_CABLE_RESULTS_CODE``        | u8     | result code         |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | ``ETHTOOL_A_CABLE_NEST_RESULT``           | nested | cable test results  |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | | ``ETHTOOL_A_CABLE_RESULTS_PAIR``        | u8     | pair number         |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | | ``ETHTOOL_A_CABLE_RESULTS_CODE``        | u8     | result code         |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | ``ETHTOOL_A_CABLE_NEST_FAULT_LENGTH``     | nested | cable length        |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | | ``ETHTOOL_A_CABLE_FAULT_LENGTH_PAIR``   | u8     | pair number         |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | | ``ETHTOOL_A_CABLE_FAULT_LENGTH_CM``     | u32    | length in cm        |
++ +-+-+-----------------------------------------+--------+---------------------+
++
++CABLE_TEST TDR
++==============
++
++Start a cable test and report raw TDR data
++
++Request contents:
++
++ +--------------------------------------------+--------+-----------------------+
++ | ``ETHTOOL_A_CABLE_TEST_TDR_HEADER``        | nested | reply header          |
++ +--------------------------------------------+--------+-----------------------+
++ | ``ETHTOOL_A_CABLE_TEST_TDR_CFG``           | nested | test configuration    |
++ +-+------------------------------------------+--------+-----------------------+
++ | | ``ETHTOOL_A_CABLE_STEP_FIRST_DISTANCE``  | u32    | first data distance   |
++ +-+-+----------------------------------------+--------+-----------------------+
++ | | ``ETHTOOL_A_CABLE_STEP_LAST_DISTANCE``   | u32    | last data distance    |
++ +-+-+----------------------------------------+--------+-----------------------+
++ | | ``ETHTOOL_A_CABLE_STEP_STEP_DISTANCE``   | u32    | distance of each step |
++ +-+-+----------------------------------------+--------+-----------------------+
++ | | ``ETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR``    | u8     | pair to test          |
++ +-+-+----------------------------------------+--------+-----------------------+
++
++The ETHTOOL_A_CABLE_TEST_TDR_CFG is optional, as well as all members
++of the nest. All distances are expressed in centimeters. The PHY takes
++the distances as a guide, and rounds to the nearest distance it
++actually supports. If a pair is passed, only that one pair will be
++tested. Otherwise all pairs are tested.
++
++Notification contents:
++
++Raw TDR data is gathered by sending a pulse down the cable and
++recording the amplitude of the reflected pulse for a given distance.
++
++It can take a number of seconds to collect TDR data, especial if the
++full 100 meters is probed at 1 meter intervals. When the test is
++started a notification will be sent containing just
++ETHTOOL_A_CABLE_TEST_TDR_STATUS with the value
++ETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED.
++
++When the test has completed a second notification will be sent
++containing ETHTOOL_A_CABLE_TEST_TDR_STATUS with the value
++ETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED and the TDR data.
++
++The message may optionally contain the amplitude of the pulse send
++down the cable. This is measured in mV. A reflection should not be
++bigger than transmitted pulse.
++
++Before the raw TDR data should be an ETHTOOL_A_CABLE_TDR_NEST_STEP
++nest containing information about the distance along the cable for the
++first reading, the last reading, and the step between each
++reading. Distances are measured in centimeters. These should be the
++exact values the PHY used. These may be different to what the user
++requested, if the native measurement resolution is greater than 1 cm.
++
++For each step along the cable, a ETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE is
++used to report the amplitude of the reflection for a given pair.
++
++ +---------------------------------------------+--------+----------------------+
++ | ``ETHTOOL_A_CABLE_TEST_TDR_HEADER``         | nested | reply header         |
++ +---------------------------------------------+--------+----------------------+
++ | ``ETHTOOL_A_CABLE_TEST_TDR_STATUS``         | u8     | completed            |
++ +---------------------------------------------+--------+----------------------+
++ | ``ETHTOOL_A_CABLE_TEST_TDR_NTF_NEST``       | nested | all the results      |
++ +-+-------------------------------------------+--------+----------------------+
++ | | ``ETHTOOL_A_CABLE_TDR_NEST_PULSE``        | nested | TX Pulse amplitude   |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | | ``ETHTOOL_A_CABLE_PULSE_mV``            | s16    | Pulse amplitude      |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | ``ETHTOOL_A_CABLE_NEST_STEP``             | nested | TDR step info        |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | | ``ETHTOOL_A_CABLE_STEP_FIRST_DISTANCE`` | u32    | First data distance  |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | | ``ETHTOOL_A_CABLE_STEP_LAST_DISTANCE``  | u32    | Last data distance   |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | | ``ETHTOOL_A_CABLE_STEP_STEP_DISTANCE``  | u32    | distance of each step|
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | ``ETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE``    | nested | Reflection amplitude |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | | ``ETHTOOL_A_CABLE_RESULTS_PAIR``        | u8     | pair number          |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | | ``ETHTOOL_A_CABLE_AMPLITUDE_mV``        | s16    | Reflection amplitude |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | ``ETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE``    | nested | Reflection amplitude |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | | ``ETHTOOL_A_CABLE_RESULTS_PAIR``        | u8     | pair number          |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | | ``ETHTOOL_A_CABLE_AMPLITUDE_mV``        | s16    | Reflection amplitude |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | ``ETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE``    | nested | Reflection amplitude |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | | ``ETHTOOL_A_CABLE_RESULTS_PAIR``        | u8     | pair number          |
++ +-+-+-----------------------------------------+--------+----------------------+
++ | | | ``ETHTOOL_A_CABLE_AMPLITUDE_mV``        | s16    | Reflection amplitude |
++ +-+-+-----------------------------------------+--------+----------------------+
++
++TUNNEL_INFO
++===========
++
++Gets information about the tunnel state NIC is aware of.
++
++Request contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_TUNNEL_INFO_HEADER``       nested  request header
++  =====================================  ======  ==========================
++
++Kernel response contents:
++
++ +---------------------------------------------+--------+---------------------+
++ | ``ETHTOOL_A_TUNNEL_INFO_HEADER``            | nested | reply header        |
++ +---------------------------------------------+--------+---------------------+
++ | ``ETHTOOL_A_TUNNEL_INFO_UDP_PORTS``         | nested | all UDP port tables |
++ +-+-------------------------------------------+--------+---------------------+
++ | | ``ETHTOOL_A_TUNNEL_UDP_TABLE``            | nested | one UDP port table  |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | | ``ETHTOOL_A_TUNNEL_UDP_TABLE_SIZE``     | u32    | max size of the     |
++ | | |                                         |        | table               |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | | ``ETHTOOL_A_TUNNEL_UDP_TABLE_TYPES``    | bitset | tunnel types which  |
++ | | |                                         |        | table can hold      |
++ +-+-+-----------------------------------------+--------+---------------------+
++ | | | ``ETHTOOL_A_TUNNEL_UDP_TABLE_ENTRY``    | nested | offloaded UDP port  |
++ +-+-+-+---------------------------------------+--------+---------------------+
++ | | | | ``ETHTOOL_A_TUNNEL_UDP_ENTRY_PORT``   | be16   | UDP port            |
++ +-+-+-+---------------------------------------+--------+---------------------+
++ | | | | ``ETHTOOL_A_TUNNEL_UDP_ENTRY_TYPE``   | u32    | tunnel type         |
++ +-+-+-+---------------------------------------+--------+---------------------+
++
++For UDP tunnel table empty ``ETHTOOL_A_TUNNEL_UDP_TABLE_TYPES`` indicates that
++the table contains static entries, hard-coded by the NIC.
++
++Request translation
++===================
++
++The following table maps ioctl commands to netlink commands providing their
++functionality. Entries with "n/a" in right column are commands which do not
++have their netlink replacement yet. Entries which "n/a" in the left column
++are netlink only.
++
++  =================================== =====================================
++  ioctl command                       netlink command
++  =================================== =====================================
++  ``ETHTOOL_GSET``                    ``ETHTOOL_MSG_LINKINFO_GET``
++                                      ``ETHTOOL_MSG_LINKMODES_GET``
++  ``ETHTOOL_SSET``                    ``ETHTOOL_MSG_LINKINFO_SET``
++                                      ``ETHTOOL_MSG_LINKMODES_SET``
++  ``ETHTOOL_GDRVINFO``                n/a
++  ``ETHTOOL_GREGS``                   n/a
++  ``ETHTOOL_GWOL``                    ``ETHTOOL_MSG_WOL_GET``
++  ``ETHTOOL_SWOL``                    ``ETHTOOL_MSG_WOL_SET``
++  ``ETHTOOL_GMSGLVL``                 ``ETHTOOL_MSG_DEBUG_GET``
++  ``ETHTOOL_SMSGLVL``                 ``ETHTOOL_MSG_DEBUG_SET``
++  ``ETHTOOL_NWAY_RST``                n/a
++  ``ETHTOOL_GLINK``                   ``ETHTOOL_MSG_LINKSTATE_GET``
++  ``ETHTOOL_GEEPROM``                 n/a
++  ``ETHTOOL_SEEPROM``                 n/a
++  ``ETHTOOL_GCOALESCE``               ``ETHTOOL_MSG_COALESCE_GET``
++  ``ETHTOOL_SCOALESCE``               ``ETHTOOL_MSG_COALESCE_SET``
++  ``ETHTOOL_GRINGPARAM``              ``ETHTOOL_MSG_RINGS_GET``
++  ``ETHTOOL_SRINGPARAM``              ``ETHTOOL_MSG_RINGS_SET``
++  ``ETHTOOL_GPAUSEPARAM``             ``ETHTOOL_MSG_PAUSE_GET``
++  ``ETHTOOL_SPAUSEPARAM``             ``ETHTOOL_MSG_PAUSE_SET``
++  ``ETHTOOL_GRXCSUM``                 ``ETHTOOL_MSG_FEATURES_GET``
++  ``ETHTOOL_SRXCSUM``                 ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GTXCSUM``                 ``ETHTOOL_MSG_FEATURES_GET``
++  ``ETHTOOL_STXCSUM``                 ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GSG``                     ``ETHTOOL_MSG_FEATURES_GET``
++  ``ETHTOOL_SSG``                     ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_TEST``                    n/a
++  ``ETHTOOL_GSTRINGS``                ``ETHTOOL_MSG_STRSET_GET``
++  ``ETHTOOL_PHYS_ID``                 n/a
++  ``ETHTOOL_GSTATS``                  n/a
++  ``ETHTOOL_GTSO``                    ``ETHTOOL_MSG_FEATURES_GET``
++  ``ETHTOOL_STSO``                    ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GPERMADDR``               rtnetlink ``RTM_GETLINK``
++  ``ETHTOOL_GUFO``                    ``ETHTOOL_MSG_FEATURES_GET``
++  ``ETHTOOL_SUFO``                    ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GGSO``                    ``ETHTOOL_MSG_FEATURES_GET``
++  ``ETHTOOL_SGSO``                    ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GFLAGS``                  ``ETHTOOL_MSG_FEATURES_GET``
++  ``ETHTOOL_SFLAGS``                  ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GPFLAGS``                 ``ETHTOOL_MSG_PRIVFLAGS_GET``
++  ``ETHTOOL_SPFLAGS``                 ``ETHTOOL_MSG_PRIVFLAGS_SET``
++  ``ETHTOOL_GRXFH``                   n/a
++  ``ETHTOOL_SRXFH``                   n/a
++  ``ETHTOOL_GGRO``                    ``ETHTOOL_MSG_FEATURES_GET``
++  ``ETHTOOL_SGRO``                    ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GRXRINGS``                n/a
++  ``ETHTOOL_GRXCLSRLCNT``             n/a
++  ``ETHTOOL_GRXCLSRULE``              n/a
++  ``ETHTOOL_GRXCLSRLALL``             n/a
++  ``ETHTOOL_SRXCLSRLDEL``             n/a
++  ``ETHTOOL_SRXCLSRLINS``             n/a
++  ``ETHTOOL_FLASHDEV``                n/a
++  ``ETHTOOL_RESET``                   n/a
++  ``ETHTOOL_SRXNTUPLE``               n/a
++  ``ETHTOOL_GRXNTUPLE``               n/a
++  ``ETHTOOL_GSSET_INFO``              ``ETHTOOL_MSG_STRSET_GET``
++  ``ETHTOOL_GRXFHINDIR``              n/a
++  ``ETHTOOL_SRXFHINDIR``              n/a
++  ``ETHTOOL_GFEATURES``               ``ETHTOOL_MSG_FEATURES_GET``
++  ``ETHTOOL_SFEATURES``               ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GCHANNELS``               ``ETHTOOL_MSG_CHANNELS_GET``
++  ``ETHTOOL_SCHANNELS``               ``ETHTOOL_MSG_CHANNELS_SET``
++  ``ETHTOOL_SET_DUMP``                n/a
++  ``ETHTOOL_GET_DUMP_FLAG``           n/a
++  ``ETHTOOL_GET_DUMP_DATA``           n/a
++  ``ETHTOOL_GET_TS_INFO``             ``ETHTOOL_MSG_TSINFO_GET``
++  ``ETHTOOL_GMODULEINFO``             n/a
++  ``ETHTOOL_GMODULEEEPROM``           n/a
++  ``ETHTOOL_GEEE``                    ``ETHTOOL_MSG_EEE_GET``
++  ``ETHTOOL_SEEE``                    ``ETHTOOL_MSG_EEE_SET``
++  ``ETHTOOL_GRSSH``                   n/a
++  ``ETHTOOL_SRSSH``                   n/a
++  ``ETHTOOL_GTUNABLE``                n/a
++  ``ETHTOOL_STUNABLE``                n/a
++  ``ETHTOOL_GPHYSTATS``               n/a
++  ``ETHTOOL_PERQUEUE``                n/a
++  ``ETHTOOL_GLINKSETTINGS``           ``ETHTOOL_MSG_LINKINFO_GET``
++                                      ``ETHTOOL_MSG_LINKMODES_GET``
++  ``ETHTOOL_SLINKSETTINGS``           ``ETHTOOL_MSG_LINKINFO_SET``
++                                      ``ETHTOOL_MSG_LINKMODES_SET``
++  ``ETHTOOL_PHY_GTUNABLE``            n/a
++  ``ETHTOOL_PHY_STUNABLE``            n/a
++  ``ETHTOOL_GFECPARAM``               n/a
++  ``ETHTOOL_SFECPARAM``               n/a
++  n/a                                 ''ETHTOOL_MSG_CABLE_TEST_ACT''
++  n/a                                 ''ETHTOOL_MSG_CABLE_TEST_TDR_ACT''
++  n/a                                 ``ETHTOOL_MSG_TUNNEL_INFO_GET``
++  =================================== =====================================
+-- 
+2.34.1
+
diff --git a/patches/0460-ethtool-add-two-link-extended-substates-of-bad-signa.patch b/patches/0460-ethtool-add-two-link-extended-substates-of-bad-signa.patch
new file mode 100644
index 0000000..fca3de3
--- /dev/null
+++ b/patches/0460-ethtool-add-two-link-extended-substates-of-bad-signa.patch
@@ -0,0 +1,123 @@
+From b63dbee6334e1890f68376bf0ec734a2ef0f604c Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sat, 21 Aug 2021 17:00:39 +0800
+Subject: [PATCH 099/283] ethtool: add two link extended substates of bad
+ signal integrity
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 5b4ecc3d4c4aab8d002fe6358885c10e7b57e432
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5b4ecc3d4c4aab8d002fe6358885c10e7b57e432
+
+----------------------------------------------------------------------
+
+ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST means the input
+external clock signal for SerDes is too weak or lost.
+
+ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS means the received signal for
+SerDes is too weak because analog loss of signal.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+(fix conflicts: replace the last line by "/**")
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	include/uapi/linux/ethtool.h
+---
+ include/uapi/linux/ethtool.h | 72 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 72 insertions(+)
+
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index 4a43996de6d0..43ac4af42346 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -553,6 +553,78 @@ struct ethtool_pauseparam {
+ 	__u32	tx_pause;
+ };
+ 
++/**
++ * enum ethtool_link_ext_state - link extended state
++ */
++enum ethtool_link_ext_state {
++	ETHTOOL_LINK_EXT_STATE_AUTONEG,
++	ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
++	ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
++	ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
++	ETHTOOL_LINK_EXT_STATE_NO_CABLE,
++	ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
++	ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE,
++	ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE,
++	ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED,
++	ETHTOOL_LINK_EXT_STATE_OVERHEAT,
++};
++
++/**
++ * enum ethtool_link_ext_substate_autoneg - more information in addition to
++ * ETHTOOL_LINK_EXT_STATE_AUTONEG.
++ */
++enum ethtool_link_ext_substate_autoneg {
++	ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1,
++	ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED,
++	ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED,
++	ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE,
++	ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE,
++	ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD,
++};
++
++/**
++ * enum ethtool_link_ext_substate_link_training - more information
++ * in addition to ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE.
++ */
++enum ethtool_link_ext_substate_link_training {
++	ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1,
++	ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT,
++	ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY,
++	ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT,
++};
++
++/**
++ * enum ethtool_link_ext_substate_logical_mismatch - more information
++ * in addition to ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH.
++ */
++enum ethtool_link_ext_substate_link_logical_mismatch {
++	ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1,
++	ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK,
++	ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS,
++	ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED,
++	ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED,
++};
++
++/**
++ * enum ethtool_link_ext_substate_bad_signal_integrity - more information in
++ * addition to ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY.
++ */
++enum ethtool_link_ext_substate_bad_signal_integrity {
++	ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1,
++	ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE,
++	ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST,
++	ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS,
++};
++
++/**
++ * enum ethtool_link_ext_substate_cable_issue - more information in
++ * addition to ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE.
++ */
++enum ethtool_link_ext_substate_cable_issue {
++	ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1,
++	ETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE,
++};
++
+ #define ETH_GSTRING_LEN		32
+ 
+ /**
+-- 
+2.34.1
+
diff --git a/patches/0461-net-hns3-add-header-file-hns3_ethtoo.h.patch b/patches/0461-net-hns3-add-header-file-hns3_ethtoo.h.patch
new file mode 100644
index 0000000..12c1dab
--- /dev/null
+++ b/patches/0461-net-hns3-add-header-file-hns3_ethtoo.h.patch
@@ -0,0 +1,104 @@
+From 1218ed8abcc882c290e50e71d16bb799ab8f7603 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sat, 21 Aug 2021 17:00:40 +0800
+Subject: [PATCH 100/283] net: hns3: add header file hns3_ethtoo.h
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit edb40bbc17eb589beb3cbd672d341e1505d6cdb1
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=edb40bbc17eb589beb3cbd672d341e1505d6cdb1
+
+----------------------------------------------------------------------
+
+Add a new file hns3_ethtool.h, and move struct type definitions from
+hns3_ethtool.c to hns3_ethtool.h.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+---
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 24 ++++--------------
+ .../ethernet/hisilicon/hns3/hns3_ethtool.h    | 25 +++++++++++++++++++
+ 2 files changed, 30 insertions(+), 19 deletions(-)
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.h
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 4197d40471f4..d4d5474d0f09 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -6,26 +6,12 @@
+ #include <linux/phy.h>
+ #include "kcompat.h"
+ #include "hns3_enet.h"
++#include "hns3_ethtool.h"
+ 
+-struct hns3_stats {
+-	char stats_string[ETH_GSTRING_LEN];
+-	int stats_offset;
+-};
+-
+-#define HNS3_MODULE_TYPE_QSFP		0x0C
+-#define HNS3_MODULE_TYPE_QSFP_P		0x0D
+-#define HNS3_MODULE_TYPE_QSFP_28	0x11
+-#define HNS3_MODULE_TYPE_SFP		0x03
+-
+-struct hns3_sfp_type {
+-	u8 type;
+-	u8 ext_type;
+-};
+-
+-struct hns3_pflag_desc {
+-	char name[ETH_GSTRING_LEN];
+-	void (*handler)(struct net_device *netdev, bool enable);
+-};
++#define HNS3_MODULE_TYPE_QSFP         0x0C
++#define HNS3_MODULE_TYPE_QSFP_P       0x0D
++#define HNS3_MODULE_TYPE_QSFP_28      0x11
++#define HNS3_MODULE_TYPE_SFP          0x03
+ 
+ /* tqp related stats */
+ #define HNS3_TQP_STAT(_string, _member)	{			\
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.h
+new file mode 100644
+index 000000000000..2f186607c6e0
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.h
+@@ -0,0 +1,25 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++// Copyright (c) 2021 Hisilicon Limited.
++
++#ifndef __HNS3_ETHTOOL_H
++#define __HNS3_ETHTOOL_H
++
++#include <linux/ethtool.h>
++#include <linux/netdevice.h>
++
++struct hns3_stats {
++	char stats_string[ETH_GSTRING_LEN];
++	int stats_offset;
++};
++
++struct hns3_sfp_type {
++	u8 type;
++	u8 ext_type;
++};
++
++struct hns3_pflag_desc {
++	char name[ETH_GSTRING_LEN];
++	void (*handler)(struct net_device *netdev, bool enable);
++};
++
++#endif
+-- 
+2.34.1
+
diff --git a/patches/0462-net-hns3-add-support-ethtool-extended-link-state.patch b/patches/0462-net-hns3-add-support-ethtool-extended-link-state.patch
new file mode 100644
index 0000000..79a1ef7
--- /dev/null
+++ b/patches/0462-net-hns3-add-support-ethtool-extended-link-state.patch
@@ -0,0 +1,247 @@
+From 88a0023ce8e2fd3c7cc21032690517968fee03f6 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Sat, 21 Aug 2021 17:00:41 +0800
+Subject: [PATCH 101/283] net: hns3: add support ethtool extended link state
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit f5c2b9f0fc078308a88de807d60cd4e352a165fc
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f5c2b9f0fc078308a88de807d60cd4e352a165fc
+
+----------------------------------------------------------------------
+
+In order to know the reason of link up failure, add supporting ethtool
+extended link state. Driver reads the link status code from firmware if
+in link down state and converts it to ethtool extended link state.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  2 +
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 66 +++++++++++++++++++
+ .../ethernet/hisilicon/hns3/hns3_ethtool.h    |  6 ++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  3 +
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 24 +++++++
+ include/linux/ethtool.h                       | 19 ++++++
+ 6 files changed, 120 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 58022716456d..918b86a9cf88 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -729,6 +729,8 @@ struct hnae3_ae_ops {
+ 			    u32 nsec, u32 sec);
+ 	int (*get_ts_info)(struct hnae3_handle *handle,
+ 			   struct ethtool_ts_info *info);
++	int (*get_link_diagnosis_info)(struct hnae3_handle *handle,
++				       u32 *status_code);
+ /* Notice! If the function is not for test, the definition must before
+  * CONFIG_HNS3_TEST! Because RoCE will use this head file, and it won't
+  * set CONFIG_HNS3_TEST, that may cause RoCE calling the wrong function.
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index d4d5474d0f09..1c3d3036de35 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1723,6 +1723,71 @@ static int hns3_get_ts_info(struct net_device *netdev,
+ 	return ethtool_op_get_ts_info(netdev, info);
+ }
+ 
++static const struct hns3_ethtool_link_ext_state_mapping
++hns3_link_ext_state_map[] = {
++	{1, ETHTOOL_LINK_EXT_STATE_AUTONEG,
++		ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD},
++	{2, ETHTOOL_LINK_EXT_STATE_AUTONEG,
++		ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED},
++
++	{256, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
++		ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT},
++	{257, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
++		ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY},
++	{512, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
++		ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT},
++
++	{513, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
++		ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK},
++	{514, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
++		ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED},
++	{515, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
++		ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED},
++
++	{768, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
++		ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS},
++	{769, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
++		ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST},
++	{770, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
++		ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS},
++
++	{1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0},
++	{1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
++		ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
++
++	{1026, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0},
++};
++
++static int hns3_get_link_ext_state(struct net_device *netdev,
++				   struct ethtool_link_ext_state_info *info)
++{
++	const struct hns3_ethtool_link_ext_state_mapping *map;
++	struct hnae3_handle *h = hns3_get_handle(netdev);
++	u32 status_code, i;
++	int ret;
++
++	if (netif_carrier_ok(netdev))
++		return -ENODATA;
++
++	if (!h->ae_algo->ops->get_link_diagnosis_info)
++		return -EOPNOTSUPP;
++
++	ret = h->ae_algo->ops->get_link_diagnosis_info(h, &status_code);
++	if (ret)
++		return ret;
++
++	for (i = 0; i < ARRAY_SIZE(hns3_link_ext_state_map); i++) {
++		map = &hns3_link_ext_state_map[i];
++		if (map->status_code == status_code) {
++			info->link_ext_state = map->link_ext_state;
++			info->__link_ext_substate = map->link_ext_substate;
++			return 0;
++		}
++	}
++
++	return -ENODATA;
++}
++
+ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ 	.supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
+ 	.get_drvinfo = hns3_get_drvinfo,
+@@ -1794,6 +1859,7 @@ static const struct ethtool_ops hns3_ethtool_ops = {
+ 	.get_tunable = hns3_get_tunable,
+ 	.set_tunable = hns3_set_tunable,
+ 	.reset = hns3_set_reset,
++	.get_link_ext_state = hns3_get_link_ext_state,
+ };
+ 
+ void hns3_ethtool_set_ops(struct net_device *netdev)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.h
+index 2f186607c6e0..822d6fcbc73b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.h
+@@ -22,4 +22,10 @@ struct hns3_pflag_desc {
+ 	void (*handler)(struct net_device *netdev, bool enable);
+ };
+ 
++struct hns3_ethtool_link_ext_state_mapping {
++	u32 status_code;
++	enum ethtool_link_ext_state link_ext_state;
++	u8 link_ext_substate;
++};
++
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 75cf58c5f0b3..5daf24ca0e4e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -321,6 +321,9 @@ enum hclge_opcode_type {
+ 	/* PHY command */
+ 	HCLGE_OPC_PHY_LINK_KSETTING	= 0x7025,
+ 	HCLGE_OPC_PHY_REG		= 0x7026,
++
++	/* Query link diagnosis info command */
++	HCLGE_OPC_QUERY_LINK_DIAGNOSIS	= 0x702A,
+ };
+ 
+ #define HCLGE_TQP_REG_OFFSET		0x80000
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 359c6fc4ca1d..480519de4992 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -12028,6 +12028,29 @@ static int hclge_get_module_eeprom(struct hnae3_handle *handle, u32 offset,
+ 	return 0;
+ }
+ 
++static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle,
++					 u32 *status_code)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_dev *hdev = vport->back;
++	struct hclge_desc desc;
++	int ret;
++
++	if (hdev->ae_dev->dev_version <= HNAE3_DEVICE_VERSION_V2)
++		return -EOPNOTSUPP;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_DIAGNOSIS, true);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to query link diagnosis info, ret = %d\n", ret);
++		return ret;
++	}
++
++	*status_code = le32_to_cpu(desc.data[0]);
++	return 0;
++}
++
+ struct hnae3_ae_ops hclge_ops = {
+ 	.init_ae_dev = hclge_init_ae_dev,
+ 	.uninit_ae_dev = hclge_uninit_ae_dev,
+@@ -12129,6 +12152,7 @@ struct hnae3_ae_ops hclge_ops = {
+ 	.set_tx_hwts_info = hclge_ptp_set_tx_info,
+ 	.get_rx_hwts = hclge_ptp_get_rx_hwts,
+ 	.get_ts_info = hclge_ptp_get_ts_info,
++	.get_link_diagnosis_info = hclge_get_link_diagnosis_info,
+ };
+ 
+ static struct hnae3_ae_algo ae_algo = {
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 65c244c2dc97..4154522d8497 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -87,6 +87,21 @@ struct net_device;
+ u32 ethtool_op_get_link(struct net_device *dev);
+ int ethtool_op_get_ts_info(struct net_device *dev, struct ethtool_ts_info *eti);
+ 
++/**
++ * struct ethtool_link_ext_state_info - link extended state and substate.
++ */
++struct ethtool_link_ext_state_info {
++	enum ethtool_link_ext_state link_ext_state;
++	union {
++		enum ethtool_link_ext_substate_autoneg autoneg;
++		enum ethtool_link_ext_substate_link_training link_training;
++		enum ethtool_link_ext_substate_link_logical_mismatch link_logical_mismatch;
++		enum ethtool_link_ext_substate_bad_signal_integrity bad_signal_integrity;
++		enum ethtool_link_ext_substate_cable_issue cable_issue;
++		u8 __link_ext_substate;
++	};
++};
++
+ /**
+  * ethtool_rxfh_indir_default - get default value for RX flow hash indirection
+  * @index: Index in RX flow hash indirection table
+@@ -381,6 +396,10 @@ struct ethtool_ops {
+ 	void	(*set_msglevel)(struct net_device *, u32);
+ 	int	(*nway_reset)(struct net_device *);
+ 	u32	(*get_link)(struct net_device *);
++#ifndef __GENKSYMS__
++	int	(*get_link_ext_state)(struct net_device *,
++				      struct ethtool_link_ext_state_info *);
++#endif
+ 	int	(*get_eeprom_len)(struct net_device *);
+ 	int	(*get_eeprom)(struct net_device *,
+ 			      struct ethtool_eeprom *, u8 *);
+-- 
+2.34.1
+
diff --git a/patches/0463-net-hns3-fix-speed-unknown-issue-in-bond-4.patch b/patches/0463-net-hns3-fix-speed-unknown-issue-in-bond-4.patch
new file mode 100644
index 0000000..c076431
--- /dev/null
+++ b/patches/0463-net-hns3-fix-speed-unknown-issue-in-bond-4.patch
@@ -0,0 +1,55 @@
+From 478e6e390f04d085a24f557ee11306bc1396cfa7 Mon Sep 17 00:00:00 2001
+From: Yonglong Liu <liuyonglong@huawei.com>
+Date: Fri, 10 Sep 2021 20:00:03 +0800
+Subject: [PATCH 102/283] net: hns3: fix speed unknown issue in bond 4
+
+mainline inclusion
+from mainline-v5.14
+commit b15c072a9f4a404c09ad589477f4389034742a8b
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b15c072a9f4a404c09ad589477f4389034742a8b
+
+----------------------------------------------------------------------
+
+In bond 4, when the link goes down and up repeatedly, the bond may get an
+unknown speed, and then this port can not work.
+
+The driver notify netif_carrier_on() before update the link state, when the
+bond receive carrier on, will query the speed of the port, if the query
+operation happens before updating the link state, will get an unknown
+speed. So need to notify netif_carrier_on() after update the link state.
+
+Fixes: 46a3df9f9718 ("net: hns3: Add HNS3 Acceleration Engine & Compatibility Layer Support")
+Fixes: e2cb1dec9779 ("net: hns3: Add HNS3 VF HCL(Hardware Compatibility Layer) Support")
+Signed-off-by: Yonglong Liu <liuyonglong@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+index ec2b4e653893..244b83e22f53 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+@@ -343,6 +343,7 @@ void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev)
+ 			/* update upper layer with new link link status */
+ 			hclgevf_update_speed_duplex(hdev, speed, duplex);
+ 			hclgevf_update_link_status(hdev, link_status);
++
+ 			if (flag & HCLGE_MBX_PUSH_LINK_STATUS_EN)
+ 				set_bit(HCLGEVF_STATE_PF_PUSH_LINK_STATUS,
+ 					&hdev->state);
+-- 
+2.34.1
+
diff --git a/patches/0464-net-hns3-fix-GRO-configuration-error-after-reset.patch b/patches/0464-net-hns3-fix-GRO-configuration-error-after-reset.patch
new file mode 100644
index 0000000..2d5aa30
--- /dev/null
+++ b/patches/0464-net-hns3-fix-GRO-configuration-error-after-reset.patch
@@ -0,0 +1,193 @@
+From e8879f80b867db69e3c017432e89c60cf63d5233 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Fri, 10 Sep 2021 20:00:06 +0800
+Subject: [PATCH 103/283] net: hns3: fix GRO configuration error after reset
+
+mainline inclusion
+from mainline-v5.14
+commit 3462207d2d684658d97499ca77c00c9ac7c87ea8
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3462207d2d684658d97499ca77c00c9ac7c87ea8
+
+----------------------------------------------------------------------
+
+The GRO configuration is enabled by default after reset. This
+is incorrect and should be restored to the user-configured value.
+So this restoration is added during reset initialization.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 18 +++++++++++++-----
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  1 +
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 19 ++++++++++++++-----
+ .../hisilicon/hns3/hns3vf/hclgevf_main.h      |  2 ++
+ 4 files changed, 30 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 480519de4992..e8937e67ea47 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1483,6 +1483,7 @@ static int hclge_configure(struct hclge_dev *hdev)
+ 	hdev->tm_info.hw_pfc_map = 0;
+ 	hdev->wanted_umv_size = cfg.umv_space;
+ 	hdev->tx_spare_buf_size = cfg.tx_spare_buf_size;
++	hdev->gro_en = true;
+ 	if (cfg.vlan_fliter_cap == HCLGE_VLAN_FLTR_CAN_MDF)
+ 		hnae3_set_bit(ae_dev->flag,
+ 			      HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, 1);
+@@ -1553,7 +1554,7 @@ static int hclge_config_tso(struct hclge_dev *hdev, u16 tso_mss_min,
+ 	return hclge_cmd_send(&hdev->hw, &desc, 1);
+ }
+ 
+-static int hclge_config_gro(struct hclge_dev *hdev, bool en)
++static int hclge_config_gro(struct hclge_dev *hdev)
+ {
+ 	struct hclge_cfg_gro_status_cmd *req;
+ 	struct hclge_desc desc;
+@@ -1565,7 +1566,7 @@ static int hclge_config_gro(struct hclge_dev *hdev, bool en)
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GRO_GENERIC_CONFIG, false);
+ 	req = (struct hclge_cfg_gro_status_cmd *)desc.data;
+ 
+-	req->gro_en = en ? 1 : 0;
++	req->gro_en = hdev->gro_en ? 1 : 0;
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret)
+@@ -10753,7 +10754,7 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 		goto err_mdiobus_unreg;
+ 	}
+ 
+-	ret = hclge_config_gro(hdev, true);
++	ret = hclge_config_gro(hdev);
+ 	if (ret)
+ 		goto err_mdiobus_unreg;
+ 
+@@ -11128,7 +11129,7 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 		return ret;
+ 	}
+ 
+-	ret = hclge_config_gro(hdev, true);
++	ret = hclge_config_gro(hdev);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -11871,8 +11872,15 @@ static int hclge_gro_en(struct hnae3_handle *handle, bool enable)
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
++	bool gro_en_old = hdev->gro_en;
++	int ret;
++
++	hdev->gro_en = enable;
++	ret = hclge_config_gro(hdev);
++	if (ret)
++		hdev->gro_en = gro_en_old;
+ 
+-	return hclge_config_gro(hdev, enable);
++	return ret;
+ }
+ 
+ static void hclge_sync_promisc_mode(struct hclge_dev *hdev)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index e04488bb7278..eda3120be294 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -876,6 +876,7 @@ struct hclge_dev {
+ 	unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
+ 	enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
+ 	u8 fd_en;
++	bool gro_en;
+ 
+ 	u16 wanted_umv_size;
+ 	/* max available unicast mac vlan space */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 4cab9c19031a..edaac904b991 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -2431,6 +2431,8 @@ static int hclgevf_configure(struct hclgevf_dev *hdev)
+ {
+ 	int ret;
+ 
++	hdev->gro_en = true;
++
+ 	ret = hclgevf_get_basic_info(hdev);
+ 	if (ret)
+ 		return ret;
+@@ -2492,7 +2494,7 @@ static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
+ 	return 0;
+ }
+ 
+-static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en)
++static int hclgevf_config_gro(struct hclgevf_dev *hdev)
+ {
+ 	struct hclgevf_cfg_gro_status_cmd *req;
+ 	struct hclgevf_desc desc;
+@@ -2505,7 +2507,7 @@ static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en)
+ 				     false);
+ 	req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
+ 
+-	req->gro_en = en ? 1 : 0;
++	req->gro_en = hdev->gro_en ? 1 : 0;
+ 
+ 	ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret)
+@@ -3181,7 +3183,7 @@ static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
+ 		return ret;
+ 	}
+ 
+-	ret = hclgevf_config_gro(hdev, true);
++	ret = hclgevf_config_gro(hdev);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -3260,7 +3262,7 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
+ 	if (ret)
+ 		goto err_config;
+ 
+-	ret = hclgevf_config_gro(hdev, true);
++	ret = hclgevf_config_gro(hdev);
+ 	if (ret)
+ 		goto err_config;
+ 
+@@ -3505,8 +3507,15 @@ void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
+ static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)
+ {
+ 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
++	bool gro_en_old = hdev->gro_en;
++	int ret;
+ 
+-	return hclgevf_config_gro(hdev, enable);
++	hdev->gro_en = enable;
++	ret = hclgevf_config_gro(hdev);
++	if (ret)
++		hdev->gro_en = gro_en_old;
++
++	return ret;
+ }
+ 
+ static void hclgevf_get_media_type(struct hnae3_handle *handle, u8 *media_type,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index e75e1b437585..fd83b80ed913 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -306,6 +306,8 @@ struct hclgevf_dev {
+ 	u16 *vector_status;
+ 	int *vector_irq;
+ 
++	bool gro_en;
++
+ 	unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
+ 
+ 	struct hclgevf_mac_table_cfg mac_table;
+-- 
+2.34.1
+
diff --git a/patches/0465-net-hns3-add-macros-for-mac-speeds-of-firmware-comma.patch b/patches/0465-net-hns3-add-macros-for-mac-speeds-of-firmware-comma.patch
new file mode 100644
index 0000000..d0882ef
--- /dev/null
+++ b/patches/0465-net-hns3-add-macros-for-mac-speeds-of-firmware-comma.patch
@@ -0,0 +1,170 @@
+From c2d68c8d8c58d761ecf66d36d69e459ba46a2f34 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 28 Sep 2021 11:51:54 +0800
+Subject: [PATCH 104/283] net: hns3: add macros for mac speeds of firmware
+ command
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 4c116f85ecf8c147450602ed47ee25de60807f45
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4c116f85ecf8c147450602ed47ee25de60807f45
+
+----------------------------------------------------------------------
+
+To improve code readability, replace digital numbers of mac speeds
+defined by firmware command with macros.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         | 13 +++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 39 +++++++++++--------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  3 +-
+ 3 files changed, 38 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 5daf24ca0e4e..c8e8ca961c53 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -1196,6 +1196,19 @@ struct hclge_dev_specs_1_cmd {
+ 	u8 rsv1[18];
+ };
+ 
++/* mac speed type defined in firmware command */
++enum HCLGE_FIRMWARE_MAC_SPEED {
++	HCLGE_FW_MAC_SPEED_1G,
++	HCLGE_FW_MAC_SPEED_10G,
++	HCLGE_FW_MAC_SPEED_25G,
++	HCLGE_FW_MAC_SPEED_40G,
++	HCLGE_FW_MAC_SPEED_50G,
++	HCLGE_FW_MAC_SPEED_100G,
++	HCLGE_FW_MAC_SPEED_10M,
++	HCLGE_FW_MAC_SPEED_100M,
++	HCLGE_FW_MAC_SPEED_200G,
++};
++
+ #define HCLGE_PHY_LINK_SETTING_BD_NUM		2
+ 
+ struct hclge_phy_link_ksetting_0_cmd {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index e8937e67ea47..ecbf9487b977 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -942,30 +942,33 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
+ static int hclge_parse_speed(u8 speed_cmd, u32 *speed)
+ {
+ 	switch (speed_cmd) {
+-	case 6:
++	case HCLGE_FW_MAC_SPEED_10M:
+ 		*speed = HCLGE_MAC_SPEED_10M;
+ 		break;
+-	case 7:
++	case HCLGE_FW_MAC_SPEED_100M:
+ 		*speed = HCLGE_MAC_SPEED_100M;
+ 		break;
+-	case 0:
++	case HCLGE_FW_MAC_SPEED_1G:
+ 		*speed = HCLGE_MAC_SPEED_1G;
+ 		break;
+-	case 1:
++	case HCLGE_FW_MAC_SPEED_10G:
+ 		*speed = HCLGE_MAC_SPEED_10G;
+ 		break;
+-	case 2:
++	case HCLGE_FW_MAC_SPEED_25G:
+ 		*speed = HCLGE_MAC_SPEED_25G;
+ 		break;
+-	case 3:
++	case HCLGE_FW_MAC_SPEED_40G:
+ 		*speed = HCLGE_MAC_SPEED_40G;
+ 		break;
+-	case 4:
++	case HCLGE_FW_MAC_SPEED_50G:
+ 		*speed = HCLGE_MAC_SPEED_50G;
+ 		break;
+-	case 5:
++	case HCLGE_FW_MAC_SPEED_100G:
+ 		*speed = HCLGE_MAC_SPEED_100G;
+ 		break;
++	case HCLGE_FW_MAC_SPEED_200G:
++		*speed = HCLGE_MAC_SPEED_200G;
++		break;
+ 	default:
+ 		return -EINVAL;
+ 	}
+@@ -2503,35 +2506,39 @@ int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
+ 	switch (speed) {
+ 	case HCLGE_MAC_SPEED_10M:
+ 		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
+-				HCLGE_CFG_SPEED_S, 6);
++				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_10M);
+ 		break;
+ 	case HCLGE_MAC_SPEED_100M:
+ 		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
+-				HCLGE_CFG_SPEED_S, 7);
++				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_100M);
+ 		break;
+ 	case HCLGE_MAC_SPEED_1G:
+ 		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
+-				HCLGE_CFG_SPEED_S, 0);
++				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_1G);
+ 		break;
+ 	case HCLGE_MAC_SPEED_10G:
+ 		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
+-				HCLGE_CFG_SPEED_S, 1);
++				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_10G);
+ 		break;
+ 	case HCLGE_MAC_SPEED_25G:
+ 		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
+-				HCLGE_CFG_SPEED_S, 2);
++				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_25G);
+ 		break;
+ 	case HCLGE_MAC_SPEED_40G:
+ 		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
+-				HCLGE_CFG_SPEED_S, 3);
++				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_40G);
+ 		break;
+ 	case HCLGE_MAC_SPEED_50G:
+ 		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
+-				HCLGE_CFG_SPEED_S, 4);
++				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_50G);
+ 		break;
+ 	case HCLGE_MAC_SPEED_100G:
+ 		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
+-				HCLGE_CFG_SPEED_S, 5);
++				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_100G);
++		break;
++	case HCLGE_MAC_SPEED_200G:
++		hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
++				HCLGE_CFG_SPEED_S, HCLGE_FW_MAC_SPEED_200G);
+ 		break;
+ 	default:
+ 		dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index eda3120be294..9dacd7136ed9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -253,7 +253,8 @@ enum HCLGE_MAC_SPEED {
+ 	HCLGE_MAC_SPEED_25G	= 25000,	/* 25000 Mbps  = 25 Gbps */
+ 	HCLGE_MAC_SPEED_40G	= 40000,	/* 40000 Mbps  = 40 Gbps */
+ 	HCLGE_MAC_SPEED_50G	= 50000,	/* 50000 Mbps  = 50 Gbps */
+-	HCLGE_MAC_SPEED_100G	= 100000	/* 100000 Mbps = 100 Gbps */
++	HCLGE_MAC_SPEED_100G	= 100000,	/* 100000 Mbps = 100 Gbps */
++	HCLGE_MAC_SPEED_200G	= 200000	/* 200000 Mbps = 200 Gbps */
+ };
+ 
+ enum HCLGE_MAC_DUPLEX {
+-- 
+2.34.1
+
diff --git a/patches/0466-net-hns3-add-hns3_state_init-to-do-state-initializat.patch b/patches/0466-net-hns3-add-hns3_state_init-to-do-state-initializat.patch
new file mode 100644
index 0000000..066dcef
--- /dev/null
+++ b/patches/0466-net-hns3-add-hns3_state_init-to-do-state-initializat.patch
@@ -0,0 +1,115 @@
+From b24c67622d6c333dfdce0df94266d3fc9a6e7e4f Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Tue, 28 Sep 2021 11:51:55 +0800
+Subject: [PATCH 105/283] net: hns3: add hns3_state_init() to do state
+ initialization
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit c511dfff4b655685d7341962a76d9a340150e0ac
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c511dfff4b655685d7341962a76d9a340150e0ac
+
+----------------------------------------------------------------------
+
+To improve the readability and maintainability, add hns3_state_init() to
+initialize the state, and this new function will be used to add more state
+initialization in the future.
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  3 +++
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 27 +++++++++++++------
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  2 ++
+ 3 files changed, 24 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 918b86a9cf88..d6063645896a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -144,6 +144,9 @@ enum HNAE3_DEV_CAP_BITS {
+ #define hnae3_dev_stash_supported(hdev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
+ 
++#define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \
++	test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps)
++
+ enum HNAE3_PF_CAP_BITS {
+ 	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
+ };
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 046c696df091..72f26221ee6c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -4681,10 +4681,27 @@ static void hns3_state_uninit(struct hnae3_handle *handle)
+ 	clear_bit(HNS3_NIC_STATE_INITED, &priv->state);
+ }
+ 
++static void hns3_state_init(struct hnae3_handle *handle)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
++	struct net_device *netdev = handle->kinfo.netdev;
++	struct hns3_nic_priv *priv = netdev_priv(netdev);
++
++	set_bit(HNS3_NIC_STATE_INITED, &priv->state);
++
++	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
++		set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
++
++	if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
++		set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
++
++	if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
++		set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
++}
++
+ static int hns3_client_init(struct hnae3_handle *handle)
+ {
+ 	struct pci_dev *pdev = handle->pdev;
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
+ 	u16 alloc_tqps, max_rss_size;
+ 	struct hns3_nic_priv *priv;
+ 	struct net_device *netdev;
+@@ -4783,13 +4800,7 @@ static int hns3_client_init(struct hnae3_handle *handle)
+ 	netdev->max_mtu = HNS3_MAX_MTU;
+ #endif
+ 
+-	if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
+-		set_bit(HNS3_NIC_STATE_HW_TX_CSUM_ENABLE, &priv->state);
+-
+-	set_bit(HNS3_NIC_STATE_INITED, &priv->state);
+-
+-	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
+-		set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
++	hns3_state_init(handle);
+ 
+ 	ret = register_netdev(netdev);
+ 	if (ret) {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 416c0c44b11d..3df794363632 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -19,6 +19,8 @@ enum hns3_nic_state {
+ 	HNS3_NIC_STATE_SERVICE_SCHED,
+ 	HNS3_NIC_STATE2_RESET_REQUESTED,
+ 	HNS3_NIC_STATE_HW_TX_CSUM_ENABLE,
++	HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE,
++	HNS3_NIC_STATE_TX_PUSH_ENABLE,
+ 	HNS3_NIC_STATE_MAX
+ };
+ 
+-- 
+2.34.1
+
diff --git a/patches/0467-net-hns3-use-memcpy-to-simplify-code.patch b/patches/0467-net-hns3-use-memcpy-to-simplify-code.patch
new file mode 100644
index 0000000..25e727d
--- /dev/null
+++ b/patches/0467-net-hns3-use-memcpy-to-simplify-code.patch
@@ -0,0 +1,60 @@
+From 3efcdbc96a9e44d11a381e2700d3e66c7077dbfc Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Tue, 28 Sep 2021 11:51:57 +0800
+Subject: [PATCH 106/283] net: hns3: use memcpy to simplify code
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 304cd8e776ddca5021dd9c1d7603ea40afc48ec6
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=304cd8e776ddca5021dd9c1d7603ea40afc48ec6
+
+----------------------------------------------------------------------
+
+Use memcpy to copy req->msg.resp_data to resp->additional_info,
+to simplify the code and improve a little efficiency.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c | 9 ++-------
+ 1 file changed, 2 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+index 244b83e22f53..41e303a42a9d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+@@ -189,8 +189,6 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
+ 	struct hclgevf_desc *desc;
+ 	u16 *msg_q;
+ 	u16 flag;
+-	u8 *temp;
+-	int i;
+ 
+ 	resp = &hdev->mbx_resp;
+ 	crq = &hdev->hw.cmq.crq;
+@@ -237,11 +235,8 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
+ 			resp->resp_status =
+ 				hclgevf_resp_to_errno(req->msg.resp_status);
+ 
+-			temp = (u8 *)req->msg.resp_data;
+-			for (i = 0; i < HCLGE_MBX_MAX_RESP_DATA_SIZE; i++) {
+-				resp->additional_info[i] = *temp;
+-				temp++;
+-			}
++			memcpy(resp->additional_info, req->msg.resp_data,
++			       HCLGE_MBX_MAX_RESP_DATA_SIZE * sizeof(u8));
+ 
+ 			/* ensure additional_info will be seen before setting
+ 			 * received_resp
+-- 
+2.34.1
+
diff --git a/patches/0468-net-hns3-remove-redundant-param-to-simplify-code.patch b/patches/0468-net-hns3-remove-redundant-param-to-simplify-code.patch
new file mode 100644
index 0000000..7d43020
--- /dev/null
+++ b/patches/0468-net-hns3-remove-redundant-param-to-simplify-code.patch
@@ -0,0 +1,56 @@
+From 84238b8c14fea96afc910475692a83e4f6eafa16 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Tue, 28 Sep 2021 11:51:58 +0800
+Subject: [PATCH 107/283] net: hns3: remove redundant param to simplify code
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 5f22a80f32deed391011f7ab3ce8951ea89282f8
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5f22a80f32deed391011f7ab3ce8951ea89282f8
+
+----------------------------------------------------------------------
+
+The param msg_q is redundant, copy &req->msg to
+hdev->arq.msg_q[hdev->arq.tail] directly makes code clean.
+So removes the redundant param msg_q.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+index 41e303a42a9d..995321058a70 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+@@ -187,7 +187,6 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
+ 	struct hclge_mbx_pf_to_vf_cmd *req;
+ 	struct hclgevf_cmq_ring *crq;
+ 	struct hclgevf_desc *desc;
+-	u16 *msg_q;
+ 	u16 flag;
+ 
+ 	resp = &hdev->mbx_resp;
+@@ -273,8 +272,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
+ 			}
+ 
+ 			/* tail the async message in arq */
+-			msg_q = hdev->arq.msg_q[hdev->arq.tail];
+-			memcpy(&msg_q[0], &req->msg,
++			memcpy(hdev->arq.msg_q[hdev->arq.tail], &req->msg,
+ 			       HCLGE_MBX_MAX_ARQ_MSG_SIZE * sizeof(u16));
+ 			hclge_mbx_tail_ptr_move_arq(hdev->arq);
+ 			atomic_inc(&hdev->arq.count);
+-- 
+2.34.1
+
diff --git a/patches/0469-net-hns3-package-new-functions-to-simplify-hclgevf_m.patch b/patches/0469-net-hns3-package-new-functions-to-simplify-hclgevf_m.patch
new file mode 100644
index 0000000..58df0b0
--- /dev/null
+++ b/patches/0469-net-hns3-package-new-functions-to-simplify-hclgevf_m.patch
@@ -0,0 +1,176 @@
+From f13115e21001b7e99a243c5ac949f0a4c378862f Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Tue, 28 Sep 2021 11:51:59 +0800
+Subject: [PATCH 108/283] net: hns3: package new functions to simplify
+ hclgevf_mbx_handler code
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit d7517f8f6b3b12c883ca0975659450ae009b1524
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d7517f8f6b3b12c883ca0975659450ae009b1524
+
+----------------------------------------------------------------------
+
+This patch packages two new function to simplify the function
+hclgevf_mbx_handler, and it can reduce the code cycle complexity
+and make code more concise.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+---
+ .../hisilicon/hns3/hns3vf/hclgevf_mbx.c       | 107 +++++++++---------
+ 1 file changed, 55 insertions(+), 52 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+index 995321058a70..510d9826e998 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+@@ -181,15 +181,66 @@ static bool hclgevf_cmd_crq_empty(struct hclgevf_hw *hw)
+ 	return tail == hw->cmq.crq.next_to_use;
+ }
+ 
++static void hclgevf_handle_mbx_response(struct hclgevf_dev *hdev,
++					struct hclge_mbx_pf_to_vf_cmd *req)
++{
++	struct hclgevf_mbx_resp_status *resp = &hdev->mbx_resp;
++
++	if (resp->received_resp)
++		dev_warn(&hdev->pdev->dev,
++			 "VF mbx resp flag not clear(%u)\n",
++			 req->msg.vf_mbx_msg_code);
++
++	resp->origin_mbx_msg =
++			(req->msg.vf_mbx_msg_code << 16);
++	resp->origin_mbx_msg |= req->msg.vf_mbx_msg_subcode;
++	resp->resp_status =
++		hclgevf_resp_to_errno(req->msg.resp_status);
++	memcpy(resp->additional_info, req->msg.resp_data,
++	       HCLGE_MBX_MAX_RESP_DATA_SIZE * sizeof(u8));
++	if (req->match_id) {
++		/* If match_id is not zero, it means PF support match_id.
++		 * if the match_id is right, VF get the right response, or
++		 * ignore the response. and driver will clear hdev->mbx_resp
++		 * when send next message which need response.
++		 */
++		if (req->match_id == resp->match_id)
++			resp->received_resp = true;
++	} else {
++		resp->received_resp = true;
++	}
++}
++
++static void hclgevf_handle_mbx_msg(struct hclgevf_dev *hdev,
++				   struct hclge_mbx_pf_to_vf_cmd *req)
++{
++	/* we will drop the async msg if we find ARQ as full
++	 * and continue with next message
++	 */
++	if (atomic_read(&hdev->arq.count) >=
++	    HCLGE_MBX_MAX_ARQ_MSG_NUM) {
++		dev_warn(&hdev->pdev->dev,
++			 "Async Q full, dropping msg(%u)\n",
++			 req->msg.code);
++		return;
++	}
++
++	/* tail the async message in arq */
++	memcpy(hdev->arq.msg_q[hdev->arq.tail], &req->msg,
++	       HCLGE_MBX_MAX_ARQ_MSG_SIZE * sizeof(u16));
++	hclge_mbx_tail_ptr_move_arq(hdev->arq);
++	atomic_inc(&hdev->arq.count);
++
++	hclgevf_mbx_task_schedule(hdev);
++}
++
+ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
+ {
+-	struct hclgevf_mbx_resp_status *resp;
+ 	struct hclge_mbx_pf_to_vf_cmd *req;
+ 	struct hclgevf_cmq_ring *crq;
+ 	struct hclgevf_desc *desc;
+ 	u16 flag;
+ 
+-	resp = &hdev->mbx_resp;
+ 	crq = &hdev->hw.cmq.crq;
+ 
+ 	while (!hclgevf_cmd_crq_empty(&hdev->hw)) {
+@@ -223,62 +274,14 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
+ 		 */
+ 		switch (req->msg.code) {
+ 		case HCLGE_MBX_PF_VF_RESP:
+-			if (resp->received_resp)
+-				dev_warn(&hdev->pdev->dev,
+-					 "VF mbx resp flag not clear(%u)\n",
+-					 req->msg.vf_mbx_msg_code);
+-
+-			resp->origin_mbx_msg =
+-					(req->msg.vf_mbx_msg_code << 16);
+-			resp->origin_mbx_msg |= req->msg.vf_mbx_msg_subcode;
+-			resp->resp_status =
+-				hclgevf_resp_to_errno(req->msg.resp_status);
+-
+-			memcpy(resp->additional_info, req->msg.resp_data,
+-			       HCLGE_MBX_MAX_RESP_DATA_SIZE * sizeof(u8));
+-
+-			/* ensure additional_info will be seen before setting
+-			 * received_resp
+-			 */
+-			smp_wmb();
+-
+-			if (req->match_id) {
+-				/* If match_id is not zero, it means PF support
+-				 * match_id. If the match_id is right, VF get
+-				 * the right response, orignore the response,
+-				 * and driver will clear hdev->mbx_resp when
+-				 * send next message which need response.
+-				 */
+-				if (req->match_id == resp->match_id)
+-					resp->received_resp = true;
+-			} else {
+-				resp->received_resp = true;
+-			}
++			hclgevf_handle_mbx_response(hdev, req);
+ 			break;
+ 		case HCLGE_MBX_LINK_STAT_CHANGE:
+ 		case HCLGE_MBX_ASSERTING_RESET:
+ 		case HCLGE_MBX_LINK_STAT_MODE:
+ 		case HCLGE_MBX_PUSH_VLAN_INFO:
+ 		case HCLGE_MBX_PUSH_PROMISC_INFO:
+-			/* we will drop the async msg if we find ARQ as full
+-			 * and continue with next message
+-			 */
+-			if (atomic_read(&hdev->arq.count) >=
+-			    HCLGE_MBX_MAX_ARQ_MSG_NUM) {
+-				dev_warn(&hdev->pdev->dev,
+-					 "Async Q full, dropping msg(%u)\n",
+-					 req->msg.code);
+-				break;
+-			}
+-
+-			/* tail the async message in arq */
+-			memcpy(hdev->arq.msg_q[hdev->arq.tail], &req->msg,
+-			       HCLGE_MBX_MAX_ARQ_MSG_SIZE * sizeof(u16));
+-			hclge_mbx_tail_ptr_move_arq(hdev->arq);
+-			atomic_inc(&hdev->arq.count);
+-
+-			hclgevf_mbx_task_schedule(hdev);
+-
++			hclgevf_handle_mbx_msg(hdev, req);
+ 			break;
+ 		default:
+ 			dev_err(&hdev->pdev->dev,
+-- 
+2.34.1
+
diff --git a/patches/0470-net-hns3-merge-some-repetitive-macros.patch b/patches/0470-net-hns3-merge-some-repetitive-macros.patch
new file mode 100644
index 0000000..946d99f
--- /dev/null
+++ b/patches/0470-net-hns3-merge-some-repetitive-macros.patch
@@ -0,0 +1,229 @@
+From 33d4de4fddc8b2e9ab0a2fed5bf93878fd8733f0 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:00 +0800
+Subject: [PATCH 109/283] net: hns3: merge some repetitive macros
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 5a24b1fd301e0cf0fc58a76f2716c54d378002cf
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5a24b1fd301e0cf0fc58a76f2716c54d378002cf
+
+----------------------------------------------------------------------
+
+There are some repetitive macros have same meaning and value, this patch
+merges them to make code clean.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         | 10 ---------
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 22 +++++++++----------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        | 22 +++++++++----------
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       | 10 ---------
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 22 +++++++++----------
+ .../hisilicon/hns3/hns3vf/hclgevf_main.h      | 21 +++++++++---------
+ 6 files changed, 44 insertions(+), 63 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index c8e8ca961c53..71aaca36e5ea 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -1015,16 +1015,6 @@ struct hclge_common_lb_cmd {
+ 
+ #define HCLGE_TYPE_CRQ			0
+ #define HCLGE_TYPE_CSQ			1
+-#define HCLGE_NIC_CSQ_BASEADDR_L_REG	0x27000
+-#define HCLGE_NIC_CSQ_BASEADDR_H_REG	0x27004
+-#define HCLGE_NIC_CSQ_DEPTH_REG		0x27008
+-#define HCLGE_NIC_CSQ_TAIL_REG		0x27010
+-#define HCLGE_NIC_CSQ_HEAD_REG		0x27014
+-#define HCLGE_NIC_CRQ_BASEADDR_L_REG	0x27018
+-#define HCLGE_NIC_CRQ_BASEADDR_H_REG	0x2701c
+-#define HCLGE_NIC_CRQ_DEPTH_REG		0x27020
+-#define HCLGE_NIC_CRQ_TAIL_REG		0x27024
+-#define HCLGE_NIC_CRQ_HEAD_REG		0x27028
+ 
+ /* this bit indicates that the driver is ready for hardware reset */
+ #define HCLGE_NIC_SW_RST_RDY_B		16
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index ecbf9487b977..31fc09b28592 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -86,23 +86,23 @@ static const struct pci_device_id ae_algo_pci_tbl[] = {
+ 
+ MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
+ 
+-static const u32 cmdq_reg_addr_list[] = {HCLGE_CMDQ_TX_ADDR_L_REG,
+-					 HCLGE_CMDQ_TX_ADDR_H_REG,
+-					 HCLGE_CMDQ_TX_DEPTH_REG,
+-					 HCLGE_CMDQ_TX_TAIL_REG,
+-					 HCLGE_CMDQ_TX_HEAD_REG,
+-					 HCLGE_CMDQ_RX_ADDR_L_REG,
+-					 HCLGE_CMDQ_RX_ADDR_H_REG,
+-					 HCLGE_CMDQ_RX_DEPTH_REG,
+-					 HCLGE_CMDQ_RX_TAIL_REG,
+-					 HCLGE_CMDQ_RX_HEAD_REG,
++static const u32 cmdq_reg_addr_list[] = {HCLGE_NIC_CSQ_BASEADDR_L_REG,
++					 HCLGE_NIC_CSQ_BASEADDR_H_REG,
++					 HCLGE_NIC_CSQ_DEPTH_REG,
++					 HCLGE_NIC_CSQ_TAIL_REG,
++					 HCLGE_NIC_CSQ_HEAD_REG,
++					 HCLGE_NIC_CRQ_BASEADDR_L_REG,
++					 HCLGE_NIC_CRQ_BASEADDR_H_REG,
++					 HCLGE_NIC_CRQ_DEPTH_REG,
++					 HCLGE_NIC_CRQ_TAIL_REG,
++					 HCLGE_NIC_CRQ_HEAD_REG,
+ 					 HCLGE_VECTOR0_CMDQ_SRC_REG,
+ 					 HCLGE_CMDQ_INTR_STS_REG,
+ 					 HCLGE_CMDQ_INTR_EN_REG,
+ 					 HCLGE_CMDQ_INTR_GEN_REG};
+ 
+ static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
+-					   HCLGE_VECTOR0_OTER_EN_REG,
++					   HCLGE_PF_OTHER_INT_REG,
+ 					   HCLGE_MISC_RESET_STS_REG,
+ 					   HCLGE_MISC_VECTOR_INT_STS,
+ 					   HCLGE_GLOBAL_RESET_REG,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 9dacd7136ed9..5889bd069a69 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -35,22 +35,22 @@
+ #define HCLGE_VECTOR_REG_OFFSET		0x4
+ #define HCLGE_VECTOR_VF_OFFSET		0x100000
+ 
+-#define HCLGE_CMDQ_TX_ADDR_L_REG	0x27000
+-#define HCLGE_CMDQ_TX_ADDR_H_REG	0x27004
+-#define HCLGE_CMDQ_TX_DEPTH_REG		0x27008
+-#define HCLGE_CMDQ_TX_TAIL_REG		0x27010
+-#define HCLGE_CMDQ_TX_HEAD_REG		0x27014
+-#define HCLGE_CMDQ_RX_ADDR_L_REG	0x27018
+-#define HCLGE_CMDQ_RX_ADDR_H_REG	0x2701C
+-#define HCLGE_CMDQ_RX_DEPTH_REG		0x27020
+-#define HCLGE_CMDQ_RX_TAIL_REG		0x27024
+-#define HCLGE_CMDQ_RX_HEAD_REG		0x27028
++#define HCLGE_NIC_CSQ_BASEADDR_L_REG	0x27000
++#define HCLGE_NIC_CSQ_BASEADDR_H_REG	0x27004
++#define HCLGE_NIC_CSQ_DEPTH_REG		0x27008
++#define HCLGE_NIC_CSQ_TAIL_REG		0x27010
++#define HCLGE_NIC_CSQ_HEAD_REG		0x27014
++#define HCLGE_NIC_CRQ_BASEADDR_L_REG	0x27018
++#define HCLGE_NIC_CRQ_BASEADDR_H_REG	0x2701C
++#define HCLGE_NIC_CRQ_DEPTH_REG		0x27020
++#define HCLGE_NIC_CRQ_TAIL_REG		0x27024
++#define HCLGE_NIC_CRQ_HEAD_REG		0x27028
++
+ #define HCLGE_CMDQ_INTR_STS_REG		0x27104
+ #define HCLGE_CMDQ_INTR_EN_REG		0x27108
+ #define HCLGE_CMDQ_INTR_GEN_REG		0x2710C
+ 
+ /* bar registers for common func */
+-#define HCLGE_VECTOR0_OTER_EN_REG	0x20600
+ #define HCLGE_GRO_EN_REG		0x28000
+ 
+ /* bar registers for rcb */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 2e857063a6b1..6a018a189097 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -254,16 +254,6 @@ struct hclgevf_cfg_tx_queue_pointer_cmd {
+ 
+ #define HCLGEVF_TYPE_CRQ		0
+ #define HCLGEVF_TYPE_CSQ		1
+-#define HCLGEVF_NIC_CSQ_BASEADDR_L_REG	0x27000
+-#define HCLGEVF_NIC_CSQ_BASEADDR_H_REG	0x27004
+-#define HCLGEVF_NIC_CSQ_DEPTH_REG	0x27008
+-#define HCLGEVF_NIC_CSQ_TAIL_REG	0x27010
+-#define HCLGEVF_NIC_CSQ_HEAD_REG	0x27014
+-#define HCLGEVF_NIC_CRQ_BASEADDR_L_REG	0x27018
+-#define HCLGEVF_NIC_CRQ_BASEADDR_H_REG	0x2701c
+-#define HCLGEVF_NIC_CRQ_DEPTH_REG	0x27020
+-#define HCLGEVF_NIC_CRQ_TAIL_REG	0x27024
+-#define HCLGEVF_NIC_CRQ_HEAD_REG	0x27028
+ 
+ /* this bit indicates that the driver is ready for hardware reset */
+ #define HCLGEVF_NIC_SW_RST_RDY_B	16
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index edaac904b991..8386baf0a6a6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -39,16 +39,16 @@ static const u8 hclgevf_hash_key[] = {
+ 
+ MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
+ 
+-static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
+-					 HCLGEVF_CMDQ_TX_ADDR_H_REG,
+-					 HCLGEVF_CMDQ_TX_DEPTH_REG,
+-					 HCLGEVF_CMDQ_TX_TAIL_REG,
+-					 HCLGEVF_CMDQ_TX_HEAD_REG,
+-					 HCLGEVF_CMDQ_RX_ADDR_L_REG,
+-					 HCLGEVF_CMDQ_RX_ADDR_H_REG,
+-					 HCLGEVF_CMDQ_RX_DEPTH_REG,
+-					 HCLGEVF_CMDQ_RX_TAIL_REG,
+-					 HCLGEVF_CMDQ_RX_HEAD_REG,
++static const u32 cmdq_reg_addr_list[] = {HCLGEVF_NIC_CSQ_BASEADDR_L_REG,
++					 HCLGEVF_NIC_CSQ_BASEADDR_H_REG,
++					 HCLGEVF_NIC_CSQ_DEPTH_REG,
++					 HCLGEVF_NIC_CSQ_TAIL_REG,
++					 HCLGEVF_NIC_CSQ_HEAD_REG,
++					 HCLGEVF_NIC_CRQ_BASEADDR_L_REG,
++					 HCLGEVF_NIC_CRQ_BASEADDR_H_REG,
++					 HCLGEVF_NIC_CRQ_DEPTH_REG,
++					 HCLGEVF_NIC_CRQ_TAIL_REG,
++					 HCLGEVF_NIC_CRQ_HEAD_REG,
+ 					 HCLGEVF_VECTOR0_CMDQ_SRC_REG,
+ 					 HCLGEVF_VECTOR0_CMDQ_STATE_REG,
+ 					 HCLGEVF_CMDQ_INTR_EN_REG,
+@@ -1924,7 +1924,7 @@ static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
+ 	dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
+ 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
+ 	dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
+-		 hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG));
++		 hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG));
+ 	dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
+ 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
+ 	dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index fd83b80ed913..4498859e6ed4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -32,16 +32,17 @@
+ #define HCLGEVF_VECTOR_VF_OFFSET		0x100000
+ 
+ /* bar registers for cmdq */
+-#define HCLGEVF_CMDQ_TX_ADDR_L_REG		0x27000
+-#define HCLGEVF_CMDQ_TX_ADDR_H_REG		0x27004
+-#define HCLGEVF_CMDQ_TX_DEPTH_REG		0x27008
+-#define HCLGEVF_CMDQ_TX_TAIL_REG		0x27010
+-#define HCLGEVF_CMDQ_TX_HEAD_REG		0x27014
+-#define HCLGEVF_CMDQ_RX_ADDR_L_REG		0x27018
+-#define HCLGEVF_CMDQ_RX_ADDR_H_REG		0x2701C
+-#define HCLGEVF_CMDQ_RX_DEPTH_REG		0x27020
+-#define HCLGEVF_CMDQ_RX_TAIL_REG		0x27024
+-#define HCLGEVF_CMDQ_RX_HEAD_REG		0x27028
++#define HCLGEVF_NIC_CSQ_BASEADDR_L_REG		0x27000
++#define HCLGEVF_NIC_CSQ_BASEADDR_H_REG		0x27004
++#define HCLGEVF_NIC_CSQ_DEPTH_REG		0x27008
++#define HCLGEVF_NIC_CSQ_TAIL_REG		0x27010
++#define HCLGEVF_NIC_CSQ_HEAD_REG		0x27014
++#define HCLGEVF_NIC_CRQ_BASEADDR_L_REG		0x27018
++#define HCLGEVF_NIC_CRQ_BASEADDR_H_REG		0x2701C
++#define HCLGEVF_NIC_CRQ_DEPTH_REG		0x27020
++#define HCLGEVF_NIC_CRQ_TAIL_REG		0x27024
++#define HCLGEVF_NIC_CRQ_HEAD_REG		0x27028
++
+ #define HCLGEVF_CMDQ_INTR_EN_REG		0x27108
+ #define HCLGEVF_CMDQ_INTR_GEN_REG		0x2710C
+ 
+-- 
+2.34.1
+
diff --git a/patches/0471-net-hns3-uniform-type-of-function-parameter-cmd.patch b/patches/0471-net-hns3-uniform-type-of-function-parameter-cmd.patch
new file mode 100644
index 0000000..1945ce8
--- /dev/null
+++ b/patches/0471-net-hns3-uniform-type-of-function-parameter-cmd.patch
@@ -0,0 +1,50 @@
+From 7b89496da42e9a5324cc1313de3eb8a789085e78 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Tue, 28 Sep 2021 11:52:01 +0800
+Subject: [PATCH 110/283] net: hns3: uniform type of function parameter cmd
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 0c5c135cdbdacdf82ca537c433db07e4a1664065
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0c5c135cdbdacdf82ca537c433db07e4a1664065
+
+----------------------------------------------------------------------
+
+The parameter cmd in function definition of hns3_dbg_bd_file_init and
+hns3_dbg_common_file_init is used type u32, this patch uniforms them
+in function declaration to type u32 too.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 6c2decba5ac4..4e936d7933f7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -38,9 +38,8 @@ static struct hns3_dbg_dentry_info hns3_dbg_dentry[] = {
+ 	},
+ };
+ 
+-static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, unsigned int cmd);
+-static int hns3_dbg_common_file_init(struct hnae3_handle *handle,
+-				     unsigned int cmd);
++static int hns3_dbg_bd_file_init(struct hnae3_handle *handle, u32 cmd);
++static int hns3_dbg_common_file_init(struct hnae3_handle *handle, u32 cmd);
+ 
+ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
+ 	{
+-- 
+2.34.1
+
diff --git a/patches/0472-net-hns3-refactor-function-hclge_parse_capability.patch b/patches/0472-net-hns3-refactor-function-hclge_parse_capability.patch
new file mode 100644
index 0000000..89cae4d
--- /dev/null
+++ b/patches/0472-net-hns3-refactor-function-hclge_parse_capability.patch
@@ -0,0 +1,115 @@
+From 2c1767861d169a2f9099a9bc1e1b5f22e09fbcbd Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:03 +0800
+Subject: [PATCH 111/283] net: hns3: refactor function hclge_parse_capability()
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit e1d93bc6ef3bf497675f9ac2b35b79c48577b970
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e1d93bc6ef3bf497675f9ac2b35b79c48577b970
+
+----------------------------------------------------------------------
+
+The function hclge_parse_capability() uses too many if statement, and
+it may add more in the future. To improve code readability, maintainability
+and simplicity, refactor this function by using a bit mapping array of IMP
+capabilities and driver capabilities.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         | 43 ++++++++++---------
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  6 +++
+ 2 files changed, 28 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 26e9d03da720..1471330ee5d9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -373,33 +373,34 @@ static void hclge_set_default_capability(struct hclge_dev *hdev)
+ 	set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
+ }
+ 
++const struct hclge_caps_bit_map hclge_cmd_caps_bit_map0[] = {
++	{HCLGE_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
++	{HCLGE_CAP_PTP_B, HNAE3_DEV_SUPPORT_PTP_B},
++	{HCLGE_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
++	{HCLGE_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
++	{HCLGE_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
++	{HCLGE_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
++	{HCLGE_CAP_FD_FORWARD_TC_B, HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B},
++	{HCLGE_CAP_FEC_B, HNAE3_DEV_SUPPORT_FEC_B},
++	{HCLGE_CAP_PAUSE_B, HNAE3_DEV_SUPPORT_PAUSE_B},
++	{HCLGE_CAP_PHY_IMP_B, HNAE3_DEV_SUPPORT_PHY_IMP_B},
++	{HCLGE_CAP_RAS_IMP_B, HNAE3_DEV_SUPPORT_RAS_IMP_B},
++	{HCLGE_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
++	{HCLGE_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B},
++	{HCLGE_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B},
++};
++
+ static void hclge_parse_capability(struct hclge_dev *hdev,
+ 				   struct hclge_query_version_cmd *cmd)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+-	u32 caps;
++	u32 caps, i;
+ 
+ 	caps = __le32_to_cpu(cmd->caps[0]);
+-	if (hnae3_get_bit(caps, HCLGE_CAP_UDP_GSO_B))
+-		set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGE_CAP_PTP_B))
+-		set_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGE_CAP_INT_QL_B))
+-		set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGE_CAP_TQP_TXRX_INDEP_B))
+-		set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGE_CAP_HW_TX_CSUM_B))
+-		set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGE_CAP_PHY_IMP_B))
+-		set_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGE_CAP_RAS_IMP_B))
+-		set_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGE_CAP_RXD_ADV_LAYOUT_B))
+-		set_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGE_CAP_PORT_VLAN_BYPASS_B)) {
+-		set_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps);
+-		set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
+-	}
++	for (i = 0; i < ARRAY_SIZE(hclge_cmd_caps_bit_map0); i++)
++		if (hnae3_get_bit(caps, hclge_cmd_caps_bit_map0[i].imp_bit))
++			set_bit(hclge_cmd_caps_bit_map0[i].local_bit,
++				ae_dev->caps);
+ }
+ 
+ static enum hclge_cmd_status
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 71aaca36e5ea..578217ff9706 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -1229,6 +1229,12 @@ struct hclge_phy_reg_cmd {
+ 	u8 rsv1[18];
+ };
+ 
++/* capabilities bits map between imp firmware and local driver */
++struct hclge_caps_bit_map {
++	u16 imp_bit;
++	u16 local_bit;
++};
++
+ int hclge_cmd_init(struct hclge_dev *hdev);
+ static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
+ {
+-- 
+2.34.1
+
diff --git a/patches/0473-net-hns3-refactor-function-hclgevf_parse_capability.patch b/patches/0473-net-hns3-refactor-function-hclgevf_parse_capability.patch
new file mode 100644
index 0000000..ac20eba
--- /dev/null
+++ b/patches/0473-net-hns3-refactor-function-hclgevf_parse_capability.patch
@@ -0,0 +1,105 @@
+From 0d601a6e3b21b7c151ea7b58e02e13115983a0d0 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:04 +0800
+Subject: [PATCH 112/283] net: hns3: refactor function
+ hclgevf_parse_capability()
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 81414ba71356b174d62370195a2bb99592e1b2a2
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=81414ba71356b174d62370195a2bb99592e1b2a2
+
+----------------------------------------------------------------------
+
+The function hclgevf_parse_capability() will add more if statement in the
+future, to improve code readability, maintainability and simplicity,
+refactor this function by using a bit mapping array of IMP capabilities
+and driver capabilities.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+---
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       | 23 +++++++++++--------
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       |  8 +++++++
+ 2 files changed, 22 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 67d44d21814e..6e5d549f0adf 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -358,21 +358,26 @@ static void hclgevf_set_default_capability(struct hclgevf_dev *hdev)
+ 	set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
+ }
+ 
++const struct hclgevf_caps_bit_map hclgevf_cmd_caps_bit_map0[] = {
++	{HCLGEVF_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
++	{HCLGEVF_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
++	{HCLGEVF_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
++	{HCLGEVF_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
++	{HCLGEVF_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
++	{HCLGEVF_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
++};
++
+ static void hclgevf_parse_capability(struct hclgevf_dev *hdev,
+ 				     struct hclgevf_query_version_cmd *cmd)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+-	u32 caps;
++	u32 caps, i;
+ 
+ 	caps = __le32_to_cpu(cmd->caps[0]);
+-	if (hnae3_get_bit(caps, HCLGEVF_CAP_UDP_GSO_B))
+-		set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGEVF_CAP_INT_QL_B))
+-		set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGEVF_CAP_TQP_TXRX_INDEP_B))
+-		set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
+-	if (hnae3_get_bit(caps, HCLGEVF_CAP_HW_TX_CSUM_B))
+-		set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
++	for (i = 0; i < ARRAY_SIZE(hclgevf_cmd_caps_bit_map0); i++)
++		if (hnae3_get_bit(caps, hclgevf_cmd_caps_bit_map0[i].imp_bit))
++			set_bit(hclgevf_cmd_caps_bit_map0[i].local_bit,
++				ae_dev->caps);
+ }
+ 
+ static int hclgevf_cmd_query_version_and_capability(struct hclgevf_dev *hdev)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 6a018a189097..824414e5fdf0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -156,6 +156,8 @@ enum HCLGEVF_CAP_BITS {
+ 	HCLGEVF_CAP_TQP_TXRX_INDEP_B,
+ 	HCLGEVF_CAP_HW_PAD_B,
+ 	HCLGEVF_CAP_STASH_B,
++	HCLGEVF_CAP_UDP_TUNNEL_CSUM_B,
++	HCLGEVF_CAP_RXD_ADV_LAYOUT_B = 15,
+ };
+ 
+ #define HCLGEVF_QUERY_CAP_LENGTH		3
+@@ -285,6 +287,12 @@ struct hclgevf_dev_specs_1_cmd {
+        u8 rsv1[18];
+ };
+ 
++/* capabilities bits map between imp firmware and local driver */
++struct hclgevf_caps_bit_map {
++	u16 imp_bit;
++	u16 local_bit;
++};
++
+ static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
+ {
+ 	writel(value, base + reg);
+-- 
+2.34.1
+
diff --git a/patches/0474-net-hns3-add-new-function-hclge_get_speed_bit.patch b/patches/0474-net-hns3-add-new-function-hclge_get_speed_bit.patch
new file mode 100644
index 0000000..9a7ac8f
--- /dev/null
+++ b/patches/0474-net-hns3-add-new-function-hclge_get_speed_bit.patch
@@ -0,0 +1,381 @@
+From 96924496f94b1099954867eefa148ed2396cfeaa Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:05 +0800
+Subject: [PATCH 113/283] net: hns3: add new function hclge_get_speed_bit()
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit aec35aecc3ccc822b358e2594ff70ff54245261e
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aec35aecc3ccc822b358e2594ff70ff54245261e
+
+----------------------------------------------------------------------
+
+Currently, function hclge_check_port_speed() uses switch/case statement
+to get speed bit according to speed. To reuse this part of code and
+improve code readability and maintainability, add a new function
+hclge_get_speed_bit() to get speed bit according to map relationship
+of speed and speed bit defined in array speed_bit_map.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |   4 +
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |   2 +
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 100 +++++++++++-------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   8 +-
+ include/uapi/linux/ethtool.h                  |  41 ++++++-
+ 5 files changed, 116 insertions(+), 39 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index d6063645896a..db061ca74d31 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -50,6 +50,10 @@
+ #define HNAE3_DEV_ID_50GE_RDMA			0xA224
+ #define HNAE3_DEV_ID_50GE_RDMA_MACSEC		0xA225
+ #define HNAE3_DEV_ID_100G_RDMA_MACSEC		0xA226
++#define HNAE3_DEV_ID_100G_ROH			0xA227
++#define HNAE3_DEV_ID_200G_RDMA			0xA228
++#define HNAE3_DEV_ID_200G_ROH			0xA22C
++#define HNAE3_DEV_ID_400G_ROH			0xA22D
+ #define HNAE3_DEV_ID_100G_VF			0xA22E
+ #define HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF	0xA22F
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 578217ff9706..d17c85959507 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -535,6 +535,8 @@ struct hclge_pf_res_cmd {
+ #define HCLGE_CFG_RSS_SIZE_M	GENMASK(31, 24)
+ #define HCLGE_CFG_SPEED_ABILITY_S	0
+ #define HCLGE_CFG_SPEED_ABILITY_M	GENMASK(7, 0)
++#define HCLGE_CFG_SPEED_ABILITY_EXT_S	10
++#define HCLGE_CFG_SPEED_ABILITY_EXT_M	GENMASK(15, 10)
+ #define HCLGE_CFG_VLAN_FLTR_CAP_S	8
+ #define HCLGE_CFG_VLAN_FLTR_CAP_M	GENMASK(9, 8)
+ #define HCLGE_CFG_UMV_TBL_SPACE_S	16
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 31fc09b28592..2e1639eeae4d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -80,6 +80,7 @@ static const struct pci_device_id ae_algo_pci_tbl[] = {
+ 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
+ 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
+ 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
+ 	/* required last entry */
+ 	{0, }
+ };
+@@ -976,41 +977,43 @@ static int hclge_parse_speed(u8 speed_cmd, u32 *speed)
+ 	return 0;
+ }
+ 
++static const struct hclge_speed_bit_map speed_bit_map[] = {
++	{HCLGE_MAC_SPEED_10M, HCLGE_SUPPORT_10M_BIT},
++	{HCLGE_MAC_SPEED_100M, HCLGE_SUPPORT_100M_BIT},
++	{HCLGE_MAC_SPEED_1G, HCLGE_SUPPORT_1G_BIT},
++	{HCLGE_MAC_SPEED_10G, HCLGE_SUPPORT_10G_BIT},
++	{HCLGE_MAC_SPEED_25G, HCLGE_SUPPORT_25G_BIT},
++	{HCLGE_MAC_SPEED_40G, HCLGE_SUPPORT_40G_BIT},
++	{HCLGE_MAC_SPEED_50G, HCLGE_SUPPORT_50G_BIT},
++	{HCLGE_MAC_SPEED_100G, HCLGE_SUPPORT_100G_BIT},
++	{HCLGE_MAC_SPEED_200G, HCLGE_SUPPORT_200G_BIT},
++};
++
++static int hclge_get_speed_bit(u32 speed, u32 *speed_bit)
++{
++	u16 i;
++
++	for (i = 0; i < ARRAY_SIZE(speed_bit_map); i++) {
++		if (speed == speed_bit_map[i].speed) {
++			*speed_bit = speed_bit_map[i].speed_bit;
++			return 0;
++		}
++	}
++
++	return -EINVAL;
++}
++
+ static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed)
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+ 	u32 speed_ability = hdev->hw.mac.speed_ability;
+ 	u32 speed_bit = 0;
++	int ret;
+ 
+-	switch (speed) {
+-	case HCLGE_MAC_SPEED_10M:
+-		speed_bit = HCLGE_SUPPORT_10M_BIT;
+-		break;
+-	case HCLGE_MAC_SPEED_100M:
+-		speed_bit = HCLGE_SUPPORT_100M_BIT;
+-		break;
+-	case HCLGE_MAC_SPEED_1G:
+-		speed_bit = HCLGE_SUPPORT_1G_BIT;
+-		break;
+-	case HCLGE_MAC_SPEED_10G:
+-		speed_bit = HCLGE_SUPPORT_10G_BIT;
+-		break;
+-	case HCLGE_MAC_SPEED_25G:
+-		speed_bit = HCLGE_SUPPORT_25G_BIT;
+-		break;
+-	case HCLGE_MAC_SPEED_40G:
+-		speed_bit = HCLGE_SUPPORT_40G_BIT;
+-		break;
+-	case HCLGE_MAC_SPEED_50G:
+-		speed_bit = HCLGE_SUPPORT_50G_BIT;
+-		break;
+-	case HCLGE_MAC_SPEED_100G:
+-		speed_bit = HCLGE_SUPPORT_100G_BIT;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
++	ret = hclge_get_speed_bit(speed, &speed_bit);
++	if (ret)
++		return ret;
+ 
+ 	if (speed_bit & speed_ability)
+ 		return 0;
+@@ -1019,7 +1022,7 @@ static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed)
+ }
+ 
+ #ifdef HAVE_ETHTOOL_CONVERT_U32_AND_LINK_MODE
+-static void hclge_convert_setting_sr(struct hclge_mac *mac, u8 speed_ability)
++static void hclge_convert_setting_sr(struct hclge_mac *mac, u16 speed_ability)
+ {
+ 	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
+@@ -1036,9 +1039,12 @@ static void hclge_convert_setting_sr(struct hclge_mac *mac, u8 speed_ability)
+ 	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
+ 				 mac->supported);
++	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
++		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
++				 mac->supported);
+ }
+ 
+-static void hclge_convert_setting_lr(struct hclge_mac *mac, u8 speed_ability)
++static void hclge_convert_setting_lr(struct hclge_mac *mac, u16 speed_ability)
+ {
+ 	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
+@@ -1052,9 +1058,13 @@ static void hclge_convert_setting_lr(struct hclge_mac *mac, u8 speed_ability)
+ 	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
+ 				 mac->supported);
++	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
++		linkmode_set_bit(
++			ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
++			mac->supported);
+ }
+ 
+-static void hclge_convert_setting_cr(struct hclge_mac *mac, u8 speed_ability)
++static void hclge_convert_setting_cr(struct hclge_mac *mac, u16 speed_ability)
+ {
+ 	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
+@@ -1071,9 +1081,12 @@ static void hclge_convert_setting_cr(struct hclge_mac *mac, u8 speed_ability)
+ 	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
+ 				 mac->supported);
++	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
++		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
++				 mac->supported);
+ }
+ 
+-static void hclge_convert_setting_kr(struct hclge_mac *mac, u8 speed_ability)
++static void hclge_convert_setting_kr(struct hclge_mac *mac, u16 speed_ability)
+ {
+ 	if (speed_ability & HCLGE_SUPPORT_1G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
+@@ -1093,6 +1106,9 @@ static void hclge_convert_setting_kr(struct hclge_mac *mac, u8 speed_ability)
+ 	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
+ 				 mac->supported);
++	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
++		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
++				 mac->supported);
+ }
+ 
+ static void hclge_convert_setting_fec(struct hclge_mac *mac)
+@@ -1119,6 +1135,7 @@ static void hclge_convert_setting_fec(struct hclge_mac *mac)
+ 			BIT(HNAE3_FEC_AUTO);
+ 		break;
+ 	case HCLGE_MAC_SPEED_100G:
++	case HCLGE_MAC_SPEED_200G:
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
+ 		mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO);
+ 		break;
+@@ -1130,7 +1147,7 @@ static void hclge_convert_setting_fec(struct hclge_mac *mac)
+ #endif
+ 
+ static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
+-					u8 speed_ability)
++					u16 speed_ability)
+ {
+ #ifdef HAVE_ETHTOOL_CONVERT_U32_AND_LINK_MODE
+ 	struct hclge_mac *mac = &hdev->hw.mac;
+@@ -1165,7 +1182,7 @@ static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
+ }
+ 
+ static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev,
+-					    u8 speed_ability)
++					    u16 speed_ability)
+ {
+ 	struct hclge_mac *mac = &hdev->hw.mac;
+ 
+@@ -1186,7 +1203,7 @@ static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev,
+ }
+ 
+ static void hclge_parse_copper_link_mode(struct hclge_dev *hdev,
+-					 u8 speed_ability)
++					 u16 speed_ability)
+ {
+ 	unsigned long *supported = hdev->hw.mac.supported;
+ 
+@@ -1216,7 +1233,7 @@ static void hclge_parse_copper_link_mode(struct hclge_dev *hdev,
+ 	linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
+ }
+ 
+-static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
++static void hclge_parse_link_mode(struct hclge_dev *hdev, u16 speed_ability)
+ {
+ 	u8 media_type = hdev->hw.mac.media_type;
+ 
+@@ -1228,8 +1245,11 @@ static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
+ 		hclge_parse_backplane_link_mode(hdev, speed_ability);
+ }
+ 
+-static u32 hclge_get_max_speed(u8 speed_ability)
++static u32 hclge_get_max_speed(u16 speed_ability)
+ {
++	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
++		return HCLGE_MAC_SPEED_200G;
++
+ 	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
+ 		return HCLGE_MAC_SPEED_100G;
+ 
+@@ -1260,9 +1280,11 @@ static u32 hclge_get_max_speed(u8 speed_ability)
+ static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
+ {
+ #define HCLGE_TX_SPARE_SIZE_UNIT		4096
++#define SPEED_ABILITY_EXT_SHIFT                 8
+ 
+ 	struct hclge_cfg_param_cmd *req;
+ 	u64 mac_addr_tmp_high;
++	u16 speed_ability_ext;
+ 	u64 mac_addr_tmp;
+ 	unsigned int i;
+ 
+@@ -1308,6 +1330,10 @@ static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
+ 	cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
+ 					     HCLGE_CFG_SPEED_ABILITY_M,
+ 					     HCLGE_CFG_SPEED_ABILITY_S);
++	speed_ability_ext = hnae3_get_field(__le32_to_cpu(req->param[1]),
++					    HCLGE_CFG_SPEED_ABILITY_EXT_M,
++					    HCLGE_CFG_SPEED_ABILITY_EXT_S);
++	cfg->speed_ability |= speed_ability_ext << SPEED_ABILITY_EXT_SHIFT;
+ 
+ 	cfg->vlan_fliter_cap = hnae3_get_field(__le32_to_cpu(req->param[1]),
+ 					       HCLGE_CFG_VLAN_FLTR_CAP_M,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 5889bd069a69..0bf287e403b3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -208,6 +208,7 @@ enum HLCGE_PORT_TYPE {
+ #define HCLGE_SUPPORT_40G_BIT		BIT(5)
+ #define HCLGE_SUPPORT_100M_BIT		BIT(6)
+ #define HCLGE_SUPPORT_10M_BIT		BIT(7)
++#define HCLGE_SUPPORT_200G_BIT         BIT(8)
+ #define HCLGE_SUPPORT_GE \
+ 	(HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
+ 
+@@ -385,7 +386,7 @@ struct hclge_cfg {
+ 	u8 default_speed;
+ 	u32 numa_node_map;
+ 	u32 tx_spare_buf_size;
+-	u8 speed_ability;
++	u16 speed_ability;
+ 	u16 umv_space;
+ };
+ 
+@@ -1012,6 +1013,11 @@ struct hclge_vport {
+ #endif
+ };
+ 
++struct hclge_speed_bit_map {
++	u32 speed;
++	u32 speed_bit;
++};
++
+ int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
+ 				 bool en_mc_pmc, bool en_bc_pmc);
+ int hclge_add_uc_addr_common(struct hclge_vport *vport,
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index 43ac4af42346..5985c5a72046 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -1529,7 +1529,46 @@ enum ethtool_link_mode_bit_indices {
+ 	ETHTOOL_LINK_MODE_FEC_NONE_BIT	= 49,
+ 	ETHTOOL_LINK_MODE_FEC_RS_BIT	= 50,
+ 	ETHTOOL_LINK_MODE_FEC_BASER_BIT	= 51,
+-
++	ETHTOOL_LINK_MODE_50000baseKR_Full_BIT		 = 52,
++	ETHTOOL_LINK_MODE_50000baseSR_Full_BIT		 = 53,
++	ETHTOOL_LINK_MODE_50000baseCR_Full_BIT		 = 54,
++	ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT	 = 55,
++	ETHTOOL_LINK_MODE_50000baseDR_Full_BIT		 = 56,
++	ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT	 = 57,
++	ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT	 = 58,
++	ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT	 = 59,
++	ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT = 60,
++	ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT	 = 61,
++	ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT	 = 62,
++	ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT	 = 63,
++	ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT = 64,
++	ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT	 = 65,
++	ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT	 = 66,
++	ETHTOOL_LINK_MODE_100baseT1_Full_BIT		 = 67,
++	ETHTOOL_LINK_MODE_1000baseT1_Full_BIT		 = 68,
++	ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT	 = 69,
++	ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT	 = 70,
++	ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,
++	ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT	 = 72,
++	ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT	 = 73,
++	ETHTOOL_LINK_MODE_FEC_LLRS_BIT			 = 74,
++	ETHTOOL_LINK_MODE_100000baseKR_Full_BIT		 = 75,
++	ETHTOOL_LINK_MODE_100000baseSR_Full_BIT		 = 76,
++	ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT	 = 77,
++	ETHTOOL_LINK_MODE_100000baseCR_Full_BIT		 = 78,
++	ETHTOOL_LINK_MODE_100000baseDR_Full_BIT		 = 79,
++	ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT	 = 80,
++	ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT	 = 81,
++	ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82,
++	ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT	 = 83,
++	ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT	 = 84,
++	ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT	 = 85,
++	ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT	 = 86,
++	ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87,
++	ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT	 = 88,
++	ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT	 = 89,
++	ETHTOOL_LINK_MODE_100baseFX_Half_BIT		 = 90,
++	ETHTOOL_LINK_MODE_100baseFX_Full_BIT		 = 91,
+ 	/* Last allowed bit for __ETHTOOL_LINK_MODE_LEGACY_MASK is bit
+ 	 * 31. Please do NOT define any SUPPORTED_* or ADVERTISED_*
+ 	 * macro for bits > 31. The only way to use indices > 31 is to
+-- 
+2.34.1
+
diff --git a/patches/0475-net-hns3-don-t-config-TM-DWRR-twice-when-set-ETS.patch b/patches/0475-net-hns3-don-t-config-TM-DWRR-twice-when-set-ETS.patch
new file mode 100644
index 0000000..860446c
--- /dev/null
+++ b/patches/0475-net-hns3-don-t-config-TM-DWRR-twice-when-set-ETS.patch
@@ -0,0 +1,56 @@
+From f6d60a8809a1aad0eeade22933c433f35be0e0b7 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:06 +0800
+Subject: [PATCH 114/283] net: hns3: don't config TM DWRR twice when set ETS
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 7f2f8cf6ef668c1c745e229023f98663f47aa702
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7f2f8cf6ef668c1c745e229023f98663f47aa702
+
+----------------------------------------------------------------------
+
+The function hclge_tm_dwrr_cfg() will be called twice in function
+hclge_ieee_setets() when map_changed is true, the calling flow is
+hclge_ieee_setets()
+    hclge_map_update()
+    |   hclge_tm_schd_setup_hw()
+    |       hclge_tm_dwrr_cfg()
+    hclge_notify_init_up()
+    hclge_tm_dwrr_cfg()
+
+It is no need to call hclge_tm_dwrr_cfg() twice actually, so just
+return after calling hclge_notify_init_up().
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+index 636f8dd996ac..72963ddc3103 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+@@ -239,9 +239,7 @@ static int hclge_ieee_setets(struct hnae3_handle *h, struct ieee_ets *ets)
+ 		if (ret)
+ 			goto err_out;
+ 
+-		ret = hclge_notify_init_up(hdev);
+-		if (ret)
+-			return ret;
++		return hclge_notify_init_up(hdev);
+ 	}
+ 
+ 	return hclge_tm_dwrr_cfg(hdev);
+-- 
+2.34.1
+
diff --git a/patches/0476-net-hns3-remove-unnecessary-static-of-local-variable.patch b/patches/0476-net-hns3-remove-unnecessary-static-of-local-variable.patch
new file mode 100644
index 0000000..468c8fc
--- /dev/null
+++ b/patches/0476-net-hns3-remove-unnecessary-static-of-local-variable.patch
@@ -0,0 +1,63 @@
+From ed7a3d9f50f2b0ec11531ed6973c830931f5248b Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Tue, 28 Sep 2021 11:52:07 +0800
+Subject: [PATCH 115/283] net: hns3: remove unnecessary "static" of local
+ variables in function
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 1026b1534fa12a9dbdcebd34d417513fca4647f0
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1026b1534fa12a9dbdcebd34d417513fca4647f0
+
+----------------------------------------------------------------------
+
+Some local variable declarations are no need to add "static", so remove it.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c       | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 4e936d7933f7..fd2debdb517c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -723,7 +723,7 @@ static void
+ hns3_dbg_dev_caps(struct hnae3_handle *h, char *buf, int len, int *pos)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
+-	static const char * const str[] = {"no", "yes"};
++	const char * const str[] = {"no", "yes"};
+ 	unsigned long *caps = ae_dev->caps;
+ 	u32 i, state;
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 6e5d549f0adf..0356af21ff44 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -72,7 +72,7 @@ static bool hclgevf_cmd_csq_done(struct hclgevf_hw *hw)
+ 
+ static bool hclgevf_is_special_opcode(u16 opcode)
+ {
+-	static const u16 spec_opcode[] = {0x30, 0x31, 0x32};
++	const u16 spec_opcode[] = {0x30, 0x31, 0x32};
+ 	int i;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
+-- 
+2.34.1
+
diff --git a/patches/0477-net-hns3-add-required-space-in-comment.patch b/patches/0477-net-hns3-add-required-space-in-comment.patch
new file mode 100644
index 0000000..40b0e0e
--- /dev/null
+++ b/patches/0477-net-hns3-add-required-space-in-comment.patch
@@ -0,0 +1,87 @@
+From c9289ca2b21ff678a5e6805f493de9285f404adb Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Tue, 28 Sep 2021 11:52:08 +0800
+Subject: [PATCH 116/283] net: hns3: add required space in comment
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 0cb0704149f0d9d3b7c68ebab932fc27222c740b
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0cb0704149f0d9d3b7c68ebab932fc27222c740b
+
+----------------------------------------------------------------------
+
+Add some required spaces in comment for cleanup.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h         | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h         | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h  | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
+index 5a13eea2742d..98045a4649e8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
+@@ -9,7 +9,7 @@
+ 
+ enum HCLGE_MBX_OPCODE {
+ 	HCLGE_MBX_RESET = 0x01,		/* (VF -> PF) assert reset */
+-	HCLGE_MBX_ASSERTING_RESET,	/* (PF -> VF) PF is asserting reset*/
++	HCLGE_MBX_ASSERTING_RESET,	/* (PF -> VF) PF is asserting reset */
+ 	HCLGE_MBX_SET_UNICAST,		/* (VF -> PF) set UC addr */
+ 	HCLGE_MBX_SET_MULTICAST,	/* (VF -> PF) set MC addr */
+ 	HCLGE_MBX_SET_VLAN,		/* (VF -> PF) set VLAN */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 3df794363632..9278c742e3b0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -340,7 +340,7 @@ enum hns3_pkt_l3type {
+ 	HNS3_L3_TYPE_LLDP,
+ 	HNS3_L3_TYPE_BPDU,
+ 	HNS3_L3_TYPE_MAC_PAUSE,
+-	HNS3_L3_TYPE_PFC_PAUSE,/* 0x9*/
++	HNS3_L3_TYPE_PFC_PAUSE, /* 0x9 */
+ 
+ 	/* reserved for 0xA~0xB */
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index d17c85959507..c06070cfd4bc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -443,7 +443,7 @@ struct hclge_tc_thrd {
+ };
+ 
+ struct hclge_priv_buf {
+-	struct hclge_waterline wl;	/* Waterline for low and high*/
++	struct hclge_waterline wl;	/* Waterline for low and high */
+ 	u32 buf_size;	/* TC private buffer size */
+ 	u32 tx_buf_size;
+ 	u32 enable;	/* Enable TC private buffer or not */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 2e1639eeae4d..30c98e0d12d4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3375,7 +3375,7 @@ static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
+ 	hclge_enable_vector(&hdev->misc_vector, false);
+ 	event_cause = hclge_check_event_cause(hdev, &clearval);
+ 
+-	/* vector 0 interrupt is shared with reset and mailbox source events.*/
++	/* vector 0 interrupt is shared with reset and mailbox source events. */
+ 	switch (event_cause) {
+ 	case HCLGE_VECTOR0_EVENT_ERR:
+ 		hclge_errhand_task_schedule(hdev);
+-- 
+2.34.1
+
diff --git a/patches/0478-net-hns3-initialize-each-member-of-structure-array-o.patch b/patches/0478-net-hns3-initialize-each-member-of-structure-array-o.patch
new file mode 100644
index 0000000..94a8e40
--- /dev/null
+++ b/patches/0478-net-hns3-initialize-each-member-of-structure-array-o.patch
@@ -0,0 +1,1854 @@
+From b22020d8794bd344bad3835a75f2dff1c59eac51 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:09 +0800
+Subject: [PATCH 117/283] net: hns3: initialize each member of structure array
+ on a separate line
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 60fe9ff9b7cbbf78a755cd849a3575d3b04b7394
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=60fe9ff9b7cbbf78a755cd849a3575d3b04b7394
+
+----------------------------------------------------------------------
+
+To make the format of each member initialization of structure array
+clearer, initialize each member on a separate line.
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_err.c         | 1711 +++++++++++------
+ .../hisilicon/hns3/hns3pf/hclge_err.h         |   24 -
+ 2 files changed, 1139 insertions(+), 596 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 3d3057fed4bb..094f49087f72 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -3,469 +3,896 @@
+ 
+ #include "hclge_err.h"
+ 
+-const struct hclge_hw_error hclge_imp_tcm_ecc_int[] = {
+-	{ .int_msk = BIT(1), .msg = "imp_itcm0_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(3), .msg = "imp_itcm1_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(5), .msg = "imp_itcm2_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(7), .msg = "imp_itcm3_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(9), .msg = "imp_dtcm0_mem0_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(11), .msg = "imp_dtcm0_mem1_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(13), .msg = "imp_dtcm1_mem0_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(15), .msg = "imp_dtcm1_mem1_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(17), .msg = "imp_itcm4_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_imp_tcm_ecc_int[] = {
++	{
++		.int_msk = BIT(1),
++		.msg = "imp_itcm0_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "imp_itcm1_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "imp_itcm2_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "imp_itcm3_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "imp_dtcm0_mem0_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(11),
++		.msg = "imp_dtcm0_mem1_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(13),
++		.msg = "imp_dtcm1_mem0_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(15),
++		.msg = "imp_dtcm1_mem1_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(17),
++		.msg = "imp_itcm4_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_cmdq_nic_mem_ecc_int[] = {
+-	{ .int_msk = BIT(1), .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(3), .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(5), .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(7), .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(9), .msg = "cmdq_nic_rx_head_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(11), .msg = "cmdq_nic_tx_head_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(13), .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(15), .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(17), .msg = "cmdq_rocee_rx_depth_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(19), .msg = "cmdq_rocee_tx_depth_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(21), .msg = "cmdq_rocee_rx_tail_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(23), .msg = "cmdq_rocee_tx_tail_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(25), .msg = "cmdq_rocee_rx_head_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(27), .msg = "cmdq_rocee_tx_head_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(29), .msg = "cmdq_rocee_rx_addr_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(31), .msg = "cmdq_rocee_tx_addr_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_cmdq_nic_mem_ecc_int[] = {
++	{
++		.int_msk = BIT(1),
++		.msg = "cmdq_nic_rx_depth_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "cmdq_nic_tx_depth_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "cmdq_nic_rx_tail_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "cmdq_nic_tx_tail_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "cmdq_nic_rx_head_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(11),
++		.msg = "cmdq_nic_tx_head_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(13),
++		.msg = "cmdq_nic_rx_addr_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(15),
++		.msg = "cmdq_nic_tx_addr_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(17),
++		.msg = "cmdq_rocee_rx_depth_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(19),
++		.msg = "cmdq_rocee_tx_depth_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(21),
++		.msg = "cmdq_rocee_rx_tail_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(23),
++		.msg = "cmdq_rocee_tx_tail_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(25),
++		.msg = "cmdq_rocee_rx_head_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(27),
++		.msg = "cmdq_rocee_tx_head_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(29),
++		.msg = "cmdq_rocee_rx_addr_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(31),
++		.msg = "cmdq_rocee_tx_addr_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_tqp_int_ecc_int[] = {
+-	{ .int_msk = BIT(6), .msg = "tqp_int_cfg_even_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(7), .msg = "tqp_int_cfg_odd_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(8), .msg = "tqp_int_ctrl_even_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(9), .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(10), .msg = "tx_que_scan_int_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(11), .msg = "rx_que_scan_int_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_tqp_int_ecc_int[] = {
++	{
++		.int_msk = BIT(6),
++		.msg = "tqp_int_cfg_even_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "tqp_int_cfg_odd_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(8),
++		.msg = "tqp_int_ctrl_even_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "tqp_int_ctrl_odd_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(10),
++		.msg = "tx_que_scan_int_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(11),
++		.msg = "rx_que_scan_int_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_msix_sram_ecc_int[] = {
+-	{ .int_msk = BIT(1), .msg = "msix_nic_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(3), .msg = "msix_rocee_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_msix_sram_ecc_int[] = {
++	{
++		.int_msk = BIT(1),
++		.msg = "msix_nic_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "msix_rocee_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_igu_int[] = {
+-	{ .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_igu_int[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "igu_rx_buf0_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "igu_rx_buf1_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_igu_egu_tnl_int[] = {
+-	{ .int_msk = BIT(0), .msg = "rx_buf_overflow",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(2), .msg = "rx_stp_fifo_underflow",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(3), .msg = "tx_buf_overflow",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(4), .msg = "tx_buf_underrun",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(5), .msg = "rx_stp_buf_overflow",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_igu_egu_tnl_int[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "rx_buf_overflow",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "rx_stp_fifo_overflow",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "rx_stp_fifo_underflow",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "tx_buf_overflow",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(4),
++		.msg = "tx_buf_underrun",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "rx_stp_buf_overflow",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ncsi_err_int[] = {
+-	{ .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ncsi_err_int[] = {
++	{
++		.int_msk = BIT(1),
++		.msg = "ncsi_tx_ecc_mbit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st1[] = {
+-	{ .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_m1bit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(27), .msg = "flow_director_ad_mem0_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(28), .msg = "flow_director_ad_mem1_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(29), .msg = "rx_vlan_tag_memory_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(30), .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st1[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "vf_vlan_ad_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "umv_mcast_group_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "umv_key_mem0_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "umv_key_mem1_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(4),
++		.msg = "umv_key_mem2_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "umv_key_mem3_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(6),
++		.msg = "umv_ad_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "rss_tc_mode_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(8),
++		.msg = "rss_idt_mem0_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "rss_idt_mem1_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(10),
++		.msg = "rss_idt_mem2_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(11),
++		.msg = "rss_idt_mem3_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(12),
++		.msg = "rss_idt_mem4_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(13),
++		.msg = "rss_idt_mem5_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(14),
++		.msg = "rss_idt_mem6_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(15),
++		.msg = "rss_idt_mem7_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(16),
++		.msg = "rss_idt_mem8_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(17),
++		.msg = "rss_idt_mem9_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(18),
++		.msg = "rss_idt_mem10_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(19),
++		.msg = "rss_idt_mem11_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(20),
++		.msg = "rss_idt_mem12_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(21),
++		.msg = "rss_idt_mem13_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(22),
++		.msg = "rss_idt_mem14_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(23),
++		.msg = "rss_idt_mem15_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(24),
++		.msg = "port_vlan_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(25),
++		.msg = "mcast_linear_table_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(26),
++		.msg = "mcast_result_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(27),
++		.msg = "flow_director_ad_mem0_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(28),
++		.msg = "flow_director_ad_mem1_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(29),
++		.msg = "rx_vlan_tag_memory_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(30),
++		.msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ppp_pf_abnormal_int[] = {
+-	{ .int_msk = BIT(0), .msg = "tx_vlan_tag_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ppp_pf_abnormal_int[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "tx_vlan_tag_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "rss_list_tc_unassigned_queue_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st3[] = {
+-	{ .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st3[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "hfs_fifo_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "rslt_descr_fifo_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "tx_vlan_tag_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "FD_CN0_memory_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(4),
++		.msg = "FD_CN1_memory_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "GRO_AD_memory_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_tm_sch_rint[] = {
+-	{ .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(12), .msg = "tm_sch_port_shap_offset_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(13), .msg = "tm_sch_port_shap_offset_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(14), .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(15), .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(16), .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(17), .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(18), .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(19), .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(20), .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(21), .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_tm_sch_rint[] = {
++	{
++		.int_msk = BIT(1),
++		.msg = "tm_sch_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "tm_sch_port_shap_sub_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "tm_sch_port_shap_sub_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(4),
++		.msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(6),
++		.msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(8),
++		.msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(10),
++		.msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(11),
++		.msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(12),
++		.msg = "tm_sch_port_shap_offset_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(13),
++		.msg = "tm_sch_port_shap_offset_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(14),
++		.msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(15),
++		.msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(16),
++		.msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(17),
++		.msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(18),
++		.msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(19),
++		.msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(20),
++		.msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(21),
++		.msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(22),
++		.msg = "tm_sch_rq_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(23),
++		.msg = "tm_sch_rq_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(24),
++		.msg = "tm_sch_nq_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(25),
++		.msg = "tm_sch_nq_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(26),
++		.msg = "tm_sch_roce_up_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(27),
++		.msg = "tm_sch_roce_up_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(28),
++		.msg = "tm_sch_rcb_byte_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(29),
++		.msg = "tm_sch_rcb_byte_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(30),
++		.msg = "tm_sch_ssu_byte_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(31),
++		.msg = "tm_sch_ssu_byte_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_qcn_fifo_rint[] = {
+-	{ .int_msk = BIT(0), .msg = "qcn_shap_gp0_sch_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(1), .msg = "qcn_shap_gp0_sch_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(2), .msg = "qcn_shap_gp1_sch_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(3), .msg = "qcn_shap_gp1_sch_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(4), .msg = "qcn_shap_gp2_sch_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(5), .msg = "qcn_shap_gp2_sch_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(6), .msg = "qcn_shap_gp3_sch_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(7), .msg = "qcn_shap_gp3_sch_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(8), .msg = "qcn_shap_gp0_offset_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(9), .msg = "qcn_shap_gp0_offset_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(10), .msg = "qcn_shap_gp1_offset_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(11), .msg = "qcn_shap_gp1_offset_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(12), .msg = "qcn_shap_gp2_offset_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(13), .msg = "qcn_shap_gp2_offset_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(14), .msg = "qcn_shap_gp3_offset_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(15), .msg = "qcn_shap_gp3_offset_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(16), .msg = "qcn_byte_info_fifo_rd_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(17), .msg = "qcn_byte_info_fifo_wr_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_qcn_fifo_rint[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "qcn_shap_gp0_sch_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "qcn_shap_gp0_sch_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "qcn_shap_gp1_sch_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "qcn_shap_gp1_sch_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(4),
++		.msg = "qcn_shap_gp2_sch_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "qcn_shap_gp2_sch_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(6),
++		.msg = "qcn_shap_gp3_sch_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "qcn_shap_gp3_sch_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(8),
++		.msg = "qcn_shap_gp0_offset_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "qcn_shap_gp0_offset_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(10),
++		.msg = "qcn_shap_gp1_offset_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(11),
++		.msg = "qcn_shap_gp1_offset_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(12),
++		.msg = "qcn_shap_gp2_offset_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(13),
++		.msg = "qcn_shap_gp2_offset_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(14),
++		.msg = "qcn_shap_gp3_offset_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(15),
++		.msg = "qcn_shap_gp3_offset_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(16),
++		.msg = "qcn_byte_info_fifo_rd_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(17),
++		.msg = "qcn_byte_info_fifo_wr_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_qcn_ecc_rint[] = {
+-	{ .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_qcn_ecc_rint[] = {
++	{
++		.int_msk = BIT(1),
++		.msg = "qcn_byte_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "qcn_time_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "qcn_fb_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "qcn_link_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "qcn_rate_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(11),
++		.msg = "qcn_tmplt_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(13),
++		.msg = "qcn_shap_cfg_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(15),
++		.msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(17),
++		.msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(19),
++		.msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(21),
++		.msg = "qcn_gp3_barral_mem_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_mac_afifo_tnl_int[] = {
+-	{ .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_mac_afifo_tnl_int[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "egu_cge_afifo_ecc_1bit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "egu_cge_afifo_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "egu_lge_afifo_ecc_1bit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "egu_lge_afifo_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(4),
++		.msg = "cge_igu_afifo_ecc_1bit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "cge_igu_afifo_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(6),
++		.msg = "lge_igu_afifo_ecc_1bit_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "lge_igu_afifo_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(8),
++		.msg = "cge_igu_afifo_overflow_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "lge_igu_afifo_overflow_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(10),
++		.msg = "egu_cge_afifo_underrun_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(11),
++		.msg = "egu_lge_afifo_underrun_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(12),
++		.msg = "egu_ge_afifo_underrun_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(13),
++		.msg = "ge_igu_afifo_overflow_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[] = {
+-	{ .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(26), .msg = "rd_bus_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(27), .msg = "wr_bus_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(28), .msg = "reg_search_miss",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(29), .msg = "rx_q_search_miss",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(30), .msg = "ooo_ecc_err_detect",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[] = {
++	{
++		.int_msk = BIT(13),
++		.msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(14),
++		.msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(15),
++		.msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(16),
++		.msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(17),
++		.msg = "rcb_tx_ring_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(18),
++		.msg = "rcb_rx_ring_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(19),
++		.msg = "rcb_tx_fbd_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(20),
++		.msg = "rcb_rx_ebd_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(21),
++		.msg = "rcb_tso_info_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(22),
++		.msg = "rcb_tx_int_info_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(23),
++		.msg = "rcb_rx_int_info_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(24),
++		.msg = "tpu_tx_pkt_0_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(25),
++		.msg = "tpu_tx_pkt_1_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(26),
++		.msg = "rd_bus_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(27),
++		.msg = "wr_bus_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(28),
++		.msg = "reg_search_miss",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(29),
++		.msg = "rx_q_search_miss",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(30),
++		.msg = "ooo_ecc_err_detect",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(31),
++		.msg = "ooo_ecc_err_multpl",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[] = {
+-	{ .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[] = {
++	{
++		.int_msk = BIT(4),
++		.msg = "gro_bd_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "gro_context_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(6),
++		.msg = "rx_stash_cfg_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "axi_rd_fbd_ecc_mbit_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ppu_pf_abnormal_int[] = {
+-	{ .int_msk = BIT(0), .msg = "over_8bd_no_fe",
+-	  .reset_level = HNAE3_FUNC_RESET },
+-	{ .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(3), .msg = "tx_rd_fbd_poison",
+-	  .reset_level = HNAE3_FUNC_RESET },
+-	{ .int_msk = BIT(4), .msg = "rx_rd_ebd_poison",
+-	  .reset_level = HNAE3_FUNC_RESET },
+-	{ .int_msk = BIT(5), .msg = "buf_wait_timeout",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ppu_pf_abnormal_int[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "over_8bd_no_fe",
++		.reset_level = HNAE3_FUNC_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "tso_mss_cmp_min_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "tso_mss_cmp_max_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "tx_rd_fbd_poison",
++		.reset_level = HNAE3_FUNC_RESET
++	}, {
++		.int_msk = BIT(4),
++		.msg = "rx_rd_ebd_poison",
++		.reset_level = HNAE3_FUNC_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "buf_wait_timeout",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ssu_com_err_int[] = {
+-	{ .int_msk = BIT(0), .msg = "buf_sum_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(1), .msg = "ppp_mb_num_err",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(2), .msg = "ppp_mbid_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(3), .msg = "ppp_rlt_mac_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(4), .msg = "ppp_rlt_host_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(5), .msg = "cks_edit_position_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(6), .msg = "cks_edit_condition_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(7), .msg = "vlan_edit_condition_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(8), .msg = "vlan_num_ot_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(9), .msg = "vlan_num_in_err",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ssu_com_err_int[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "buf_sum_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "ppp_mb_num_err",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "ppp_mbid_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "ppp_rlt_mac_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(4),
++		.msg = "ppp_rlt_host_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "cks_edit_position_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(6),
++		.msg = "cks_edit_condition_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "vlan_edit_condition_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(8),
++		.msg = "vlan_num_ot_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "vlan_num_in_err",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+ #define HCLGE_SSU_MEM_ECC_ERR(x) \
+-	{ .int_msk = BIT(x), .msg = "ssu_mem" #x "_ecc_mbit_err", \
+-	  .reset_level = HNAE3_GLOBAL_RESET }
++{ \
++	.int_msk = BIT(x), \
++	.msg = "ssu_mem" #x "_ecc_mbit_err", \
++	.reset_level = HNAE3_GLOBAL_RESET \
++}
+ 
+ const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[] = {
+ 	HCLGE_SSU_MEM_ECC_ERR(0),
+@@ -503,132 +930,270 @@ const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[] = {
+ 	{ /* sentinel */ }
+ };
+ 
+-const struct hclge_hw_error hclge_ssu_port_based_err_int[] = {
+-	{ .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
+-	  .reset_level = HNAE3_FUNC_RESET },
+-	{ .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(2), .msg = "igu_pkt_without_key_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(3), .msg = "roc_eof_mis_match_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(5), .msg = "igu_eof_mis_match_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(6), .msg = "roc_sof_mis_match_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(8), .msg = "igu_sof_mis_match_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(11), .msg = "ets_rd_int_rx_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(12), .msg = "ets_wr_int_rx_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(13), .msg = "ets_rd_int_tx_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(14), .msg = "ets_wr_int_tx_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ssu_port_based_err_int[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "roc_pkt_without_key_port",
++		.reset_level = HNAE3_FUNC_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "tpu_pkt_without_key_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "igu_pkt_without_key_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "roc_eof_mis_match_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(4),
++		.msg = "tpu_eof_mis_match_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "igu_eof_mis_match_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(6),
++		.msg = "roc_sof_mis_match_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "tpu_sof_mis_match_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(8),
++		.msg = "igu_sof_mis_match_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(11),
++		.msg = "ets_rd_int_rx_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(12),
++		.msg = "ets_wr_int_rx_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(13),
++		.msg = "ets_rd_int_tx_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(14),
++		.msg = "ets_wr_int_tx_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ssu_fifo_overflow_int[] = {
+-	{ .int_msk = BIT(0), .msg = "ig_mac_inf_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(1), .msg = "ig_host_inf_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(2), .msg = "ig_roc_buf_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(3), .msg = "ig_host_data_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(4), .msg = "ig_host_key_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(5), .msg = "tx_qcn_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(6), .msg = "rx_qcn_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(9), .msg = "qm_eof_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(10), .msg = "mb_rlt_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(15), .msg = "host_cmd_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(16), .msg = "mac_cmd_fifo_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(19), .msg = "dup_bitmap_empty_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ssu_fifo_overflow_int[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "ig_mac_inf_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "ig_host_inf_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "ig_roc_buf_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "ig_host_data_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(4),
++		.msg = "ig_host_key_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(5),
++		.msg = "tx_qcn_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(6),
++		.msg = "rx_qcn_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(7),
++		.msg = "tx_pf_rd_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(8),
++		.msg = "rx_pf_rd_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "qm_eof_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(10),
++		.msg = "mb_rlt_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(11),
++		.msg = "dup_uncopy_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(12),
++		.msg = "dup_cnt_rd_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(13),
++		.msg = "dup_cnt_drop_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(14),
++		.msg = "dup_cnt_wrb_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(15),
++		.msg = "host_cmd_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(16),
++		.msg = "mac_cmd_fifo_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(17),
++		.msg = "host_cmd_bitmap_empty_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(18),
++		.msg = "mac_cmd_bitmap_empty_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(19),
++		.msg = "dup_bitmap_empty_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(20),
++		.msg = "out_queue_bitmap_empty_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(21),
++		.msg = "bank2_bitmap_empty_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(22),
++		.msg = "bank1_bitmap_empty_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(23),
++		.msg = "bank0_bitmap_empty_int",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ssu_ets_tcg_int[] = {
+-	{ .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ssu_ets_tcg_int[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "ets_rd_int_rx_tcg",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(1),
++		.msg = "ets_wr_int_rx_tcg",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(2),
++		.msg = "ets_rd_int_tx_tcg",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		.int_msk = BIT(3),
++		.msg = "ets_wr_int_tx_tcg",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_ssu_port_based_pf_int[] = {
+-	{ .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
+-	  .reset_level = HNAE3_FUNC_RESET },
+-	{ .int_msk = BIT(9), .msg = "low_water_line_err_port",
+-	  .reset_level = HNAE3_NONE_RESET },
+-	{ .int_msk = BIT(10), .msg = "hi_water_line_err_port",
+-	  .reset_level = HNAE3_GLOBAL_RESET },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_ssu_port_based_pf_int[] = {
++	{
++		.int_msk = BIT(0),
++		.msg = "roc_pkt_without_key_port",
++		.reset_level = HNAE3_FUNC_RESET
++	}, {
++		.int_msk = BIT(9),
++		.msg = "low_water_line_err_port",
++		.reset_level = HNAE3_NONE_RESET
++	}, {
++		.int_msk = BIT(10),
++		.msg = "hi_water_line_err_port",
++		.reset_level = HNAE3_GLOBAL_RESET
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+-const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[] = {
+-	{ .int_msk = 0, .msg = "rocee qmm ovf: sgid invalid err" },
+-	{ .int_msk = 0x4, .msg = "rocee qmm ovf: sgid ovf err" },
+-	{ .int_msk = 0x8, .msg = "rocee qmm ovf: smac invalid err" },
+-	{ .int_msk = 0xC, .msg = "rocee qmm ovf: smac ovf err" },
+-	{ .int_msk = 0x10, .msg = "rocee qmm ovf: cqc invalid err" },
+-	{ .int_msk = 0x11, .msg = "rocee qmm ovf: cqc ovf err" },
+-	{ .int_msk = 0x12, .msg = "rocee qmm ovf: cqc hopnum err" },
+-	{ .int_msk = 0x13, .msg = "rocee qmm ovf: cqc ba0 err" },
+-	{ .int_msk = 0x14, .msg = "rocee qmm ovf: srqc invalid err" },
+-	{ .int_msk = 0x15, .msg = "rocee qmm ovf: srqc ovf err" },
+-	{ .int_msk = 0x16, .msg = "rocee qmm ovf: srqc hopnum err" },
+-	{ .int_msk = 0x17, .msg = "rocee qmm ovf: srqc ba0 err" },
+-	{ .int_msk = 0x18, .msg = "rocee qmm ovf: mpt invalid err" },
+-	{ .int_msk = 0x19, .msg = "rocee qmm ovf: mpt ovf err" },
+-	{ .int_msk = 0x1A, .msg = "rocee qmm ovf: mpt hopnum err" },
+-	{ .int_msk = 0x1B, .msg = "rocee qmm ovf: mpt ba0 err" },
+-	{ .int_msk = 0x1C, .msg = "rocee qmm ovf: qpc invalid err" },
+-	{ .int_msk = 0x1D, .msg = "rocee qmm ovf: qpc ovf err" },
+-	{ .int_msk = 0x1E, .msg = "rocee qmm ovf: qpc hopnum err" },
+-	{ .int_msk = 0x1F, .msg = "rocee qmm ovf: qpc ba0 err" },
+-	{ /* sentinel */ }
++static const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[] = {
++	{
++		.int_msk = 0,
++		.msg = "rocee qmm ovf: sgid invalid err"
++	}, {
++		.int_msk = 0x4,
++		.msg = "rocee qmm ovf: sgid ovf err"
++	}, {
++		.int_msk = 0x8,
++		.msg = "rocee qmm ovf: smac invalid err"
++	}, {
++		.int_msk = 0xC,
++		.msg = "rocee qmm ovf: smac ovf err"
++	}, {
++		.int_msk = 0x10,
++		.msg = "rocee qmm ovf: cqc invalid err"
++	}, {
++		.int_msk = 0x11,
++		.msg = "rocee qmm ovf: cqc ovf err"
++	}, {
++		.int_msk = 0x12,
++		.msg = "rocee qmm ovf: cqc hopnum err"
++	}, {
++		.int_msk = 0x13,
++		.msg = "rocee qmm ovf: cqc ba0 err"
++	}, {
++		.int_msk = 0x14,
++		.msg = "rocee qmm ovf: srqc invalid err"
++	}, {
++		.int_msk = 0x15,
++		.msg = "rocee qmm ovf: srqc ovf err"
++	}, {
++		.int_msk = 0x16,
++		.msg = "rocee qmm ovf: srqc hopnum err"
++	}, {
++		.int_msk = 0x17,
++		.msg = "rocee qmm ovf: srqc ba0 err"
++	}, {
++		.int_msk = 0x18,
++		.msg = "rocee qmm ovf: mpt invalid err"
++	}, {
++		.int_msk = 0x19,
++		.msg = "rocee qmm ovf: mpt ovf err"
++	}, {
++		.int_msk = 0x1A,
++		.msg = "rocee qmm ovf: mpt hopnum err"
++	}, {
++		.int_msk = 0x1B,
++		.msg = "rocee qmm ovf: mpt ba0 err"
++	}, {
++		.int_msk = 0x1C,
++		.msg = "rocee qmm ovf: qpc invalid err"
++	}, {
++		.int_msk = 0x1D,
++		.msg = "rocee qmm ovf: qpc ovf err"
++	}, {
++		.int_msk = 0x1E,
++		.msg = "rocee qmm ovf: qpc hopnum err"
++	}, {
++		.int_msk = 0x1F,
++		.msg = "rocee qmm ovf: qpc ba0 err"
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+ static const struct hclge_hw_module_id hclge_hw_module_id_st[] = {
+@@ -1712,34 +2277,36 @@ int hclge_handle_rocee_ras_error(struct hnae3_ae_dev *ae_dev)
+ 
+ static const struct hclge_hw_blk hw_blk[] = {
+ 	{
+-	  .msk = BIT(0), .name = "IGU_EGU",
+-	  .config_err_int = hclge_config_igu_egu_hw_err_int,
+-	},
+-	{
+-	  .msk = BIT(1), .name = "PPP",
+-	  .config_err_int = hclge_config_ppp_hw_err_int,
+-	},
+-	{
+-	  .msk = BIT(2), .name = "SSU",
+-	  .config_err_int = hclge_config_ssu_hw_err_int,
+-	},
+-	{
+-	  .msk = BIT(3), .name = "PPU",
+-	  .config_err_int = hclge_config_ppu_hw_err_int,
+-	},
+-	{
+-	  .msk = BIT(4), .name = "TM",
+-	  .config_err_int = hclge_config_tm_hw_err_int,
+-	},
+-	{
+-	  .msk = BIT(5), .name = "COMMON",
+-	  .config_err_int = hclge_config_common_hw_err_int,
+-	},
+-	{
+-	  .msk = BIT(8), .name = "MAC",
+-	  .config_err_int = hclge_config_mac_err_int,
+-	},
+-	{ /* sentinel */ }
++		.msk = BIT(0),
++		.name = "IGU_EGU",
++		.config_err_int = hclge_config_igu_egu_hw_err_int,
++	}, {
++		.msk = BIT(1),
++		.name = "PPP",
++		.config_err_int = hclge_config_ppp_hw_err_int,
++	}, {
++		.msk = BIT(2),
++		.name = "SSU",
++		.config_err_int = hclge_config_ssu_hw_err_int,
++	}, {
++		.msk = BIT(3),
++		.name = "PPU",
++		.config_err_int = hclge_config_ppu_hw_err_int,
++	}, {
++		.msk = BIT(4),
++		.name = "TM",
++		.config_err_int = hclge_config_tm_hw_err_int,
++	}, {
++		.msk = BIT(5),
++		.name = "COMMON",
++		.config_err_int = hclge_config_common_hw_err_int,
++	}, {
++		.msk = BIT(8),
++		.name = "MAC",
++		.config_err_int = hclge_config_mac_err_int,
++	}, {
++		/* sentinel */
++	}
+ };
+ 
+ static void hclge_config_all_msix_error(struct hclge_dev *hdev, bool enable)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+index a53781491473..05612658423a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+@@ -185,30 +185,6 @@ struct hclge_hw_error {
+ 	enum hnae3_reset_type reset_level;
+ };
+ 
+-extern const struct hclge_hw_error hclge_imp_tcm_ecc_int[];
+-extern const struct hclge_hw_error hclge_cmdq_nic_mem_ecc_int[];
+-extern const struct hclge_hw_error hclge_tqp_int_ecc_int[];
+-extern const struct hclge_hw_error hclge_msix_sram_ecc_int[];
+-extern const struct hclge_hw_error hclge_igu_int[];
+-extern const struct hclge_hw_error hclge_igu_egu_tnl_int[];
+-extern const struct hclge_hw_error hclge_ncsi_err_int[];
+-extern const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st1[];
+-extern const struct hclge_hw_error hclge_ppp_pf_abnormal_int[];
+-extern const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st3[];
+-extern const struct hclge_hw_error hclge_tm_sch_rint[];
+-extern const struct hclge_hw_error hclge_qcn_fifo_rint[];
+-extern const struct hclge_hw_error hclge_qcn_ecc_rint[];
+-extern const struct hclge_hw_error hclge_mac_afifo_tnl_int[];
+-extern const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[];
+-extern const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[];
+-extern const struct hclge_hw_error hclge_ppu_pf_abnormal_int[];
+-extern const struct hclge_hw_error hclge_ssu_com_err_int[];
+-extern const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[];
+-extern const struct hclge_hw_error hclge_ssu_port_based_err_int[];
+-extern const struct hclge_hw_error hclge_ssu_fifo_overflow_int[];
+-extern const struct hclge_hw_error hclge_ssu_ets_tcg_int[];
+-extern const struct hclge_hw_error hclge_ssu_port_based_pf_int[];
+-extern const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[];
+ struct hclge_hw_module_id {
+ 	enum hclge_mod_name_list module_id;
+ 	const char *msg;
+-- 
+2.34.1
+
diff --git a/patches/0479-net-hns3-reconstruct-function-hns3_self_test.patch b/patches/0479-net-hns3-reconstruct-function-hns3_self_test.patch
new file mode 100644
index 0000000..e71b3fa
--- /dev/null
+++ b/patches/0479-net-hns3-reconstruct-function-hns3_self_test.patch
@@ -0,0 +1,190 @@
+From e85a7e7b022c6e8518e3437b98f91dd5824c3558 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:10 +0800
+Subject: [PATCH 118/283] net: hns3: reconstruct function hns3_self_test
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 4c8dab1c709c5a715bce14efdb8f4e889d86aa04
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4c8dab1c709c5a715bce14efdb8f4e889d86aa04
+
+----------------------------------------------------------------------
+
+This patch reconstructs function hns3_self_test to reduce the code
+cycle complexity and make code more concise.
+
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+---
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 111 +++++++++++-------
+ 1 file changed, 66 insertions(+), 45 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 1c3d3036de35..f54d00a1e150 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -306,37 +306,8 @@ static int hns3_lp_run_test(struct net_device *ndev, enum hnae3_loop mode)
+ 	return ret_val;
+ }
+ 
+-/**
+- * hns3_nic_self_test - self test
+- * @ndev: net device
+- * @eth_test: test cmd
+- * @data: test result
+- */
+-static void hns3_self_test(struct net_device *ndev,
+-			   struct ethtool_test *eth_test, u64 *data)
++static void hns3_set_selftest_param(struct hnae3_handle *h, int (*st_param)[2])
+ {
+-	struct hns3_nic_priv *priv = netdev_priv(ndev);
+-	struct hnae3_handle *h = priv->ae_handle;
+-	int st_param[HNS3_SELF_TEST_TYPE_NUM][2];
+-	bool if_running = netif_running(ndev);
+-#if IS_ENABLED(CONFIG_VLAN_8021Q)
+-	bool dis_vlan_filter;
+-#endif
+-	int test_index = 0;
+-	u32 i;
+-
+-	if (hns3_nic_resetting(ndev)) {
+-		netdev_err(ndev, "dev resetting!");
+-		return;
+-	}
+-
+-	/* Only do offline selftest, or pass by default */
+-	if (eth_test->flags != ETH_TEST_FL_OFFLINE)
+-		return;
+-
+-	if (netif_msg_ifdown(h))
+-		netdev_info(ndev, "self test start\n");
+-
+ 	st_param[HNAE3_LOOP_APP][0] = HNAE3_LOOP_APP;
+ 	st_param[HNAE3_LOOP_APP][1] =
+ 			h->flags & HNAE3_SUPPORT_APP_LOOPBACK;
+@@ -353,15 +324,26 @@ static void hns3_self_test(struct net_device *ndev,
+ 	st_param[HNAE3_LOOP_PHY][0] = HNAE3_LOOP_PHY;
+ 	st_param[HNAE3_LOOP_PHY][1] =
+ 			h->flags & HNAE3_SUPPORT_PHY_LOOPBACK;
++}
++
++static void hns3_selftest_prepare(struct net_device *ndev,
++				  bool if_running, int (*st_param)[2])
++{
++	struct hns3_nic_priv *priv = netdev_priv(ndev);
++	struct hnae3_handle *h = priv->ae_handle;
++
++	if (netif_msg_ifdown(h))
++		netdev_info(ndev, "self test start\n");
++
++	hns3_set_selftest_param(h, st_param);
+ 
+ 	if (if_running)
+ 		ndev->netdev_ops->ndo_stop(ndev);
+ 
+ #if IS_ENABLED(CONFIG_VLAN_8021Q)
+ 	/* Disable the vlan filter for selftest does not support it */
+-	dis_vlan_filter = (ndev->features & NETIF_F_HW_VLAN_CTAG_FILTER) &&
+-				h->ae_algo->ops->enable_vlan_filter;
+-	if (dis_vlan_filter)
++	if (h->ae_algo->ops->enable_vlan_filter &&
++	    ndev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
+ 		h->ae_algo->ops->enable_vlan_filter(h, false);
+ #endif
+ 
+@@ -373,6 +355,35 @@ static void hns3_self_test(struct net_device *ndev,
+ 		h->ae_algo->ops->halt_autoneg(h, true);
+ 
+ 	set_bit(HNS3_NIC_STATE_TESTING, &priv->state);
++}
++
++static void hns3_selftest_restore(struct net_device *ndev, bool if_running)
++{
++	struct hns3_nic_priv *priv = netdev_priv(ndev);
++	struct hnae3_handle *h = priv->ae_handle;
++
++	clear_bit(HNS3_NIC_STATE_TESTING, &priv->state);
++
++	if (h->ae_algo->ops->halt_autoneg)
++		h->ae_algo->ops->halt_autoneg(h, false);
++
++#if IS_ENABLED(CONFIG_VLAN_8021Q)
++	if (h->ae_algo->ops->enable_vlan_filter)
++		h->ae_algo->ops->enable_vlan_filter(h, true);
++#endif
++
++	if (if_running)
++		ndev->netdev_ops->ndo_open(ndev);
++
++	if (netif_msg_ifdown(h))
++		netdev_info(ndev, "self test end\n");
++}
++
++static void hns3_do_selftest(struct net_device *ndev, int (*st_param)[2],
++			     struct ethtool_test *eth_test, u64 *data)
++{
++	int test_index = 0;
++	u32 i;
+ 
+ 	for (i = 0; i < HNS3_SELF_TEST_TYPE_NUM; i++) {
+ 		enum hnae3_loop loop_type = (enum hnae3_loop)st_param[i][0];
+@@ -391,22 +402,32 @@ static void hns3_self_test(struct net_device *ndev,
+ 
+ 		test_index++;
+ 	}
++}
+ 
+-	clear_bit(HNS3_NIC_STATE_TESTING, &priv->state);
+-
+-	if (h->ae_algo->ops->halt_autoneg)
+-		h->ae_algo->ops->halt_autoneg(h, false);
++/**
++ * hns3_nic_self_test - self test
++ * @ndev: net device
++ * @eth_test: test cmd
++ * @data: test result
++ */
++static void hns3_self_test(struct net_device *ndev,
++			   struct ethtool_test *eth_test, u64 *data)
++{
++	int st_param[HNS3_SELF_TEST_TYPE_NUM][2];
++	bool if_running = netif_running(ndev);
+ 
+-#if IS_ENABLED(CONFIG_VLAN_8021Q)
+-	if (dis_vlan_filter)
+-		h->ae_algo->ops->enable_vlan_filter(h, true);
+-#endif
++	if (hns3_nic_resetting(ndev)) {
++		netdev_err(ndev, "dev resetting!");
++		return;
++	}
+ 
+-	if (if_running)
+-		ndev->netdev_ops->ndo_open(ndev);
++	/* Only do offline selftest, or pass by default */
++	if (eth_test->flags != ETH_TEST_FL_OFFLINE)
++		return;
+ 
+-	if (netif_msg_ifdown(h))
+-		netdev_info(ndev, "self test end\n");
++	hns3_selftest_prepare(ndev, if_running, st_param);
++	hns3_do_selftest(ndev, st_param, eth_test, data);
++	hns3_selftest_restore(ndev, if_running);
+ }
+ 
+ static void hns3_update_limit_promisc_mode(struct net_device *netdev,
+-- 
+2.34.1
+
diff --git a/patches/0480-net-hns3-reconstruct-function-hclge_ets_validate.patch b/patches/0480-net-hns3-reconstruct-function-hclge_ets_validate.patch
new file mode 100644
index 0000000..7f92ec0
--- /dev/null
+++ b/patches/0480-net-hns3-reconstruct-function-hclge_ets_validate.patch
@@ -0,0 +1,106 @@
+From d0918941875e598dc5b66269c26b581526dcf490 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:11 +0800
+Subject: [PATCH 119/283] net: hns3: reconstruct function hclge_ets_validate()
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 161ad669e6c23529415bffed5cb3bfa012e46cb4
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=161ad669e6c23529415bffed5cb3bfa012e46cb4
+
+----------------------------------------------------------------------
+
+This patch reconstructs function hclge_ets_validate() to reduce the code
+cycle complexity and make code more concise.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_dcb.c         | 47 ++++++++++++++-----
+ 1 file changed, 35 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+index 72963ddc3103..65c38d972a4d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+@@ -104,26 +104,30 @@ static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc,
+ 	return 0;
+ }
+ 
+-static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
+-			      u8 *tc, bool *changed)
++static u8 hclge_ets_tc_changed(struct hclge_dev *hdev, struct ieee_ets *ets,
++			       bool *changed)
+ {
+-	bool has_ets_tc = false;
+-	u32 total_ets_bw = 0;
+-	u8 max_tc = 0;
+-	int ret;
++	u8 max_tc_id = 0;
+ 	u8 i;
+ 
+ 	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
+ 		if (ets->prio_tc[i] != hdev->tm_info.prio_tc[i])
+ 			*changed = true;
+ 
+-		if (ets->prio_tc[i] > max_tc)
+-			max_tc = ets->prio_tc[i];
++		if (ets->prio_tc[i] > max_tc_id)
++			max_tc_id = ets->prio_tc[i];
+ 	}
+ 
+-	ret = hclge_dcb_common_validate(hdev, max_tc + 1, ets->prio_tc);
+-	if (ret)
+-		return ret;
++	/* return max tc number, max tc id need to plus 1 */
++	return max_tc_id + 1;
++}
++
++static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev,
++				       struct ieee_ets *ets, bool *changed)
++{
++	bool has_ets_tc = false;
++	u32 total_ets_bw = 0;
++	u8 i;
+ 
+ 	for (i = 0; i < hdev->tc_max; i++) {
+ 		switch (ets->tc_tsa[i]) {
+@@ -148,7 +152,26 @@ static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
+ 	if (has_ets_tc && total_ets_bw != BW_PERCENT)
+ 		return -EINVAL;
+ 
+-	*tc = max_tc + 1;
++	return 0;
++}
++
++static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
++			      u8 *tc, bool *changed)
++{
++	u8 tc_num;
++	int ret;
++
++	tc_num = hclge_ets_tc_changed(hdev, ets, changed);
++
++	ret = hclge_dcb_common_validate(hdev, tc_num, ets->prio_tc);
++	if (ret)
++		return ret;
++
++	ret = hclge_ets_sch_mode_validate(hdev, ets, changed);
++	if (ret)
++		return ret;
++
++	*tc = tc_num;
+ 	if (*tc != hdev->tm_info.num_tc)
+ 		*changed = true;
+ 
+-- 
+2.34.1
+
diff --git a/patches/0481-net-hns3-refine-function-hclge_dbg_dump_tm_pri.patch b/patches/0481-net-hns3-refine-function-hclge_dbg_dump_tm_pri.patch
new file mode 100644
index 0000000..52e06b3
--- /dev/null
+++ b/patches/0481-net-hns3-refine-function-hclge_dbg_dump_tm_pri.patch
@@ -0,0 +1,144 @@
+From 11c3cda9a64e91c9ca65293ba7bd0931ceb17b7b Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:12 +0800
+Subject: [PATCH 120/283] net: hns3: refine function hclge_dbg_dump_tm_pri()
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 04d96139ddb32dd15e5941c303f511a92759a5be
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=04d96139ddb32dd15e5941c303f511a92759a5be
+
+----------------------------------------------------------------------
+
+To improve flexibility, simplicity and maintainability to dump info of
+every element of tm priority, add a struct hclge_dbg_item array of tm
+priority and fill string of every data according to this array.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  1 +
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     | 70 +++++++++++--------
+ 2 files changed, 43 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index c06070cfd4bc..770a572003f3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -167,6 +167,7 @@ enum hclge_opcode_type {
+ 	HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
+ 	HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
+ 	HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
++	HCLGE_OPC_TM_NODES		= 0x0816,
+ 	HCLGE_OPC_ETS_TC_WEIGHT		= 0x0843,
+ 	HCLGE_OPC_QSET_DFX_STS		= 0x0844,
+ 	HCLGE_OPC_PRI_DFX_STS		= 0x0845,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index 6350ad7353d1..01324fdf397a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -890,26 +890,45 @@ static int hclge_dbg_dump_tm_map(struct hclge_dev *hdev, char *buf, int len)
+ 	return 0;
+ }
+ 
++static const struct hclge_dbg_item tm_pri_items[] = {
++	{ "ID", 4 },
++	{ "MODE", 2 },
++	{ "DWRR", 2 },
++	{ "C_IR_B", 2 },
++	{ "C_IR_U", 2 },
++	{ "C_IR_S", 2 },
++	{ "C_BS_B", 2 },
++	{ "C_BS_S", 2 },
++	{ "C_FLAG", 2 },
++	{ "C_RATE(Mbps)", 2 },
++	{ "P_IR_B", 2 },
++	{ "P_IR_U", 2 },
++	{ "P_IR_S", 2 },
++	{ "P_BS_B", 2 },
++	{ "P_BS_S", 2 },
++	{ "P_FLAG", 2 },
++	{ "P_RATE(Mbps)", 0 }
++};
++
+ static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)
+ {
+-	struct hclge_tm_shaper_para c_shaper_para;
+-	struct hclge_tm_shaper_para p_shaper_para;
+-	u8 pri_num, sch_mode, weight;
+-	char *sch_mode_str;
+-	int pos = 0;
+-	int ret;
+-	u8 i;
++	char data_str[ARRAY_SIZE(tm_pri_items)][HCLGE_DBG_DATA_STR_LEN];
++	struct hclge_tm_shaper_para c_shaper_para, p_shaper_para;
++	char *result[ARRAY_SIZE(tm_pri_items)], *sch_mode_str;
++	char content[HCLGE_DBG_TM_INFO_LEN];
++	u8 pri_num, sch_mode, weight, i, j;
++	int pos, ret;
+ 
+ 	ret = hclge_tm_get_pri_num(hdev, &pri_num);
+ 	if (ret)
+ 		return ret;
+ 
+-	pos += scnprintf(buf + pos, len - pos,
+-			 "ID    MODE  DWRR  C_IR_B  C_IR_U  C_IR_S  C_BS_B  ");
+-	pos += scnprintf(buf + pos, len - pos,
+-			 "C_BS_S  C_FLAG  C_RATE(Mbps)  P_IR_B  P_IR_U  ");
+-	pos += scnprintf(buf + pos, len - pos,
+-			 "P_IR_S  P_BS_B  P_BS_S  P_FLAG  P_RATE(Mbps)\n");
++	for (i = 0; i < ARRAY_SIZE(tm_pri_items); i++)
++		result[i] = &data_str[i][0];
++
++	hclge_dbg_fill_content(content, sizeof(content), tm_pri_items,
++			       NULL, ARRAY_SIZE(tm_pri_items));
++	pos = scnprintf(buf, len, "%s", content);
+ 
+ 	for (i = 0; i < pri_num; i++) {
+ 		ret = hclge_tm_get_pri_sch_mode(hdev, i, &sch_mode);
+@@ -935,21 +954,16 @@ static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)
+ 		sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" :
+ 			       "sp";
+ 
+-		pos += scnprintf(buf + pos, len - pos,
+-				 "%04u  %4s  %3u   %3u     %3u     %3u     ",
+-				 i, sch_mode_str, weight, c_shaper_para.ir_b,
+-				 c_shaper_para.ir_u, c_shaper_para.ir_s);
+-		pos += scnprintf(buf + pos, len - pos,
+-				 "%3u     %3u       %1u     %6u        ",
+-				 c_shaper_para.bs_b, c_shaper_para.bs_s,
+-				 c_shaper_para.flag, c_shaper_para.rate);
+-		pos += scnprintf(buf + pos, len - pos,
+-				 "%3u     %3u     %3u     %3u     %3u       ",
+-				 p_shaper_para.ir_b, p_shaper_para.ir_u,
+-				 p_shaper_para.ir_s, p_shaper_para.bs_b,
+-				 p_shaper_para.bs_s);
+-		pos += scnprintf(buf + pos, len - pos, "%1u     %6u\n",
+-				 p_shaper_para.flag, p_shaper_para.rate);
++		j = 0;
++		sprintf(result[j++], "%04u", i);
++		sprintf(result[j++], "%4s", sch_mode_str);
++		sprintf(result[j++], "%3u", weight);
++		hclge_dbg_fill_shaper_content(&c_shaper_para, result, &j);
++		hclge_dbg_fill_shaper_content(&p_shaper_para, result, &j);
++		hclge_dbg_fill_content(content, sizeof(content), tm_pri_items,
++				       (const char **)result,
++				       ARRAY_SIZE(tm_pri_items));
++		pos += scnprintf(buf + pos, len - pos, "%s", content);
+ 	}
+ 
+ 	return 0;
+-- 
+2.34.1
+
diff --git a/patches/0482-net-hnss3-use-max-to-simplify-code.patch b/patches/0482-net-hnss3-use-max-to-simplify-code.patch
new file mode 100644
index 0000000..35907b5
--- /dev/null
+++ b/patches/0482-net-hnss3-use-max-to-simplify-code.patch
@@ -0,0 +1,46 @@
+From 0619878a9e2b36da422ef94c5eb6b69b9b921aea Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Tue, 28 Sep 2021 11:52:14 +0800
+Subject: [PATCH 121/283] net: hnss3: use max() to simplify code
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 38b99e1ede3280f0e286071956bd8632737be57b
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=38b99e1ede3280f0e286071956bd8632737be57b
+
+----------------------------------------------------------------------
+
+Replace the "? :" statement wich max() to simplify code.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 72f26221ee6c..f02b976a89bc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -675,8 +675,7 @@ static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
+ 	/* The free tx buffer is divided into two part, so pick the
+ 	 * larger one.
+ 	 */
+-	return (ntc > (tx_spare->len - ntu) ? ntc :
+-			(tx_spare->len - ntu)) - 1;
++	return max(ntc, tx_spare->len - ntu) - 1;
+ }
+ 
+ static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
+-- 
+2.34.1
+
diff --git a/patches/0483-net-hns3-uniform-parameter-name-of-hclge_ptp_clean_t.patch b/patches/0483-net-hns3-uniform-parameter-name-of-hclge_ptp_clean_t.patch
new file mode 100644
index 0000000..1d06746
--- /dev/null
+++ b/patches/0483-net-hns3-uniform-parameter-name-of-hclge_ptp_clean_t.patch
@@ -0,0 +1,48 @@
+From d85bc64929674d776f3ee71cb639648c615f7876 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Tue, 28 Sep 2021 11:52:15 +0800
+Subject: [PATCH 122/283] net: hns3: uniform parameter name of
+ hclge_ptp_clean_tx_hwts()
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 52d89333d21918ff0ac25d6f8307b7fe6cbfde11
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=52d89333d21918ff0ac25d6f8307b7fe6cbfde11
+
+----------------------------------------------------------------------
+
+The parameter name of hclge_ptp_clean_tx_hwts() in declaration is "dev",
+but the definition of this function is used the common name "hdev" as
+other functions, so modify it.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
+index dbf5f4c08019..7a9b77de632a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
+@@ -127,7 +127,7 @@ static inline struct hclge_dev *hclge_ptp_get_hdev(struct ptp_clock_info *info)
+ }
+ 
+ bool hclge_ptp_set_tx_info(struct hnae3_handle *handle, struct sk_buff *skb);
+-void hclge_ptp_clean_tx_hwts(struct hclge_dev *dev);
++void hclge_ptp_clean_tx_hwts(struct hclge_dev *hdev);
+ void hclge_ptp_get_rx_hwts(struct hnae3_handle *handle, struct sk_buff *skb,
+ 			   u32 nsec, u32 sec);
+ int hclge_ptp_get_cfg(struct hclge_dev *hdev, struct ifreq *ifr);
+-- 
+2.34.1
+
diff --git a/patches/0484-net-hns3-refine-function-hns3_set_default_feature.patch b/patches/0484-net-hns3-refine-function-hns3_set_default_feature.patch
new file mode 100644
index 0000000..d088942
--- /dev/null
+++ b/patches/0484-net-hns3-refine-function-hns3_set_default_feature.patch
@@ -0,0 +1,134 @@
+From 7ac8dac643da2af42736e095cb33e33c4e8e5c7f Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:16 +0800
+Subject: [PATCH 123/283] net: hns3: refine function hns3_set_default_feature()
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit dc9b5ce03124cf86bac3bd714369a8387d6e2012
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=dc9b5ce03124cf86bac3bd714369a8387d6e2012
+
+----------------------------------------------------------------------
+
+Currently, the driver sets default feature for netdev->features,
+netdev->hw_features, netdev->vlan_features and
+netdev->hw_enc_features separately. It's fussy, because most
+of the feature bits are same. So refine it by copy value from
+netdev->features.
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 67 ++++++-------------
+ 1 file changed, 22 insertions(+), 45 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index f02b976a89bc..907d8e62e174 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -2820,17 +2820,7 @@ static void hns3_set_default_feature(struct net_device *netdev)
+ 
+ 	netdev->priv_flags |= IFF_UNICAST_FLT;
+ 
+-	netdev->hw_enc_features |= NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
+-		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
+-		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
+-		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
+-		NETIF_F_FRAGLIST;
+-
+-#ifdef NETIF_F_GSO_PARTIAL
+-	netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
+-
+ 	netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
+-#endif
+ 
+ 	netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
+ 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
+@@ -2840,50 +2830,37 @@ static void hns3_set_default_feature(struct net_device *netdev)
+ 		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
+ 		NETIF_F_FRAGLIST;
+ 
+-	netdev->vlan_features |= NETIF_F_RXCSUM |
+-		NETIF_F_SG | NETIF_F_GSO | NETIF_F_GRO |
+-		NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
+-		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
+-		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
+-		NETIF_F_FRAGLIST;
+-
+-	netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
+-		NETIF_F_HW_VLAN_CTAG_RX |
+-		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
+-		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
+-		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
+-		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
+-		NETIF_F_FRAGLIST;
+-
+ 	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+-#ifdef NETIF_F_GRO_HW
+ 		netdev->features |= NETIF_F_GRO_HW;
+-		netdev->hw_features |= NETIF_F_GRO_HW;
+-#endif
+-		if (!(h->flags & HNAE3_SUPPORT_VF)) {
+-			netdev->hw_features |= NETIF_F_NTUPLE;
++
++		if (!(h->flags & HNAE3_SUPPORT_VF))
+ 			netdev->features |= NETIF_F_NTUPLE;
+-		}
+ 	}
+ 
+-	if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps)) {
+-		netdev->hw_features |= NETIF_F_GSO_UDP_L4;
++	if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
+ 		netdev->features |= NETIF_F_GSO_UDP_L4;
+-		netdev->vlan_features |= NETIF_F_GSO_UDP_L4;
+-		netdev->hw_enc_features |= NETIF_F_GSO_UDP_L4;
+-	}
+ 
+-	if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps)) {
+-		netdev->hw_features |= NETIF_F_HW_CSUM;
++	if (test_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps))
+ 		netdev->features |= NETIF_F_HW_CSUM;
+-		netdev->vlan_features |= NETIF_F_HW_CSUM;
+-		netdev->hw_enc_features |= NETIF_F_HW_CSUM;
+-	} else {
+-		netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
++	else
+ 		netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
+-		netdev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
+-		netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
+-	}
++
++	if (test_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps))
++		netdev->features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
++
++	if (test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps))
++		netdev->features |= NETIF_F_HW_TC;
++
++	netdev->hw_features |= netdev->features;
++	if (!test_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps))
++		netdev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
++
++	netdev->vlan_features |= netdev->features &
++		~(NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX |
++		  NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_GRO_HW | NETIF_F_NTUPLE |
++		  NETIF_F_HW_TC);
++
++	netdev->hw_enc_features |= netdev->vlan_features | NETIF_F_TSO_MANGLEID;
+ }
+ 
+ static int hns3_alloc_buffer(struct hns3_enet_ring *ring,
+-- 
+2.34.1
+
diff --git a/patches/0485-net-hns3-clean-up-a-type-mismatch-warning.patch b/patches/0485-net-hns3-clean-up-a-type-mismatch-warning.patch
new file mode 100644
index 0000000..61f5f2a
--- /dev/null
+++ b/patches/0485-net-hns3-clean-up-a-type-mismatch-warning.patch
@@ -0,0 +1,68 @@
+From 0a9130da92709247e025bc6c5d4aade914f1b0f9 Mon Sep 17 00:00:00 2001
+From: Guojia Liao <liaoguojia@huawei.com>
+Date: Tue, 28 Sep 2021 11:52:17 +0800
+Subject: [PATCH 124/283] net: hns3: clean up a type mismatch warning
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit e79c0e324b011b0288cd411a5b53870a7730f163
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e79c0e324b011b0288cd411a5b53870a7730f163
+
+----------------------------------------------------------------------
+
+abs() returns signed long, which could not convert the type
+as unsigned, and it may cause a mismatch type warning from
+static tools. To fix it, this patch uses an variable to save
+the abs()'s result and does a explicit conversion.
+
+Signed-off-by: Guojia Liao <liaoguojia@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+---
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c | 18 +++++++-----------
+ 1 file changed, 7 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+index a9dd7d0601ab..07d0aaa0634e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+@@ -23,18 +23,14 @@ static const struct errno_respcode_map err_code_map[] = {
+ 
+ static u16 hclge_errno_to_resp(int errno)
+ {
+-#define UNKNOWN_ERR	0xFFFF
++	int resp = abs(errno);
+ 
+-	u32 i;
+-
+-	for (i = 0;
+-	     i < sizeof(err_code_map) / sizeof(struct errno_respcode_map);
+-	     i++) {
+-		if (err_code_map[i].errno == errno)
+-			return err_code_map[i].resp_code;
+-	}
+-
+-	return UNKNOWN_ERR;
++	/* The status for pf to vf msg cmd is u16, constrainted by HW.
++	 * We need to keep the same type with it.
++	 * The intput errno is the stander error code, it's safely to
++	 * use a u16 to store the abs(errno).
++	 */
++	return (u16)resp;
+ }
+ 
+ /* hclge_gen_resp_to_vf: used to generate a synchronous response to VF when PF
+-- 
+2.34.1
+
diff --git a/patches/0486-net-hns3-add-some-required-spaces.patch b/patches/0486-net-hns3-add-some-required-spaces.patch
new file mode 100644
index 0000000..cde3627
--- /dev/null
+++ b/patches/0486-net-hns3-add-some-required-spaces.patch
@@ -0,0 +1,160 @@
+From efbdf2cedadf8a944d2af44f90ece0fa46284868 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Tue, 28 Sep 2021 11:52:18 +0800
+Subject: [PATCH 125/283] net: hns3: add some required spaces
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit c74e503572ea0dbfa6ef3449944a286354f9f9b4
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c74e503572ea0dbfa6ef3449944a286354f9f9b4
+
+----------------------------------------------------------------------
+
+Add some required spaces to improve readability.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  3 ++-
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    | 10 ++++-----
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  2 +-
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   | 13 +++++++++--
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 22 +++++++++----------
+ 5 files changed, 30 insertions(+), 20 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index db061ca74d31..1e53128787f9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -68,7 +68,8 @@
+ #define HNAE3_KNIC_CLIENT_INITED_B		0x3
+ #define HNAE3_UNIC_CLIENT_INITED_B		0x4
+ #define HNAE3_ROCE_CLIENT_INITED_B		0x5
+-#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\
++
++#define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \
+ 		BIT(HNAE3_DEV_SUPPORT_ROCE_B))
+ 
+ #define hnae3_dev_roce_supported(hdev) \
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index fd2debdb517c..3ec72f8b2d87 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -840,11 +840,11 @@ static const struct hns3_dbg_item tx_bd_info_items[] = {
+ 	{ "SIZE", 2 },
+ 	{ "T_CS_VLAN_TSO", 2 },
+ 	{ "OT_VLAN_TAG", 3 },
+-	{ "TV", 5 },
+-	{ "OLT_VLAN_LEN", 2},
+-	{ "PAYLEN_OL4CS", 2},
+-	{ "BD_FE_SC_VLD", 2},
+-	{ "MSS", 2},
++	{ "TV", 2 },
++	{ "OLT_VLAN_LEN", 2 },
++	{ "PAYLEN_OL4CS", 2 },
++	{ "BD_FE_SC_VLD", 2 },
++	{ "MSS_HW_CSUM", 0 },
+ };
+ 
+ static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 907d8e62e174..c5b55b238f18 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -62,7 +62,7 @@ MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to opt
+ 
+ #define HNS3_SGL_SIZE(nfrag)	(sizeof(struct scatterlist) * (nfrag) +	\
+ 				 sizeof(struct sg_table))
+-#define HNS3_MAX_SGL_SIZE	ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM),\
++#define HNS3_MAX_SGL_SIZE	ALIGN(HNS3_SGL_SIZE(HNS3_MAX_TSO_BD_NUM), \
+ 				      dma_get_cache_alignment())
+ 
+ #define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 9278c742e3b0..2dd652fe4514 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -383,6 +383,14 @@ enum hns3_pkt_ol4type {
+ 	HNS3_OL4_TYPE_UNKNOWN
+ };
+ 
++struct hns3_rx_ptype {
++	u32 ptype : 8;
++	u32 csum_level : 2;
++	u32 ip_summed : 2;
++	u32 l3_type : 4;
++	u32 valid : 1;
++};
++
+ struct ring_stats {
+ 	u64 sw_err_cnt;
+ 	u64 seg_pkt_cnt;
+@@ -502,8 +510,9 @@ struct hns3_enet_coalesce {
+ 	u16 int_gl;
+ 	u16 int_ql;
+ 	u16 int_ql_max;
+-	u8 adapt_enable:1;
+-	u8 ql_enable:1;
++	u8 adapt_enable : 1;
++	u8 ql_enable : 1;
++	u8 unit_1us : 1;
+ 	enum hns3_flow_level_range flow_level;
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 30c98e0d12d4..ab8df97248ca 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -370,14 +370,14 @@ static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = {
+ };
+ 
+ static const struct key_info meta_data_key_info[] = {
+-	{ PACKET_TYPE_ID, 6},
+-	{ IP_FRAGEMENT, 1},
+-	{ ROCE_TYPE, 1},
+-	{ NEXT_KEY, 5},
+-	{ VLAN_NUMBER, 2},
+-	{ SRC_VPORT, 12},
+-	{ DST_VPORT, 12},
+-	{ TUNNEL_PACKET, 1},
++	{ PACKET_TYPE_ID, 6 },
++	{ IP_FRAGEMENT, 1 },
++	{ ROCE_TYPE, 1 },
++	{ NEXT_KEY, 5 },
++	{ VLAN_NUMBER, 2 },
++	{ SRC_VPORT, 12 },
++	{ DST_VPORT, 12 },
++	{ TUNNEL_PACKET, 1 },
+ };
+ 
+ static const struct key_info tuple_key_info[] = {
+@@ -723,9 +723,9 @@ static void hclge_update_stats(struct hnae3_handle *handle,
+ 
+ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
+ {
+-#define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
+-		HNAE3_SUPPORT_PHY_LOOPBACK |\
+-		HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
++#define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \
++		HNAE3_SUPPORT_PHY_LOOPBACK | \
++		HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \
+ 		HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
+ 
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+-- 
+2.34.1
+
diff --git a/patches/0487-net-hns3-remove-unnecessary-spaces.patch b/patches/0487-net-hns3-remove-unnecessary-spaces.patch
new file mode 100644
index 0000000..9d82456
--- /dev/null
+++ b/patches/0487-net-hns3-remove-unnecessary-spaces.patch
@@ -0,0 +1,59 @@
+From 956b042fce40a245e8d3d24e16a61fe679dd582a Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Tue, 28 Sep 2021 11:52:19 +0800
+Subject: [PATCH 126/283] net: hns3: remove unnecessary spaces
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 7f2d4b7ffa42565a41f0fd6aa147d84863bb088b
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7f2d4b7ffa42565a41f0fd6aa147d84863bb088b
+
+----------------------------------------------------------------------
+
+This patch removes some unnecessary spaces for cleanup.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c         | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index c5b55b238f18..76bf5fc69e7d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -98,7 +98,7 @@ const struct pci_device_id hns3_pci_tbl[] = {
+ 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
+ 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
+ 	/* required last entry */
+-	{0, }
++	{0,}
+ };
+ MODULE_DEVICE_TABLE(pci, hns3_pci_tbl);
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index ab8df97248ca..438f419f4132 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -5623,7 +5623,7 @@ static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
+ 	cur_key_x = key_x;
+ 	cur_key_y = key_y;
+ 
+-	for (i = 0 ; i < MAX_TUPLE; i++) {
++	for (i = 0; i < MAX_TUPLE; i++) {
+ 		bool tuple_valid;
+ 		u32 check_tuple;
+ 
+-- 
+2.34.1
+
diff --git a/patches/0488-net-hns3-make-hclgevf_cmd_caps_bit_map0-and-hclge_cm.patch b/patches/0488-net-hns3-make-hclgevf_cmd_caps_bit_map0-and-hclge_cm.patch
new file mode 100644
index 0000000..85a878d
--- /dev/null
+++ b/patches/0488-net-hns3-make-hclgevf_cmd_caps_bit_map0-and-hclge_cm.patch
@@ -0,0 +1,70 @@
+From 3d768317f46cd3e34e929f9a3151a89478abc7bd Mon Sep 17 00:00:00 2001
+From: chongjiapeng <jiapeng.chong@linux.alibaba.com>
+Date: Mon, 11 Oct 2021 11:13:19 +0800
+Subject: [PATCH 127/283] net: hns3: make hclgevf_cmd_caps_bit_map0 and
+ hclge_cmd_caps_bit_map0 static
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit 0c0383918a3ec4250e318cdbdd32e1caef12c14c
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0c0383918a3ec4250e318cdbdd32e1caef12c14c
+
+----------------------------------------------------------------------
+
+This symbols is not used outside of hclge_cmd.c and hclgevf_cmd.c, so marks
+it static.
+
+Fix the following sparse warning:
+
+drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c:345:35:
+warning: symbol 'hclgevf_cmd_caps_bit_map0' was not declared. Should it
+be static?
+
+drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c:365:33: warning:
+symbol 'hclge_cmd_caps_bit_map0' was not declared. Should it be static?
+
+Reported-by: Abaci Robot <abaci@linux.alibaba.com>
+Signed-off-by: chongjiapeng <jiapeng.chong@linux.alibaba.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c   | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 1471330ee5d9..64a6031c64fe 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -373,7 +373,7 @@ static void hclge_set_default_capability(struct hclge_dev *hdev)
+ 	set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
+ }
+ 
+-const struct hclge_caps_bit_map hclge_cmd_caps_bit_map0[] = {
++static const struct hclge_caps_bit_map hclge_cmd_caps_bit_map0[] = {
+ 	{HCLGE_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
+ 	{HCLGE_CAP_PTP_B, HNAE3_DEV_SUPPORT_PTP_B},
+ 	{HCLGE_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 0356af21ff44..37e0fc7e570b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -358,7 +358,7 @@ static void hclgevf_set_default_capability(struct hclgevf_dev *hdev)
+ 	set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
+ }
+ 
+-const struct hclgevf_caps_bit_map hclgevf_cmd_caps_bit_map0[] = {
++static const struct hclgevf_caps_bit_map hclgevf_cmd_caps_bit_map0[] = {
+ 	{HCLGEVF_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
+ 	{HCLGEVF_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
+ 	{HCLGEVF_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
+-- 
+2.34.1
+
diff --git a/patches/0489-net-hns3-fix-misuse-vf-id-and-vport-id-in-some-logs.patch b/patches/0489-net-hns3-fix-misuse-vf-id-and-vport-id-in-some-logs.patch
new file mode 100644
index 0000000..78d6486
--- /dev/null
+++ b/patches/0489-net-hns3-fix-misuse-vf-id-and-vport-id-in-some-logs.patch
@@ -0,0 +1,54 @@
+From 27fb70e76f8226914d0163b9bf635f03df5ebe58 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Mon, 11 Oct 2021 11:13:27 +0800
+Subject: [PATCH 128/283] net: hns3: fix misuse vf id and vport id in some logs
+
+mainline inclusion
+from mainline-v5.15-rc3
+commit 311c0aaa9b4bb8dc65f22634e15963316b17c921
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=311c0aaa9b4bb8dc65f22634e15963316b17c921
+
+----------------------------------------------------------------------
+
+vport_id include PF and VFs, vport_id = 0 means PF, other values mean VFs.
+So the actual vf id is equal to vport_id minus 1.
+
+Some VF print logs are actually vport, and logs of vf id actually use
+vport id, so this patch fixes them.
+
+Fixes: ac887be5b0fe ("net: hns3: change print level of RAS error log from warning to error")
+Fixes: adcf738b804b ("net: hns3: cleanup some print format warning")
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 094f49087f72..dd607bfad25d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -2467,7 +2467,7 @@ static void hclge_handle_over_8bd_err(struct hclge_dev *hdev,
+ 		ret = hclge_inform_reset_assert_to_vf(&hdev->vport[vf_id]);
+ 		if (ret)
+ 			dev_err(dev, "inform reset to vport(%u) failed %d!\n",
+-				hdev->vport->vport_id, ret);
++				vf_id, ret);
+ 	} else {
+ 		set_bit(HNAE3_FUNC_RESET, reset_requests);
+ 	}
+-- 
+2.34.1
+
diff --git a/patches/0490-net-hns3-optimize-the-rx-page-reuse-handling-process.patch b/patches/0490-net-hns3-optimize-the-rx-page-reuse-handling-process.patch
new file mode 100644
index 0000000..e496cbe
--- /dev/null
+++ b/patches/0490-net-hns3-optimize-the-rx-page-reuse-handling-process.patch
@@ -0,0 +1,166 @@
+From eb403e52b15e84ee38bbce5b6145147a4df78b4f Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Sat, 24 Jul 2021 15:45:26 +0800
+Subject: [PATCH 129/283] net: hns3: optimize the rx page reuse handling
+ process
+
+mainline inclusion
+from mainline-v5.14-rc1
+commit fa7711b888f24ee9291d90f8fbdaccfc80ed72c7
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fa7711b888f24ee9291d90f8fbdaccfc80ed72c7
+
+----------------------------------------------------------------------
+
+Current rx page offset only reset to zero when all the below
+conditions are satisfied:
+1. rx page is only owned by driver.
+2. rx page is reusable.
+3. the page offset that is above to be given to the stack has
+reached the end of the page.
+
+If the page offset is over the hns3_buf_size(), it means the
+buffer below the offset of the page is usable when the above
+condition 1 & 2 are satisfied, so page offset can be reset to
+zero instead of increasing the offset. We may be able to always
+reuse the first 4K buffer of a 64K page, which means we can
+limit the hot buffer size as much as possible.
+
+The above optimization is a side effect when refacting the
+rx page reuse handling in order to support the rx copybreak.
+
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 60 +++++++++++--------
+ include/linux/skbuff.h                        | 16 +++++
+ 2 files changed, 50 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 76bf5fc69e7d..c84a5e942b68 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -3194,7 +3194,35 @@ static bool hns3_page_is_reusable(struct page *page)
+ 
+ static bool hns3_can_reuse_page(struct hns3_desc_cb *cb)
+ {
+-	return (page_count(cb->priv) - cb->pagecnt_bias) == 1;
++	return page_count(cb->priv) == cb->pagecnt_bias;
++}
++
++static int hns3_handle_rx_copybreak(struct sk_buff *skb, int i,
++				    struct hns3_enet_ring *ring,
++				    int pull_len,
++				    struct hns3_desc_cb *desc_cb)
++{
++	struct hns3_desc *desc = &ring->desc[ring->next_to_clean];
++	u32 frag_offset = desc_cb->page_offset + pull_len;
++	int size = le16_to_cpu(desc->rx.size);
++	u32 frag_size = size - pull_len;
++	void *frag = napi_alloc_frag(frag_size);
++
++	if (unlikely(!frag)) {
++		hns3_ring_stats_update(ring, frag_alloc_err);
++
++		hns3_rl_err(ring_to_netdev(ring),
++			    "failed to allocate rx frag\n");
++		return -ENOMEM;
++	}
++
++	desc_cb->reuse_flag = 1;
++	memcpy(frag, desc_cb->buf + frag_offset, frag_size);
++	skb_add_rx_frag(skb, i, virt_to_page(frag),
++			offset_in_page(frag), frag_size, frag_size);
++
++	hns3_ring_stats_update(ring, frag_alloc);
++	return 0;
+ }
+ 
+ static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
+@@ -3206,13 +3234,12 @@ static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
+ 	int size = le16_to_cpu(desc->rx.size);
+ 	u32 truesize = hns3_buf_size(ring);
+ 	u32 frag_size = size - pull_len;
++	int ret = 0;
+ 	bool reused;
+ 
+-	if (unlikely(!hns3_page_is_reusable(desc_cb->priv)) ||
+-	    (!desc_cb->page_offset && !hns3_can_reuse_page(desc_cb))) {
+-		__page_frag_cache_drain(desc_cb->priv, desc_cb->pagecnt_bias);
+-		return;
+-	}
++	/* Avoid re-using remote or pfmem page */
++	if (unlikely(!dev_page_is_reusable(desc_cb->priv)))
++		goto out;
+ 
+ 	reused = hns3_can_reuse_page(desc_cb);
+ 
+@@ -3236,26 +3263,7 @@ static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
+ 		desc_cb->page_offset = 0;
+ 		desc_cb->reuse_flag = 1;
+ 	} else if (frag_size <= ring->rx_copybreak) {
+-		void *frag = napi_alloc_frag(frag_size);
+-
+-		if (unlikely(!frag)) {
+-			u64_stats_update_begin(&ring->syncp);
+-			ring->stats.frag_alloc_err++;
+-			u64_stats_update_end(&ring->syncp);
+-
+-			hns3_rl_err(ring_to_netdev(ring),
+-				    "failed to allocate rx frag\n");
+-			goto out;
+-		}
+-
+-		desc_cb->reuse_flag = 1;
+-		memcpy(frag, desc_cb->buf + frag_offset, frag_size);
+-		skb_add_rx_frag(skb, i, virt_to_page(frag),
+-				offset_in_page(frag), frag_size, frag_size);
+-
+-		u64_stats_update_begin(&ring->syncp);
+-		ring->stats.frag_alloc++;
+-		u64_stats_update_end(&ring->syncp);
++		ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
+ 		return;
+ 	}
+ 
+diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
+index b67d42871ee9..bf080a114205 100644
+--- a/include/linux/skbuff.h
++++ b/include/linux/skbuff.h
+@@ -2789,6 +2789,22 @@ static inline struct page *dev_alloc_page(void)
+ 	return dev_alloc_pages(0);
+ }
+ 
++/**
++ * dev_page_is_reusable - check whether a page can be reused for network Rx
++ * @page: the page to test
++ *
++ * A page shouldn't be considered for reusing/recycling if it was allocated
++ * under memory pressure or at a distant memory node.
++ *
++ * Returns false if this page should be returned to page allocator, true
++ * otherwise.
++ */
++static inline bool dev_page_is_reusable(struct page *page)
++{
++	return likely(page_to_nid(page) == numa_mem_id() &&
++		      !page_is_pfmemalloc(page));
++}
++
+ /**
+  *	skb_propagate_pfmemalloc - Propagate pfmemalloc if skb is allocated after RX page
+  *	@page: The page that was allocated from skb_alloc_page
+-- 
+2.34.1
+
diff --git a/patches/0491-net-hns3-do-not-allow-call-hns3_nic_net_open-repeate.patch b/patches/0491-net-hns3-do-not-allow-call-hns3_nic_net_open-repeate.patch
new file mode 100644
index 0000000..033a893
--- /dev/null
+++ b/patches/0491-net-hns3-do-not-allow-call-hns3_nic_net_open-repeate.patch
@@ -0,0 +1,99 @@
+From 175240131298a56f823ae21e8629bb605cd99308 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Mon, 15 Nov 2021 19:40:52 +0800
+Subject: [PATCH 130/283] net: hns3: do not allow call hns3_nic_net_open
+ repeatedly
+
+mainline inclusion
+from mainline-v5.15-rc4
+commit 5b09e88e1bf7fe86540fab4b5f3eece8abead39e
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5b09e88e1bf7fe86540fab4b5f3eece8abead39e
+
+--------------------------------
+
+[ Upstream commit 5b09e88e1bf7fe86540fab4b5f3eece8abead39e ]
+
+hns3_nic_net_open() is not allowed to called repeatly, but there
+is no checking for this. When doing device reset and setup tc
+concurrently, there is a small oppotunity to call hns3_nic_net_open
+repeatedly, and cause kernel bug by calling napi_enable twice.
+
+The calltrace information is like below:
+[ 3078.222780] ------------[ cut here ]------------
+[ 3078.230255] kernel BUG at net/core/dev.c:6991!
+[ 3078.236224] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
+[ 3078.243431] Modules linked in: hns3 hclgevf hclge hnae3 vfio_iommu_type1 vfio_pci vfio_virqfd vfio pv680_mii(O)
+[ 3078.258880] CPU: 0 PID: 295 Comm: kworker/u8:5 Tainted: G           O      5.14.0-rc4+ #1
+[ 3078.269102] Hardware name:  , BIOS KpxxxFPGA 1P B600 V181 08/12/2021
+[ 3078.276801] Workqueue: hclge hclge_service_task [hclge]
+[ 3078.288774] pstate: 60400009 (nZCv daif +PAN -UAO -TCO BTYPE=--)
+[ 3078.296168] pc : napi_enable+0x80/0x84
+tc qdisc sho[w  3d0e7v8 .e3t0h218 79] lr : hns3_nic_net_open+0x138/0x510 [hns3]
+
+[ 3078.314771] sp : ffff8000108abb20
+[ 3078.319099] x29: ffff8000108abb20 x28: 0000000000000000 x27: ffff0820a8490300
+[ 3078.329121] x26: 0000000000000001 x25: ffff08209cfc6200 x24: 0000000000000000
+[ 3078.339044] x23: ffff0820a8490300 x22: ffff08209cd76000 x21: ffff0820abfe3880
+[ 3078.349018] x20: 0000000000000000 x19: ffff08209cd76900 x18: 0000000000000000
+[ 3078.358620] x17: 0000000000000000 x16: ffffc816e1727a50 x15: 0000ffff8f4ff930
+[ 3078.368895] x14: 0000000000000000 x13: 0000000000000000 x12: 0000259e9dbeb6b4
+[ 3078.377987] x11: 0096a8f7e764eb40 x10: 634615ad28d3eab5 x9 : ffffc816ad8885b8
+[ 3078.387091] x8 : ffff08209cfc6fb8 x7 : ffff0820ac0da058 x6 : ffff0820a8490344
+[ 3078.396356] x5 : 0000000000000140 x4 : 0000000000000003 x3 : ffff08209cd76938
+[ 3078.405365] x2 : 0000000000000000 x1 : 0000000000000010 x0 : ffff0820abfe38a0
+[ 3078.414657] Call trace:
+[ 3078.418517]  napi_enable+0x80/0x84
+[ 3078.424626]  hns3_reset_notify_up_enet+0x78/0xd0 [hns3]
+[ 3078.433469]  hns3_reset_notify+0x64/0x80 [hns3]
+[ 3078.441430]  hclge_notify_client+0x68/0xb0 [hclge]
+[ 3078.450511]  hclge_reset_rebuild+0x524/0x884 [hclge]
+[ 3078.458879]  hclge_reset_service_task+0x3c4/0x680 [hclge]
+[ 3078.467470]  hclge_service_task+0xb0/0xb54 [hclge]
+[ 3078.475675]  process_one_work+0x1dc/0x48c
+[ 3078.481888]  worker_thread+0x15c/0x464
+[ 3078.487104]  kthread+0x160/0x170
+[ 3078.492479]  ret_from_fork+0x10/0x18
+[ 3078.498785] Code: c8027c81 35ffffa2 d50323bf d65f03c0 (d4210000)
+[ 3078.506889] ---[ end trace 8ebe0340a1b0fb44 ]---
+
+Once hns3_nic_net_open() is excute success, the flag
+HNS3_NIC_STATE_DOWN will be cleared. So add checking for this
+flag, directly return when HNS3_NIC_STATE_DOWN is no set.
+
+Fixes: e888402789b9 ("net: hns3: call hns3_nic_net_open() while doing HNAE3_UP_CLIENT")
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Acked-by: Weilong Chen <chenweilong@huawei.com>
+
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index c84a5e942b68..5b4553743987 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -481,6 +481,11 @@ static int hns3_nic_net_open(struct net_device *netdev)
+ 	if (hns3_nic_resetting(netdev))
+ 		return -EBUSY;
+ 
++	if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
++		netdev_warn(netdev, "net open repeatedly!\n");
++		return 0;
++	}
++
+ 	netif_carrier_off(netdev);
+ 
+ 	ret = hns3_nic_set_real_num_queue(netdev);
+-- 
+2.34.1
+
diff --git a/patches/0492-net-hns3-fix-show-wrong-state-when-add-existing-uc-m.patch b/patches/0492-net-hns3-fix-show-wrong-state-when-add-existing-uc-m.patch
new file mode 100644
index 0000000..3e8f076
--- /dev/null
+++ b/patches/0492-net-hns3-fix-show-wrong-state-when-add-existing-uc-m.patch
@@ -0,0 +1,78 @@
+From 9a0dab187b71a973fe8b452daa4df052ee5aeb4b Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Mon, 15 Nov 2021 19:40:54 +0800
+Subject: [PATCH 131/283] net: hns3: fix show wrong state when add existing uc
+ mac address
+
+mainline inclusion
+from mainline-v5.15-rc4
+commit 108b3c7810e14892c4a1819b1d268a2c785c087c
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=108b3c7810e14892c4a1819b1d268a2c785c087c
+
+--------------------------------
+
+[ Upstream commit 108b3c7810e14892c4a1819b1d268a2c785c087c ]
+
+Currently, if function adds an existing unicast mac address, eventhough
+driver will not add this address into hardware, but it will return 0 in
+function hclge_add_uc_addr_common(). It will cause the state of this
+unicast mac address is ACTIVE in driver, but it should be in TO-ADD state.
+
+To fix this problem, function hclge_add_uc_addr_common() returns -EEXIST
+if mac address is existing, and delete two error log to avoid printing
+them all the time after this modification.
+
+Fixes: 72110b567479 ("net: hns3: return 0 and print warning when hit duplicate MAC")
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Acked-by: Weilong Chen <chenweilong@huawei.com>
+
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c  | 12 +++++++-----
+ 1 file changed, 7 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 438f419f4132..64371eeaf9e7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -7931,10 +7931,6 @@ int hclge_add_uc_addr_common(struct hclge_vport *vport,
+ 	if (!ret)
+ 		return -EEXIST;
+ 
+-	dev_err(&hdev->pdev->dev,
+-		"PF failed to add unicast entry(%pM) in the MAC table\n",
+-		addr);
+-
+ 	return -ENOSPC;
+ }
+ 
+@@ -8091,7 +8087,13 @@ static void hclge_sync_mac_list(struct hclge_vport *vport,
+ 		} else {
+ 			set_bit(HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
+ 				&vport->state);
+-			break;
++
++			/* If one unicast mac address is existing in hardware,
++			 * we need to try whether other unicast mac addresses
++			 * are new addresses that can be added.
++			 */
++			if (ret != -EEXIST)
++				break;
+ 		}
+ 	}
+ }
+-- 
+2.34.1
+
diff --git a/patches/0493-net-hns3-fix-always-enable-rx-vlan-filter-problem-af.patch b/patches/0493-net-hns3-fix-always-enable-rx-vlan-filter-problem-af.patch
new file mode 100644
index 0000000..d6b4504
--- /dev/null
+++ b/patches/0493-net-hns3-fix-always-enable-rx-vlan-filter-problem-af.patch
@@ -0,0 +1,57 @@
+From 6342321447769074b8dbecec431e44c399090881 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Mon, 15 Nov 2021 19:40:56 +0800
+Subject: [PATCH 132/283] net: hns3: fix always enable rx vlan filter problem
+ after selftest
+
+mainline inclusion
+from mainline-v5.15-rc4
+commit 27bf4af69fcb9845fb2f0076db5d562ec072e70f
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=27bf4af69fcb9845fb2f0076db5d562ec072e70f
+
+--------------------------------
+
+[ Upstream commit 27bf4af69fcb9845fb2f0076db5d562ec072e70f ]
+
+Currently, the rx vlan filter will always be disabled before selftest and
+be enabled after selftest as the rx vlan filter feature is fixed on in
+old device earlier than V3.
+
+However, this feature is not fixed in some new devices and it can be
+disabled by user. In this case, it is wrong if rx vlan filter is enabled
+after selftest. So fix it.
+
+Fixes: bcc26e8dc432 ("net: hns3: remove unused code in hns3_self_test()")
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Acked-by: Weilong Chen <chenweilong@huawei.com>
+
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index f54d00a1e150..1624df0ac6e4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -368,7 +368,8 @@ static void hns3_selftest_restore(struct net_device *ndev, bool if_running)
+ 		h->ae_algo->ops->halt_autoneg(h, false);
+ 
+ #if IS_ENABLED(CONFIG_VLAN_8021Q)
+-	if (h->ae_algo->ops->enable_vlan_filter)
++	if (h->ae_algo->ops->enable_vlan_filter &&
++	    ndev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
+ 		h->ae_algo->ops->enable_vlan_filter(h, true);
+ #endif
+ 
+-- 
+2.34.1
+
diff --git a/patches/0494-net-hns3-add-limit-ets-dwrr-bandwidth-cannot-be-0.patch b/patches/0494-net-hns3-add-limit-ets-dwrr-bandwidth-cannot-be-0.patch
new file mode 100644
index 0000000..cf68ada
--- /dev/null
+++ b/patches/0494-net-hns3-add-limit-ets-dwrr-bandwidth-cannot-be-0.patch
@@ -0,0 +1,60 @@
+From 37eebb9dc894682b3f816a2d4905646b29a8fc90 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Mon, 15 Nov 2021 19:47:18 +0800
+Subject: [PATCH 133/283] net: hns3: add limit ets dwrr bandwidth cannot be 0
+
+mainline inclusion
+from mainline-v5.15-rc7
+commit 731797fdffa3d083db536e2fdd07ceb050bb40b1
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=731797fdffa3d083db536e2fdd07ceb050bb40b1
+
+--------------------------------
+
+[ Upstream commit 731797fdffa3d083db536e2fdd07ceb050bb40b1 ]
+
+If ets dwrr bandwidth of tc is set to 0, the hardware will switch to SP
+mode. In this case, this tc may occupy all the tx bandwidth if it has
+huge traffic, so it violates the purpose of the user setting.
+
+To fix this problem, limit the ets dwrr bandwidth must greater than 0.
+
+Fixes: cacde272dd00 ("net: hns3: Add hclge_dcb module for the support of DCB feature")
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Acked-by: Weilong Chen <chenweilong@huawei.com>
+
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+index 65c38d972a4d..188daf75be32 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+@@ -137,6 +137,15 @@ static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev,
+ 				*changed = true;
+ 			break;
+ 		case IEEE_8021QAZ_TSA_ETS:
++			/* The hardware will switch to sp mode if bandwidth is
++			 * 0, so limit ets bandwidth must be greater than 0.
++			 */
++			if (!ets->tc_tx_bw[i]) {
++				dev_err(&hdev->pdev->dev,
++					"tc%u ets bw cannot be 0\n", i);
++				return -EINVAL;
++			}
++
+ 			if (hdev->tm_info.tc_info[i].tc_sch_mode !=
+ 				HCLGE_SCH_MODE_DWRR)
+ 				*changed = true;
+-- 
+2.34.1
+
diff --git a/patches/0495-net-hns3-disable-sriov-before-unload-hclge-layer.patch b/patches/0495-net-hns3-disable-sriov-before-unload-hclge-layer.patch
new file mode 100644
index 0000000..8ce88b7
--- /dev/null
+++ b/patches/0495-net-hns3-disable-sriov-before-unload-hclge-layer.patch
@@ -0,0 +1,104 @@
+From d04406bd4d87014610beeae0dea1f577b0263b44 Mon Sep 17 00:00:00 2001
+From: Peng Li <lipeng321@huawei.com>
+Date: Mon, 15 Nov 2021 19:47:20 +0800
+Subject: [PATCH 134/283] net: hns3: disable sriov before unload hclge layer
+
+mainline inclusion
+from mainline-v5.15-rc7
+commit 0dd8a25f355b4df2d41c08df1716340854c7d4c5
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0dd8a25f355b4df2d41c08df1716340854c7d4c5
+
+--------------------------------
+
+[ Upstream commit 0dd8a25f355b4df2d41c08df1716340854c7d4c5 ]
+
+HNS3 driver includes hns3.ko, hnae3.ko and hclge.ko.
+hns3.ko includes network stack and pci_driver, hclge.ko includes
+HW device action, algo_ops and timer task, hnae3.ko includes some
+register function.
+
+When SRIOV is enable and hclge.ko is removed, HW device is unloaded
+but VF still exists, PF will not reply VF mbx messages, and cause
+errors.
+
+This patch fix it by disable SRIOV before remove hclge.ko.
+
+Fixes: e2cb1dec9779 ("net: hns3: Add HNS3 VF HCL(Hardware Compatibility Layer) Support")
+Signed-off-by: Peng Li <lipeng321@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Acked-by: Weilong Chen <chenweilong@huawei.com>
+
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.c   | 21 +++++++++++++++++++
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  1 +
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  1 +
+ 3 files changed, 23 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.c b/drivers/net/ethernet/hisilicon/hns3/hnae3.c
+index 53a87b318713..a90921bd07e7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.c
+@@ -10,6 +10,27 @@ static LIST_HEAD(hnae3_ae_algo_list);
+ static LIST_HEAD(hnae3_client_list);
+ static LIST_HEAD(hnae3_ae_dev_list);
+ 
++void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo)
++{
++	const struct pci_device_id *pci_id;
++	struct hnae3_ae_dev *ae_dev;
++
++	if (!ae_algo)
++		return;
++
++	list_for_each_entry(ae_dev, &hnae3_ae_dev_list, node) {
++		if (!hnae3_get_bit(ae_dev->flag, HNAE3_DEV_INITED_B))
++			continue;
++
++		pci_id = pci_match_id(ae_algo->pdev_id_table, ae_dev->pdev);
++		if (!pci_id)
++			continue;
++		if (IS_ENABLED(CONFIG_PCI_IOV))
++			pci_disable_sriov(ae_dev->pdev);
++	}
++}
++EXPORT_SYMBOL(hnae3_unregister_ae_algo_prepare);
++
+ /* we are keeping things simple and using single lock for all the
+  * list. This is a non-critical code so other updations, if happen
+  * in parallel, can wait.
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 1e53128787f9..46e9e3879826 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -925,6 +925,7 @@ struct hnae3_handle {
+ int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
+ void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
+ 
++void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo);
+ void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo);
+ void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo);
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 64371eeaf9e7..8c3cd8e52c7f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -12224,6 +12224,7 @@ module_init(hclge_init);
+ 
+ static void hclge_exit(void)
+ {
++	hnae3_unregister_ae_algo_prepare(&ae_algo);
+ 	hnae3_unregister_ae_algo(&ae_algo);
+ 	destroy_workqueue(hclge_wq);
+ }
+-- 
+2.34.1
+
diff --git a/patches/0496-net-hns3-fix-the-max-tx-size-according-to-user-manua.patch b/patches/0496-net-hns3-fix-the-max-tx-size-according-to-user-manua.patch
new file mode 100644
index 0000000..575578a
--- /dev/null
+++ b/patches/0496-net-hns3-fix-the-max-tx-size-according-to-user-manua.patch
@@ -0,0 +1,80 @@
+From 70bef4cc14e4a49a6cc2a931cd6a6e0bc3155888 Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Mon, 15 Nov 2021 19:48:01 +0800
+Subject: [PATCH 135/283] net: hns3: fix the max tx size according to user
+ manual
+
+mainline inclusion
+from mainline-v5.15-rc7
+commit adfb7b4966c0c4c63a791f202b8b3837b07a9ece
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=adfb7b4966c0c4c63a791f202b8b3837b07a9ece
+
+--------------------------------
+
+commit adfb7b4966c0c4c63a791f202b8b3837b07a9ece upstream.
+
+Currently the max tx size supported by the hw is calculated by
+using the max BD num supported by the hw. According to the hw
+user manual, the max tx size is fixed value for both non-TSO and
+TSO skb.
+
+This patch updates the max tx size according to the manual.
+
+Fixes: 8ae10cfb5089("net: hns3: support tx-scatter-gather-fraglist feature")
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Acked-by: Weilong Chen <chenweilong@huawei.com>
+
+Signed-off-by: Chen Jun <chenjun102@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 3 ++-
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 7 ++-----
+ 2 files changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 5b4553743987..b0699bffb22a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -1559,7 +1559,8 @@ void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size)
+ 		size[i] = skb_frag_size(&shinfo->frags[i]);
+ }
+ 
+-static int hns3_skb_linearize(struct hns3_enet_ring *ring, struct sk_buff *skb,
++static int hns3_skb_linearize(struct hns3_enet_ring *ring,
++			      struct sk_buff *skb,
+ 			      unsigned int bd_num)
+ {
+ 	/* 'bd_num == UINT_MAX' means the skb' fraglist has a
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 2dd652fe4514..b082f0fa7064 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -185,11 +185,8 @@ enum hns3_nic_state {
+ #define HNS3_MAX_BD_SIZE			65535
+ #define HNS3_MAX_NON_TSO_BD_NUM			8U
+ #define HNS3_MAX_TSO_BD_NUM			63U
+-#define HNS3_MAX_TSO_SIZE \
+-	(HNS3_MAX_BD_SIZE * HNS3_MAX_TSO_BD_NUM)
+-
+-#define HNS3_MAX_NON_TSO_SIZE \
+-	(HNS3_MAX_BD_SIZE * HNS3_MAX_NON_TSO_BD_NUM)
++#define HNS3_MAX_TSO_SIZE			1048576U
++#define HNS3_MAX_NON_TSO_SIZE			9728U
+ 
+ #define HNS3_VECTOR_GL0_OFFSET			0x100
+ #define HNS3_VECTOR_GL1_OFFSET			0x200
+-- 
+2.34.1
+
diff --git a/patches/0497-xdp-Fixed-an-issue-where-the-trace_mem_disconnect-fu.patch b/patches/0497-xdp-Fixed-an-issue-where-the-trace_mem_disconnect-fu.patch
new file mode 100644
index 0000000..08cc500
--- /dev/null
+++ b/patches/0497-xdp-Fixed-an-issue-where-the-trace_mem_disconnect-fu.patch
@@ -0,0 +1,36 @@
+From d57440c33c4f59d39b1a41863269e3ca693b9613 Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Mon, 3 Jul 2023 17:03:00 +0800
+Subject: [PATCH 136/283] xdp: Fixed an issue where the trace_mem_disconnect
+ function cannot find the definition.
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+
+--------------------------------
+
+Fix kabi changes caused by the introduction of new xdp header files.
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ net/core/xdp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/net/core/xdp.c b/net/core/xdp.c
+index 89b6785cef2a..978bd4432a73 100644
+--- a/net/core/xdp.c
++++ b/net/core/xdp.c
+@@ -14,6 +14,9 @@
+ #include <net/page_pool.h>
+ 
+ #include <net/xdp.h>
++#ifndef __GENKSYMS__
++#include <trace/events/xdp.h>
++#endif
+ 
+ #define REG_STATE_NEW		0x0
+ #define REG_STATE_REGISTERED	0x1
+-- 
+2.34.1
+
diff --git a/patches/0498-net-hns3-fix-hclge_dbg_dump_tm_pg-stack-usage.patch b/patches/0498-net-hns3-fix-hclge_dbg_dump_tm_pg-stack-usage.patch
new file mode 100644
index 0000000..fe23b8a
--- /dev/null
+++ b/patches/0498-net-hns3-fix-hclge_dbg_dump_tm_pg-stack-usage.patch
@@ -0,0 +1,95 @@
+From 565e3a423b4b225f7ada13c18d5005c8822710a4 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 18 Nov 2021 20:44:30 +0800
+Subject: [PATCH 137/283] net: hns3: fix hclge_dbg_dump_tm_pg() stack usage
+
+mainline inclusion
+from mainline-v5.15-rc4
+commit c894b51e2a23c8c00acb3cea5045c5b70691e790
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c894b51e2a23c8c00acb3cea5045c5b70691e790
+
+----------------------------------------------------------------------
+
+This function copies strings around between multiple buffers
+including a large on-stack array that causes a build warning
+on 32-bit systems:
+
+drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c: In function 'hclge_dbg_dump_tm_pg':
+drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c:782:1: error: the frame size of 1424 bytes is larger than 1400 bytes [-Werror=frame-larger-than=]
+
+The function can probably be cleaned up a lot, to go back to
+printing directly into the output buffer, but dynamically allocating
+the structure is a simpler workaround for now.
+
+Fixes: 04d96139ddb3 ("net: hns3: refine function hclge_dbg_dump_tm_pri()")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     | 28 ++++++++++++++++---
+ 1 file changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index 01324fdf397a..6d03af2597b3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -716,9 +716,9 @@ static void hclge_dbg_fill_shaper_content(struct hclge_tm_shaper_para *para,
+ 	sprintf(result[(*index)++], "%6u", para->rate);
+ }
+ 
+-static int hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *buf, int len)
++static int __hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *data_str,
++				  char *buf, int len)
+ {
+-	char data_str[ARRAY_SIZE(tm_pg_items)][HCLGE_DBG_DATA_STR_LEN];
+ 	struct hclge_tm_shaper_para c_shaper_para, p_shaper_para;
+ 	char *result[ARRAY_SIZE(tm_pg_items)], *sch_mode_str;
+ 	u8 pg_id, sch_mode, weight, pri_bit_map, i, j;
+@@ -726,8 +726,10 @@ static int hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *buf, int len)
+ 	int pos = 0;
+ 	int ret;
+ 
+-	for (i = 0; i < ARRAY_SIZE(tm_pg_items); i++)
+-		result[i] = &data_str[i][0];
++	for (i = 0; i < ARRAY_SIZE(tm_pg_items); i++) {
++		result[i] = data_str;
++		data_str += HCLGE_DBG_DATA_STR_LEN;
++	}
+ 
+ 	hclge_dbg_fill_content(content, sizeof(content), tm_pg_items,
+ 			       NULL, ARRAY_SIZE(tm_pg_items));
+@@ -778,6 +780,24 @@ static int hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *buf, int len)
+ 	return 0;
+ }
+ 
++static int hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *buf, int len)
++{
++	char *data_str;
++	int ret;
++
++	data_str = kcalloc(ARRAY_SIZE(tm_pg_items),
++			   HCLGE_DBG_DATA_STR_LEN, GFP_KERNEL);
++
++	if (!data_str)
++		return -ENOMEM;
++
++	ret = __hclge_dbg_dump_tm_pg(hdev, data_str, buf, len);
++
++	kfree(data_str);
++
++	return ret;
++}
++
+ static int hclge_dbg_dump_tm_port(struct hclge_dev *hdev,  char *buf, int len)
+ {
+ 	struct hclge_tm_shaper_para shaper_para;
+-- 
+2.34.1
+
diff --git a/patches/0499-net-hns3-don-t-rollback-when-destroy-mqprio-fail.patch b/patches/0499-net-hns3-don-t-rollback-when-destroy-mqprio-fail.patch
new file mode 100644
index 0000000..2f0c284
--- /dev/null
+++ b/patches/0499-net-hns3-don-t-rollback-when-destroy-mqprio-fail.patch
@@ -0,0 +1,73 @@
+From a9a74beb23488ffb9370d5b533f2f2152e08f3b9 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:32 +0800
+Subject: [PATCH 138/283] net: hns3: don't rollback when destroy mqprio fail
+
+mainline inclusion
+from mainline-v5.15-rc4
+commit d82650be60ee92e7486f755f5387023278aa933f
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d82650be60ee92e7486f755f5387023278aa933f
+
+----------------------------------------------------------------------
+
+For destroy mqprio is irreversible in stack, so it's unnecessary
+to rollback the tc configuration when destroy mqprio failed.
+Otherwise, it may cause the configuration being inconsistent
+between driver and netstack.
+
+As the failure is usually caused by reset, and the driver will
+restore the configuration after reset, so it can keep the
+configuration being consistent between driver and hardware.
+
+Fixes: 5a5c90917467 ("net: hns3: add support for tc mqprio offload")
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_dcb.c         | 19 ++++++++++++-------
+ 1 file changed, 12 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+index 188daf75be32..d748c6404436 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+@@ -525,13 +525,18 @@ static int hclge_setup_tc(struct hnae3_handle *h,
+ 	return hclge_notify_init_up(hdev);
+ 
+ err_out:
+-	/* roll-back */
+-	memcpy(&kinfo->tc_info, &old_tc_info, sizeof(old_tc_info));
+-	if (hclge_config_tc(hdev, &kinfo->tc_info))
+-		dev_err(&hdev->pdev->dev,
+-			"failed to roll back tc configuration\n");
+-
+-	(void)hclge_notify_init_up(hdev);
++	if (!tc) {
++		dev_warn(&hdev->pdev->dev,
++			 "failed to destroy mqprio, will active after reset, ret = %d\n",
++			 ret);
++	} else {
++		/* roll-back */
++		memcpy(&kinfo->tc_info, &old_tc_info, sizeof(old_tc_info));
++		if (hclge_config_tc(hdev, &kinfo->tc_info))
++			dev_err(&hdev->pdev->dev,
++				"failed to roll back tc configuration\n");
++	}
++	hclge_notify_init_up(hdev);
+ 
+ 	return ret;
+ }
+-- 
+2.34.1
+
diff --git a/patches/0500-net-hns3-PF-enable-promisc-for-VF-when-mac-table-is-.patch b/patches/0500-net-hns3-PF-enable-promisc-for-VF-when-mac-table-is-.patch
new file mode 100644
index 0000000..f1d397c
--- /dev/null
+++ b/patches/0500-net-hns3-PF-enable-promisc-for-VF-when-mac-table-is-.patch
@@ -0,0 +1,58 @@
+From df14cd82752d4472c5ee577425cec047578b92fa Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:33 +0800
+Subject: [PATCH 139/283] net: hns3: PF enable promisc for VF when mac table is
+ overflow
+
+mainline inclusion
+from mainline-v5.15-rc4
+commit 276e60421668d019dc655973b1832ea354c0f36c
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=276e60421668d019dc655973b1832ea354c0f36c
+
+----------------------------------------------------------------------
+
+If unicast mac address table is full, and user add a new mac address, the
+unicast promisc needs to be enabled for the new unicast mac address can be
+used. So does the multicast promisc.
+
+Now this feature has been implemented for PF, and VF should be implemented
+too. When the mac table of VF is overflow, PF will enable promisc for this
+VF.
+
+Fixes: 1e6e76101fd9 ("net: hns3: configure promisc mode for VF asynchronously")
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 8c3cd8e52c7f..e9d9c44d6cc3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -11955,8 +11955,12 @@ static void hclge_sync_promisc_mode(struct hclge_dev *hdev)
+ 			continue;
+ 
+ 		if (vport->vf_info.trusted) {
+-			uc_en = vport->vf_info.request_uc_en > 0;
+-			mc_en = vport->vf_info.request_mc_en > 0;
++			uc_en = vport->vf_info.request_uc_en > 0 ||
++				vport->overflow_promisc_flags &
++				HNAE3_OVERFLOW_UPE;
++			mc_en = vport->vf_info.request_mc_en > 0 ||
++				vport->overflow_promisc_flags &
++				HNAE3_OVERFLOW_MPE;
+ 		}
+ 		bc_en = vport->vf_info.request_bc_en > 0;
+ 
+-- 
+2.34.1
+
diff --git a/patches/0501-net-hns3-fix-for-miscalculation-of-rx-unused-desc.patch b/patches/0501-net-hns3-fix-for-miscalculation-of-rx-unused-desc.patch
new file mode 100644
index 0000000..af24ce6
--- /dev/null
+++ b/patches/0501-net-hns3-fix-for-miscalculation-of-rx-unused-desc.patch
@@ -0,0 +1,111 @@
+From d2324558512bc6ce618c81544a0c27b69ce2979f Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:38 +0800
+Subject: [PATCH 140/283] net: hns3: fix for miscalculation of rx unused desc
+
+mainline inclusion
+from mainline-v5.15-rc7
+commit 9f9f0f19994b42b3e5e8735d41b9c5136828a76c
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9f9f0f19994b42b3e5e8735d41b9c5136828a76c
+
+----------------------------------------------------------------------
+
+rx unused desc is the desc that need attatching new buffer
+before refilling to hw to receive new packet, the number of
+desc need attatching new buffer is calculated using next_to_use
+and next_to_clean. when next_to_use == next_to_clean, currently
+hns3 driver assumes that all the desc has the buffer attatched,
+but 'next_to_use == next_to_clean' also means all the desc need
+attatching new buffer if hw has comsumed all the desc and the
+driver has not attatched any buffer to the desc yet.
+
+This patch adds 'refill' in desc_cb to indicate whether a new
+buffer has been refilled to a desc.
+
+Fixes: 76ad4f0ee747 ("net: hns3: Add support of HNS3 Ethernet Driver for hip08 SoC")
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 9 ++++++++-
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 1 +
+ 2 files changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index b0699bffb22a..9acb48ff8c6f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -2931,6 +2931,7 @@ static void hns3_buffer_detach(struct hns3_enet_ring *ring, int i)
+ {
+ 	hns3_unmap_buffer(ring, &ring->desc_cb[i]);
+ 	ring->desc[i].addr = 0;
++	ring->desc_cb[i].refill = 0;
+ }
+ 
+ static void hns3_free_buffer_detach(struct hns3_enet_ring *ring, int i,
+@@ -3008,7 +3009,7 @@ static int hns3_alloc_and_attach_buffer(struct hns3_enet_ring *ring, int i)
+ 		return ret;
+ 
+ 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
+-
++	ring->desc_cb[i].refill = 1;
+ 	return 0;
+ }
+ 
+@@ -3037,6 +3038,7 @@ static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
+ {
+ 	hns3_unmap_buffer(ring, &ring->desc_cb[i]);
+ 	ring->desc_cb[i] = *res_cb;
++	ring->desc_cb[i].refill = 1;
+ 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma);
+ 	ring->desc[i].rx.bd_base_info = 0;
+ }
+@@ -3044,6 +3046,7 @@ static void hns3_replace_buffer(struct hns3_enet_ring *ring, int i,
+ static void hns3_reuse_buffer(struct hns3_enet_ring *ring, int i)
+ {
+ 	ring->desc_cb[i].reuse_flag = 0;
++	ring->desc_cb[i].refill = 1;
+ 	ring->desc[i].addr = cpu_to_le64(ring->desc_cb[i].dma +
+ 					 ring->desc_cb[i].page_offset);
+ 	ring->desc[i].rx.bd_base_info = 0;
+@@ -3149,6 +3152,9 @@ static int hns3_desc_unused(struct hns3_enet_ring *ring)
+ 	int ntc = ring->next_to_clean;
+ 	int ntu = ring->next_to_use;
+ 
++	if (unlikely(ntc == ntu && !ring->desc_cb[ntc].refill))
++		return ring->desc_num;
++
+ 	return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
+ }
+ 
+@@ -3464,6 +3470,7 @@ static void hns3_rx_ring_move_fw(struct hns3_enet_ring *ring)
+ {
+ 	ring->desc[ring->next_to_clean].rx.bd_base_info &=
+ 		cpu_to_le32(~BIT(HNS3_RXD_VLD_B));
++	ring->desc_cb[ring->next_to_clean].refill = 0;
+ 	ring->next_to_clean += 1;
+ 
+ 	if (unlikely(ring->next_to_clean == ring->desc_num))
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index b082f0fa7064..433422fda7b8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -321,6 +321,7 @@ struct hns3_desc_cb {
+ 	u32 length;     /* length of the buffer */
+ 
+ 	u16 reuse_flag;
++	u16 refill;
+ 
+ 	/* desc type, used by the ring user to mark the type of the priv data */
+ 	u16 type;
+-- 
+2.34.1
+
diff --git a/patches/0502-net-hns3-schedule-the-polling-again-when-allocation-.patch b/patches/0502-net-hns3-schedule-the-polling-again-when-allocation-.patch
new file mode 100644
index 0000000..e32ec03
--- /dev/null
+++ b/patches/0502-net-hns3-schedule-the-polling-again-when-allocation-.patch
@@ -0,0 +1,115 @@
+From 5dd2f85c9e5862d0165495d716b78a00ebb533dd Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:39 +0800
+Subject: [PATCH 141/283] net: hns3: schedule the polling again when allocation
+ fails
+
+mainline inclusion
+from mainline-v5.15-rc7
+commit 68752b24f51a71d4f350a764d890b670f59062c5
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=68752b24f51a71d4f350a764d890b670f59062c5
+
+----------------------------------------------------------------------
+
+Currently when there is a rx page allocation failure, it is
+possible that polling may be stopped if there is no more packet
+to be reveiced, which may cause queue stall problem under memory
+pressure.
+
+This patch makes sure polling is scheduled again when there is
+any rx page allocation failure, and polling will try to allocate
+receive buffers until it succeeds.
+
+Now the allocation retry is added, it is unnecessary to do the rx
+page allocation at the end of rx cleaning, so remove it. And reset
+the unused_count to zero after calling hns3_nic_alloc_rx_buffers()
+to avoid calling hns3_nic_alloc_rx_buffers() repeatedly under
+memory pressure.
+
+Fixes: 76ad4f0ee747 ("net: hns3: Add support of HNS3 Ethernet Driver for hip08 SoC")
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 22 ++++++++++---------
+ 1 file changed, 12 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 9acb48ff8c6f..69170427c55d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -3158,7 +3158,8 @@ static int hns3_desc_unused(struct hns3_enet_ring *ring)
+ 	return ((ntc >= ntu) ? 0 : ring->desc_num) + ntc - ntu;
+ }
+ 
+-static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
++/* Return true if there is any allocation failure */
++static bool hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
+ 				      int cleand_count)
+ {
+ 	struct hns3_desc_cb *desc_cb;
+@@ -3183,7 +3184,10 @@ static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
+ 				hns3_rl_err(ring_to_netdev(ring),
+ 					    "alloc rx buffer failed: %d\n",
+ 					    ret);
+-				break;
++
++				writel(i, ring->tqp->io_base +
++				       HNS3_RING_RX_RING_HEAD_REG);
++				return true;
+ 			}
+ 			hns3_replace_buffer(ring, ring->next_to_use, &res_cbs);
+ 
+@@ -3196,6 +3200,7 @@ static void hns3_nic_alloc_rx_buffers(struct hns3_enet_ring *ring,
+ 	}
+ 
+ 	writel(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
++	return false;
+ }
+ 
+ static bool hns3_page_is_reusable(struct page *page)
+@@ -3807,6 +3812,7 @@ int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
+ {
+ #define RCB_NOF_ALLOC_RX_BUFF_ONCE 16
+ 	int unused_count = hns3_desc_unused(ring);
++	bool failure = false;
+ 	int recv_pkts = 0;
+ 	int err;
+ 
+@@ -3815,9 +3821,9 @@ int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
+ 	while (recv_pkts < budget) {
+ 		/* Reuse or realloc buffers */
+ 		if (unused_count >= RCB_NOF_ALLOC_RX_BUFF_ONCE) {
+-			hns3_nic_alloc_rx_buffers(ring, unused_count);
+-			unused_count = hns3_desc_unused(ring) -
+-					ring->pending_buf;
++			failure = failure ||
++				hns3_nic_alloc_rx_buffers(ring, unused_count);
++			unused_count = 0;
+ 		}
+ 
+ 		/* Poll one pkt */
+@@ -3836,11 +3842,7 @@ int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
+ 	}
+ 
+ out:
+-	/* Make all data has been write before submit */
+-	if (unused_count > 0)
+-		hns3_nic_alloc_rx_buffers(ring, unused_count);
+-
+-	return recv_pkts;
++	return failure ? budget : recv_pkts;
+ }
+ 
+ static bool hns3_get_new_flow_lvl(struct hns3_enet_ring_group *ring_group)
+-- 
+2.34.1
+
diff --git a/patches/0503-net-hns3-modify-mac-statistics-update-process-for-co.patch b/patches/0503-net-hns3-modify-mac-statistics-update-process-for-co.patch
new file mode 100644
index 0000000..213a152
--- /dev/null
+++ b/patches/0503-net-hns3-modify-mac-statistics-update-process-for-co.patch
@@ -0,0 +1,238 @@
+From ac3596b0c6bfcce427e9e5fd92aaa318458caac5 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:41 +0800
+Subject: [PATCH 142/283] net: hns3: modify mac statistics update process for
+ compatibility
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit 0bd7e894dffaa1fdbef9dcf68b5994a18ff32024
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0bd7e894dffa
+
+----------------------------------------------------------------------
+
+After querying mac statistics from firmware, driver copies data from
+descriptors to struct mac_stats of hdev, and the number of copied data
+is just according to the register number queried from firmware. There is
+a problem that if the register number queried from firmware is larger
+than data number of struct mac_stats, it will cause a copy overflow.
+
+So if the firmware adds more mac statistics in later version, it is not
+compatible with driver of old version.
+
+To fix this problem, the number of copied data needs to be used the
+minimum value between the register number queried from firmware and
+data number of struct mac_stats.
+
+The first descriptor has three data and there is one reserved, to
+optimize the copy process, add this reserverd data to struct mac_stats.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 92 +++++++++----------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  5 +-
+ 2 files changed, 47 insertions(+), 50 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index e9d9c44d6cc3..60ec024314ae 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -420,8 +420,9 @@ static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
+ 	u64 *data = (u64 *)(&hdev->mac_stats);
+ 	struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
+ 	__le64 *desc_data;
+-	int i, k, n;
++	u32 data_size;
+ 	int ret;
++	u32 i;
+ 
+ 	memset(desc, 0, sizeof(desc));
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
+@@ -433,33 +434,36 @@ static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
+ 		return ret;
+ 	}
+ 
+-	for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
+-		/* for special opcode 0032, only the first desc has the head */
+-		if (unlikely(i == 0)) {
+-			desc_data = (__le64 *)(&desc[i].data[0]);
+-			n = HCLGE_RD_FIRST_STATS_NUM;
+-		} else {
+-			desc_data = (__le64 *)(&desc[i]);
+-			n = HCLGE_RD_OTHER_STATS_NUM;
+-		}
++	/* The first desc has a 64-bit header, so data size need to minus 1 */
++	data_size = sizeof(desc) / (sizeof(u64)) - 1;
+ 
+-		for (k = 0; k < n; k++) {
+-			*data += le64_to_cpu(*desc_data);
+-			data++;
+-			desc_data++;
+-		}
++	desc_data = (__le64 *)(&desc[0].data[0]);
++	for (i = 0; i < data_size; i++) {
++		/* data memory is continuous becase only the first desc has a
++		 * header in this command
++		 */
++		*data += le64_to_cpu(*desc_data);
++		data++;
++		desc_data++;
+ 	}
+ 
+ 	return 0;
+ }
+ 
+-static int hclge_mac_update_stats_complete(struct hclge_dev *hdev, u32 desc_num)
++static int hclge_mac_update_stats_complete(struct hclge_dev *hdev, u32 reg_num)
+ {
++#define HCLGE_REG_NUM_PER_DESC		4
++
+ 	u64 *data = (u64 *)(&hdev->mac_stats);
+ 	struct hclge_desc *desc;
+ 	__le64 *desc_data;
+-	u16 i, k, n;
++	u32 data_size;
++	u32 desc_num;
+ 	int ret;
++	u32 i;
++
++	/* The first desc has a 64-bit header, so need to consider it */
++	desc_num = reg_num / HCLGE_REG_NUM_PER_DESC + 1;
+ 
+ 	/* This may be called inside atomic sections,
+ 	 * so GFP_ATOMIC is more suitalbe here
+@@ -475,21 +479,16 @@ static int hclge_mac_update_stats_complete(struct hclge_dev *hdev, u32 desc_num)
+ 		return ret;
+ 	}
+ 
+-	for (i = 0; i < desc_num; i++) {
+-		/* for special opcode 0034, only the first desc has the head */
+-		if (i == 0) {
+-			desc_data = (__le64 *)(&desc[i].data[0]);
+-			n = HCLGE_RD_FIRST_STATS_NUM;
+-		} else {
+-			desc_data = (__le64 *)(&desc[i]);
+-			n = HCLGE_RD_OTHER_STATS_NUM;
+-		}
++	data_size = min_t(u32, sizeof(hdev->mac_stats) / sizeof(u64), reg_num);
+ 
+-		for (k = 0; k < n; k++) {
+-			*data += le64_to_cpu(*desc_data);
+-			data++;
+-			desc_data++;
+-		}
++	desc_data = (__le64 *)(&desc[0].data[0]);
++	for (i = 0; i < data_size; i++) {
++		/* data memory is continuous becase only the first desc has a
++		 * header in this command
++		 */
++		*data += le64_to_cpu(*desc_data);
++		data++;
++		desc_data++;
+ 	}
+ 
+ 	kfree(desc);
+@@ -497,26 +496,25 @@ static int hclge_mac_update_stats_complete(struct hclge_dev *hdev, u32 desc_num)
+ 	return 0;
+ }
+ 
+-static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *desc_num)
++static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)
+ {
+ 	struct hclge_desc desc;
+-	__le32 *desc_data;
+-	u32 reg_num;
+ 	int ret;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+-	if (ret)
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to query mac statistic reg number, ret = %d\n",
++			ret);
+ 		return ret;
++	}
+ 
+-	desc_data = (__le32 *)(&desc.data[0]);
+-	reg_num = le32_to_cpu(*desc_data);
+-
+-	*desc_num = 1 + ((reg_num - 3) >> 2) +
+-		    (u32)(((reg_num - 3) & 0x3) ? 1 : 0);
+-	if (!(*desc_num)) {
+-		dev_err(&hdev->pdev->dev, "Invalid desc num: %u\n", *desc_num);
+-		return -EINVAL;
++	*reg_num = le32_to_cpu(desc.data[0]);
++	if (*reg_num == 0) {
++		dev_err(&hdev->pdev->dev,
++			"mac statistic reg number is invalid!\n");
++		return -ENODATA;
+ 	}
+ 
+ 	return 0;
+@@ -524,17 +522,15 @@ static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *desc_num)
+ 
+ int hclge_mac_update_stats(struct hclge_dev *hdev)
+ {
+-	u32 desc_num;
++	u32 reg_num;
+ 	int ret;
+ 
+-	ret = hclge_mac_query_reg_num(hdev, &desc_num);
++	ret = hclge_mac_query_reg_num(hdev, &reg_num);
+ 	/* The firmware supports the new statistics acquisition method */
+ 	if (!ret)
+-		ret = hclge_mac_update_stats_complete(hdev, desc_num);
++		ret = hclge_mac_update_stats_complete(hdev, reg_num);
+ 	else if (ret == -EOPNOTSUPP)
+ 		ret = hclge_mac_update_stats_defective(hdev);
+-	else
+-		dev_err(&hdev->pdev->dev, "query mac reg num fail!\n");
+ 
+ 	return ret;
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 0bf287e403b3..8e01aada3962 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -411,6 +411,7 @@ struct hclge_comm_stats_str {
+ struct hclge_mac_stats {
+ 	u64 mac_tx_mac_pause_num;
+ 	u64 mac_rx_mac_pause_num;
++	u64 rsv0;
+ 	u64 mac_tx_pfc_pri0_pkt_num;
+ 	u64 mac_tx_pfc_pri1_pkt_num;
+ 	u64 mac_tx_pfc_pri2_pkt_num;
+@@ -447,7 +448,7 @@ struct hclge_mac_stats {
+ 	u64 mac_tx_1519_2047_oct_pkt_num;
+ 	u64 mac_tx_2048_4095_oct_pkt_num;
+ 	u64 mac_tx_4096_8191_oct_pkt_num;
+-	u64 rsv0;
++	u64 rsv1;
+ 	u64 mac_tx_8192_9216_oct_pkt_num;
+ 	u64 mac_tx_9217_12287_oct_pkt_num;
+ 	u64 mac_tx_12288_16383_oct_pkt_num;
+@@ -474,7 +475,7 @@ struct hclge_mac_stats {
+ 	u64 mac_rx_1519_2047_oct_pkt_num;
+ 	u64 mac_rx_2048_4095_oct_pkt_num;
+ 	u64 mac_rx_4096_8191_oct_pkt_num;
+-	u64 rsv1;
++	u64 rsv2;
+ 	u64 mac_rx_8192_9216_oct_pkt_num;
+ 	u64 mac_rx_9217_12287_oct_pkt_num;
+ 	u64 mac_rx_12288_16383_oct_pkt_num;
+-- 
+2.34.1
+
diff --git a/patches/0504-net-hns3-device-specifications-add-number-of-mac-sta.patch b/patches/0504-net-hns3-device-specifications-add-number-of-mac-sta.patch
new file mode 100644
index 0000000..f838e2d
--- /dev/null
+++ b/patches/0504-net-hns3-device-specifications-add-number-of-mac-sta.patch
@@ -0,0 +1,138 @@
+From ebfa5b4485a5df87d420848a84cc8ac0fd047439 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:42 +0800
+Subject: [PATCH 143/283] net: hns3: device specifications add number of mac
+ statistics
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit 4e4c03f6ab636e9c39558845da5bfbcd60baf33d
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=4e4c03f6ab636e9c39558845da5bfbcd60baf33d
+
+----------------------------------------------------------------------
+
+Currently, driver queries number of mac statistics before querying mac
+statistics. As the number of mac statistics is a fixed value in firmware,
+it is redundant to query this number everytime before querying mac
+statistics, it can just be queried once in initialization process and
+saved in device specifications.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  3 ++
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    |  2 ++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 34 +++++++++++++------
+ 3 files changed, 28 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 46e9e3879826..744c0d4db199 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -349,6 +349,9 @@ struct hnae3_dev_specs {
+ 	u16 max_int_gl; /* max value of interrupt coalesce based on INT_GL */
+ 	u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */
+ 	u16 max_qset_num;
++	u16 umv_size;
++	u16 mc_mac_size;
++	u32 mac_stats_num;
+ };
+ 
+ struct hnae3_client_ops {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 3ec72f8b2d87..b13cd5ea7bd7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -780,6 +780,8 @@ hns3_dbg_dev_specs(struct hnae3_handle *h, char *buf, int len, int *pos)
+ 			  dev_specs->max_tm_rate);
+ 	*pos += scnprintf(buf + *pos, len - *pos, "MAX QSET number: %u\n",
+ 			  dev_specs->max_qset_num);
++	*pos += scnprintf(buf + *pos, len - *pos, "MAC statistics number: %u\n",
++			  dev_specs->mac_stats_num);
+ }
+ 
+ static int hns3_dbg_dev_info(struct hnae3_handle *h, char *buf, int len)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 60ec024314ae..0c5f3f005757 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -450,10 +450,11 @@ static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
+ 	return 0;
+ }
+ 
+-static int hclge_mac_update_stats_complete(struct hclge_dev *hdev, u32 reg_num)
++static int hclge_mac_update_stats_complete(struct hclge_dev *hdev)
+ {
+ #define HCLGE_REG_NUM_PER_DESC		4
+ 
++	u32 reg_num = hdev->ae_dev->dev_specs.mac_stats_num;
+ 	u64 *data = (u64 *)(&hdev->mac_stats);
+ 	struct hclge_desc *desc;
+ 	__le64 *desc_data;
+@@ -522,17 +523,11 @@ static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)
+ 
+ int hclge_mac_update_stats(struct hclge_dev *hdev)
+ {
+-	u32 reg_num;
+-	int ret;
+-
+-	ret = hclge_mac_query_reg_num(hdev, &reg_num);
+ 	/* The firmware supports the new statistics acquisition method */
+-	if (!ret)
+-		ret = hclge_mac_update_stats_complete(hdev, reg_num);
+-	else if (ret == -EOPNOTSUPP)
+-		ret = hclge_mac_update_stats_defective(hdev);
+-
+-	return ret;
++	if (hdev->ae_dev->dev_specs.mac_stats_num)
++		return hclge_mac_update_stats_complete(hdev);
++	else
++		return hclge_mac_update_stats_defective(hdev);
+ }
+ 
+ static int hclge_tqps_update_stats(struct hnae3_handle *handle)
+@@ -1421,12 +1416,29 @@ static void hclge_parse_dev_specs(struct hclge_dev *hdev,
+ 	ae_dev->dev_specs.max_int_gl = le16_to_cpu(req1->max_int_gl);
+ }
+ 
++static int hclge_query_mac_stats_num(struct hclge_dev *hdev)
++{
++	u32 reg_num = 0;
++	int ret;
++
++	ret = hclge_mac_query_reg_num(hdev, &reg_num);
++	if (ret && ret != -EOPNOTSUPP)
++		return ret;
++
++	hdev->ae_dev->dev_specs.mac_stats_num = reg_num;
++	return 0;
++}
++
+ static int hclge_query_dev_specs(struct hclge_dev *hdev)
+ {
+ 	struct hclge_desc desc[HCLGE_QUERY_DEV_SPECS_BD_NUM];
+ 	int ret;
+ 	int i;
+ 
++	ret = hclge_query_mac_stats_num(hdev);
++	if (ret)
++		return ret;
++
+ 	/* set default specifications as devices lower than version V3 do not
+ 	 * support querying specifications from firmware.
+ 	 */
+-- 
+2.34.1
+
diff --git a/patches/0505-net-hns3-add-support-pause-pfc-durations-for-mac-sta.patch b/patches/0505-net-hns3-add-support-pause-pfc-durations-for-mac-sta.patch
new file mode 100644
index 0000000..31398d8
--- /dev/null
+++ b/patches/0505-net-hns3-add-support-pause-pfc-durations-for-mac-sta.patch
@@ -0,0 +1,514 @@
+From c15e653ee36f1844878ace852947d2b75121f1d2 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:43 +0800
+Subject: [PATCH 144/283] net: hns3: add support pause/pfc durations for mac
+ statistics
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit c8af2887c941fbe15637e7d9b0d75fa100cb7827
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c8af2887c941fbe15637e7d9b0d75fa100cb7827
+
+----------------------------------------------------------------------
+
+The mac statistics add pause/pfc durations in device version V3, we can
+get total active cycle of pause/pfc from these durations.
+
+As driver gets register number from firmware to calculate desc number to
+query mac statistics, it needs to set mac statistics extended enable bit
+in firmware command 0x701A to tell firmware that driver supports extended
+mac statistics, otherwise firmware only returns register number of
+version V1.
+
+As pause/pfc durations are not supported by hardware of old version, they
+should not been shown in command "ethtool -S ethX" in this case, so add
+checking max register number of each mac statistic in their version.
+If the max register number of one mac statistic is greater than register
+number got from firmware, it means hardware does not support this mac
+statistic, so ignore this statistic when get string and data of mac
+statistic.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         |   2 -
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |   1 +
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 245 +++++++++++-------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  27 ++
+ 4 files changed, 181 insertions(+), 94 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 64a6031c64fe..6e28dd4524b8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -487,8 +487,6 @@ static int hclge_firmware_compat_config(struct hclge_dev *hdev, bool en)
+ 
+ 		hnae3_set_bit(compat, HCLGE_LINK_EVENT_REPORT_EN_B, 1);
+ 		hnae3_set_bit(compat, HCLGE_NCSI_ERROR_REPORT_EN_B, 1);
+-		if (hnae3_dev_phy_imp_supported(hdev))
+-			hnae3_set_bit(compat, HCLGE_PHY_IMP_EN_B, 1);
+ 		req->compat = cpu_to_le32(compat);
+ 	}
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 770a572003f3..e96c58eeb9b4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -1148,6 +1148,7 @@ struct hclge_query_ppu_pf_other_int_dfx_cmd {
+ #define HCLGE_LINK_EVENT_REPORT_EN_B	0
+ #define HCLGE_NCSI_ERROR_REPORT_EN_B	1
+ #define HCLGE_PHY_IMP_EN_B		2
++#define HCLGE_MAC_STATS_EXT_EN_B	3
+ struct hclge_firmware_compat_cmd {
+ 	__le32 compat;
+ 	u8 rsv[20];
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 0c5f3f005757..f774ba3f05c0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -151,174 +151,210 @@ static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
+ };
+ 
+ static const struct hclge_comm_stats_str g_mac_stats_string[] = {
+-	{"mac_tx_mac_pause_num",
++	{"mac_tx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
+-	{"mac_rx_mac_pause_num",
++	{"mac_rx_mac_pause_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
+-	{"mac_tx_control_pkt_num",
++	{"mac_tx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pause_xoff_time)},
++	{"mac_rx_pause_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pause_xoff_time)},
++	{"mac_tx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_ctrl_pkt_num)},
+-	{"mac_rx_control_pkt_num",
++	{"mac_rx_control_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_ctrl_pkt_num)},
+-	{"mac_tx_pfc_pkt_num",
++	{"mac_tx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pause_pkt_num)},
+-	{"mac_tx_pfc_pri0_pkt_num",
++	{"mac_tx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
+-	{"mac_tx_pfc_pri1_pkt_num",
++	{"mac_tx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
+-	{"mac_tx_pfc_pri2_pkt_num",
++	{"mac_tx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
+-	{"mac_tx_pfc_pri3_pkt_num",
++	{"mac_tx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
+-	{"mac_tx_pfc_pri4_pkt_num",
++	{"mac_tx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
+-	{"mac_tx_pfc_pri5_pkt_num",
++	{"mac_tx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
+-	{"mac_tx_pfc_pri6_pkt_num",
++	{"mac_tx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
+-	{"mac_tx_pfc_pri7_pkt_num",
++	{"mac_tx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
+-	{"mac_rx_pfc_pkt_num",
++	{"mac_tx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_xoff_time)},
++	{"mac_tx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_xoff_time)},
++	{"mac_tx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_xoff_time)},
++	{"mac_tx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_xoff_time)},
++	{"mac_tx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_xoff_time)},
++	{"mac_tx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_xoff_time)},
++	{"mac_tx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_xoff_time)},
++	{"mac_tx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_xoff_time)},
++	{"mac_rx_pfc_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pause_pkt_num)},
+-	{"mac_rx_pfc_pri0_pkt_num",
++	{"mac_rx_pfc_pri0_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
+-	{"mac_rx_pfc_pri1_pkt_num",
++	{"mac_rx_pfc_pri1_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
+-	{"mac_rx_pfc_pri2_pkt_num",
++	{"mac_rx_pfc_pri2_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
+-	{"mac_rx_pfc_pri3_pkt_num",
++	{"mac_rx_pfc_pri3_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
+-	{"mac_rx_pfc_pri4_pkt_num",
++	{"mac_rx_pfc_pri4_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
+-	{"mac_rx_pfc_pri5_pkt_num",
++	{"mac_rx_pfc_pri5_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
+-	{"mac_rx_pfc_pri6_pkt_num",
++	{"mac_rx_pfc_pri6_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
+-	{"mac_rx_pfc_pri7_pkt_num",
++	{"mac_rx_pfc_pri7_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
+-	{"mac_tx_total_pkt_num",
++	{"mac_rx_pfc_pri0_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_xoff_time)},
++	{"mac_rx_pfc_pri1_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_xoff_time)},
++	{"mac_rx_pfc_pri2_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_xoff_time)},
++	{"mac_rx_pfc_pri3_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_xoff_time)},
++	{"mac_rx_pfc_pri4_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_xoff_time)},
++	{"mac_rx_pfc_pri5_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_xoff_time)},
++	{"mac_rx_pfc_pri6_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_xoff_time)},
++	{"mac_rx_pfc_pri7_xoff_time", HCLGE_MAC_STATS_MAX_NUM_V2,
++		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_xoff_time)},
++	{"mac_tx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
+-	{"mac_tx_total_oct_num",
++	{"mac_tx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
+-	{"mac_tx_good_pkt_num",
++	{"mac_tx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
+-	{"mac_tx_bad_pkt_num",
++	{"mac_tx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
+-	{"mac_tx_good_oct_num",
++	{"mac_tx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
+-	{"mac_tx_bad_oct_num",
++	{"mac_tx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
+-	{"mac_tx_uni_pkt_num",
++	{"mac_tx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
+-	{"mac_tx_multi_pkt_num",
++	{"mac_tx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
+-	{"mac_tx_broad_pkt_num",
++	{"mac_tx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
+-	{"mac_tx_undersize_pkt_num",
++	{"mac_tx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
+-	{"mac_tx_oversize_pkt_num",
++	{"mac_tx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
+-	{"mac_tx_64_oct_pkt_num",
++	{"mac_tx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
+-	{"mac_tx_65_127_oct_pkt_num",
++	{"mac_tx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
+-	{"mac_tx_128_255_oct_pkt_num",
++	{"mac_tx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
+-	{"mac_tx_256_511_oct_pkt_num",
++	{"mac_tx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
+-	{"mac_tx_512_1023_oct_pkt_num",
++	{"mac_tx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
+-	{"mac_tx_1024_1518_oct_pkt_num",
++	{"mac_tx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
+-	{"mac_tx_1519_2047_oct_pkt_num",
++	{"mac_tx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
+-	{"mac_tx_2048_4095_oct_pkt_num",
++	{"mac_tx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
+-	{"mac_tx_4096_8191_oct_pkt_num",
++	{"mac_tx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
+-	{"mac_tx_8192_9216_oct_pkt_num",
++	{"mac_tx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
+-	{"mac_tx_9217_12287_oct_pkt_num",
++	{"mac_tx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
+-	{"mac_tx_12288_16383_oct_pkt_num",
++	{"mac_tx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
+-	{"mac_tx_1519_max_good_pkt_num",
++	{"mac_tx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
+-	{"mac_tx_1519_max_bad_pkt_num",
++	{"mac_tx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
+-	{"mac_rx_total_pkt_num",
++	{"mac_rx_total_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
+-	{"mac_rx_total_oct_num",
++	{"mac_rx_total_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
+-	{"mac_rx_good_pkt_num",
++	{"mac_rx_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
+-	{"mac_rx_bad_pkt_num",
++	{"mac_rx_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
+-	{"mac_rx_good_oct_num",
++	{"mac_rx_good_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
+-	{"mac_rx_bad_oct_num",
++	{"mac_rx_bad_oct_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
+-	{"mac_rx_uni_pkt_num",
++	{"mac_rx_uni_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
+-	{"mac_rx_multi_pkt_num",
++	{"mac_rx_multi_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
+-	{"mac_rx_broad_pkt_num",
++	{"mac_rx_broad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
+-	{"mac_rx_undersize_pkt_num",
++	{"mac_rx_undersize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
+-	{"mac_rx_oversize_pkt_num",
++	{"mac_rx_oversize_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
+-	{"mac_rx_64_oct_pkt_num",
++	{"mac_rx_64_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
+-	{"mac_rx_65_127_oct_pkt_num",
++	{"mac_rx_65_127_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
+-	{"mac_rx_128_255_oct_pkt_num",
++	{"mac_rx_128_255_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
+-	{"mac_rx_256_511_oct_pkt_num",
++	{"mac_rx_256_511_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
+-	{"mac_rx_512_1023_oct_pkt_num",
++	{"mac_rx_512_1023_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
+-	{"mac_rx_1024_1518_oct_pkt_num",
++	{"mac_rx_1024_1518_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
+-	{"mac_rx_1519_2047_oct_pkt_num",
++	{"mac_rx_1519_2047_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
+-	{"mac_rx_2048_4095_oct_pkt_num",
++	{"mac_rx_2048_4095_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
+-	{"mac_rx_4096_8191_oct_pkt_num",
++	{"mac_rx_4096_8191_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
+-	{"mac_rx_8192_9216_oct_pkt_num",
++	{"mac_rx_8192_9216_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
+-	{"mac_rx_9217_12287_oct_pkt_num",
++	{"mac_rx_9217_12287_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
+-	{"mac_rx_12288_16383_oct_pkt_num",
++	{"mac_rx_12288_16383_oct_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
+-	{"mac_rx_1519_max_good_pkt_num",
++	{"mac_rx_1519_max_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
+-	{"mac_rx_1519_max_bad_pkt_num",
++	{"mac_rx_1519_max_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
+ 
+-	{"mac_tx_fragment_pkt_num",
++	{"mac_tx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
+-	{"mac_tx_undermin_pkt_num",
++	{"mac_tx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
+-	{"mac_tx_jabber_pkt_num",
++	{"mac_tx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
+-	{"mac_tx_err_all_pkt_num",
++	{"mac_tx_err_all_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
+-	{"mac_tx_from_app_good_pkt_num",
++	{"mac_tx_from_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
+-	{"mac_tx_from_app_bad_pkt_num",
++	{"mac_tx_from_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
+-	{"mac_rx_fragment_pkt_num",
++	{"mac_rx_fragment_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
+-	{"mac_rx_undermin_pkt_num",
++	{"mac_rx_undermin_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
+-	{"mac_rx_jabber_pkt_num",
++	{"mac_rx_jabber_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
+-	{"mac_rx_fcs_err_pkt_num",
++	{"mac_rx_fcs_err_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
+-	{"mac_rx_send_app_good_pkt_num",
++	{"mac_rx_send_app_good_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
+-	{"mac_rx_send_app_bad_pkt_num",
++	{"mac_rx_send_app_bad_pkt_num", HCLGE_MAC_STATS_MAX_NUM_V1,
+ 		HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
+ };
+ 
+@@ -635,20 +671,39 @@ static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
+ 	return buff;
+ }
+ 
+-static u64 *hclge_comm_get_stats(const void *comm_stats,
++static int hclge_comm_get_count(struct hclge_dev *hdev,
++				const struct hclge_comm_stats_str strs[],
++				u32 size)
++{
++	int count = 0;
++	u32 i;
++
++	for (i = 0; i < size; i++)
++		if (strs[i].stats_num <= hdev->ae_dev->dev_specs.mac_stats_num)
++			count++;
++
++	return count;
++}
++
++static u64 *hclge_comm_get_stats(struct hclge_dev *hdev,
+ 				 const struct hclge_comm_stats_str strs[],
+ 				 int size, u64 *data)
+ {
+ 	u64 *buf = data;
+ 	u32 i;
+ 
+-	for (i = 0; i < size; i++)
+-		buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
++	for (i = 0; i < size; i++) {
++		if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
++			continue;
++
++		*buf = HCLGE_STATS_READ(&hdev->mac_stats, strs[i].offset);
++		buf++;
++	}
+ 
+-	return buf + size;
++	return buf;
+ }
+ 
+-static u8 *hclge_comm_get_strings(u32 stringset,
++static u8 *hclge_comm_get_strings(struct hclge_dev *hdev, u32 stringset,
+ 				  const struct hclge_comm_stats_str strs[],
+ 				  int size, u8 *data)
+ {
+@@ -659,6 +714,9 @@ static u8 *hclge_comm_get_strings(u32 stringset,
+ 		return buff;
+ 
+ 	for (i = 0; i < size; i++) {
++		if (strs[i].stats_num > hdev->ae_dev->dev_specs.mac_stats_num)
++			continue;
++
+ 		snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc);
+ 		buff = buff + ETH_GSTRING_LEN;
+ 	}
+@@ -750,7 +808,8 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
+ 			handle->flags |= HNAE3_SUPPORT_PHY_LOOPBACK;
+ 		}
+ 	} else if (stringset == ETH_SS_STATS) {
+-		count = ARRAY_SIZE(g_mac_stats_string) +
++		count = hclge_comm_get_count(hdev, g_mac_stats_string,
++					     ARRAY_SIZE(g_mac_stats_string)) +
+ 			hclge_tqps_get_sset_count(handle, stringset);
+ 	}
+ 
+@@ -760,12 +819,14 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
+ static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset,
+ 			      u8 *data)
+ {
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_dev *hdev = vport->back;
+ 	u8 *p = (char *)data;
+ 	int size;
+ 
+ 	if (stringset == ETH_SS_STATS) {
+ 		size = ARRAY_SIZE(g_mac_stats_string);
+-		p = hclge_comm_get_strings(stringset, g_mac_stats_string,
++		p = hclge_comm_get_strings(hdev, stringset, g_mac_stats_string,
+ 					   size, p);
+ 		p = hclge_tqps_get_strings(handle, p);
+ 	} else if (stringset == ETH_SS_TEST) {
+@@ -799,7 +860,7 @@ static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
+ 	struct hclge_dev *hdev = vport->back;
+ 	u64 *p;
+ 
+-	p = hclge_comm_get_stats(&hdev->mac_stats, g_mac_stats_string,
++	p = hclge_comm_get_stats(hdev, g_mac_stats_string,
+ 				 ARRAY_SIZE(g_mac_stats_string), data);
+ 	p = hclge_tqps_get_stats(handle, p);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 8e01aada3962..ad786ae8ae4a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -402,8 +402,13 @@ struct hclge_tm_info {
+ 	u8 pfc_en;	/* PFC enabled or not for user priority */
+ };
+ 
++/* max number of mac statistics on each version */
++#define HCLGE_MAC_STATS_MAX_NUM_V1		84
++#define HCLGE_MAC_STATS_MAX_NUM_V2		105
++
+ struct hclge_comm_stats_str {
+ 	char desc[ETH_GSTRING_LEN];
++	u32 stats_num;
+ 	unsigned long offset;
+ };
+ 
+@@ -498,6 +503,28 @@ struct hclge_mac_stats {
+ 	u64 mac_rx_pfc_pause_pkt_num;
+ 	u64 mac_tx_ctrl_pkt_num;
+ 	u64 mac_rx_ctrl_pkt_num;
++
++	/* duration of pfc */
++	u64 mac_tx_pfc_pri0_xoff_time;
++	u64 mac_tx_pfc_pri1_xoff_time;
++	u64 mac_tx_pfc_pri2_xoff_time;
++	u64 mac_tx_pfc_pri3_xoff_time;
++	u64 mac_tx_pfc_pri4_xoff_time;
++	u64 mac_tx_pfc_pri5_xoff_time;
++	u64 mac_tx_pfc_pri6_xoff_time;
++	u64 mac_tx_pfc_pri7_xoff_time;
++	u64 mac_rx_pfc_pri0_xoff_time;
++	u64 mac_rx_pfc_pri1_xoff_time;
++	u64 mac_rx_pfc_pri2_xoff_time;
++	u64 mac_rx_pfc_pri3_xoff_time;
++	u64 mac_rx_pfc_pri4_xoff_time;
++	u64 mac_rx_pfc_pri5_xoff_time;
++	u64 mac_rx_pfc_pri6_xoff_time;
++	u64 mac_rx_pfc_pri7_xoff_time;
++
++	/* duration of pause */
++	u64 mac_tx_pause_xoff_time;
++	u64 mac_rx_pause_xoff_time;
+ };
+ 
+ #define HCLGE_STATS_TIMER_INTERVAL	300UL
+-- 
+2.34.1
+
diff --git a/patches/0506-net-hns3-modify-functions-of-converting-speed-abilit.patch b/patches/0506-net-hns3-modify-functions-of-converting-speed-abilit.patch
new file mode 100644
index 0000000..215ca30
--- /dev/null
+++ b/patches/0506-net-hns3-modify-functions-of-converting-speed-abilit.patch
@@ -0,0 +1,230 @@
+From c50d2600a4852ea1583b58a7868ee5a3bdeef168 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:44 +0800
+Subject: [PATCH 145/283] net: hns3: modify functions of converting speed
+ ability to ethtool link mode
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit 58cb422ef625750fe8719045d1b8557e15875a9e
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=58cb422ef625750fe8719045d1b8557e15875a9e
+
+----------------------------------------------------------------------
+
+The functions of converting speed ability to ethtool link mode just
+support setting mac->supported currently, to reuse these functions to
+set ethtool link mode for others(i.e. advertising), delete the argument
+mac and add argument link_mode.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  3 +
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 77 ++++++++++---------
+ 2 files changed, 45 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 744c0d4db199..9eb545677c05 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -149,6 +149,9 @@ enum HNAE3_DEV_CAP_BITS {
+ #define hnae3_dev_stash_supported(hdev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps)
+ 
++#define hnae3_dev_pause_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_PAUSE_B, (hdev)->ae_dev->caps)
++
+ #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps)
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index f774ba3f05c0..85087927a7f3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1073,94 +1073,100 @@ static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed)
+ 	return -EINVAL;
+ }
+ 
+-#ifdef HAVE_ETHTOOL_CONVERT_U32_AND_LINK_MODE
+-static void hclge_convert_setting_sr(struct hclge_mac *mac, u16 speed_ability)
++static void hclge_convert_setting_sr(u16 speed_ability,
++				     unsigned long *link_mode)
+ {
+ 	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_25G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_40G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_50G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ }
+ 
+-static void hclge_convert_setting_lr(struct hclge_mac *mac, u16 speed_ability)
++static void hclge_convert_setting_lr(u16 speed_ability,
++				     unsigned long *link_mode)
+ {
+ 	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_25G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
+-				 mac->supported);
++				 link_mode);
++	if (speed_ability & HCLGE_SUPPORT_50G_BIT)
++		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_40G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
+ 		linkmode_set_bit(
+ 			ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
+-			mac->supported);
++			link_mode);
+ }
+ 
+-static void hclge_convert_setting_cr(struct hclge_mac *mac, u16 speed_ability)
++static void hclge_convert_setting_cr(u16 speed_ability,
++				     unsigned long *link_mode)
+ {
+ 	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_25G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_40G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_50G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ }
+ 
+-static void hclge_convert_setting_kr(struct hclge_mac *mac, u16 speed_ability)
++static void hclge_convert_setting_kr(u16 speed_ability,
++				     unsigned long *link_mode)
+ {
+ 	if (speed_ability & HCLGE_SUPPORT_1G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_10G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_25G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_40G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_50G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_100G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ 	if (speed_ability & HCLGE_SUPPORT_200G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
+-				 mac->supported);
++				 link_mode);
+ }
+ 
+ static void hclge_convert_setting_fec(struct hclge_mac *mac)
+@@ -1196,7 +1202,6 @@ static void hclge_convert_setting_fec(struct hclge_mac *mac)
+ 		break;
+ 	}
+ }
+-#endif
+ 
+ static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
+ 					u16 speed_ability)
+@@ -1208,10 +1213,10 @@ static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ 				 mac->supported);
+ 
+-	hclge_convert_setting_sr(mac, speed_ability);
+-	hclge_convert_setting_lr(mac, speed_ability);
+-	hclge_convert_setting_cr(mac, speed_ability);
+-	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
++	hclge_convert_setting_sr(speed_ability, mac->supported);
++	hclge_convert_setting_lr(speed_ability, mac->supported);
++	hclge_convert_setting_cr(speed_ability, mac->supported);
++	if (hnae3_dev_fec_supported(hdev))
+ 		hclge_convert_setting_fec(mac);
+ 
+ 	linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, mac->supported);
+@@ -1239,9 +1244,10 @@ static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev,
+ 	struct hclge_mac *mac = &hdev->hw.mac;
+ 
+ #ifdef HAVE_ETHTOOL_CONVERT_U32_AND_LINK_MODE
+-	hclge_convert_setting_kr(mac, speed_ability);
++	hclge_convert_setting_kr(speed_ability, mac->supported);
+ 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+ 		hclge_convert_setting_fec(mac);
++
+ #else
+ 	if (speed_ability & HCLGE_SUPPORT_1G_BIT)
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
+@@ -1250,6 +1256,7 @@ static void hclge_parse_backplane_link_mode(struct hclge_dev *hdev,
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
+ 				 mac->supported);
+ #endif
++
+ 	linkmode_set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, mac->supported);
+ 	linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->supported);
+ }
+-- 
+2.34.1
+
diff --git a/patches/0507-net-hns3-add-update-ethtool-advertised-link-modes-fo.patch b/patches/0507-net-hns3-add-update-ethtool-advertised-link-modes-fo.patch
new file mode 100644
index 0000000..b0db050
--- /dev/null
+++ b/patches/0507-net-hns3-add-update-ethtool-advertised-link-modes-fo.patch
@@ -0,0 +1,179 @@
+From e3c2384cd05be7f3e2b7f9eedd6803855dde8569 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:45 +0800
+Subject: [PATCH 146/283] net: hns3: add update ethtool advertised link modes
+ for FIBRE port when autoneg off
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit 6eaed433ee5f607f8b46ed9f15b3aa1112404704
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6eaed433ee5f607f8b46ed9f15b3aa1112404704
+
+----------------------------------------------------------------------
+
+Currently, the ethtool advertised link modes of FIBRE port is cleared to
+zero when autoneg is off, so user can not get the advertised link modes
+info directly from "ethtool <dev>" command.
+
+In order to ameliorate this situation, update data of speeds, fec and pause
+of advertised link modes when autoneg is off.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 92 +++++++++++++++++--
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  9 ++
+ 2 files changed, 94 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 85087927a7f3..2169c60aad03 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -2994,12 +2994,90 @@ static void hclge_update_link_status(struct hclge_dev *hdev)
+ 	clear_bit(HCLGE_STATE_LINK_UPDATING, &hdev->state);
+ }
+ 
+-static void hclge_update_port_capability(struct hclge_mac *mac)
++static void hclge_update_speed_advertising(struct hclge_mac *mac)
+ {
+-#ifdef HAVE_ETHTOOL_CONVERT_U32_AND_LINK_MODE
+-	/* update fec ability by speed */
+-	hclge_convert_setting_fec(mac);
+-#endif
++	u32 speed_ability;
++
++	if (hclge_get_speed_bit(mac->speed, &speed_ability))
++		return;
++
++	switch (mac->module_type) {
++	case HNAE3_MODULE_TYPE_FIBRE_LR:
++		hclge_convert_setting_lr(speed_ability, mac->advertising);
++		break;
++	case HNAE3_MODULE_TYPE_FIBRE_SR:
++	case HNAE3_MODULE_TYPE_AOC:
++		hclge_convert_setting_sr(speed_ability, mac->advertising);
++		break;
++	case HNAE3_MODULE_TYPE_CR:
++		hclge_convert_setting_cr(speed_ability, mac->advertising);
++		break;
++	case HNAE3_MODULE_TYPE_KR:
++		hclge_convert_setting_kr(speed_ability, mac->advertising);
++		break;
++	default:
++		break;
++	}
++}
++
++static void hclge_update_fec_advertising(struct hclge_mac *mac)
++{
++	if (mac->fec_mode & BIT(HNAE3_FEC_RS))
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
++				 mac->advertising);
++	else if (mac->fec_mode & BIT(HNAE3_FEC_BASER))
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
++				 mac->advertising);
++	else
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
++				 mac->advertising);
++}
++
++static void hclge_update_pause_advertising(struct hclge_dev *hdev)
++{
++	struct hclge_mac *mac = &hdev->hw.mac;
++	bool rx_en, tx_en;
++
++	switch (hdev->fc_mode_last_time) {
++	case HCLGE_FC_RX_PAUSE:
++		rx_en = true;
++		tx_en = false;
++		break;
++	case HCLGE_FC_TX_PAUSE:
++		rx_en = false;
++		tx_en = true;
++		break;
++	case HCLGE_FC_FULL:
++		rx_en = true;
++		tx_en = true;
++		break;
++	default:
++		rx_en = false;
++		tx_en = false;
++		break;
++	}
++
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, mac->advertising, rx_en);
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, mac->advertising,
++			 rx_en ^ tx_en);
++}
++
++static void hclge_update_advertising(struct hclge_dev *hdev)
++{
++	struct hclge_mac *mac = &hdev->hw.mac;
++
++	linkmode_zero(mac->advertising);
++	hclge_update_speed_advertising(mac);
++	hclge_update_fec_advertising(mac);
++	hclge_update_pause_advertising(hdev);
++}
++
++static void hclge_update_port_capability(struct hclge_dev *hdev,
++					 struct hclge_mac *mac)
++{
++	if (hnae3_dev_fec_supported(hdev))
++		hclge_convert_setting_fec(mac);
++
+ 	/* firmware can not identify back plane type, the media type
+ 	 * read from configuration can help deal it
+ 	 */
+@@ -3015,7 +3093,7 @@ static void hclge_update_port_capability(struct hclge_mac *mac)
+ 	} else {
+ 		linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+ 				   mac->supported);
+-		linkmode_zero(mac->advertising);
++		hclge_update_advertising(hdev);
+ 	}
+ }
+ 
+@@ -3253,7 +3331,7 @@ static int hclge_update_port_info(struct hclge_dev *hdev)
+ 
+ 	if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
+ 		if (mac->speed_type == QUERY_ACTIVE_SPEED) {
+-			hclge_update_port_capability(mac);
++			hclge_update_port_capability(hdev, mac);
+ 			return 0;
+ 		}
+ 		return hclge_cfg_mac_speed_dup(hdev, mac->speed,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index ad786ae8ae4a..7acf0f091b40 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -1069,6 +1069,15 @@ static inline int hclge_get_queue_id(struct hnae3_queue *queue)
+ 	return tqp->index;
+ }
+ 
++static inline void linkmode_mod_bit(int nr, volatile unsigned long *addr,
++				    int set)
++{
++	if (set)
++		linkmode_set_bit(nr, addr);
++	else
++		linkmode_clear_bit(nr, addr);
++}
++
+ static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
+ {
+ 	return !!hdev->reset_pending;
+-- 
+2.34.1
+
diff --git a/patches/0508-net-hns3-add-new-ras-error-type-for-roce.patch b/patches/0508-net-hns3-add-new-ras-error-type-for-roce.patch
new file mode 100644
index 0000000..7e805c0
--- /dev/null
+++ b/patches/0508-net-hns3-add-new-ras-error-type-for-roce.patch
@@ -0,0 +1,62 @@
+From a8db90eed71df1bde62c097ae4748f128617742b Mon Sep 17 00:00:00 2001
+From: Weihang Li <liweihang@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:46 +0800
+Subject: [PATCH 147/283] net: hns3: add new ras error type for roce
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit b566ef60394c528ae201a7c33182539183edd3bf
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b566ef60394c528ae201a7c33182539183edd3bf
+
+----------------------------------------------------------------------
+
+This patch adds one ras error of bus related for roce, this error
+including RRESP/BRESP and read poison error.
+
+Signed-off-by: Weihang Li <liweihang@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 5 ++++-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | 1 +
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index dd607bfad25d..0af187c1e052 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -1321,7 +1321,10 @@ static const struct hclge_hw_type_id hclge_hw_type_id_st[] = {
+ 	}, {
+ 		.type_id = ROCEE_OVF_ERR,
+ 		.msg = "rocee_ovf_error"
+-	}
++	}, {
++		.type_id = ROCEE_BUS_ERR,
++		.msg = "rocee_bus_error"
++	},
+ };
+ 
+ void hclge_log_error(struct device *dev, char *reg,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+index 05612658423a..efe08946050a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+@@ -170,6 +170,7 @@ enum hclge_err_type_list {
+ 	/* add new ERROR TYPE for NIC here in order */
+ 	ROCEE_NORMAL_ERR	= 40,
+ 	ROCEE_OVF_ERR		= 41,
++	ROCEE_BUS_ERR		= 42,
+ 	/* add new ERROR TYPE for ROCEE here in order */
+ };
+ 
+-- 
+2.34.1
+
diff --git a/patches/0509-net-hns3-add-error-recovery-module-and-type-for-hima.patch b/patches/0509-net-hns3-add-error-recovery-module-and-type-for-hima.patch
new file mode 100644
index 0000000..e5db3ec
--- /dev/null
+++ b/patches/0509-net-hns3-add-error-recovery-module-and-type-for-hima.patch
@@ -0,0 +1,83 @@
+From 1efa434df86b299acf3e845e5074968fadd9b2b0 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:47 +0800
+Subject: [PATCH 148/283] net: hns3: add error recovery module and type for
+ himac
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit da3fea80fea481dc5d135c3087b5c686e1656cea
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=da3fea80fea481dc5d135c3087b5c686e1656cea
+
+----------------------------------------------------------------------
+
+This patch adds himac error recovery module, link_error type and
+ptp_error type for himac.
+
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 9 +++++++++
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | 3 +++
+ 2 files changed, 12 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 0af187c1e052..5733f7c25bde 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -1242,6 +1242,9 @@ static const struct hclge_hw_module_id hclge_hw_module_id_st[] = {
+ 	}, {
+ 		.module_id = MODULE_MASTER,
+ 		.msg = "MODULE_MASTER"
++	}, {
++		.module_id = MODULE_HIMAC,
++		.msg = "MODULE_HIMAC"
+ 	}, {
+ 		.module_id = MODULE_ROCEE_TOP,
+ 		.msg = "MODULE_ROCEE_TOP"
+@@ -1315,6 +1318,12 @@ static const struct hclge_hw_type_id hclge_hw_type_id_st[] = {
+ 	}, {
+ 		.type_id = GLB_ERROR,
+ 		.msg = "glb_error"
++	}, {
++		.type_id = LINK_ERROR,
++		.msg = "link_error"
++	}, {
++		.type_id = PTP_ERROR,
++		.msg = "ptp_error"
+ 	}, {
+ 		.type_id = ROCEE_NORMAL_ERR,
+ 		.msg = "rocee_normal_error"
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+index efe08946050a..f36d73cd3abd 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+@@ -139,6 +139,7 @@ enum hclge_mod_name_list {
+ 	MODULE_RCB_TX		= 12,
+ 	MODULE_TXDMA		= 13,
+ 	MODULE_MASTER		= 14,
++	MODULE_HIMAC		= 15,
+ 	/* add new MODULE NAME for NIC here in order */
+ 	MODULE_ROCEE_TOP	= 40,
+ 	MODULE_ROCEE_TIMER	= 41,
+@@ -167,6 +168,8 @@ enum hclge_err_type_list {
+ 	ETS_ERROR		= 10,
+ 	NCSI_ERROR		= 11,
+ 	GLB_ERROR		= 12,
++	LINK_ERROR		= 13,
++	PTP_ERROR		= 14,
+ 	/* add new ERROR TYPE for NIC here in order */
+ 	ROCEE_NORMAL_ERR	= 40,
+ 	ROCEE_OVF_ERR		= 41,
+-- 
+2.34.1
+
diff --git a/patches/0510-net-hns3-fix-data-endian-problem-of-some-functions-o.patch b/patches/0510-net-hns3-fix-data-endian-problem-of-some-functions-o.patch
new file mode 100644
index 0000000..e7d3e25
--- /dev/null
+++ b/patches/0510-net-hns3-fix-data-endian-problem-of-some-functions-o.patch
@@ -0,0 +1,53 @@
+From 865c859f743fb79b81a51d751a81cdb95e705ff6 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:50 +0800
+Subject: [PATCH 149/283] net: hns3: fix data endian problem of some functions
+ of debugfs
+
+mainline inclusion
+from mainline-v5.15
+commit 2a21dab594a98c338c4bfbc31864cbca15888549
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2a21dab594a98c338c4bfbc31864cbca15888549
+
+----------------------------------------------------------------------
+
+The member data in struct hclge_desc is type of __le32, it needs endian
+conversion before using it, and some functions of debugfs didn't do that,
+so this patch fixes it.
+
+Fixes: c0ebebb9ccc1 ("net: hns3: Add "dcb register" status information query function")
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index 6d03af2597b3..985e6677ea27 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -521,7 +521,8 @@ static int hclge_dbg_dump_dcb_port(struct hclge_dev *hdev, char *buf, int len,
+ 
+ 	req.bitmap = (u8)le32_to_cpu(desc.data[1]);
+ 
+-	*pos += scnprintf(buf + *pos, len - *pos, "port_mask: %#x\n", req.bit0);
++	*pos += scnprintf(buf + *pos, len - *pos, "port_mask: %#x\n",
++			 req.bit0);
+ 	*pos += scnprintf(buf + *pos, len - *pos, "port_shaping_pass: %#x\n",
+ 			 req.bit1);
+ 
+-- 
+2.34.1
+
diff --git a/patches/0511-net-hns3-add-more-string-spaces-for-dumping-packets-.patch b/patches/0511-net-hns3-add-more-string-spaces-for-dumping-packets-.patch
new file mode 100644
index 0000000..39d48c5
--- /dev/null
+++ b/patches/0511-net-hns3-add-more-string-spaces-for-dumping-packets-.patch
@@ -0,0 +1,49 @@
+From 65536c5c087b6b522e78d9d22626246be2f5313c Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:51 +0800
+Subject: [PATCH 150/283] net: hns3: add more string spaces for dumping packets
+ number of queue info in debugfs
+
+mainline inclusion
+from mainline-v5.15
+commit 6754614a787cbcbf87bae8a75619c24a33ea6791
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6754614a787cbcbf87bae8a75619c24a33ea6791
+
+----------------------------------------------------------------------
+
+As the width of packets number registers is 32 bits, they needs at most
+10 characters for decimal data printing, but now the string spaces is not
+enough, so this patch fixes it.
+
+Fixes: e44c495d95e ("net: hns3: refactor queue info of debugfs")
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index b13cd5ea7bd7..c0a255f93dbd 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -448,7 +448,7 @@ static const struct hns3_dbg_item rx_queue_info_items[] = {
+ 	{ "TAIL", 2 },
+ 	{ "HEAD", 2 },
+ 	{ "FBDNUM", 2 },
+-	{ "PKTNUM", 2 },
++	{ "PKTNUM", 5 },
+ 	{ "COPYBREAK", 2 },
+ 	{ "RING_EN", 2 },
+ 	{ "RX_RING_EN", 2 },
+-- 
+2.34.1
+
diff --git a/patches/0512-net-hns3-adjust-string-spaces-of-some-parameters-of-.patch b/patches/0512-net-hns3-adjust-string-spaces-of-some-parameters-of-.patch
new file mode 100644
index 0000000..16dd5af
--- /dev/null
+++ b/patches/0512-net-hns3-adjust-string-spaces-of-some-parameters-of-.patch
@@ -0,0 +1,46 @@
+From 8470d9c6890f685e36ba6b19ad9b4fc096538d3c Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:53 +0800
+Subject: [PATCH 151/283] net: hns3: adjust string spaces of some parameters of
+ tx bd info in debugfs
+
+mainline inclusion
+from mainline-v5.15
+commit 630a6738da82e2c29e1c38eafd6f8328e0a4963c
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=630a6738da82e2c29e1c38eafd6f8328e0a4963c
+
+----------------------------------------------------------------------
+
+This patch adjusts the string spaces of some parameters of tx bd info in
+debugfs according to their maximum needs.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index c0a255f93dbd..f535b7ea39c0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -842,7 +842,7 @@ static const struct hns3_dbg_item tx_bd_info_items[] = {
+ 	{ "SIZE", 2 },
+ 	{ "T_CS_VLAN_TSO", 2 },
+ 	{ "OT_VLAN_TAG", 3 },
+-	{ "TV", 2 },
++	{ "TV", 5 },
+ 	{ "OLT_VLAN_LEN", 2 },
+ 	{ "PAYLEN_OL4CS", 2 },
+ 	{ "BD_FE_SC_VLD", 2 },
+-- 
+2.34.1
+
diff --git a/patches/0513-net-hisilicon-fix-hsn3_ethtool-kernel-doc-warnings.patch b/patches/0513-net-hisilicon-fix-hsn3_ethtool-kernel-doc-warnings.patch
new file mode 100644
index 0000000..0603f68
--- /dev/null
+++ b/patches/0513-net-hisilicon-fix-hsn3_ethtool-kernel-doc-warnings.patch
@@ -0,0 +1,59 @@
+From 6137d5eda93889675e6156568705fa50018d3672 Mon Sep 17 00:00:00 2001
+From: Randy Dunlap <rdunlap@infradead.org>
+Date: Thu, 18 Nov 2021 20:44:54 +0800
+Subject: [PATCH 152/283] net: hisilicon: fix hsn3_ethtool kernel-doc warnings
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit 85879f131d78151847baf29f9557c5be1aa8e066
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=85879f131d78151847baf29f9557c5be1aa8e066
+
+----------------------------------------------------------------------
+
+Fix kernel-doc warnings and spacing in hns3_ethtool.c:
+
+hns3_ethtool.c:246: warning: No description found for return value of 'hns3_lp_run_test'
+hns3_ethtool.c:408: warning: expecting prototype for hns3_nic_self_test(). Prototype was for hns3_self_test() instead
+
+Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
+Reported-by: kernel test robot <lkp@intel.com>
+Cc: Peng Li <lipeng321@huawei.com>
+Cc: Guangbin Huang <huangguangbin2@huawei.com>
+Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
+Cc: Salil Mehta <salil.mehta@huawei.com>
+Cc: "David S. Miller" <davem@davemloft.net>
+Cc: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+(fix conflicts: remove hns3_do_selftest's fix due to a previous fix: 65b017dc58d6 "net: hns3: fix prototype warning")
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 1624df0ac6e4..f7bb9c85e243 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -246,9 +246,11 @@ static void hns3_lb_clear_tx_ring(struct hns3_nic_priv *priv, u32 start_ringid,
+ }
+ 
+ /**
+- * hns3_lp_run_test -  run loopback test
++ * hns3_lp_run_test - run loopback test
+  * @ndev: net device
+  * @mode: loopback type
++ *
++ * Return: %0 for success or a NIC loopback test error code on failure
+  */
+ static int hns3_lp_run_test(struct net_device *ndev, enum hnae3_loop mode)
+ {
+-- 
+2.34.1
+
diff --git a/patches/0514-net-hns3-add-support-for-pf-querying-new-interrupt-r.patch b/patches/0514-net-hns3-add-support-for-pf-querying-new-interrupt-r.patch
new file mode 100644
index 0000000..512f1a1
--- /dev/null
+++ b/patches/0514-net-hns3-add-support-for-pf-querying-new-interrupt-r.patch
@@ -0,0 +1,483 @@
+From 3779944f2f2d81decc4c2cf2d126abdd7f8b4ec5 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Wed, 14 Jul 2021 20:55:30 +0800
+Subject: [PATCH 153/283] net: hns3: add support for pf querying new interrupt
+ resources
+
+mainline inclusion
+from mainline-v5.11-rc1
+commit 3a6863e4e8ee212c7f86594299d9ff0d6a15ecbc
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3a6863e4e8ee212c7f86594299d9ff0d6a15ecbc
+
+----------------------------------------------------------------------
+
+For HNAE3_DEVICE_VERSION_V3, a maximum of 1281 interrupt
+resources are supported. To utilize these new resources,
+extend the corresponding field or variable to 16bit type,
+and remove the restriction of NIC client that only use a
+maximum of 65 interrupt vectors. In addition, the I/O address
+of the extended interrupt resources are different, so an extra
+handler is needed.
+
+Currently, the total number of interrupts is the sum of RoCE's
+number and RoCE's offset (RoCE is in front of NIC), since
+the number of both NIC and RoCE are same. For readability,
+rewrite the corresponding field of the command, rename the
+RoCE's offset field as the number of NIC interrupts, then
+the total number of interrupts is sum of the number of RoCE
+and NIC, and replace vport->back with hdev in
+hclge_init_roce_base_info() for simplifying the code.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: li yongxin <liyongxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |   1 +
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   |   3 -
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  16 +--
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 131 ++++++++++++------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   4 +-
+ .../hisilicon/hns3/hns3pf/hclge_mbx.c         |   2 +-
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |  33 +++++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.h      |   1 +
+ 8 files changed, 138 insertions(+), 53 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 9eb545677c05..4f77d80b01f4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -834,6 +834,7 @@ struct hnae3_knic_private_info {
+ struct hnae3_roce_private_info {
+ 	struct net_device *netdev;
+ 	void __iomem *roce_io_base;
++	void __iomem *roce_mem_base;
+ 	int base_vector;
+ 	int num_vectors;
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 69170427c55d..9691d43a9b52 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -4253,8 +4253,6 @@ static void hns3_nic_init_coal_cfg(struct hns3_nic_priv *priv)
+ 
+ static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
+ {
+-#define HNS3_VECTOR_PF_MAX_NUM		64
+-
+ 	struct hnae3_handle *h = priv->ae_handle;
+ 	struct hns3_enet_tqp_vector *tqp_vector;
+ 	struct hnae3_vector_info *vector;
+@@ -4267,7 +4265,6 @@ static int hns3_nic_alloc_vector_data(struct hns3_nic_priv *priv)
+ 	/* RSS size, cpu online and vector_num should be the same */
+ 	/* Should consider 2p/4p later */
+ 	vector_num = min_t(u16, num_online_cpus(), tqp_num);
+-	vector_num = min_t(u16, vector_num, HNS3_VECTOR_PF_MAX_NUM);
+ 
+ 	vector = devm_kcalloc(&pdev->dev, vector_num, sizeof(*vector),
+ 			      GFP_KERNEL);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index e96c58eeb9b4..16e41f546e21 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -359,7 +359,9 @@ enum hclge_int_type {
+ };
+ 
+ struct hclge_ctrl_vector_chain_cmd {
+-	u8 int_vector_id;
++#define HCLGE_VECTOR_ID_L_S	0
++#define HCLGE_VECTOR_ID_L_M	GENMASK(7, 0)
++	u8 int_vector_id_l;
+ 	u8 int_cause_num;
+ #define HCLGE_INT_TYPE_S	0
+ #define HCLGE_INT_TYPE_M	GENMASK(1, 0)
+@@ -369,7 +371,9 @@ struct hclge_ctrl_vector_chain_cmd {
+ #define HCLGE_INT_GL_IDX_M	GENMASK(14, 13)
+ 	__le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
+ 	u8 vfid;
+-	u8 rsv;
++#define HCLGE_VECTOR_ID_H_S	8
++#define HCLGE_VECTOR_ID_H_M	GENMASK(15, 8)
++	u8 int_vector_id_h;
+ };
+ 
+ #define HCLGE_MAX_TC_NUM		8
+@@ -499,12 +503,8 @@ struct hclge_pf_res_cmd {
+ 	__le16 tqp_num;
+ 	__le16 buf_size;
+ 	__le16 msixcap_localid_ba_nic;
+-	__le16 msixcap_localid_ba_rocee;
+-#define HCLGE_MSIX_OFT_ROCEE_S		0
+-#define HCLGE_MSIX_OFT_ROCEE_M		GENMASK(15, 0)
+-#define HCLGE_PF_VEC_NUM_S		0
+-#define HCLGE_PF_VEC_NUM_M		GENMASK(7, 0)
+-	__le16 pf_intr_vector_number;
++	__le16 msixcap_localid_number_nic;
++	__le16 pf_intr_vector_number_roce;
+ 	__le16 pf_own_fun_number;
+ 	__le16 tx_buf_size;
+ 	__le16 dv_buf_size;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 2169c60aad03..6d41c3151916 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -958,35 +958,24 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
+ 
+ 	hdev->dv_buf_size = roundup(hdev->dv_buf_size, HCLGE_BUF_SIZE_UNIT);
+ 
++	hdev->num_nic_msi = le16_to_cpu(req->msixcap_localid_number_nic);
++	if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) {
++		dev_err(&hdev->pdev->dev,
++			"only %u msi resources available, not enough for pf(min:2).\n",
++			hdev->num_nic_msi);
++		return -EINVAL;
++	}
++
+ 	if (hnae3_dev_roce_supported(hdev)) {
+-		hdev->roce_base_msix_offset =
+-		hnae3_get_field(le16_to_cpu(req->msixcap_localid_ba_rocee),
+-				HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
+ 		hdev->num_roce_msi =
+-		hnae3_get_field(le16_to_cpu(req->pf_intr_vector_number),
+-				HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
+-
+-		/* nic's msix numbers is always equals to the roce's. */
+-		hdev->num_nic_msi = hdev->num_roce_msi;
++			le16_to_cpu(req->pf_intr_vector_number_roce);
+ 
+ 		/* PF should have NIC vectors and Roce vectors,
+ 		 * NIC vectors are queued before Roce vectors.
+ 		 */
+-		hdev->num_msi = hdev->num_roce_msi +
+-				hdev->roce_base_msix_offset;
++		hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi;
+ 	} else {
+-		hdev->num_msi =
+-		hnae3_get_field(le16_to_cpu(req->pf_intr_vector_number),
+-				HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
+-
+-		hdev->num_nic_msi = hdev->num_msi;
+-	}
+-
+-	if (hdev->num_nic_msi < HNAE3_MIN_VECTOR_NUM) {
+-		dev_err(&hdev->pdev->dev,
+-			"Just %u msi resources, not enough for pf(min:2).\n",
+-			hdev->num_nic_msi);
+-		return -EINVAL;
++		hdev->num_msi = hdev->num_nic_msi;
+ 	}
+ 
+ 	return 0;
+@@ -2517,17 +2506,18 @@ static int hclge_init_roce_base_info(struct hclge_vport *vport)
+ {
+ 	struct hnae3_handle *roce = &vport->roce;
+ 	struct hnae3_handle *nic = &vport->nic;
++	struct hclge_dev *hdev = vport->back;
+ 
+ 	roce->rinfo.num_vectors = vport->back->num_roce_msi;
+ 
+-	if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
+-	    vport->back->num_msi_left == 0)
++	if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi)
+ 		return -EINVAL;
+ 
+-	roce->rinfo.base_vector = vport->back->roce_base_vector;
++	roce->rinfo.base_vector = hdev->roce_base_vector;
+ 
+ 	roce->rinfo.netdev = nic->kinfo.netdev;
+-	roce->rinfo.roce_io_base = vport->back->hw.io_base;
++	roce->rinfo.roce_io_base = hdev->hw.io_base;
++	roce->rinfo.roce_mem_base = hdev->hw.mem_base;
+ 
+ 	roce->pdev = nic->pdev;
+ 	roce->ae_algo = nic->ae_algo;
+@@ -2561,7 +2551,7 @@ static int hclge_init_msi(struct hclge_dev *hdev)
+ 
+ 	hdev->base_msi_vector = pdev->irq;
+ 	hdev->roce_base_vector = hdev->base_msi_vector +
+-				hdev->roce_base_msix_offset;
++				hdev->num_nic_msi;
+ 
+ 	hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
+ 					   sizeof(u16), GFP_KERNEL);
+@@ -4591,6 +4581,30 @@ struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
+ 		return container_of(handle, struct hclge_vport, nic);
+ }
+ 
++static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx,
++				  struct hnae3_vector_info *vector_info)
++{
++#define HCLGE_PF_MAX_VECTOR_NUM_DEV_V2	64
++
++	vector_info->vector = pci_irq_vector(hdev->pdev, idx);
++
++	/* need an extend offset to config vector >= 64 */
++	if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2)
++		vector_info->io_addr = hdev->hw.io_base +
++				HCLGE_VECTOR_REG_BASE +
++				(idx - 1) * HCLGE_VECTOR_REG_OFFSET;
++	else
++		vector_info->io_addr = hdev->hw.io_base +
++				HCLGE_VECTOR_EXT_REG_BASE +
++				(idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
++				HCLGE_VECTOR_REG_OFFSET_H +
++				(idx - 1) % HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
++				HCLGE_VECTOR_REG_OFFSET;
++
++	hdev->vector_status[idx] = hdev->vport[0].vport_id;
++	hdev->vector_irq[idx] = vector_info->vector;
++}
++
+ static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
+ 			    struct hnae3_vector_info *vector_info)
+ {
+@@ -4598,23 +4612,16 @@ static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
+ 	struct hnae3_vector_info *vector = vector_info;
+ 	struct hclge_dev *hdev = vport->back;
+ 	int alloc = 0;
+-	int i, j;
++	u16 i = 0;
++	u16 j;
+ 
+ 	vector_num = min_t(u16, hdev->num_nic_msi - 1, vector_num);
+ 	vector_num = min(hdev->num_msi_left, vector_num);
+ 
+ 	for (j = 0; j < vector_num; j++) {
+-		for (i = 1; i < hdev->num_msi; i++) {
++		while (++i < hdev->num_nic_msi) {
+ 			if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
+-				vector->vector = pci_irq_vector(hdev->pdev, i);
+-				vector->io_addr = hdev->hw.io_base +
+-					HCLGE_VECTOR_REG_BASE +
+-					(i - 1) * HCLGE_VECTOR_REG_OFFSET +
+-					vport->vport_id *
+-					HCLGE_VECTOR_VF_OFFSET;
+-				hdev->vector_status[i] = vport->vport_id;
+-				hdev->vector_irq[i] = vector->vector;
+-
++				hclge_get_vector_info(hdev, i, vector);
+ 				vector++;
+ 				alloc++;
+ 
+@@ -5205,7 +5212,12 @@ int hclge_bind_ring_with_vector(struct hclge_vport *vport,
+ 
+ 	op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
+ 	hclge_cmd_setup_basic_desc(&desc, op, false);
+-	req->int_vector_id = vector_id;
++	req->int_vector_id_l = hnae3_get_field(vector_id,
++					       HCLGE_VECTOR_ID_L_M,
++					       HCLGE_VECTOR_ID_L_S);
++	req->int_vector_id_h = hnae3_get_field(vector_id,
++					       HCLGE_VECTOR_ID_H_M,
++					       HCLGE_VECTOR_ID_H_S);
+ 
+ 	i = 0;
+ 	for (node = ring_chain; node; node = node->next) {
+@@ -5237,7 +5249,14 @@ int hclge_bind_ring_with_vector(struct hclge_vport *vport,
+ 			hclge_cmd_setup_basic_desc(&desc,
+ 						   op,
+ 						   false);
+-			req->int_vector_id = vector_id;
++			req->int_vector_id_l =
++				hnae3_get_field(vector_id,
++						HCLGE_VECTOR_ID_L_M,
++						HCLGE_VECTOR_ID_L_S);
++			req->int_vector_id_h =
++				hnae3_get_field(vector_id,
++						HCLGE_VECTOR_ID_H_M,
++						HCLGE_VECTOR_ID_H_S);
+ 		}
+ 	}
+ 
+@@ -10670,6 +10689,28 @@ static void hclge_uninit_client_instance(struct hnae3_client *client,
+ 	}
+ }
+ 
++static int hclge_dev_mem_map(struct hclge_dev *hdev)
++{
++#define HCLGE_MEM_BAR          4
++
++	struct pci_dev *pdev = hdev->pdev;
++	struct hclge_hw *hw = &hdev->hw;
++
++	/* for device does not have device memory, return directly */
++	if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR)))
++		return 0;
++
++	hw->mem_base = devm_ioremap_wc(&pdev->dev,
++				       pci_resource_start(pdev, HCLGE_MEM_BAR),
++				       pci_resource_len(pdev, HCLGE_MEM_BAR));
++	if (!hw->mem_base) {
++		dev_err(&pdev->dev, "failed to map device memroy\n");
++		return -EFAULT;
++	}
++
++	return 0;
++}
++
+ static int hclge_pci_init(struct hclge_dev *hdev)
+ {
+ 	struct pci_dev *pdev = hdev->pdev;
+@@ -10708,9 +10749,16 @@ static int hclge_pci_init(struct hclge_dev *hdev)
+ 		goto err_clr_master;
+ 	}
+ 
++	ret = hclge_dev_mem_map(hdev);
++	if (ret)
++		goto err_unmap_io_base;
++
+ 	hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
+ 
+ 	return 0;
++
++err_unmap_io_base:
++	pcim_iounmap(pdev, hdev->hw.io_base);
+ err_clr_master:
+ 	pci_clear_master(pdev);
+ 	pci_release_regions(pdev);
+@@ -10724,6 +10772,9 @@ static void hclge_pci_uninit(struct hclge_dev *hdev)
+ {
+ 	struct pci_dev *pdev = hdev->pdev;
+ 
++	if (hdev->hw.mem_base)
++		devm_iounmap(&pdev->dev, hdev->hw.mem_base);
++
+ 	pcim_iounmap(pdev, hdev->hw.io_base);
+ 	pci_free_irq_vectors(pdev);
+ 	pci_clear_master(pdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 7acf0f091b40..5ff61230d79f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -30,9 +30,11 @@
+ 	(HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
+ 
+ #define HCLGE_VECTOR_REG_BASE		0x20000
++#define HCLGE_VECTOR_EXT_REG_BASE	0x30000
+ #define HCLGE_MISC_VECTOR_REG_BASE	0x20400
+ 
+ #define HCLGE_VECTOR_REG_OFFSET		0x4
++#define HCLGE_VECTOR_REG_OFFSET_H	0x1000
+ #define HCLGE_VECTOR_VF_OFFSET		0x100000
+ 
+ #define HCLGE_NIC_CSQ_BASEADDR_L_REG	0x27000
+@@ -295,6 +297,7 @@ struct hclge_mac {
+ 
+ struct hclge_hw {
+ 	void __iomem *io_base;
++	void __iomem *mem_base;
+ 	struct hclge_mac mac;
+ 	int num_vec;
+ 	struct hclge_cmq cmq;
+@@ -850,7 +853,6 @@ struct hclge_dev {
+ 	u16 num_msi;
+ 	u16 num_msi_left;
+ 	u16 num_msi_used;
+-	u16 roce_base_msix_offset;
+ 	u32 base_msi_vector;
+ 	u16 *vector_status;
+ 	int *vector_irq;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+index 07d0aaa0634e..7b27a012bbd1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+@@ -311,7 +311,7 @@ static int hclge_get_vf_ring_vector_map(struct hclge_vport *vport,
+ 	resp->data[HCLGE_RING_TYPE_OFFSET] = req->msg.param[0].ring_type;
+ 	resp->data[HCLGE_TQP_INDEX_OFFSET] = req->msg.param[0].tqp_index;
+ 	resp->data[HCLGE_INT_GL_INDEX_OFFSET] = int_gl_index;
+-	resp->data[HCLGE_VECTOR_ID_OFFSET] = data->int_vector_id;
++	resp->data[HCLGE_VECTOR_ID_OFFSET] = data->int_vector_id_l;
+ 	resp->len = HCLGE_RING_VECTOR_MAP_INFO_LEN;
+ 
+ 	hclge_free_vector_ring_chain(&ring_chain);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 8386baf0a6a6..082361e3713c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -2486,6 +2486,7 @@ static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
+ 
+ 	roce->rinfo.netdev = nic->kinfo.netdev;
+ 	roce->rinfo.roce_io_base = hdev->hw.io_base;
++	roce->rinfo.roce_mem_base = hdev->hw.mem_base;
+ 
+ 	roce->pdev = nic->pdev;
+ 	roce->ae_algo = nic->ae_algo;
+@@ -2946,6 +2947,29 @@ static void hclgevf_uninit_client_instance(struct hnae3_client *client,
+ 	}
+ }
+ 
++static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev)
++{
++#define HCLGEVF_MEM_BAR                4
++
++	struct pci_dev *pdev = hdev->pdev;
++	struct hclgevf_hw *hw = &hdev->hw;
++
++	/* for device does not have device memory, return directly */
++	if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR)))
++		return 0;
++
++	hw->mem_base = devm_ioremap_wc(&pdev->dev,
++				       pci_resource_start(pdev,
++							  HCLGEVF_MEM_BAR),
++			pci_resource_len(pdev, HCLGEVF_MEM_BAR));
++	if (!hw->mem_base) {
++		dev_err(&pdev->dev, "failed to map device memroy\n");
++		return -EFAULT;
++	}
++
++	return 0;
++}
++
+ static int hclgevf_pci_init(struct hclgevf_dev *hdev)
+ {
+ 	struct pci_dev *pdev = hdev->pdev;
+@@ -2980,8 +3004,14 @@ static int hclgevf_pci_init(struct hclgevf_dev *hdev)
+ 		goto err_clr_master;
+ 	}
+ 
++	ret = hclgevf_dev_mem_map(hdev);
++	if (ret)
++		goto err_unmap_io_base;
++
+ 	return 0;
+ 
++err_unmap_io_base:
++	pci_iounmap(pdev, hdev->hw.io_base);
+ err_clr_master:
+ 	pci_clear_master(pdev);
+ 	pci_release_regions(pdev);
+@@ -2995,6 +3025,9 @@ static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
+ {
+ 	struct pci_dev *pdev = hdev->pdev;
+ 
++	if (hdev->hw.mem_base)
++		devm_iounmap(&pdev->dev, hdev->hw.mem_base);
++
+ 	pci_iounmap(pdev, hdev->hw.io_base);
+ 	pci_clear_master(pdev);
+ 	pci_release_regions(pdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index 4498859e6ed4..45313a59a380 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -168,6 +168,7 @@ struct hclgevf_mac {
+ 
+ struct hclgevf_hw {
+ 	void __iomem *io_base;
++	void __iomem *mem_base;
+ 	int num_vec;
+ 	struct hclgevf_cmq cmq;
+ 	struct hclgevf_mac mac;
+-- 
+2.34.1
+
diff --git a/patches/0515-net-hns3-fix-ROCE-base-interrupt-vector-initializati.patch b/patches/0515-net-hns3-fix-ROCE-base-interrupt-vector-initializati.patch
new file mode 100644
index 0000000..9284a9f
--- /dev/null
+++ b/patches/0515-net-hns3-fix-ROCE-base-interrupt-vector-initializati.patch
@@ -0,0 +1,120 @@
+From 0da9cf5bd89d57ff5cb0e14e52cdc9af4b37e075 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:56 +0800
+Subject: [PATCH 154/283] net: hns3: fix ROCE base interrupt vector
+ initialization bug
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit beb27ca451a57a1c0e52b5268703f3c3173c1f8c
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=beb27ca451a57a1c0e52b5268703f3c3173c1f8c
+
+----------------------------------------------------------------------
+
+Currently, NIC init ROCE interrupt vector with MSIX interrupt. But ROCE use
+pci_irq_vector() to get interrupt vector, which adds the relative interrupt
+vector again and gets wrong interrupt vector.
+
+So fixes it by assign relative interrupt vector to ROCE instead of MSIX
+interrupt vector and delete the unused struct member base_msi_vector
+declaration of hclgevf_dev.
+
+Fixes: 46a3df9f9718 ("net: hns3: Add HNS3 Acceleration Engine & Compatibility Layer Support")
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c   | 6 +-----
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h   | 2 --
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 5 +----
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 2 --
+ 4 files changed, 2 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 6d41c3151916..e0ef00440f79 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -2513,7 +2513,7 @@ static int hclge_init_roce_base_info(struct hclge_vport *vport)
+ 	if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi)
+ 		return -EINVAL;
+ 
+-	roce->rinfo.base_vector = hdev->roce_base_vector;
++	roce->rinfo.base_vector = hdev->num_nic_msi;
+ 
+ 	roce->rinfo.netdev = nic->kinfo.netdev;
+ 	roce->rinfo.roce_io_base = hdev->hw.io_base;
+@@ -2549,10 +2549,6 @@ static int hclge_init_msi(struct hclge_dev *hdev)
+ 	hdev->num_msi = vectors;
+ 	hdev->num_msi_left = vectors;
+ 
+-	hdev->base_msi_vector = pdev->irq;
+-	hdev->roce_base_vector = hdev->base_msi_vector +
+-				hdev->num_nic_msi;
+-
+ 	hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
+ 					   sizeof(u16), GFP_KERNEL);
+ 	if (!hdev->vector_status) {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 5ff61230d79f..51f46d68c05f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -853,12 +853,10 @@ struct hclge_dev {
+ 	u16 num_msi;
+ 	u16 num_msi_left;
+ 	u16 num_msi_used;
+-	u32 base_msi_vector;
+ 	u16 *vector_status;
+ 	int *vector_irq;
+ 	u16 num_nic_msi;	/* Num of nic vectors for this PF */
+ 	u16 num_roce_msi;	/* Num of roce vectors for this PF */
+-	int roce_base_vector;
+ 
+ 	unsigned long service_timer_period;
+ 	unsigned long service_timer_previous;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 082361e3713c..2457feb0e95f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -2482,7 +2482,7 @@ static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
+ 	    hdev->num_msi_left == 0)
+ 		return -EINVAL;
+ 
+-	roce->rinfo.base_vector = hdev->roce_base_vector;
++	roce->rinfo.base_vector = hdev->roce_base_msix_offset;
+ 
+ 	roce->rinfo.netdev = nic->kinfo.netdev;
+ 	roce->rinfo.roce_io_base = hdev->hw.io_base;
+@@ -2738,9 +2738,6 @@ static int hclgevf_init_msi(struct hclgevf_dev *hdev)
+ 	hdev->num_msi = vectors;
+ 	hdev->num_msi_left = vectors;
+ 
+-	hdev->base_msi_vector = pdev->irq;
+-	hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
+-
+ 	hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
+ 					   sizeof(u16), GFP_KERNEL);
+ 	if (!hdev->vector_status) {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index 45313a59a380..a9624b9adcfd 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -303,8 +303,6 @@ struct hclgevf_dev {
+ 	u16 num_nic_msix;	/* Num of nic vectors for this VF */
+ 	u16 num_roce_msix;	/* Num of roce vectors for this VF */
+ 	u16 roce_base_msix_offset;
+-	int roce_base_vector;
+-	u32 base_msi_vector;
+ 	u16 *vector_status;
+ 	int *vector_irq;
+ 
+-- 
+2.34.1
+
diff --git a/patches/0516-net-hns3-sync-rx-ring-head-in-echo-common-pull.patch b/patches/0516-net-hns3-sync-rx-ring-head-in-echo-common-pull.patch
new file mode 100644
index 0000000..6a370f2
--- /dev/null
+++ b/patches/0516-net-hns3-sync-rx-ring-head-in-echo-common-pull.patch
@@ -0,0 +1,177 @@
+From 1d8787a29618a0489a3d005c58d55a50cf8f75b8 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:58 +0800
+Subject: [PATCH 155/283] net: hns3: sync rx ring head in echo common pull
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit 3b6db4a0492beed36545a2bc6075117faecebfe2
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3b6db4a0492beed36545a2bc6075117faecebfe2
+
+----------------------------------------------------------------------
+
+When the driver processes rx packets, the head pointer is updated only
+after the number of received packets reaches 16. However, hardware
+relies on the head pointer to calculate the number of FBDs. As a result,
+the hardware calculates the FBD incorrectly. Therefore, the driver
+proactively updates the head pointer in each common poll to ensure that
+the number of FBDs calculated by the hardware is correct.
+
+Fixes: 68752b24f51a ("net: hns3: schedule the polling again when allocation fails")
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  7 ++++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         |  5 +++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  1 +
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       | 32 +++++++++++++++++++
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       |  9 ++++++
+ 5 files changed, 54 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 9691d43a9b52..6cf947cd96eb 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -3842,6 +3842,13 @@ int hns3_clean_rx_ring(struct hns3_enet_ring *ring, int budget,
+ 	}
+ 
+ out:
++	/* sync head pointer before exiting, since hardware will calculate
++	 * FBD number with head pointer
++	 */
++	if (unused_count > 0)
++		failure = failure ||
++			  hns3_nic_alloc_rx_buffers(ring, unused_count);
++
+ 	return failure ? budget : recv_pkts;
+ }
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 6e28dd4524b8..6d9c3945328a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -487,6 +487,11 @@ static int hclge_firmware_compat_config(struct hclge_dev *hdev, bool en)
+ 
+ 		hnae3_set_bit(compat, HCLGE_LINK_EVENT_REPORT_EN_B, 1);
+ 		hnae3_set_bit(compat, HCLGE_NCSI_ERROR_REPORT_EN_B, 1);
++		if (hnae3_dev_phy_imp_supported(hdev))
++			hnae3_set_bit(compat, HCLGE_PHY_IMP_EN_B, 1);
++		hnae3_set_bit(compat, HCLGE_MAC_STATS_EXT_EN_B, 1);
++		hnae3_set_bit(compat, HCLGE_SYNC_RX_RING_HEAD_EN_B, 1);
++
+ 		req->compat = cpu_to_le32(compat);
+ 	}
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 16e41f546e21..882e14a15128 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -1149,6 +1149,7 @@ struct hclge_query_ppu_pf_other_int_dfx_cmd {
+ #define HCLGE_NCSI_ERROR_REPORT_EN_B	1
+ #define HCLGE_PHY_IMP_EN_B		2
+ #define HCLGE_MAC_STATS_EXT_EN_B	3
++#define HCLGE_SYNC_RX_RING_HEAD_EN_B	4
+ struct hclge_firmware_compat_cmd {
+ 	__le32 compat;
+ 	u8 rsv[20];
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 37e0fc7e570b..12b241c0db0a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -445,8 +445,28 @@ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
+ 	return ret;
+ }
+ 
++static int hclgevf_firmware_compat_config(struct hclgevf_dev *hdev, bool en)
++{
++	struct hclgevf_firmware_compat_cmd *req;
++	struct hclgevf_desc desc;
++	u32 compat = 0;
++
++	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_IMP_COMPAT_CFG, false);
++
++	if (en) {
++		req = (struct hclgevf_firmware_compat_cmd *)desc.data;
++
++		hnae3_set_bit(compat, HCLGEVF_SYNC_RX_RING_HEAD_EN_B, 1);
++
++		req->compat = cpu_to_le32(compat);
++	}
++
++	return hclgevf_cmd_send(&hdev->hw, &desc, 1);
++}
++
+ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ {
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	int ret;
+ 
+ 	spin_lock_bh(&hdev->hw.cmq.csq.lock);
+@@ -496,6 +516,17 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ 		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE0_MASK,
+ 				HNAE3_FW_VERSION_BYTE0_SHIFT));
+ 
++	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
++		/* ask the firmware to enable some features, driver can work
++		 * without it.
++		 */
++		ret = hclgevf_firmware_compat_config(hdev, true);
++		if (ret)
++			dev_warn(&hdev->pdev->dev,
++				 "Firmware compatible features not enabled(%d).\n",
++				 ret);
++	}
++
+ 	return 0;
+ 
+ err_cmd_init:
+@@ -506,6 +537,7 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ 
+ void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
+ {
++	hclgevf_firmware_compat_config(hdev, false);
+ 	set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
+ 	/* wait to ensure that the firmware completes the possible left
+ 	 * over commands.
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 824414e5fdf0..6d0540c15487 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -15,6 +15,12 @@
+ struct hclgevf_hw;
+ struct hclgevf_dev;
+ 
++#define HCLGEVF_SYNC_RX_RING_HEAD_EN_B	4
++struct hclgevf_firmware_compat_cmd {
++	__le32 compat;
++	u8 rsv[20];
++};
++
+ struct hclgevf_desc {
+ 	__le16 opcode;
+ 	__le16 flag;
+@@ -107,6 +113,9 @@ enum hclgevf_opcode_type {
+ 	HCLGEVF_OPC_RSS_TC_MODE		= 0x0D08,
+ 	/* Mailbox cmd */
+ 	HCLGEVF_OPC_MBX_VF_TO_PF	= 0x2001,
++
++	/* IMP stats command */
++	HCLGEVF_OPC_IMP_COMPAT_CFG	= 0x701A,
+ };
+ 
+ #define HCLGEVF_TQP_REG_OFFSET		0x80000
+-- 
+2.34.1
+
diff --git a/patches/0517-net-hns3-fix-some-mac-statistics-is-always-0-in-devi.patch b/patches/0517-net-hns3-fix-some-mac-statistics-is-always-0-in-devi.patch
new file mode 100644
index 0000000..51d1d8b
--- /dev/null
+++ b/patches/0517-net-hns3-fix-some-mac-statistics-is-always-0-in-devi.patch
@@ -0,0 +1,75 @@
+From 3ebad05eeddf64eb84b546b2f2ac937947c650f4 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Thu, 18 Nov 2021 20:45:00 +0800
+Subject: [PATCH 156/283] net: hns3: fix some mac statistics is always 0 in
+ device version V2
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit 1122eac19476c5ccf200009d4e4dc9b11458019c
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1122eac19476c5ccf200009d4e4dc9b11458019c
+
+----------------------------------------------------------------------
+
+When driver queries the register number of mac statistics from firmware,
+the old firmware runs in device version V2 only returns number of valid
+registers, not include number of three reserved registers among of them.
+It cause driver doesn't record the last three data when query mac
+statistics.
+
+To fix this problem, driver never query register number in device version
+V2 and set it to a fixed value which include three reserved registers.
+
+Fixes: c8af2887c941 ("net: hns3: add support pause/pfc durations for mac statistics")
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c    | 10 ++++++++++
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h    |  2 +-
+ 2 files changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index e0ef00440f79..3ff2eb9fcf5f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -538,6 +538,16 @@ static int hclge_mac_query_reg_num(struct hclge_dev *hdev, u32 *reg_num)
+ 	struct hclge_desc desc;
+ 	int ret;
+ 
++	/* Driver needs total register number of both valid registers and
++	 * reserved registers, but the old firmware only returns number
++	 * of valid registers in device V2. To be compatible with these
++	 * devices, driver uses a fixed value.
++	 */
++	if (hdev->ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
++		*reg_num = HCLGE_MAC_STATS_MAX_NUM_V1;
++		return 0;
++	}
++
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_REG_NUM, true);
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret) {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 51f46d68c05f..7ba42bbcf370 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -406,7 +406,7 @@ struct hclge_tm_info {
+ };
+ 
+ /* max number of mac statistics on each version */
+-#define HCLGE_MAC_STATS_MAX_NUM_V1		84
++#define HCLGE_MAC_STATS_MAX_NUM_V1		87
+ #define HCLGE_MAC_STATS_MAX_NUM_V2		105
+ 
+ struct hclge_comm_stats_str {
+-- 
+2.34.1
+
diff --git a/patches/0518-net-hns3-allow-configure-ETS-bandwidth-of-all-TCs.patch b/patches/0518-net-hns3-allow-configure-ETS-bandwidth-of-all-TCs.patch
new file mode 100644
index 0000000..7e02a99
--- /dev/null
+++ b/patches/0518-net-hns3-allow-configure-ETS-bandwidth-of-all-TCs.patch
@@ -0,0 +1,76 @@
+From a391ba966923aedcf9caec80df612cacafa5202a Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Thu, 18 Nov 2021 20:45:02 +0800
+Subject: [PATCH 157/283] net: hns3: allow configure ETS bandwidth of all TCs
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit 688db0c7a4a69ddc8b8143a1cac01eb20082a3aa
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EMYT
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=688db0c7a4a69ddc8b8143a1cac01eb20082a3aa
+
+----------------------------------------------------------------------
+
+Currently, driver only allow configuring ETS bandwidth of TCs according
+to the max TC number queried from firmware. However, the hardware actually
+supports 8 TCs and users may need to configure ETS bandwidth of all TCs,
+so remove the restriction.
+
+Fixes: 330baff5423b ("net: hns3: add ETS TC weight setting in SSU module")
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c  | 9 +--------
+ 2 files changed, 2 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+index d748c6404436..428bb7d6ab94 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+@@ -129,7 +129,7 @@ static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev,
+ 	u32 total_ets_bw = 0;
+ 	u8 i;
+ 
+-	for (i = 0; i < hdev->tc_max; i++) {
++	for (i = 0; i < HNAE3_MAX_TC; i++) {
+ 		switch (ets->tc_tsa[i]) {
+ 		case IEEE_8021QAZ_TSA_STRICT:
+ 			if (hdev->tm_info.tc_info[i].tc_sch_mode !=
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index 434e6dfca032..48382bfc84f6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -1057,7 +1057,6 @@ static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
+ 
+ static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
+ {
+-#define DEFAULT_TC_WEIGHT	1
+ #define DEFAULT_TC_OFFSET	14
+ 
+ 	struct hclge_ets_tc_weight_cmd *ets_weight;
+@@ -1070,13 +1069,7 @@ static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
+ 	for (i = 0; i < HNAE3_MAX_TC; i++) {
+ 		struct hclge_pg_info *pg_info;
+ 
+-		ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
+-
+-		if (!(hdev->hw_tc_map & BIT(i)))
+-			continue;
+-
+-		pg_info =
+-			&hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
++		pg_info = &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
+ 		ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
+ 	}
+ 
+-- 
+2.34.1
+
diff --git a/patches/0519-ethtool-move-to-its-own-directory.patch b/patches/0519-ethtool-move-to-its-own-directory.patch
new file mode 100644
index 0000000..6010a56
--- /dev/null
+++ b/patches/0519-ethtool-move-to-its-own-directory.patch
@@ -0,0 +1,76 @@
+From 4f772f16ad4bf23a6daee30f3908133f3d0c3a90 Mon Sep 17 00:00:00 2001
+From: Michal Kubecek <mkubecek@suse.cz>
+Date: Wed, 11 Dec 2019 10:58:24 +0100
+Subject: [PATCH 158/283] ethtool: move to its own directory
+
+mainline inclusion
+from mainline-v5.6-rc1
+commit 9ce48e5a09ea63a7867647af68caa0605d99757d
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9ce48e5a09ea63a7867647af68caa0605d99757d
+
+--------------------------------
+
+The ethtool netlink interface is going to be split into multiple files so
+that it will be more convenient to put all of them in a separate directory
+net/ethtool. Start by moving current ethtool.c with ioctl interface into
+this directory and renaming it to ioctl.c.
+
+Signed-off-by: Michal Kubecek <mkubecek@suse.cz>
+Acked-by: Jiri Pirko <jiri@mellanox.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ net/Makefile                            | 2 +-
+ net/core/Makefile                       | 2 +-
+ net/ethtool/Makefile                    | 3 +++
+ net/{core/ethtool.c => ethtool/ioctl.c} | 0
+ 4 files changed, 5 insertions(+), 2 deletions(-)
+ create mode 100644 net/ethtool/Makefile
+ rename net/{core/ethtool.c => ethtool/ioctl.c} (100%)
+
+diff --git a/net/Makefile b/net/Makefile
+index 177b6fbac29c..77417f82cf3f 100644
+--- a/net/Makefile
++++ b/net/Makefile
+@@ -13,7 +13,7 @@ obj-$(CONFIG_NET)		+= $(tmp-y)
+ 
+ # LLC has to be linked before the files in net/802/
+ obj-$(CONFIG_LLC)		+= llc/
+-obj-$(CONFIG_NET)		+= ethernet/ 802/ sched/ netlink/ bpf/
++obj-$(CONFIG_NET)		+= ethernet/ 802/ sched/ netlink/ bpf/ ethtool/
+ obj-$(CONFIG_NETFILTER)		+= netfilter/
+ obj-$(CONFIG_INET)		+= ipv4/
+ obj-$(CONFIG_TLS)		+= tls/
+diff --git a/net/core/Makefile b/net/core/Makefile
+index 80175e6a2eb8..55734d0a1603 100644
+--- a/net/core/Makefile
++++ b/net/core/Makefile
+@@ -8,7 +8,7 @@ obj-y := sock.o request_sock.o skbuff.o datagram.o stream.o scm.o \
+ 
+ obj-$(CONFIG_SYSCTL) += sysctl_net_core.o
+ 
+-obj-y		     += dev.o ethtool.o dev_addr_lists.o dst.o netevent.o \
++obj-y		     += dev.o dev_addr_lists.o dst.o netevent.o \
+ 			neighbour.o rtnetlink.o utils.o link_watch.o filter.o \
+ 			sock_diag.o dev_ioctl.o tso.o sock_reuseport.o \
+ 			fib_notifier.o xdp.o
+diff --git a/net/ethtool/Makefile b/net/ethtool/Makefile
+new file mode 100644
+index 000000000000..7e5c9eb85c90
+--- /dev/null
++++ b/net/ethtool/Makefile
+@@ -0,0 +1,3 @@
++# SPDX-License-Identifier: GPL-2.0-only
++
++obj-y		+= ioctl.o
+diff --git a/net/core/ethtool.c b/net/ethtool/ioctl.c
+similarity index 100%
+rename from net/core/ethtool.c
+rename to net/ethtool/ioctl.c
+-- 
+2.34.1
+
diff --git a/patches/0520-ethtool-move-string-arrays-into-common-file.patch b/patches/0520-ethtool-move-string-arrays-into-common-file.patch
new file mode 100644
index 0000000..c3cb04f
--- /dev/null
+++ b/patches/0520-ethtool-move-string-arrays-into-common-file.patch
@@ -0,0 +1,276 @@
+From dfcc145529b0a9b787ab4a1293c7b5dd9d3da0fb Mon Sep 17 00:00:00 2001
+From: Michal Kubecek <mkubecek@suse.cz>
+Date: Wed, 11 Dec 2019 10:58:29 +0100
+Subject: [PATCH 159/283] ethtool: move string arrays into common file
+
+mainline inclusion
+from mainline-v5.6-rc1
+commit d44e13108b6da4e1c4778bd654a470208e02ef37
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d44e13108b6da4e1c4778bd654a470208e02ef37
+
+--------------------------------
+
+Introduce file net/ethtool/common.c for code shared by ioctl and netlink
+ethtool interface. Move name tables of features, RSS hash functions,
+tunables and PHY tunables into this file.
+
+Signed-off-by: Michal Kubecek <mkubecek@suse.cz>
+Reviewed-by: Jiri Pirko <jiri@mellanox.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	net/ethtool/ioctl.c
+---
+ include/uapi/linux/ethtool.h |  2 +
+ net/ethtool/Makefile         |  2 +-
+ net/ethtool/common.c         | 85 ++++++++++++++++++++++++++++++++++++
+ net/ethtool/common.h         | 17 ++++++++
+ net/ethtool/ioctl.c          | 82 +---------------------------------
+ 5 files changed, 107 insertions(+), 81 deletions(-)
+ create mode 100644 net/ethtool/common.c
+ create mode 100644 net/ethtool/common.h
+
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index 5985c5a72046..2574ceb9d2f3 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -259,6 +259,8 @@ struct ethtool_tunable {
+ enum phy_tunable_id {
+ 	ETHTOOL_PHY_ID_UNSPEC,
+ 	ETHTOOL_PHY_DOWNSHIFT,
++	ETHTOOL_PHY_FAST_LINK_DOWN,
++	ETHTOOL_PHY_EDPD,
+ 	/*
+ 	 * Add your fresh new phy tunable attribute above and remember to update
+ 	 * phy_tunable_strings[] in net/core/ethtool.c
+diff --git a/net/ethtool/Makefile b/net/ethtool/Makefile
+index 7e5c9eb85c90..f68387618973 100644
+--- a/net/ethtool/Makefile
++++ b/net/ethtool/Makefile
+@@ -1,3 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ 
+-obj-y		+= ioctl.o
++obj-y		+= ioctl.o common.o
+diff --git a/net/ethtool/common.c b/net/ethtool/common.c
+new file mode 100644
+index 000000000000..8b5e11e7e0a6
+--- /dev/null
++++ b/net/ethtool/common.c
+@@ -0,0 +1,85 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include "common.h"
++
++const char netdev_features_strings[NETDEV_FEATURE_COUNT][ETH_GSTRING_LEN] = {
++	[NETIF_F_SG_BIT] =               "tx-scatter-gather",
++	[NETIF_F_IP_CSUM_BIT] =          "tx-checksum-ipv4",
++	[NETIF_F_HW_CSUM_BIT] =          "tx-checksum-ip-generic",
++	[NETIF_F_IPV6_CSUM_BIT] =        "tx-checksum-ipv6",
++	[NETIF_F_HIGHDMA_BIT] =          "highdma",
++	[NETIF_F_FRAGLIST_BIT] =         "tx-scatter-gather-fraglist",
++	[NETIF_F_HW_VLAN_CTAG_TX_BIT] =  "tx-vlan-hw-insert",
++
++	[NETIF_F_HW_VLAN_CTAG_RX_BIT] =  "rx-vlan-hw-parse",
++	[NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
++	[NETIF_F_HW_VLAN_STAG_TX_BIT] =  "tx-vlan-stag-hw-insert",
++	[NETIF_F_HW_VLAN_STAG_RX_BIT] =  "rx-vlan-stag-hw-parse",
++	[NETIF_F_HW_VLAN_STAG_FILTER_BIT] = "rx-vlan-stag-filter",
++	[NETIF_F_VLAN_CHALLENGED_BIT] =  "vlan-challenged",
++	[NETIF_F_GSO_BIT] =              "tx-generic-segmentation",
++	[NETIF_F_LLTX_BIT] =             "tx-lockless",
++	[NETIF_F_NETNS_LOCAL_BIT] =      "netns-local",
++	[NETIF_F_GRO_BIT] =              "rx-gro",
++	[NETIF_F_GRO_HW_BIT] =           "rx-gro-hw",
++	[NETIF_F_LRO_BIT] =              "rx-lro",
++
++	[NETIF_F_TSO_BIT] =              "tx-tcp-segmentation",
++	[NETIF_F_GSO_ROBUST_BIT] =       "tx-gso-robust",
++	[NETIF_F_TSO_ECN_BIT] =          "tx-tcp-ecn-segmentation",
++	[NETIF_F_TSO_MANGLEID_BIT] =	 "tx-tcp-mangleid-segmentation",
++	[NETIF_F_TSO6_BIT] =             "tx-tcp6-segmentation",
++	[NETIF_F_FSO_BIT] =              "tx-fcoe-segmentation",
++	[NETIF_F_GSO_GRE_BIT] =		 "tx-gre-segmentation",
++	[NETIF_F_GSO_GRE_CSUM_BIT] =	 "tx-gre-csum-segmentation",
++	[NETIF_F_GSO_IPXIP4_BIT] =	 "tx-ipxip4-segmentation",
++	[NETIF_F_GSO_IPXIP6_BIT] =	 "tx-ipxip6-segmentation",
++	[NETIF_F_GSO_UDP_TUNNEL_BIT] =	 "tx-udp_tnl-segmentation",
++	[NETIF_F_GSO_UDP_TUNNEL_CSUM_BIT] = "tx-udp_tnl-csum-segmentation",
++	[NETIF_F_GSO_PARTIAL_BIT] =	 "tx-gso-partial",
++	[NETIF_F_GSO_SCTP_BIT] =	 "tx-sctp-segmentation",
++	[NETIF_F_GSO_ESP_BIT] =		 "tx-esp-segmentation",
++	[NETIF_F_GSO_UDP_L4_BIT] =	 "tx-udp-segmentation",
++
++	[NETIF_F_FCOE_CRC_BIT] =         "tx-checksum-fcoe-crc",
++	[NETIF_F_SCTP_CRC_BIT] =        "tx-checksum-sctp",
++	[NETIF_F_FCOE_MTU_BIT] =         "fcoe-mtu",
++	[NETIF_F_NTUPLE_BIT] =           "rx-ntuple-filter",
++	[NETIF_F_RXHASH_BIT] =           "rx-hashing",
++	[NETIF_F_RXCSUM_BIT] =           "rx-checksum",
++	[NETIF_F_NOCACHE_COPY_BIT] =     "tx-nocache-copy",
++	[NETIF_F_LOOPBACK_BIT] =         "loopback",
++	[NETIF_F_RXFCS_BIT] =            "rx-fcs",
++	[NETIF_F_RXALL_BIT] =            "rx-all",
++	[NETIF_F_HW_L2FW_DOFFLOAD_BIT] = "l2-fwd-offload",
++	[NETIF_F_HW_TC_BIT] =		 "hw-tc-offload",
++	[NETIF_F_HW_ESP_BIT] =		 "esp-hw-offload",
++	[NETIF_F_HW_ESP_TX_CSUM_BIT] =	 "esp-tx-csum-hw-offload",
++	[NETIF_F_RX_UDP_TUNNEL_PORT_BIT] =	 "rx-udp_tunnel-port-offload",
++	[NETIF_F_HW_TLS_RECORD_BIT] =	"tls-hw-record",
++	[NETIF_F_HW_TLS_TX_BIT] =	 "tls-hw-tx-offload",
++	[NETIF_F_HW_TLS_RX_BIT] =	 "tls-hw-rx-offload",
++};
++
++const char
++rss_hash_func_strings[ETH_RSS_HASH_FUNCS_COUNT][ETH_GSTRING_LEN] = {
++	[ETH_RSS_HASH_TOP_BIT] =	"toeplitz",
++	[ETH_RSS_HASH_XOR_BIT] =	"xor",
++	[ETH_RSS_HASH_CRC32_BIT] =	"crc32",
++};
++
++const char
++tunable_strings[__ETHTOOL_TUNABLE_COUNT][ETH_GSTRING_LEN] = {
++	[ETHTOOL_ID_UNSPEC]     = "Unspec",
++	[ETHTOOL_RX_COPYBREAK]	= "rx-copybreak",
++	[ETHTOOL_TX_COPYBREAK]	= "tx-copybreak",
++	[ETHTOOL_PFC_PREVENTION_TOUT] = "pfc-prevention-tout",
++};
++
++const char
++phy_tunable_strings[__ETHTOOL_PHY_TUNABLE_COUNT][ETH_GSTRING_LEN] = {
++	[ETHTOOL_ID_UNSPEC]     = "Unspec",
++	[ETHTOOL_PHY_DOWNSHIFT]	= "phy-downshift",
++	[ETHTOOL_PHY_FAST_LINK_DOWN] = "phy-fast-link-down",
++	[ETHTOOL_PHY_EDPD]	= "phy-energy-detect-power-down",
++};
+diff --git a/net/ethtool/common.h b/net/ethtool/common.h
+new file mode 100644
+index 000000000000..336566430be4
+--- /dev/null
++++ b/net/ethtool/common.h
+@@ -0,0 +1,17 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef _ETHTOOL_COMMON_H
++#define _ETHTOOL_COMMON_H
++
++#include <linux/ethtool.h>
++
++extern const char
++netdev_features_strings[NETDEV_FEATURE_COUNT][ETH_GSTRING_LEN];
++extern const char
++rss_hash_func_strings[ETH_RSS_HASH_FUNCS_COUNT][ETH_GSTRING_LEN];
++extern const char
++tunable_strings[__ETHTOOL_TUNABLE_COUNT][ETH_GSTRING_LEN];
++extern const char
++phy_tunable_strings[__ETHTOOL_PHY_TUNABLE_COUNT][ETH_GSTRING_LEN];
++
++#endif /* _ETHTOOL_COMMON_H */
+diff --git a/net/ethtool/ioctl.c b/net/ethtool/ioctl.c
+index 4db9512feba8..fab4dae2da1b 100644
+--- a/net/ethtool/ioctl.c
++++ b/net/ethtool/ioctl.c
+@@ -28,6 +28,8 @@
+ #include <linux/sched/signal.h>
+ #include <linux/net.h>
+ 
++#include "common.h"
++
+ /*
+  * Some useful ethtool_ops methods that're device independent.
+  * If we find that all drivers want to do the same thing here,
+@@ -55,86 +57,6 @@ EXPORT_SYMBOL(ethtool_op_get_ts_info);
+ 
+ #define ETHTOOL_DEV_FEATURE_WORDS	((NETDEV_FEATURE_COUNT + 31) / 32)
+ 
+-static const char netdev_features_strings[NETDEV_FEATURE_COUNT][ETH_GSTRING_LEN] = {
+-	[NETIF_F_SG_BIT] =               "tx-scatter-gather",
+-	[NETIF_F_IP_CSUM_BIT] =          "tx-checksum-ipv4",
+-	[NETIF_F_HW_CSUM_BIT] =          "tx-checksum-ip-generic",
+-	[NETIF_F_IPV6_CSUM_BIT] =        "tx-checksum-ipv6",
+-	[NETIF_F_HIGHDMA_BIT] =          "highdma",
+-	[NETIF_F_FRAGLIST_BIT] =         "tx-scatter-gather-fraglist",
+-	[NETIF_F_HW_VLAN_CTAG_TX_BIT] =  "tx-vlan-hw-insert",
+-
+-	[NETIF_F_HW_VLAN_CTAG_RX_BIT] =  "rx-vlan-hw-parse",
+-	[NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
+-	[NETIF_F_HW_VLAN_STAG_TX_BIT] =  "tx-vlan-stag-hw-insert",
+-	[NETIF_F_HW_VLAN_STAG_RX_BIT] =  "rx-vlan-stag-hw-parse",
+-	[NETIF_F_HW_VLAN_STAG_FILTER_BIT] = "rx-vlan-stag-filter",
+-	[NETIF_F_VLAN_CHALLENGED_BIT] =  "vlan-challenged",
+-	[NETIF_F_GSO_BIT] =              "tx-generic-segmentation",
+-	[NETIF_F_LLTX_BIT] =             "tx-lockless",
+-	[NETIF_F_NETNS_LOCAL_BIT] =      "netns-local",
+-	[NETIF_F_GRO_BIT] =              "rx-gro",
+-	[NETIF_F_GRO_HW_BIT] =           "rx-gro-hw",
+-	[NETIF_F_LRO_BIT] =              "rx-lro",
+-
+-	[NETIF_F_TSO_BIT] =              "tx-tcp-segmentation",
+-	[NETIF_F_GSO_ROBUST_BIT] =       "tx-gso-robust",
+-	[NETIF_F_TSO_ECN_BIT] =          "tx-tcp-ecn-segmentation",
+-	[NETIF_F_TSO_MANGLEID_BIT] =	 "tx-tcp-mangleid-segmentation",
+-	[NETIF_F_TSO6_BIT] =             "tx-tcp6-segmentation",
+-	[NETIF_F_FSO_BIT] =              "tx-fcoe-segmentation",
+-	[NETIF_F_GSO_GRE_BIT] =		 "tx-gre-segmentation",
+-	[NETIF_F_GSO_GRE_CSUM_BIT] =	 "tx-gre-csum-segmentation",
+-	[NETIF_F_GSO_IPXIP4_BIT] =	 "tx-ipxip4-segmentation",
+-	[NETIF_F_GSO_IPXIP6_BIT] =	 "tx-ipxip6-segmentation",
+-	[NETIF_F_GSO_UDP_TUNNEL_BIT] =	 "tx-udp_tnl-segmentation",
+-	[NETIF_F_GSO_UDP_TUNNEL_CSUM_BIT] = "tx-udp_tnl-csum-segmentation",
+-	[NETIF_F_GSO_PARTIAL_BIT] =	 "tx-gso-partial",
+-	[NETIF_F_GSO_SCTP_BIT] =	 "tx-sctp-segmentation",
+-	[NETIF_F_GSO_ESP_BIT] =		 "tx-esp-segmentation",
+-	[NETIF_F_GSO_UDP_L4_BIT] =	 "tx-udp-segmentation",
+-
+-	[NETIF_F_FCOE_CRC_BIT] =         "tx-checksum-fcoe-crc",
+-	[NETIF_F_SCTP_CRC_BIT] =        "tx-checksum-sctp",
+-	[NETIF_F_FCOE_MTU_BIT] =         "fcoe-mtu",
+-	[NETIF_F_NTUPLE_BIT] =           "rx-ntuple-filter",
+-	[NETIF_F_RXHASH_BIT] =           "rx-hashing",
+-	[NETIF_F_RXCSUM_BIT] =           "rx-checksum",
+-	[NETIF_F_NOCACHE_COPY_BIT] =     "tx-nocache-copy",
+-	[NETIF_F_LOOPBACK_BIT] =         "loopback",
+-	[NETIF_F_RXFCS_BIT] =            "rx-fcs",
+-	[NETIF_F_RXALL_BIT] =            "rx-all",
+-	[NETIF_F_HW_L2FW_DOFFLOAD_BIT] = "l2-fwd-offload",
+-	[NETIF_F_HW_TC_BIT] =		 "hw-tc-offload",
+-	[NETIF_F_HW_ESP_BIT] =		 "esp-hw-offload",
+-	[NETIF_F_HW_ESP_TX_CSUM_BIT] =	 "esp-tx-csum-hw-offload",
+-	[NETIF_F_RX_UDP_TUNNEL_PORT_BIT] =	 "rx-udp_tunnel-port-offload",
+-	[NETIF_F_HW_TLS_RECORD_BIT] =	"tls-hw-record",
+-	[NETIF_F_HW_TLS_TX_BIT] =	 "tls-hw-tx-offload",
+-	[NETIF_F_HW_TLS_RX_BIT] =	 "tls-hw-rx-offload",
+-};
+-
+-static const char
+-rss_hash_func_strings[ETH_RSS_HASH_FUNCS_COUNT][ETH_GSTRING_LEN] = {
+-	[ETH_RSS_HASH_TOP_BIT] =	"toeplitz",
+-	[ETH_RSS_HASH_XOR_BIT] =	"xor",
+-	[ETH_RSS_HASH_CRC32_BIT] =	"crc32",
+-};
+-
+-static const char
+-tunable_strings[__ETHTOOL_TUNABLE_COUNT][ETH_GSTRING_LEN] = {
+-	[ETHTOOL_ID_UNSPEC]     = "Unspec",
+-	[ETHTOOL_RX_COPYBREAK]	= "rx-copybreak",
+-	[ETHTOOL_TX_COPYBREAK]	= "tx-copybreak",
+-	[ETHTOOL_PFC_PREVENTION_TOUT] = "pfc-prevention-tout",
+-};
+-
+-static const char
+-phy_tunable_strings[__ETHTOOL_PHY_TUNABLE_COUNT][ETH_GSTRING_LEN] = {
+-	[ETHTOOL_ID_UNSPEC]     = "Unspec",
+-	[ETHTOOL_PHY_DOWNSHIFT]	= "phy-downshift",
+-};
+-
+ static int ethtool_get_features(struct net_device *dev, void __user *useraddr)
+ {
+ 	struct ethtool_gfeatures cmd = {
+-- 
+2.34.1
+
diff --git a/patches/0521-ethtool-provide-link-mode-names-as-a-string-set.patch b/patches/0521-ethtool-provide-link-mode-names-as-a-string-set.patch
new file mode 100644
index 0000000..3c0dbaf
--- /dev/null
+++ b/patches/0521-ethtool-provide-link-mode-names-as-a-string-set.patch
@@ -0,0 +1,213 @@
+From 95d8a3ff2989fc3b83d349b8b2ba6083f1224e79 Mon Sep 17 00:00:00 2001
+From: Michal Kubecek <mkubecek@suse.cz>
+Date: Wed, 11 Dec 2019 10:58:34 +0100
+Subject: [PATCH 160/283] ethtool: provide link mode names as a string set
+
+mainline inclusion
+from mainline-v5.6-rc1
+commit 428c122f5f6b54f40bd51c47495104b534b5a57c
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=428c122f5f6b54f40bd51c47495104b534b5a57c
+
+--------------------------------
+
+Unlike e.g. netdev features, the ethtool ioctl interface requires link mode
+table to be in sync between kernel and userspace for userspace to be able
+to display and set all link modes supported by kernel. The way arbitrary
+length bitsets are implemented in netlink interface, this will be no longer
+needed.
+
+To allow userspace to access all link modes running kernel supports, add
+table of ethernet link mode names and make it available as a string set to
+userspace GET_STRSET requests. Add build time check to make sure names
+are defined for all modes declared in enum ethtool_link_mode_bit_indices.
+
+Once the string set is available, make it also accessible via ioctl.
+
+Signed-off-by: Michal Kubecek <mkubecek@suse.cz>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Jiri Pirko <jiri@mellanox.com>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ include/uapi/linux/ethtool.h |  4 +-
+ net/ethtool/common.c         | 86 ++++++++++++++++++++++++++++++++++++
+ net/ethtool/common.h         |  5 +++
+ net/ethtool/ioctl.c          |  6 +++
+ 4 files changed, 100 insertions(+), 1 deletion(-)
+
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index 2574ceb9d2f3..e519138e2a38 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -641,6 +641,7 @@ enum ethtool_link_ext_substate_cable_issue {
+  * @ETH_SS_RSS_HASH_FUNCS: RSS hush function names
+  * @ETH_SS_PHY_STATS: Statistic names, for use with %ETHTOOL_GPHYSTATS
+  * @ETH_SS_PHY_TUNABLES: PHY tunable names
++ * @ETH_SS_LINK_MODES: link mode names
+  */
+ enum ethtool_stringset {
+ 	ETH_SS_TEST		= 0,
+@@ -652,6 +653,7 @@ enum ethtool_stringset {
+ 	ETH_SS_TUNABLES,
+ 	ETH_SS_PHY_STATS,
+ 	ETH_SS_PHY_TUNABLES,
++	ETH_SS_LINK_MODES,
+ };
+ 
+ /**
+@@ -1576,7 +1578,7 @@ enum ethtool_link_mode_bit_indices {
+ 	 * macro for bits > 31. The only way to use indices > 31 is to
+ 	 * use the new ETHTOOL_GLINKSETTINGS/ETHTOOL_SLINKSETTINGS API.
+ 	 */
+-
++	__ETHTOOL_LINK_MODE_MASK_NBITS,
+ 	__ETHTOOL_LINK_MODE_LAST
+ 	  = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
+ };
+diff --git a/net/ethtool/common.c b/net/ethtool/common.c
+index 8b5e11e7e0a6..11a12af88165 100644
+--- a/net/ethtool/common.c
++++ b/net/ethtool/common.c
+@@ -83,3 +83,89 @@ phy_tunable_strings[__ETHTOOL_PHY_TUNABLE_COUNT][ETH_GSTRING_LEN] = {
+ 	[ETHTOOL_PHY_FAST_LINK_DOWN] = "phy-fast-link-down",
+ 	[ETHTOOL_PHY_EDPD]	= "phy-energy-detect-power-down",
+ };
++
++#define __LINK_MODE_NAME(speed, type, duplex) \
++	(#speed "base" #type "/" #duplex)
++#define __DEFINE_LINK_MODE_NAME(speed, type, duplex) \
++	[ETHTOOL_LINK_MODE(speed, type, duplex)] = \
++	__LINK_MODE_NAME(speed, type, duplex)
++#define __DEFINE_SPECIAL_MODE_NAME(_mode, _name) \
++	[ETHTOOL_LINK_MODE_ ## _mode ## _BIT] = _name
++
++const char link_mode_names[][ETH_GSTRING_LEN] = {
++	__DEFINE_LINK_MODE_NAME(10, T, Half),
++	__DEFINE_LINK_MODE_NAME(10, T, Full),
++	__DEFINE_LINK_MODE_NAME(100, T, Half),
++	__DEFINE_LINK_MODE_NAME(100, T, Full),
++	__DEFINE_LINK_MODE_NAME(1000, T, Half),
++	__DEFINE_LINK_MODE_NAME(1000, T, Full),
++	__DEFINE_SPECIAL_MODE_NAME(Autoneg, "Autoneg"),
++	__DEFINE_SPECIAL_MODE_NAME(TP, "TP"),
++	__DEFINE_SPECIAL_MODE_NAME(AUI, "AUI"),
++	__DEFINE_SPECIAL_MODE_NAME(MII, "MII"),
++	__DEFINE_SPECIAL_MODE_NAME(FIBRE, "FIBRE"),
++	__DEFINE_SPECIAL_MODE_NAME(BNC, "BNC"),
++	__DEFINE_LINK_MODE_NAME(10000, T, Full),
++	__DEFINE_SPECIAL_MODE_NAME(Pause, "Pause"),
++	__DEFINE_SPECIAL_MODE_NAME(Asym_Pause, "Asym_Pause"),
++	__DEFINE_LINK_MODE_NAME(2500, X, Full),
++	__DEFINE_SPECIAL_MODE_NAME(Backplane, "Backplane"),
++	__DEFINE_LINK_MODE_NAME(1000, KX, Full),
++	__DEFINE_LINK_MODE_NAME(10000, KX4, Full),
++	__DEFINE_LINK_MODE_NAME(10000, KR, Full),
++	__DEFINE_SPECIAL_MODE_NAME(10000baseR_FEC, "10000baseR_FEC"),
++	__DEFINE_LINK_MODE_NAME(20000, MLD2, Full),
++	__DEFINE_LINK_MODE_NAME(20000, KR2, Full),
++	__DEFINE_LINK_MODE_NAME(40000, KR4, Full),
++	__DEFINE_LINK_MODE_NAME(40000, CR4, Full),
++	__DEFINE_LINK_MODE_NAME(40000, SR4, Full),
++	__DEFINE_LINK_MODE_NAME(40000, LR4, Full),
++	__DEFINE_LINK_MODE_NAME(56000, KR4, Full),
++	__DEFINE_LINK_MODE_NAME(56000, CR4, Full),
++	__DEFINE_LINK_MODE_NAME(56000, SR4, Full),
++	__DEFINE_LINK_MODE_NAME(56000, LR4, Full),
++	__DEFINE_LINK_MODE_NAME(25000, CR, Full),
++	__DEFINE_LINK_MODE_NAME(25000, KR, Full),
++	__DEFINE_LINK_MODE_NAME(25000, SR, Full),
++	__DEFINE_LINK_MODE_NAME(50000, CR2, Full),
++	__DEFINE_LINK_MODE_NAME(50000, KR2, Full),
++	__DEFINE_LINK_MODE_NAME(100000, KR4, Full),
++	__DEFINE_LINK_MODE_NAME(100000, SR4, Full),
++	__DEFINE_LINK_MODE_NAME(100000, CR4, Full),
++	__DEFINE_LINK_MODE_NAME(100000, LR4_ER4, Full),
++	__DEFINE_LINK_MODE_NAME(50000, SR2, Full),
++	__DEFINE_LINK_MODE_NAME(1000, X, Full),
++	__DEFINE_LINK_MODE_NAME(10000, CR, Full),
++	__DEFINE_LINK_MODE_NAME(10000, SR, Full),
++	__DEFINE_LINK_MODE_NAME(10000, LR, Full),
++	__DEFINE_LINK_MODE_NAME(10000, LRM, Full),
++	__DEFINE_LINK_MODE_NAME(10000, ER, Full),
++	__DEFINE_LINK_MODE_NAME(2500, T, Full),
++	__DEFINE_LINK_MODE_NAME(5000, T, Full),
++	__DEFINE_SPECIAL_MODE_NAME(FEC_NONE, "None"),
++	__DEFINE_SPECIAL_MODE_NAME(FEC_RS, "RS"),
++	__DEFINE_SPECIAL_MODE_NAME(FEC_BASER, "BASER"),
++	__DEFINE_LINK_MODE_NAME(50000, KR, Full),
++	__DEFINE_LINK_MODE_NAME(50000, SR, Full),
++	__DEFINE_LINK_MODE_NAME(50000, CR, Full),
++	__DEFINE_LINK_MODE_NAME(50000, LR_ER_FR, Full),
++	__DEFINE_LINK_MODE_NAME(50000, DR, Full),
++	__DEFINE_LINK_MODE_NAME(100000, KR2, Full),
++	__DEFINE_LINK_MODE_NAME(100000, SR2, Full),
++	__DEFINE_LINK_MODE_NAME(100000, CR2, Full),
++	__DEFINE_LINK_MODE_NAME(100000, LR2_ER2_FR2, Full),
++	__DEFINE_LINK_MODE_NAME(100000, DR2, Full),
++	__DEFINE_LINK_MODE_NAME(200000, KR4, Full),
++	__DEFINE_LINK_MODE_NAME(200000, SR4, Full),
++	__DEFINE_LINK_MODE_NAME(200000, LR4_ER4_FR4, Full),
++	__DEFINE_LINK_MODE_NAME(200000, DR4, Full),
++	__DEFINE_LINK_MODE_NAME(200000, CR4, Full),
++	__DEFINE_LINK_MODE_NAME(100, T1, Full),
++	__DEFINE_LINK_MODE_NAME(1000, T1, Full),
++	__DEFINE_LINK_MODE_NAME(400000, KR8, Full),
++	__DEFINE_LINK_MODE_NAME(400000, SR8, Full),
++	__DEFINE_LINK_MODE_NAME(400000, LR8_ER8_FR8, Full),
++	__DEFINE_LINK_MODE_NAME(400000, DR8, Full),
++	__DEFINE_LINK_MODE_NAME(400000, CR8, Full),
++};
++static_assert(ARRAY_SIZE(link_mode_names) == ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
+diff --git a/net/ethtool/common.h b/net/ethtool/common.h
+index 336566430be4..bbb788908cb1 100644
+--- a/net/ethtool/common.h
++++ b/net/ethtool/common.h
+@@ -5,6 +5,10 @@
+ 
+ #include <linux/ethtool.h>
+ 
++/* compose link mode index from speed, type and duplex */
++#define ETHTOOL_LINK_MODE(speed, type, duplex) \
++	ETHTOOL_LINK_MODE_ ## speed ## base ## type ## _ ## duplex ## _BIT
++
+ extern const char
+ netdev_features_strings[NETDEV_FEATURE_COUNT][ETH_GSTRING_LEN];
+ extern const char
+@@ -13,5 +17,6 @@ extern const char
+ tunable_strings[__ETHTOOL_TUNABLE_COUNT][ETH_GSTRING_LEN];
+ extern const char
+ phy_tunable_strings[__ETHTOOL_PHY_TUNABLE_COUNT][ETH_GSTRING_LEN];
++extern const char link_mode_names[][ETH_GSTRING_LEN];
+ 
+ #endif /* _ETHTOOL_COMMON_H */
+diff --git a/net/ethtool/ioctl.c b/net/ethtool/ioctl.c
+index fab4dae2da1b..7799062c2b97 100644
+--- a/net/ethtool/ioctl.c
++++ b/net/ethtool/ioctl.c
+@@ -155,6 +155,9 @@ static int __ethtool_get_sset_count(struct net_device *dev, int sset)
+ 	    !ops->get_ethtool_phy_stats)
+ 		return phy_ethtool_get_sset_count(dev->phydev);
+ 
++	if (sset == ETH_SS_LINK_MODES)
++		return __ETHTOOL_LINK_MODE_MASK_NBITS;
++
+ 	if (ops->get_sset_count && ops->get_strings)
+ 		return ops->get_sset_count(dev, sset);
+ 	else
+@@ -179,6 +182,9 @@ static void __ethtool_get_strings(struct net_device *dev,
+ 	else if (stringset == ETH_SS_PHY_STATS && dev->phydev &&
+ 		 !ops->get_ethtool_phy_stats)
+ 		phy_ethtool_get_strings(dev->phydev, data);
++	else if (stringset == ETH_SS_LINK_MODES)
++		memcpy(data, link_mode_names,
++		       __ETHTOOL_LINK_MODE_MASK_NBITS * ETH_GSTRING_LEN);
+ 	else
+ 		/* ops->get_strings is valid because checked earlier */
+ 		ops->get_strings(dev, stringset, data);
+-- 
+2.34.1
+
diff --git a/patches/0522-ethtool-introduce-ethtool-netlink-interface.patch b/patches/0522-ethtool-introduce-ethtool-netlink-interface.patch
new file mode 100644
index 0000000..8c6991a
--- /dev/null
+++ b/patches/0522-ethtool-introduce-ethtool-netlink-interface.patch
@@ -0,0 +1,1471 @@
+From a8224734c8ab1eb2efe3a410165fb8d0ef4055e2 Mon Sep 17 00:00:00 2001
+From: Michal Kubecek <mkubecek@suse.cz>
+Date: Fri, 27 Dec 2019 15:55:18 +0100
+Subject: [PATCH 161/283] ethtool: introduce ethtool netlink interface
+
+mainline inclusion
+from mainline-v5.6-rc1
+commit 2b4a8990b7df55875745a80a609a1ceaaf51f322
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2b4a8990b7df55875745a80a609a1ceaaf51f322
+
+--------------------------------
+
+Basic genetlink and init infrastructure for the netlink interface, register
+genetlink family "ethtool". Add CONFIG_ETHTOOL_NETLINK Kconfig option to
+make the build optional. Add initial overall interface description into
+Documentation/networking/ethtool-netlink.rst, further patches will add more
+detailed information.
+
+Signed-off-by: Michal Kubecek <mkubecek@suse.cz>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	Documentation/networking/ethtool-netlink.rst
+	Documentation/networking/index.rst
+---
+ Documentation/networking/ethtool-netlink.rst | 1177 +-----------------
+ Documentation/networking/index.rst           |   10 +-
+ include/linux/ethtool_netlink.h              |    9 +
+ include/uapi/linux/ethtool_netlink.h         |   36 +
+ net/Kconfig                                  |    8 +
+ net/ethtool/Makefile                         |    6 +-
+ net/ethtool/netlink.c                        |   33 +
+ net/ethtool/netlink.h                        |   10 +
+ 8 files changed, 152 insertions(+), 1137 deletions(-)
+ create mode 100644 include/linux/ethtool_netlink.h
+ create mode 100644 include/uapi/linux/ethtool_netlink.h
+ create mode 100644 net/ethtool/netlink.c
+ create mode 100644 net/ethtool/netlink.h
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+index f7b88ee9227d..fc550a3e82b1 100644
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -68,7 +68,6 @@ the flags may not apply to requests. Recognized flags are:
+   =================================  ===================================
+   ``ETHTOOL_FLAG_COMPACT_BITSETS``   use compact format bitsets in reply
+   ``ETHTOOL_FLAG_OMIT_REPLY``        omit optional reply (_SET and _ACT)
+-  ``ETHTOOL_FLAG_STATS``             include optional device statistics
+   =================================  ===================================
+ 
+ New request flags should follow the general idea that if the flag is not set,
+@@ -77,8 +76,6 @@ of the flag should be interpreted the way the client expects. A client must
+ not set flags it does not understand.
+ 
+ 
+-Bit sets
+-========
+ 
+ For short bitmaps of (reasonably) fixed length, standard ``NLA_BITFIELD32``
+ type is used. For arbitrary length bitmaps, ethtool netlink uses a nested
+@@ -161,6 +158,7 @@ determined by ``ETHTOOL_FLAG_COMPACT_BITSETS`` flag in flags field of request
+ header. Semantics of value and mask depends on the attribute.
+ 
+ 
++=======
+ List of message types
+ =====================
+ 
+@@ -177,73 +175,6 @@ according to message purpose:
+   ``_NTF``          kernel notification
+   ==============    ======================================
+ 
+-Userspace to kernel:
+-
+-  ===================================== ================================
+-  ``ETHTOOL_MSG_STRSET_GET``            get string set
+-  ``ETHTOOL_MSG_LINKINFO_GET``          get link settings
+-  ``ETHTOOL_MSG_LINKINFO_SET``          set link settings
+-  ``ETHTOOL_MSG_LINKMODES_GET``         get link modes info
+-  ``ETHTOOL_MSG_LINKMODES_SET``         set link modes info
+-  ``ETHTOOL_MSG_LINKSTATE_GET``         get link state
+-  ``ETHTOOL_MSG_DEBUG_GET``             get debugging settings
+-  ``ETHTOOL_MSG_DEBUG_SET``             set debugging settings
+-  ``ETHTOOL_MSG_WOL_GET``               get wake-on-lan settings
+-  ``ETHTOOL_MSG_WOL_SET``               set wake-on-lan settings
+-  ``ETHTOOL_MSG_FEATURES_GET``          get device features
+-  ``ETHTOOL_MSG_FEATURES_SET``          set device features
+-  ``ETHTOOL_MSG_PRIVFLAGS_GET``         get private flags
+-  ``ETHTOOL_MSG_PRIVFLAGS_SET``         set private flags
+-  ``ETHTOOL_MSG_RINGS_GET``             get ring sizes
+-  ``ETHTOOL_MSG_RINGS_SET``             set ring sizes
+-  ``ETHTOOL_MSG_CHANNELS_GET``          get channel counts
+-  ``ETHTOOL_MSG_CHANNELS_SET``          set channel counts
+-  ``ETHTOOL_MSG_COALESCE_GET``          get coalescing parameters
+-  ``ETHTOOL_MSG_COALESCE_SET``          set coalescing parameters
+-  ``ETHTOOL_MSG_PAUSE_GET``             get pause parameters
+-  ``ETHTOOL_MSG_PAUSE_SET``             set pause parameters
+-  ``ETHTOOL_MSG_EEE_GET``               get EEE settings
+-  ``ETHTOOL_MSG_EEE_SET``               set EEE settings
+-  ``ETHTOOL_MSG_TSINFO_GET``		get timestamping info
+-  ``ETHTOOL_MSG_CABLE_TEST_ACT``        action start cable test
+-  ``ETHTOOL_MSG_CABLE_TEST_TDR_ACT``    action start raw TDR cable test
+-  ``ETHTOOL_MSG_TUNNEL_INFO_GET``       get tunnel offload info
+-  ===================================== ================================
+-
+-Kernel to userspace:
+-
+-  ===================================== =================================
+-  ``ETHTOOL_MSG_STRSET_GET_REPLY``      string set contents
+-  ``ETHTOOL_MSG_LINKINFO_GET_REPLY``    link settings
+-  ``ETHTOOL_MSG_LINKINFO_NTF``          link settings notification
+-  ``ETHTOOL_MSG_LINKMODES_GET_REPLY``   link modes info
+-  ``ETHTOOL_MSG_LINKMODES_NTF``         link modes notification
+-  ``ETHTOOL_MSG_LINKSTATE_GET_REPLY``   link state info
+-  ``ETHTOOL_MSG_DEBUG_GET_REPLY``       debugging settings
+-  ``ETHTOOL_MSG_DEBUG_NTF``             debugging settings notification
+-  ``ETHTOOL_MSG_WOL_GET_REPLY``         wake-on-lan settings
+-  ``ETHTOOL_MSG_WOL_NTF``               wake-on-lan settings notification
+-  ``ETHTOOL_MSG_FEATURES_GET_REPLY``    device features
+-  ``ETHTOOL_MSG_FEATURES_SET_REPLY``    optional reply to FEATURES_SET
+-  ``ETHTOOL_MSG_FEATURES_NTF``          netdev features notification
+-  ``ETHTOOL_MSG_PRIVFLAGS_GET_REPLY``   private flags
+-  ``ETHTOOL_MSG_PRIVFLAGS_NTF``         private flags
+-  ``ETHTOOL_MSG_RINGS_GET_REPLY``       ring sizes
+-  ``ETHTOOL_MSG_RINGS_NTF``             ring sizes
+-  ``ETHTOOL_MSG_CHANNELS_GET_REPLY``    channel counts
+-  ``ETHTOOL_MSG_CHANNELS_NTF``          channel counts
+-  ``ETHTOOL_MSG_COALESCE_GET_REPLY``    coalescing parameters
+-  ``ETHTOOL_MSG_COALESCE_NTF``          coalescing parameters
+-  ``ETHTOOL_MSG_PAUSE_GET_REPLY``       pause parameters
+-  ``ETHTOOL_MSG_PAUSE_NTF``             pause parameters
+-  ``ETHTOOL_MSG_EEE_GET_REPLY``         EEE settings
+-  ``ETHTOOL_MSG_EEE_NTF``               EEE settings
+-  ``ETHTOOL_MSG_TSINFO_GET_REPLY``	timestamping info
+-  ``ETHTOOL_MSG_CABLE_TEST_NTF``        Cable test results
+-  ``ETHTOOL_MSG_CABLE_TEST_TDR_NTF``    Cable test TDR results
+-  ``ETHTOOL_MSG_TUNNEL_INFO_GET_REPLY`` tunnel offload info
+-  ===================================== =================================
+-
+ ``GET`` requests are sent by userspace applications to retrieve device
+ information. They usually do not contain any message specific attributes.
+ Kernel replies with corresponding "GET_REPLY" message. For most types, ``GET``
+@@ -275,1074 +206,59 @@ an ``ACT_REPLY`` message. Performing an action also triggers a notification
+ Later sections describe the format and semantics of these messages.
+ 
+ 
+-STRSET_GET
+-==========
+-
+-Requests contents of a string set as provided by ioctl commands
+-``ETHTOOL_GSSET_INFO`` and ``ETHTOOL_GSTRINGS.`` String sets are not user
+-writeable so that the corresponding ``STRSET_SET`` message is only used in
+-kernel replies. There are two types of string sets: global (independent of
+-a device, e.g. device feature names) and device specific (e.g. device private
+-flags).
+-
+-Request contents:
+-
+- +---------------------------------------+--------+------------------------+
+- | ``ETHTOOL_A_STRSET_HEADER``           | nested | request header         |
+- +---------------------------------------+--------+------------------------+
+- | ``ETHTOOL_A_STRSET_STRINGSETS``       | nested | string set to request  |
+- +-+-------------------------------------+--------+------------------------+
+- | | ``ETHTOOL_A_STRINGSETS_STRINGSET+`` | nested | one string set         |
+- +-+-+-----------------------------------+--------+------------------------+
+- | | | ``ETHTOOL_A_STRINGSET_ID``        | u32    | set id                 |
+- +-+-+-----------------------------------+--------+------------------------+
+-
+-Kernel response contents:
+-
+- +---------------------------------------+--------+-----------------------+
+- | ``ETHTOOL_A_STRSET_HEADER``           | nested | reply header          |
+- +---------------------------------------+--------+-----------------------+
+- | ``ETHTOOL_A_STRSET_STRINGSETS``       | nested | array of string sets  |
+- +-+-------------------------------------+--------+-----------------------+
+- | | ``ETHTOOL_A_STRINGSETS_STRINGSET+`` | nested | one string set        |
+- +-+-+-----------------------------------+--------+-----------------------+
+- | | | ``ETHTOOL_A_STRINGSET_ID``        | u32    | set id                |
+- +-+-+-----------------------------------+--------+-----------------------+
+- | | | ``ETHTOOL_A_STRINGSET_COUNT``     | u32    | number of strings     |
+- +-+-+-----------------------------------+--------+-----------------------+
+- | | | ``ETHTOOL_A_STRINGSET_STRINGS``   | nested | array of strings      |
+- +-+-+-+---------------------------------+--------+-----------------------+
+- | | | | ``ETHTOOL_A_STRINGS_STRING+``   | nested | one string            |
+- +-+-+-+-+-------------------------------+--------+-----------------------+
+- | | | | | ``ETHTOOL_A_STRING_INDEX``    | u32    | string index          |
+- +-+-+-+-+-------------------------------+--------+-----------------------+
+- | | | | | ``ETHTOOL_A_STRING_VALUE``    | string | string value          |
+- +-+-+-+-+-------------------------------+--------+-----------------------+
+- | ``ETHTOOL_A_STRSET_COUNTS_ONLY``      | flag   | return only counts    |
+- +---------------------------------------+--------+-----------------------+
+-
+-Device identification in request header is optional. Depending on its presence
+-a and ``NLM_F_DUMP`` flag, there are three type of ``STRSET_GET`` requests:
+-
+- - no ``NLM_F_DUMP,`` no device: get "global" stringsets
+- - no ``NLM_F_DUMP``, with device: get string sets related to the device
+- - ``NLM_F_DUMP``, no device: get device related string sets for all devices
+-
+-If there is no ``ETHTOOL_A_STRSET_STRINGSETS`` array, all string sets of
+-requested type are returned, otherwise only those specified in the request.
+-Flag ``ETHTOOL_A_STRSET_COUNTS_ONLY`` tells kernel to only return string
+-counts of the sets, not the actual strings.
+-
+-
+-LINKINFO_GET
+-============
+-
+-Requests link settings as provided by ``ETHTOOL_GLINKSETTINGS`` except for
+-link modes and autonegotiation related information. The request does not use
+-any attributes.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_LINKINFO_HEADER``         nested  request header
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_LINKINFO_HEADER``         nested  reply header
+-  ``ETHTOOL_A_LINKINFO_PORT``           u8      physical port
+-  ``ETHTOOL_A_LINKINFO_PHYADDR``        u8      phy MDIO address
+-  ``ETHTOOL_A_LINKINFO_TP_MDIX``        u8      MDI(-X) status
+-  ``ETHTOOL_A_LINKINFO_TP_MDIX_CTRL``   u8      MDI(-X) control
+-  ``ETHTOOL_A_LINKINFO_TRANSCEIVER``    u8      transceiver
+-  ====================================  ======  ==========================
+-
+-Attributes and their values have the same meaning as matching members of the
+-corresponding ioctl structures.
+-
+-``LINKINFO_GET`` allows dump requests (kernel returns reply message for all
+-devices supporting the request).
+-
+-
+-LINKINFO_SET
+-============
+-
+-``LINKINFO_SET`` request allows setting some of the attributes reported by
+-``LINKINFO_GET``.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_LINKINFO_HEADER``         nested  request header
+-  ``ETHTOOL_A_LINKINFO_PORT``           u8      physical port
+-  ``ETHTOOL_A_LINKINFO_PHYADDR``        u8      phy MDIO address
+-  ``ETHTOOL_A_LINKINFO_TP_MDIX_CTRL``   u8      MDI(-X) control
+-  ====================================  ======  ==========================
+-
+-MDI(-X) status and transceiver cannot be set, request with the corresponding
+-attributes is rejected.
+-
+-
+-LINKMODES_GET
+-=============
+-
+-Requests link modes (supported, advertised and peer advertised) and related
+-information (autonegotiation status, link speed and duplex) as provided by
+-``ETHTOOL_GLINKSETTINGS``. The request does not use any attributes.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_LINKMODES_HEADER``        nested  request header
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  ==========================================  ======  ==========================
+-  ``ETHTOOL_A_LINKMODES_HEADER``              nested  reply header
+-  ``ETHTOOL_A_LINKMODES_AUTONEG``             u8      autonegotiation status
+-  ``ETHTOOL_A_LINKMODES_OURS``                bitset  advertised link modes
+-  ``ETHTOOL_A_LINKMODES_PEER``                bitset  partner link modes
+-  ``ETHTOOL_A_LINKMODES_SPEED``               u32     link speed (Mb/s)
+-  ``ETHTOOL_A_LINKMODES_DUPLEX``              u8      duplex mode
+-  ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG``    u8      Master/slave port mode
+-  ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE``  u8      Master/slave port state
+-  ==========================================  ======  ==========================
+-
+-For ``ETHTOOL_A_LINKMODES_OURS``, value represents advertised modes and mask
+-represents supported modes. ``ETHTOOL_A_LINKMODES_PEER`` in the reply is a bit
+-list.
+-
+-``LINKMODES_GET`` allows dump requests (kernel returns reply messages for all
+-devices supporting the request).
+-
+-
+-LINKMODES_SET
+-=============
+-
+-Request contents:
+-
+-  ==========================================  ======  ==========================
+-  ``ETHTOOL_A_LINKMODES_HEADER``              nested  request header
+-  ``ETHTOOL_A_LINKMODES_AUTONEG``             u8      autonegotiation status
+-  ``ETHTOOL_A_LINKMODES_OURS``                bitset  advertised link modes
+-  ``ETHTOOL_A_LINKMODES_PEER``                bitset  partner link modes
+-  ``ETHTOOL_A_LINKMODES_SPEED``               u32     link speed (Mb/s)
+-  ``ETHTOOL_A_LINKMODES_DUPLEX``              u8      duplex mode
+-  ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG``    u8      Master/slave port mode
+-  ==========================================  ======  ==========================
+-
+-``ETHTOOL_A_LINKMODES_OURS`` bit set allows setting advertised link modes. If
+-autonegotiation is on (either set now or kept from before), advertised modes
+-are not changed (no ``ETHTOOL_A_LINKMODES_OURS`` attribute) and at least one
+-of speed and duplex is specified, kernel adjusts advertised modes to all
+-supported modes matching speed, duplex or both (whatever is specified). This
+-autoselection is done on ethtool side with ioctl interface, netlink interface
+-is supposed to allow requesting changes without knowing what exactly kernel
+-supports.
+-
+-
+-LINKSTATE_GET
+-=============
+-
+-Requests link state information. Link up/down flag (as provided by
+-``ETHTOOL_GLINK`` ioctl command) is provided. Optionally, extended state might
+-be provided as well. In general, extended state describes reasons for why a port
+-is down, or why it operates in some non-obvious mode. This request does not have
+-any attributes.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_LINKSTATE_HEADER``        nested  request header
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  ====================================  ======  ============================
+-  ``ETHTOOL_A_LINKSTATE_HEADER``        nested  reply header
+-  ``ETHTOOL_A_LINKSTATE_LINK``          bool    link state (up/down)
+-  ``ETHTOOL_A_LINKSTATE_SQI``           u32     Current Signal Quality Index
+-  ``ETHTOOL_A_LINKSTATE_SQI_MAX``       u32     Max support SQI value
+-  ``ETHTOOL_A_LINKSTATE_EXT_STATE``     u8      link extended state
+-  ``ETHTOOL_A_LINKSTATE_EXT_SUBSTATE``  u8      link extended substate
+-  ====================================  ======  ============================
+-
+-For most NIC drivers, the value of ``ETHTOOL_A_LINKSTATE_LINK`` returns
+-carrier flag provided by ``netif_carrier_ok()`` but there are drivers which
+-define their own handler.
+-
+-``ETHTOOL_A_LINKSTATE_EXT_STATE`` and ``ETHTOOL_A_LINKSTATE_EXT_SUBSTATE`` are
+-optional values. ethtool core can provide either both
+-``ETHTOOL_A_LINKSTATE_EXT_STATE`` and ``ETHTOOL_A_LINKSTATE_EXT_SUBSTATE``,
+-or only ``ETHTOOL_A_LINKSTATE_EXT_STATE``, or none of them.
+-
+-``LINKSTATE_GET`` allows dump requests (kernel returns reply messages for all
+-devices supporting the request).
+-
+-
+-Link extended states:
+-
+-  ================================================      ============================================
+-  ``ETHTOOL_LINK_EXT_STATE_AUTONEG``                    States relating to the autonegotiation or
+-                                                        issues therein
+-
+-  ``ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE``      Failure during link training
+-
+-  ``ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH``      Logical mismatch in physical coding sublayer
+-                                                        or forward error correction sublayer
+-
+-  ``ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY``       Signal integrity issues
+-
+-  ``ETHTOOL_LINK_EXT_STATE_NO_CABLE``                   No cable connected
+-
+-  ``ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE``                Failure is related to cable,
+-                                                        e.g., unsupported cable
+-
+-  ``ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE``               Failure is related to EEPROM, e.g., failure
+-                                                        during reading or parsing the data
+-
+-  ``ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE``        Failure during calibration algorithm
+-
+-  ``ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED``      The hardware is not able to provide the
+-                                                        power required from cable or module
+-
+-  ``ETHTOOL_LINK_EXT_STATE_OVERHEAT``                   The module is overheated
+-  ================================================      ============================================
+-
+-Link extended substates:
+-
+-  Autoneg substates:
+-
+-  ===============================================================   ================================
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED``              Peer side is down
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED``                 Ack not received from peer side
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED``        Next page exchange failed
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE``   Peer side is down during force
+-                                                                    mode or there is no agreement of
+-                                                                    speed
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE``     Forward error correction modes
+-                                                                    in both sides are mismatched
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD``                           No Highest Common Denominator
+-  ===============================================================   ================================
+-
+-  Link training substates:
+-
+-  ===========================================================================   ====================
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED``                    Frames were not
+-                                                                                 recognized, the
+-                                                                                 lock failed
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT``                       The lock did not
+-                                                                                 occur before
+-                                                                                 timeout
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY``    Peer side did not
+-                                                                                 send ready signal
+-                                                                                 after training
+-                                                                                 process
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT``                                  Remote side is not
+-                                                                                 ready yet
+-  ===========================================================================   ====================
+-
+-  Link logical mismatch substates:
+-
+-  ================================================================   ===============================
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK``   Physical coding sublayer was
+-                                                                     not locked in first phase -
+-                                                                     block lock
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK``      Physical coding sublayer was
+-                                                                     not locked in second phase -
+-                                                                     alignment markers lock
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS``     Physical coding sublayer did
+-                                                                     not get align status
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED``             FC forward error correction is
+-                                                                     not locked
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED``             RS forward error correction is
+-                                                                     not locked
+-  ================================================================   ===============================
+-
+-  Bad signal integrity substates:
+-
+-  =================================================================    =============================
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS``    Large number of physical
+-                                                                       errors
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE``                   The system attempted to
+-                                                                       operate the cable at a rate
+-                                                                       that is not formally
+-                                                                       supported, which led to
+-                                                                       signal integrity issues
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_REFERENCE_CLOCK_LOST``        The external clock signal for
+-                                                                       SerDes is too weak or
+-                                                                       unavailable.
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_BSI_SERDES_ALOS``                        The received signal for
+-                                                                       SerDes is too weak because
+-                                                                       analog loss of signal.
+-  =================================================================    =============================
+-
+-  Cable issue substates:
+-
+-  ===================================================   ============================================
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE``    Unsupported cable
+-
+-  ``ETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE``   Cable test failure
+-  ===================================================   ============================================
+-
+-DEBUG_GET
+-=========
+-
+-Requests debugging settings of a device. At the moment, only message mask is
+-provided.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_DEBUG_HEADER``            nested  request header
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_DEBUG_HEADER``            nested  reply header
+-  ``ETHTOOL_A_DEBUG_MSGMASK``           bitset  message mask
+-  ====================================  ======  ==========================
+-
+-The message mask (``ETHTOOL_A_DEBUG_MSGMASK``) is equal to message level as
+-provided by ``ETHTOOL_GMSGLVL`` and set by ``ETHTOOL_SMSGLVL`` in ioctl
+-interface. While it is called message level there for historical reasons, most
+-drivers and almost all newer drivers use it as a mask of enabled message
+-classes (represented by ``NETIF_MSG_*`` constants); therefore netlink
+-interface follows its actual use in practice.
+-
+-``DEBUG_GET`` allows dump requests (kernel returns reply messages for all
+-devices supporting the request).
+-
+-
+-DEBUG_SET
+-=========
+-
+-Set or update debugging settings of a device. At the moment, only message mask
+-is supported.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_DEBUG_HEADER``            nested  request header
+-  ``ETHTOOL_A_DEBUG_MSGMASK``           bitset  message mask
+-  ====================================  ======  ==========================
+-
+-``ETHTOOL_A_DEBUG_MSGMASK`` bit set allows setting or modifying mask of
+-enabled debugging message types for the device.
+-
+-
+-WOL_GET
+-=======
+-
+-Query device wake-on-lan settings. Unlike most "GET" type requests,
+-``ETHTOOL_MSG_WOL_GET`` requires (netns) ``CAP_NET_ADMIN`` privileges as it
+-(potentially) provides SecureOn(tm) password which is confidential.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_WOL_HEADER``              nested  request header
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_WOL_HEADER``              nested  reply header
+-  ``ETHTOOL_A_WOL_MODES``               bitset  mask of enabled WoL modes
+-  ``ETHTOOL_A_WOL_SOPASS``              binary  SecureOn(tm) password
+-  ====================================  ======  ==========================
+-
+-In reply, ``ETHTOOL_A_WOL_MODES`` mask consists of modes supported by the
+-device, value of modes which are enabled. ``ETHTOOL_A_WOL_SOPASS`` is only
+-included in reply if ``WAKE_MAGICSECURE`` mode is supported.
+-
+-
+-WOL_SET
+-=======
+-
+-Set or update wake-on-lan settings.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_WOL_HEADER``              nested  request header
+-  ``ETHTOOL_A_WOL_MODES``               bitset  enabled WoL modes
+-  ``ETHTOOL_A_WOL_SOPASS``              binary  SecureOn(tm) password
+-  ====================================  ======  ==========================
+-
+-``ETHTOOL_A_WOL_SOPASS`` is only allowed for devices supporting
+-``WAKE_MAGICSECURE`` mode.
+-
+-
+-FEATURES_GET
+-============
+-
+-Gets netdev features like ``ETHTOOL_GFEATURES`` ioctl request.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_FEATURES_HEADER``         nested  request header
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_FEATURES_HEADER``         nested  reply header
+-  ``ETHTOOL_A_FEATURES_HW``             bitset  dev->hw_features
+-  ``ETHTOOL_A_FEATURES_WANTED``         bitset  dev->wanted_features
+-  ``ETHTOOL_A_FEATURES_ACTIVE``         bitset  dev->features
+-  ``ETHTOOL_A_FEATURES_NOCHANGE``       bitset  NETIF_F_NEVER_CHANGE
+-  ====================================  ======  ==========================
+-
+-Bitmaps in kernel response have the same meaning as bitmaps used in ioctl
+-interference but attribute names are different (they are based on
+-corresponding members of struct net_device). Legacy "flags" are not provided,
+-if userspace needs them (most likely only ethtool for backward compatibility),
+-it can calculate their values from related feature bits itself.
+-ETHA_FEATURES_HW uses mask consisting of all features recognized by kernel (to
+-provide all names when using verbose bitmap format), the other three use no
+-mask (simple bit lists).
+-
+-
+-FEATURES_SET
+-============
+-
+-Request to set netdev features like ``ETHTOOL_SFEATURES`` ioctl request.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_FEATURES_HEADER``         nested  request header
+-  ``ETHTOOL_A_FEATURES_WANTED``         bitset  requested features
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_FEATURES_HEADER``         nested  reply header
+-  ``ETHTOOL_A_FEATURES_WANTED``         bitset  diff wanted vs. result
+-  ``ETHTOOL_A_FEATURES_ACTIVE``         bitset  diff old vs. new active
+-  ====================================  ======  ==========================
+-
+-Request constains only one bitset which can be either value/mask pair (request
+-to change specific feature bits and leave the rest) or only a value (request
+-to set all features to specified set).
+-
+-As request is subject to netdev_change_features() sanity checks, optional
+-kernel reply (can be suppressed by ``ETHTOOL_FLAG_OMIT_REPLY`` flag in request
+-header) informs client about the actual result. ``ETHTOOL_A_FEATURES_WANTED``
+-reports the difference between client request and actual result: mask consists
+-of bits which differ between requested features and result (dev->features
+-after the operation), value consists of values of these bits in the request
+-(i.e. negated values from resulting features). ``ETHTOOL_A_FEATURES_ACTIVE``
+-reports the difference between old and new dev->features: mask consists of
+-bits which have changed, values are their values in new dev->features (after
+-the operation).
+-
+-``ETHTOOL_MSG_FEATURES_NTF`` notification is sent not only if device features
+-are modified using ``ETHTOOL_MSG_FEATURES_SET`` request or on of ethtool ioctl
+-request but also each time features are modified with netdev_update_features()
+-or netdev_change_features().
+-
+-
+-PRIVFLAGS_GET
+-=============
+-
+-Gets private flags like ``ETHTOOL_GPFLAGS`` ioctl request.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_PRIVFLAGS_HEADER``        nested  request header
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_PRIVFLAGS_HEADER``        nested  reply header
+-  ``ETHTOOL_A_PRIVFLAGS_FLAGS``         bitset  private flags
+-  ====================================  ======  ==========================
+-
+-``ETHTOOL_A_PRIVFLAGS_FLAGS`` is a bitset with values of device private flags.
+-These flags are defined by driver, their number and names (and also meaning)
+-are device dependent. For compact bitset format, names can be retrieved as
+-``ETH_SS_PRIV_FLAGS`` string set. If verbose bitset format is requested,
+-response uses all private flags supported by the device as mask so that client
+-gets the full information without having to fetch the string set with names.
+-
+-
+-PRIVFLAGS_SET
+-=============
+-
+-Sets or modifies values of device private flags like ``ETHTOOL_SPFLAGS``
+-ioctl request.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_PRIVFLAGS_HEADER``        nested  request header
+-  ``ETHTOOL_A_PRIVFLAGS_FLAGS``         bitset  private flags
+-  ====================================  ======  ==========================
+-
+-``ETHTOOL_A_PRIVFLAGS_FLAGS`` can either set the whole set of private flags or
+-modify only values of some of them.
+-
+-
+-RINGS_GET
+-=========
+-
+-Gets ring sizes like ``ETHTOOL_GRINGPARAM`` ioctl request.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_RINGS_HEADER``            nested  request header
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_RINGS_HEADER``            nested  reply header
+-  ``ETHTOOL_A_RINGS_RX_MAX``            u32     max size of RX ring
+-  ``ETHTOOL_A_RINGS_RX_MINI_MAX``       u32     max size of RX mini ring
+-  ``ETHTOOL_A_RINGS_RX_JUMBO_MAX``      u32     max size of RX jumbo ring
+-  ``ETHTOOL_A_RINGS_TX_MAX``            u32     max size of TX ring
+-  ``ETHTOOL_A_RINGS_RX``                u32     size of RX ring
+-  ``ETHTOOL_A_RINGS_RX_MINI``           u32     size of RX mini ring
+-  ``ETHTOOL_A_RINGS_RX_JUMBO``          u32     size of RX jumbo ring
+-  ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
+-  ====================================  ======  ==========================
+-
+-
+-RINGS_SET
+-=========
+-
+-Sets ring sizes like ``ETHTOOL_SRINGPARAM`` ioctl request.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_RINGS_HEADER``            nested  reply header
+-  ``ETHTOOL_A_RINGS_RX``                u32     size of RX ring
+-  ``ETHTOOL_A_RINGS_RX_MINI``           u32     size of RX mini ring
+-  ``ETHTOOL_A_RINGS_RX_JUMBO``          u32     size of RX jumbo ring
+-  ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
+-  ====================================  ======  ==========================
+-
+-Kernel checks that requested ring sizes do not exceed limits reported by
+-driver. Driver may impose additional constraints and may not suspport all
+-attributes.
+-
+-
+-CHANNELS_GET
+-============
+-
+-Gets channel counts like ``ETHTOOL_GCHANNELS`` ioctl request.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_CHANNELS_HEADER``         nested  request header
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_CHANNELS_HEADER``          nested  reply header
+-  ``ETHTOOL_A_CHANNELS_RX_MAX``          u32     max receive channels
+-  ``ETHTOOL_A_CHANNELS_TX_MAX``          u32     max transmit channels
+-  ``ETHTOOL_A_CHANNELS_OTHER_MAX``       u32     max other channels
+-  ``ETHTOOL_A_CHANNELS_COMBINED_MAX``    u32     max combined channels
+-  ``ETHTOOL_A_CHANNELS_RX_COUNT``        u32     receive channel count
+-  ``ETHTOOL_A_CHANNELS_TX_COUNT``        u32     transmit channel count
+-  ``ETHTOOL_A_CHANNELS_OTHER_COUNT``     u32     other channel count
+-  ``ETHTOOL_A_CHANNELS_COMBINED_COUNT``  u32     combined channel count
+-  =====================================  ======  ==========================
+-
+-
+-CHANNELS_SET
+-============
+-
+-Sets channel counts like ``ETHTOOL_SCHANNELS`` ioctl request.
+-
+-Request contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_CHANNELS_HEADER``          nested  request header
+-  ``ETHTOOL_A_CHANNELS_RX_COUNT``        u32     receive channel count
+-  ``ETHTOOL_A_CHANNELS_TX_COUNT``        u32     transmit channel count
+-  ``ETHTOOL_A_CHANNELS_OTHER_COUNT``     u32     other channel count
+-  ``ETHTOOL_A_CHANNELS_COMBINED_COUNT``  u32     combined channel count
+-  =====================================  ======  ==========================
+-
+-Kernel checks that requested channel counts do not exceed limits reported by
+-driver. Driver may impose additional constraints and may not suspport all
+-attributes.
+-
+-
+-COALESCE_GET
+-============
+-
+-Gets coalescing parameters like ``ETHTOOL_GCOALESCE`` ioctl request.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_COALESCE_HEADER``         nested  request header
+-  ====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  ===========================================  ======  =======================
+-  ``ETHTOOL_A_COALESCE_HEADER``                nested  reply header
+-  ``ETHTOOL_A_COALESCE_RX_USECS``              u32     delay (us), normal Rx
+-  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES``         u32     max packets, normal Rx
+-  ``ETHTOOL_A_COALESCE_RX_USECS_IRQ``          u32     delay (us), Rx in IRQ
+-  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ``     u32     max packets, Rx in IRQ
+-  ``ETHTOOL_A_COALESCE_TX_USECS``              u32     delay (us), normal Tx
+-  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES``         u32     max packets, normal Tx
+-  ``ETHTOOL_A_COALESCE_TX_USECS_IRQ``          u32     delay (us), Tx in IRQ
+-  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ``     u32     IRQ packets, Tx in IRQ
+-  ``ETHTOOL_A_COALESCE_STATS_BLOCK_USECS``     u32     delay of stats update
+-  ``ETHTOOL_A_COALESCE_USE_ADAPTIVE_RX``       bool    adaptive Rx coalesce
+-  ``ETHTOOL_A_COALESCE_USE_ADAPTIVE_TX``       bool    adaptive Tx coalesce
+-  ``ETHTOOL_A_COALESCE_PKT_RATE_LOW``          u32     threshold for low rate
+-  ``ETHTOOL_A_COALESCE_RX_USECS_LOW``          u32     delay (us), low Rx
+-  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW``     u32     max packets, low Rx
+-  ``ETHTOOL_A_COALESCE_TX_USECS_LOW``          u32     delay (us), low Tx
+-  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW``     u32     max packets, low Tx
+-  ``ETHTOOL_A_COALESCE_PKT_RATE_HIGH``         u32     threshold for high rate
+-  ``ETHTOOL_A_COALESCE_RX_USECS_HIGH``         u32     delay (us), high Rx
+-  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH``    u32     max packets, high Rx
+-  ``ETHTOOL_A_COALESCE_TX_USECS_HIGH``         u32     delay (us), high Tx
+-  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH``    u32     max packets, high Tx
+-  ``ETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL``  u32     rate sampling interval
+-  ===========================================  ======  =======================
+-
+-Attributes are only included in reply if their value is not zero or the
+-corresponding bit in ``ethtool_ops::supported_coalesce_params`` is set (i.e.
+-they are declared as supported by driver).
+-
+-
+-COALESCE_SET
+-============
+-
+-Sets coalescing parameters like ``ETHTOOL_SCOALESCE`` ioctl request.
+-
+-Request contents:
+-
+-  ===========================================  ======  =======================
+-  ``ETHTOOL_A_COALESCE_HEADER``                nested  request header
+-  ``ETHTOOL_A_COALESCE_RX_USECS``              u32     delay (us), normal Rx
+-  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES``         u32     max packets, normal Rx
+-  ``ETHTOOL_A_COALESCE_RX_USECS_IRQ``          u32     delay (us), Rx in IRQ
+-  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_IRQ``     u32     max packets, Rx in IRQ
+-  ``ETHTOOL_A_COALESCE_TX_USECS``              u32     delay (us), normal Tx
+-  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES``         u32     max packets, normal Tx
+-  ``ETHTOOL_A_COALESCE_TX_USECS_IRQ``          u32     delay (us), Tx in IRQ
+-  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_IRQ``     u32     IRQ packets, Tx in IRQ
+-  ``ETHTOOL_A_COALESCE_STATS_BLOCK_USECS``     u32     delay of stats update
+-  ``ETHTOOL_A_COALESCE_USE_ADAPTIVE_RX``       bool    adaptive Rx coalesce
+-  ``ETHTOOL_A_COALESCE_USE_ADAPTIVE_TX``       bool    adaptive Tx coalesce
+-  ``ETHTOOL_A_COALESCE_PKT_RATE_LOW``          u32     threshold for low rate
+-  ``ETHTOOL_A_COALESCE_RX_USECS_LOW``          u32     delay (us), low Rx
+-  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_LOW``     u32     max packets, low Rx
+-  ``ETHTOOL_A_COALESCE_TX_USECS_LOW``          u32     delay (us), low Tx
+-  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_LOW``     u32     max packets, low Tx
+-  ``ETHTOOL_A_COALESCE_PKT_RATE_HIGH``         u32     threshold for high rate
+-  ``ETHTOOL_A_COALESCE_RX_USECS_HIGH``         u32     delay (us), high Rx
+-  ``ETHTOOL_A_COALESCE_RX_MAX_FRAMES_HIGH``    u32     max packets, high Rx
+-  ``ETHTOOL_A_COALESCE_TX_USECS_HIGH``         u32     delay (us), high Tx
+-  ``ETHTOOL_A_COALESCE_TX_MAX_FRAMES_HIGH``    u32     max packets, high Tx
+-  ``ETHTOOL_A_COALESCE_RATE_SAMPLE_INTERVAL``  u32     rate sampling interval
+-  ===========================================  ======  =======================
+-
+-Request is rejected if it attributes declared as unsupported by driver (i.e.
+-such that the corresponding bit in ``ethtool_ops::supported_coalesce_params``
+-is not set), regardless of their values. Driver may impose additional
+-constraints on coalescing parameters and their values.
+-
+-
+-PAUSE_GET
+-============
+-
+-Gets channel counts like ``ETHTOOL_GPAUSE`` ioctl request.
+-
+-Request contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_PAUSE_HEADER``             nested  request header
+-  =====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_PAUSE_HEADER``             nested  request header
+-  ``ETHTOOL_A_PAUSE_AUTONEG``            bool    pause autonegotiation
+-  ``ETHTOOL_A_PAUSE_RX``                 bool    receive pause frames
+-  ``ETHTOOL_A_PAUSE_TX``                 bool    transmit pause frames
+-  ``ETHTOOL_A_PAUSE_STATS``              nested  pause statistics
+-  =====================================  ======  ==========================
+-
+-``ETHTOOL_A_PAUSE_STATS`` are reported if ``ETHTOOL_FLAG_STATS`` was set
+-in ``ETHTOOL_A_HEADER_FLAGS``.
+-It will be empty if driver did not report any statistics. Drivers fill in
+-the statistics in the following structure:
+-
+-.. kernel-doc:: include/linux/ethtool.h
+-    :identifiers: ethtool_pause_stats
+-
+-Each member has a corresponding attribute defined.
+-
+-PAUSE_SET
+-============
+-
+-Sets pause parameters like ``ETHTOOL_GPAUSEPARAM`` ioctl request.
+-
+-Request contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_PAUSE_HEADER``             nested  request header
+-  ``ETHTOOL_A_PAUSE_AUTONEG``            bool    pause autonegotiation
+-  ``ETHTOOL_A_PAUSE_RX``                 bool    receive pause frames
+-  ``ETHTOOL_A_PAUSE_TX``                 bool    transmit pause frames
+-  =====================================  ======  ==========================
+-
+-
+-EEE_GET
+-=======
+-
+-Gets channel counts like ``ETHTOOL_GEEE`` ioctl request.
+-
+-Request contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_EEE_HEADER``               nested  request header
+-  =====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_EEE_HEADER``               nested  request header
+-  ``ETHTOOL_A_EEE_MODES_OURS``           bool    supported/advertised modes
+-  ``ETHTOOL_A_EEE_MODES_PEER``           bool    peer advertised link modes
+-  ``ETHTOOL_A_EEE_ACTIVE``               bool    EEE is actively used
+-  ``ETHTOOL_A_EEE_ENABLED``              bool    EEE is enabled
+-  ``ETHTOOL_A_EEE_TX_LPI_ENABLED``       bool    Tx lpi enabled
+-  ``ETHTOOL_A_EEE_TX_LPI_TIMER``         u32     Tx lpi timeout (in us)
+-  =====================================  ======  ==========================
+-
+-In ``ETHTOOL_A_EEE_MODES_OURS``, mask consists of link modes for which EEE is
+-enabled, value of link modes for which EEE is advertised. Link modes for which
+-peer advertises EEE are listed in ``ETHTOOL_A_EEE_MODES_PEER`` (no mask). The
+-netlink interface allows reporting EEE status for all link modes but only
+-first 32 are provided by the ``ethtool_ops`` callback.
+-
+-
+-EEE_SET
+-=======
+-
+-Sets pause parameters like ``ETHTOOL_GEEEPARAM`` ioctl request.
+-
+-Request contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_EEE_HEADER``               nested  request header
+-  ``ETHTOOL_A_EEE_MODES_OURS``           bool    advertised modes
+-  ``ETHTOOL_A_EEE_ENABLED``              bool    EEE is enabled
+-  ``ETHTOOL_A_EEE_TX_LPI_ENABLED``       bool    Tx lpi enabled
+-  ``ETHTOOL_A_EEE_TX_LPI_TIMER``         u32     Tx lpi timeout (in us)
+-  =====================================  ======  ==========================
+-
+-``ETHTOOL_A_EEE_MODES_OURS`` is used to either list link modes to advertise
+-EEE for (if there is no mask) or specify changes to the list (if there is
+-a mask). The netlink interface allows reporting EEE status for all link modes
+-but only first 32 can be set at the moment as that is what the ``ethtool_ops``
+-callback supports.
+-
+-
+-TSINFO_GET
+-==========
+-
+-Gets timestamping information like ``ETHTOOL_GET_TS_INFO`` ioctl request.
+-
+-Request contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_TSINFO_HEADER``            nested  request header
+-  =====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_TSINFO_HEADER``            nested  request header
+-  ``ETHTOOL_A_TSINFO_TIMESTAMPING``      bitset  SO_TIMESTAMPING flags
+-  ``ETHTOOL_A_TSINFO_TX_TYPES``          bitset  supported Tx types
+-  ``ETHTOOL_A_TSINFO_RX_FILTERS``        bitset  supported Rx filters
+-  ``ETHTOOL_A_TSINFO_PHC_INDEX``         u32     PTP hw clock index
+-  =====================================  ======  ==========================
+-
+-``ETHTOOL_A_TSINFO_PHC_INDEX`` is absent if there is no associated PHC (there
+-is no special value for this case). The bitset attributes are omitted if they
+-would be empty (no bit set).
+-
+-CABLE_TEST
+-==========
+-
+-Start a cable test.
+-
+-Request contents:
+-
+-  ====================================  ======  ==========================
+-  ``ETHTOOL_A_CABLE_TEST_HEADER``       nested  request header
+-  ====================================  ======  ==========================
+-
+-Notification contents:
+-
+-An Ethernet cable typically contains 1, 2 or 4 pairs. The length of
+-the pair can only be measured when there is a fault in the pair and
+-hence a reflection. Information about the fault may not be available,
+-depending on the specific hardware. Hence the contents of the notify
+-message are mostly optional. The attributes can be repeated an
+-arbitrary number of times, in an arbitrary order, for an arbitrary
+-number of pairs.
+-
+-The example shows the notification sent when the test is completed for
+-a T2 cable, i.e. two pairs. One pair is OK and hence has no length
+-information. The second pair has a fault and does have length
+-information.
+-
+- +---------------------------------------------+--------+---------------------+
+- | ``ETHTOOL_A_CABLE_TEST_HEADER``             | nested | reply header        |
+- +---------------------------------------------+--------+---------------------+
+- | ``ETHTOOL_A_CABLE_TEST_STATUS``             | u8     | completed           |
+- +---------------------------------------------+--------+---------------------+
+- | ``ETHTOOL_A_CABLE_TEST_NTF_NEST``           | nested | all the results     |
+- +-+-------------------------------------------+--------+---------------------+
+- | | ``ETHTOOL_A_CABLE_NEST_RESULT``           | nested | cable test result   |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | | ``ETHTOOL_A_CABLE_RESULTS_PAIR``        | u8     | pair number         |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | | ``ETHTOOL_A_CABLE_RESULTS_CODE``        | u8     | result code         |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | ``ETHTOOL_A_CABLE_NEST_RESULT``           | nested | cable test results  |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | | ``ETHTOOL_A_CABLE_RESULTS_PAIR``        | u8     | pair number         |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | | ``ETHTOOL_A_CABLE_RESULTS_CODE``        | u8     | result code         |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | ``ETHTOOL_A_CABLE_NEST_FAULT_LENGTH``     | nested | cable length        |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | | ``ETHTOOL_A_CABLE_FAULT_LENGTH_PAIR``   | u8     | pair number         |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | | ``ETHTOOL_A_CABLE_FAULT_LENGTH_CM``     | u32    | length in cm        |
+- +-+-+-----------------------------------------+--------+---------------------+
+-
+-CABLE_TEST TDR
+-==============
+-
+-Start a cable test and report raw TDR data
+-
+-Request contents:
+-
+- +--------------------------------------------+--------+-----------------------+
+- | ``ETHTOOL_A_CABLE_TEST_TDR_HEADER``        | nested | reply header          |
+- +--------------------------------------------+--------+-----------------------+
+- | ``ETHTOOL_A_CABLE_TEST_TDR_CFG``           | nested | test configuration    |
+- +-+------------------------------------------+--------+-----------------------+
+- | | ``ETHTOOL_A_CABLE_STEP_FIRST_DISTANCE``  | u32    | first data distance   |
+- +-+-+----------------------------------------+--------+-----------------------+
+- | | ``ETHTOOL_A_CABLE_STEP_LAST_DISTANCE``   | u32    | last data distance    |
+- +-+-+----------------------------------------+--------+-----------------------+
+- | | ``ETHTOOL_A_CABLE_STEP_STEP_DISTANCE``   | u32    | distance of each step |
+- +-+-+----------------------------------------+--------+-----------------------+
+- | | ``ETHTOOL_A_CABLE_TEST_TDR_CFG_PAIR``    | u8     | pair to test          |
+- +-+-+----------------------------------------+--------+-----------------------+
+-
+-The ETHTOOL_A_CABLE_TEST_TDR_CFG is optional, as well as all members
+-of the nest. All distances are expressed in centimeters. The PHY takes
+-the distances as a guide, and rounds to the nearest distance it
+-actually supports. If a pair is passed, only that one pair will be
+-tested. Otherwise all pairs are tested.
+-
+-Notification contents:
+-
+-Raw TDR data is gathered by sending a pulse down the cable and
+-recording the amplitude of the reflected pulse for a given distance.
+-
+-It can take a number of seconds to collect TDR data, especial if the
+-full 100 meters is probed at 1 meter intervals. When the test is
+-started a notification will be sent containing just
+-ETHTOOL_A_CABLE_TEST_TDR_STATUS with the value
+-ETHTOOL_A_CABLE_TEST_NTF_STATUS_STARTED.
+-
+-When the test has completed a second notification will be sent
+-containing ETHTOOL_A_CABLE_TEST_TDR_STATUS with the value
+-ETHTOOL_A_CABLE_TEST_NTF_STATUS_COMPLETED and the TDR data.
+-
+-The message may optionally contain the amplitude of the pulse send
+-down the cable. This is measured in mV. A reflection should not be
+-bigger than transmitted pulse.
+-
+-Before the raw TDR data should be an ETHTOOL_A_CABLE_TDR_NEST_STEP
+-nest containing information about the distance along the cable for the
+-first reading, the last reading, and the step between each
+-reading. Distances are measured in centimeters. These should be the
+-exact values the PHY used. These may be different to what the user
+-requested, if the native measurement resolution is greater than 1 cm.
+-
+-For each step along the cable, a ETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE is
+-used to report the amplitude of the reflection for a given pair.
+-
+- +---------------------------------------------+--------+----------------------+
+- | ``ETHTOOL_A_CABLE_TEST_TDR_HEADER``         | nested | reply header         |
+- +---------------------------------------------+--------+----------------------+
+- | ``ETHTOOL_A_CABLE_TEST_TDR_STATUS``         | u8     | completed            |
+- +---------------------------------------------+--------+----------------------+
+- | ``ETHTOOL_A_CABLE_TEST_TDR_NTF_NEST``       | nested | all the results      |
+- +-+-------------------------------------------+--------+----------------------+
+- | | ``ETHTOOL_A_CABLE_TDR_NEST_PULSE``        | nested | TX Pulse amplitude   |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | | ``ETHTOOL_A_CABLE_PULSE_mV``            | s16    | Pulse amplitude      |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | ``ETHTOOL_A_CABLE_NEST_STEP``             | nested | TDR step info        |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | | ``ETHTOOL_A_CABLE_STEP_FIRST_DISTANCE`` | u32    | First data distance  |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | | ``ETHTOOL_A_CABLE_STEP_LAST_DISTANCE``  | u32    | Last data distance   |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | | ``ETHTOOL_A_CABLE_STEP_STEP_DISTANCE``  | u32    | distance of each step|
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | ``ETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE``    | nested | Reflection amplitude |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | | ``ETHTOOL_A_CABLE_RESULTS_PAIR``        | u8     | pair number          |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | | ``ETHTOOL_A_CABLE_AMPLITUDE_mV``        | s16    | Reflection amplitude |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | ``ETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE``    | nested | Reflection amplitude |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | | ``ETHTOOL_A_CABLE_RESULTS_PAIR``        | u8     | pair number          |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | | ``ETHTOOL_A_CABLE_AMPLITUDE_mV``        | s16    | Reflection amplitude |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | ``ETHTOOL_A_CABLE_TDR_NEST_AMPLITUDE``    | nested | Reflection amplitude |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | | ``ETHTOOL_A_CABLE_RESULTS_PAIR``        | u8     | pair number          |
+- +-+-+-----------------------------------------+--------+----------------------+
+- | | | ``ETHTOOL_A_CABLE_AMPLITUDE_mV``        | s16    | Reflection amplitude |
+- +-+-+-----------------------------------------+--------+----------------------+
+-
+-TUNNEL_INFO
+-===========
+-
+-Gets information about the tunnel state NIC is aware of.
+-
+-Request contents:
+-
+-  =====================================  ======  ==========================
+-  ``ETHTOOL_A_TUNNEL_INFO_HEADER``       nested  request header
+-  =====================================  ======  ==========================
+-
+-Kernel response contents:
+-
+- +---------------------------------------------+--------+---------------------+
+- | ``ETHTOOL_A_TUNNEL_INFO_HEADER``            | nested | reply header        |
+- +---------------------------------------------+--------+---------------------+
+- | ``ETHTOOL_A_TUNNEL_INFO_UDP_PORTS``         | nested | all UDP port tables |
+- +-+-------------------------------------------+--------+---------------------+
+- | | ``ETHTOOL_A_TUNNEL_UDP_TABLE``            | nested | one UDP port table  |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | | ``ETHTOOL_A_TUNNEL_UDP_TABLE_SIZE``     | u32    | max size of the     |
+- | | |                                         |        | table               |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | | ``ETHTOOL_A_TUNNEL_UDP_TABLE_TYPES``    | bitset | tunnel types which  |
+- | | |                                         |        | table can hold      |
+- +-+-+-----------------------------------------+--------+---------------------+
+- | | | ``ETHTOOL_A_TUNNEL_UDP_TABLE_ENTRY``    | nested | offloaded UDP port  |
+- +-+-+-+---------------------------------------+--------+---------------------+
+- | | | | ``ETHTOOL_A_TUNNEL_UDP_ENTRY_PORT``   | be16   | UDP port            |
+- +-+-+-+---------------------------------------+--------+---------------------+
+- | | | | ``ETHTOOL_A_TUNNEL_UDP_ENTRY_TYPE``   | u32    | tunnel type         |
+- +-+-+-+---------------------------------------+--------+---------------------+
+-
+-For UDP tunnel table empty ``ETHTOOL_A_TUNNEL_UDP_TABLE_TYPES`` indicates that
+-the table contains static entries, hard-coded by the NIC.
+-
+ Request translation
+ ===================
+ 
+ The following table maps ioctl commands to netlink commands providing their
+ functionality. Entries with "n/a" in right column are commands which do not
+-have their netlink replacement yet. Entries which "n/a" in the left column
+-are netlink only.
++have their netlink replacement yet.
+ 
+   =================================== =====================================
+   ioctl command                       netlink command
+   =================================== =====================================
+-  ``ETHTOOL_GSET``                    ``ETHTOOL_MSG_LINKINFO_GET``
+-                                      ``ETHTOOL_MSG_LINKMODES_GET``
+-  ``ETHTOOL_SSET``                    ``ETHTOOL_MSG_LINKINFO_SET``
+-                                      ``ETHTOOL_MSG_LINKMODES_SET``
++  ``ETHTOOL_GSET``                    n/a
++  ``ETHTOOL_SSET``                    n/a
+   ``ETHTOOL_GDRVINFO``                n/a
+   ``ETHTOOL_GREGS``                   n/a
+-  ``ETHTOOL_GWOL``                    ``ETHTOOL_MSG_WOL_GET``
+-  ``ETHTOOL_SWOL``                    ``ETHTOOL_MSG_WOL_SET``
+-  ``ETHTOOL_GMSGLVL``                 ``ETHTOOL_MSG_DEBUG_GET``
+-  ``ETHTOOL_SMSGLVL``                 ``ETHTOOL_MSG_DEBUG_SET``
++  ``ETHTOOL_GWOL``                    n/a
++  ``ETHTOOL_SWOL``                    n/a
++  ``ETHTOOL_GMSGLVL``                 n/a
++  ``ETHTOOL_SMSGLVL``                 n/a
+   ``ETHTOOL_NWAY_RST``                n/a
+-  ``ETHTOOL_GLINK``                   ``ETHTOOL_MSG_LINKSTATE_GET``
++  ``ETHTOOL_GLINK``                   n/a
+   ``ETHTOOL_GEEPROM``                 n/a
+   ``ETHTOOL_SEEPROM``                 n/a
+-  ``ETHTOOL_GCOALESCE``               ``ETHTOOL_MSG_COALESCE_GET``
+-  ``ETHTOOL_SCOALESCE``               ``ETHTOOL_MSG_COALESCE_SET``
+-  ``ETHTOOL_GRINGPARAM``              ``ETHTOOL_MSG_RINGS_GET``
+-  ``ETHTOOL_SRINGPARAM``              ``ETHTOOL_MSG_RINGS_SET``
+-  ``ETHTOOL_GPAUSEPARAM``             ``ETHTOOL_MSG_PAUSE_GET``
+-  ``ETHTOOL_SPAUSEPARAM``             ``ETHTOOL_MSG_PAUSE_SET``
+-  ``ETHTOOL_GRXCSUM``                 ``ETHTOOL_MSG_FEATURES_GET``
+-  ``ETHTOOL_SRXCSUM``                 ``ETHTOOL_MSG_FEATURES_SET``
+-  ``ETHTOOL_GTXCSUM``                 ``ETHTOOL_MSG_FEATURES_GET``
+-  ``ETHTOOL_STXCSUM``                 ``ETHTOOL_MSG_FEATURES_SET``
+-  ``ETHTOOL_GSG``                     ``ETHTOOL_MSG_FEATURES_GET``
+-  ``ETHTOOL_SSG``                     ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GCOALESCE``               n/a
++  ``ETHTOOL_SCOALESCE``               n/a
++  ``ETHTOOL_GRINGPARAM``              n/a
++  ``ETHTOOL_SRINGPARAM``              n/a
++  ``ETHTOOL_GPAUSEPARAM``             n/a
++  ``ETHTOOL_SPAUSEPARAM``             n/a
++  ``ETHTOOL_GRXCSUM``                 n/a
++  ``ETHTOOL_SRXCSUM``                 n/a
++  ``ETHTOOL_GTXCSUM``                 n/a
++  ``ETHTOOL_STXCSUM``                 n/a
++  ``ETHTOOL_GSG``                     n/a
++  ``ETHTOOL_SSG``                     n/a
+   ``ETHTOOL_TEST``                    n/a
+-  ``ETHTOOL_GSTRINGS``                ``ETHTOOL_MSG_STRSET_GET``
++  ``ETHTOOL_GSTRINGS``                n/a
+   ``ETHTOOL_PHYS_ID``                 n/a
+   ``ETHTOOL_GSTATS``                  n/a
+-  ``ETHTOOL_GTSO``                    ``ETHTOOL_MSG_FEATURES_GET``
+-  ``ETHTOOL_STSO``                    ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GTSO``                    n/a
++  ``ETHTOOL_STSO``                    n/a
+   ``ETHTOOL_GPERMADDR``               rtnetlink ``RTM_GETLINK``
+-  ``ETHTOOL_GUFO``                    ``ETHTOOL_MSG_FEATURES_GET``
+-  ``ETHTOOL_SUFO``                    ``ETHTOOL_MSG_FEATURES_SET``
+-  ``ETHTOOL_GGSO``                    ``ETHTOOL_MSG_FEATURES_GET``
+-  ``ETHTOOL_SGSO``                    ``ETHTOOL_MSG_FEATURES_SET``
+-  ``ETHTOOL_GFLAGS``                  ``ETHTOOL_MSG_FEATURES_GET``
+-  ``ETHTOOL_SFLAGS``                  ``ETHTOOL_MSG_FEATURES_SET``
+-  ``ETHTOOL_GPFLAGS``                 ``ETHTOOL_MSG_PRIVFLAGS_GET``
+-  ``ETHTOOL_SPFLAGS``                 ``ETHTOOL_MSG_PRIVFLAGS_SET``
++  ``ETHTOOL_GUFO``                    n/a
++  ``ETHTOOL_SUFO``                    n/a
++  ``ETHTOOL_GGSO``                    n/a
++  ``ETHTOOL_SGSO``                    n/a
++  ``ETHTOOL_GFLAGS``                  n/a
++  ``ETHTOOL_SFLAGS``                  n/a
++  ``ETHTOOL_GPFLAGS``                 n/a
++  ``ETHTOOL_SPFLAGS``                 n/a
+   ``ETHTOOL_GRXFH``                   n/a
+   ``ETHTOOL_SRXFH``                   n/a
+-  ``ETHTOOL_GGRO``                    ``ETHTOOL_MSG_FEATURES_GET``
+-  ``ETHTOOL_SGRO``                    ``ETHTOOL_MSG_FEATURES_SET``
++  ``ETHTOOL_GGRO``                    n/a
++  ``ETHTOOL_SGRO``                    n/a
+   ``ETHTOOL_GRXRINGS``                n/a
+   ``ETHTOOL_GRXCLSRLCNT``             n/a
+   ``ETHTOOL_GRXCLSRULE``              n/a
+@@ -1353,36 +269,31 @@ are netlink only.
+   ``ETHTOOL_RESET``                   n/a
+   ``ETHTOOL_SRXNTUPLE``               n/a
+   ``ETHTOOL_GRXNTUPLE``               n/a
+-  ``ETHTOOL_GSSET_INFO``              ``ETHTOOL_MSG_STRSET_GET``
++  ``ETHTOOL_GSSET_INFO``              n/a
+   ``ETHTOOL_GRXFHINDIR``              n/a
+   ``ETHTOOL_SRXFHINDIR``              n/a
+-  ``ETHTOOL_GFEATURES``               ``ETHTOOL_MSG_FEATURES_GET``
+-  ``ETHTOOL_SFEATURES``               ``ETHTOOL_MSG_FEATURES_SET``
+-  ``ETHTOOL_GCHANNELS``               ``ETHTOOL_MSG_CHANNELS_GET``
+-  ``ETHTOOL_SCHANNELS``               ``ETHTOOL_MSG_CHANNELS_SET``
++  ``ETHTOOL_GFEATURES``               n/a
++  ``ETHTOOL_SFEATURES``               n/a
++  ``ETHTOOL_GCHANNELS``               n/a
++  ``ETHTOOL_SCHANNELS``               n/a
+   ``ETHTOOL_SET_DUMP``                n/a
+   ``ETHTOOL_GET_DUMP_FLAG``           n/a
+   ``ETHTOOL_GET_DUMP_DATA``           n/a
+-  ``ETHTOOL_GET_TS_INFO``             ``ETHTOOL_MSG_TSINFO_GET``
++  ``ETHTOOL_GET_TS_INFO``             n/a
+   ``ETHTOOL_GMODULEINFO``             n/a
+   ``ETHTOOL_GMODULEEEPROM``           n/a
+-  ``ETHTOOL_GEEE``                    ``ETHTOOL_MSG_EEE_GET``
+-  ``ETHTOOL_SEEE``                    ``ETHTOOL_MSG_EEE_SET``
++  ``ETHTOOL_GEEE``                    n/a
++  ``ETHTOOL_SEEE``                    n/a
+   ``ETHTOOL_GRSSH``                   n/a
+   ``ETHTOOL_SRSSH``                   n/a
+   ``ETHTOOL_GTUNABLE``                n/a
+   ``ETHTOOL_STUNABLE``                n/a
+   ``ETHTOOL_GPHYSTATS``               n/a
+   ``ETHTOOL_PERQUEUE``                n/a
+-  ``ETHTOOL_GLINKSETTINGS``           ``ETHTOOL_MSG_LINKINFO_GET``
+-                                      ``ETHTOOL_MSG_LINKMODES_GET``
+-  ``ETHTOOL_SLINKSETTINGS``           ``ETHTOOL_MSG_LINKINFO_SET``
+-                                      ``ETHTOOL_MSG_LINKMODES_SET``
++  ``ETHTOOL_GLINKSETTINGS``           n/a
++  ``ETHTOOL_SLINKSETTINGS``           n/a
+   ``ETHTOOL_PHY_GTUNABLE``            n/a
+   ``ETHTOOL_PHY_STUNABLE``            n/a
+   ``ETHTOOL_GFECPARAM``               n/a
+   ``ETHTOOL_SFECPARAM``               n/a
+-  n/a                                 ''ETHTOOL_MSG_CABLE_TEST_ACT''
+-  n/a                                 ''ETHTOOL_MSG_CABLE_TEST_TDR_ACT''
+-  n/a                                 ``ETHTOOL_MSG_TUNNEL_INFO_GET``
+   =================================== =====================================
+diff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst
+index 3786f3b7274c..510d4c45270d 100644
+--- a/Documentation/networking/index.rst
++++ b/Documentation/networking/index.rst
+@@ -11,9 +11,13 @@ Contents:
+    batman-adv
+    can
+    can_ucan_protocol
+-   dpaa2/index
+-   e100
+-   e1000
++   device_drivers/index
++   dsa/index
++   devlink-info-versions
++   devlink-trap
++   devlink-trap-netdevsim
++   ethtool-netlink
++   ieee802154
+    j1939
+    kapi
+    z8530book
+diff --git a/include/linux/ethtool_netlink.h b/include/linux/ethtool_netlink.h
+new file mode 100644
+index 000000000000..f27e92b5f344
+--- /dev/null
++++ b/include/linux/ethtool_netlink.h
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef _LINUX_ETHTOOL_NETLINK_H_
++#define _LINUX_ETHTOOL_NETLINK_H_
++
++#include <uapi/linux/ethtool_netlink.h>
++#include <linux/ethtool.h>
++
++#endif /* _LINUX_ETHTOOL_NETLINK_H_ */
+diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
+new file mode 100644
+index 000000000000..3c93276ba066
+--- /dev/null
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -0,0 +1,36 @@
++/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
++/*
++ * include/uapi/linux/ethtool_netlink.h - netlink interface for ethtool
++ *
++ * See Documentation/networking/ethtool-netlink.txt in kernel source tree for
++ * doucumentation of the interface.
++ */
++
++#ifndef _UAPI_LINUX_ETHTOOL_NETLINK_H_
++#define _UAPI_LINUX_ETHTOOL_NETLINK_H_
++
++#include <linux/ethtool.h>
++
++/* message types - userspace to kernel */
++enum {
++	ETHTOOL_MSG_USER_NONE,
++
++	/* add new constants above here */
++	__ETHTOOL_MSG_USER_CNT,
++	ETHTOOL_MSG_USER_MAX = __ETHTOOL_MSG_USER_CNT - 1
++};
++
++/* message types - kernel to userspace */
++enum {
++	ETHTOOL_MSG_KERNEL_NONE,
++
++	/* add new constants above here */
++	__ETHTOOL_MSG_KERNEL_CNT,
++	ETHTOOL_MSG_KERNEL_MAX = __ETHTOOL_MSG_KERNEL_CNT - 1
++};
++
++/* generic netlink info */
++#define ETHTOOL_GENL_NAME "ethtool"
++#define ETHTOOL_GENL_VERSION 1
++
++#endif /* _UAPI_LINUX_ETHTOOL_NETLINK_H_ */
+diff --git a/net/Kconfig b/net/Kconfig
+index 4bef62b4c806..a279f66876c9 100644
+--- a/net/Kconfig
++++ b/net/Kconfig
+@@ -443,6 +443,14 @@ config FAILOVER
+ 	  migration of VMs with direct attached VFs by failing over to the
+ 	  paravirtual datapath when the VF is unplugged.
+ 
++config ETHTOOL_NETLINK
++	bool "Netlink interface for ethtool"
++	default y
++	help
++	  An alternative userspace interface for ethtool based on generic
++	  netlink. It provides better extensibility and some new features,
++	  e.g. notification messages.
++
+ endif   # if NET
+ 
+ # Used by archs to tell that they support BPF JIT compiler plus which flavour.
+diff --git a/net/ethtool/Makefile b/net/ethtool/Makefile
+index f68387618973..59d5ee230c29 100644
+--- a/net/ethtool/Makefile
++++ b/net/ethtool/Makefile
+@@ -1,3 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ 
+-obj-y		+= ioctl.o common.o
++obj-y				+= ioctl.o common.o
++
++obj-$(CONFIG_ETHTOOL_NETLINK)	+= ethtool_nl.o
++
++ethtool_nl-y	:= netlink.o
+diff --git a/net/ethtool/netlink.c b/net/ethtool/netlink.c
+new file mode 100644
+index 000000000000..59e1ebde2f15
+--- /dev/null
++++ b/net/ethtool/netlink.c
+@@ -0,0 +1,33 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include <linux/ethtool_netlink.h>
++#include "netlink.h"
++
++/* genetlink setup */
++
++static const struct genl_ops ethtool_genl_ops[] = {
++};
++
++static struct genl_family ethtool_genl_family = {
++	.name		= ETHTOOL_GENL_NAME,
++	.version	= ETHTOOL_GENL_VERSION,
++	.netnsok	= true,
++	.parallel_ops	= true,
++	.ops		= ethtool_genl_ops,
++	.n_ops		= ARRAY_SIZE(ethtool_genl_ops),
++};
++
++/* module setup */
++
++static int __init ethnl_init(void)
++{
++	int ret;
++
++	ret = genl_register_family(&ethtool_genl_family);
++	if (WARN(ret < 0, "ethtool: genetlink family registration failed"))
++		return ret;
++
++	return 0;
++}
++
++subsys_initcall(ethnl_init);
+diff --git a/net/ethtool/netlink.h b/net/ethtool/netlink.h
+new file mode 100644
+index 000000000000..e4220780d368
+--- /dev/null
++++ b/net/ethtool/netlink.h
+@@ -0,0 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef _NET_ETHTOOL_NETLINK_H
++#define _NET_ETHTOOL_NETLINK_H
++
++#include <linux/ethtool_netlink.h>
++#include <linux/netdevice.h>
++#include <net/genetlink.h>
++
++#endif /* _NET_ETHTOOL_NETLINK_H */
+-- 
+2.34.1
+
diff --git a/patches/0523-ethtool-helper-functions-for-netlink-interface.patch b/patches/0523-ethtool-helper-functions-for-netlink-interface.patch
new file mode 100644
index 0000000..c1aff8e
--- /dev/null
+++ b/patches/0523-ethtool-helper-functions-for-netlink-interface.patch
@@ -0,0 +1,497 @@
+From 7e87f8157790f29cd39bd193db294eec19ecf6e5 Mon Sep 17 00:00:00 2001
+From: Michal Kubecek <mkubecek@suse.cz>
+Date: Fri, 27 Dec 2019 15:55:23 +0100
+Subject: [PATCH 162/283] ethtool: helper functions for netlink interface
+
+mainline inclusion
+from mainline-v5.6-rc1
+commit 041b1c5d4a53e97fc9e029ae32469552ca12cb9b
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=041b1c5d4a53e97fc9e029ae32469552ca12cb9b
+
+--------------------------------
+
+Add common request/reply header definition and helpers to parse request
+header and fill reply header. Provide ethnl_update_* helpers to update
+structure members from request attributes (to be used for *_SET requests).
+
+Signed-off-by: Michal Kubecek <mkubecek@suse.cz>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ include/net/netlink.h                |   6 +
+ include/uapi/linux/ethtool_netlink.h |  21 +++
+ include/uapi/linux/if.h              |   1 +
+ net/ethtool/netlink.c                | 166 ++++++++++++++++++++++
+ net/ethtool/netlink.h                | 205 +++++++++++++++++++++++++++
+ 5 files changed, 399 insertions(+)
+
+diff --git a/include/net/netlink.h b/include/net/netlink.h
+index 39e1d875d507..d6e48d6ad67d 100644
+--- a/include/net/netlink.h
++++ b/include/net/netlink.h
+@@ -173,6 +173,7 @@ enum {
+ 	NLA_MSECS,
+ 	NLA_NESTED,
+ 	NLA_NESTED_COMPAT,
++	NLA_NESTED_ARRAY,
+ 	NLA_NUL_STRING,
+ 	NLA_BINARY,
+ 	NLA_S8,
+@@ -180,7 +181,12 @@ enum {
+ 	NLA_S32,
+ 	NLA_S64,
+ 	NLA_BITFIELD32,
++	NLA_REJECT,
++	NLA_EXACT_LEN,
++	NLA_EXACT_LEN_WARN,
++	NLA_MIN_LEN,
+ 	__NLA_TYPE_MAX,
++
+ };
+ 
+ #define NLA_TYPE_MAX (__NLA_TYPE_MAX - 1)
+diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
+index 3c93276ba066..82fc3b5f41c9 100644
+--- a/include/uapi/linux/ethtool_netlink.h
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -29,6 +29,27 @@ enum {
+ 	ETHTOOL_MSG_KERNEL_MAX = __ETHTOOL_MSG_KERNEL_CNT - 1
+ };
+ 
++/* request header */
++
++/* use compact bitsets in reply */
++#define ETHTOOL_FLAG_COMPACT_BITSETS	(1 << 0)
++/* provide optional reply for SET or ACT requests */
++#define ETHTOOL_FLAG_OMIT_REPLY	(1 << 1)
++
++#define ETHTOOL_FLAG_ALL (ETHTOOL_FLAG_COMPACT_BITSETS | \
++			  ETHTOOL_FLAG_OMIT_REPLY)
++
++enum {
++	ETHTOOL_A_HEADER_UNSPEC,
++	ETHTOOL_A_HEADER_DEV_INDEX,		/* u32 */
++	ETHTOOL_A_HEADER_DEV_NAME,		/* string */
++	ETHTOOL_A_HEADER_FLAGS,			/* u32 - ETHTOOL_FLAG_* */
++
++	/* add new constants above here */
++	__ETHTOOL_A_HEADER_CNT,
++	ETHTOOL_A_HEADER_MAX = __ETHTOOL_A_HEADER_CNT - 1
++};
++
+ /* generic netlink info */
+ #define ETHTOOL_GENL_NAME "ethtool"
+ #define ETHTOOL_GENL_VERSION 1
+diff --git a/include/uapi/linux/if.h b/include/uapi/linux/if.h
+index 7fea0fd7d6f5..4bf33344aab1 100644
+--- a/include/uapi/linux/if.h
++++ b/include/uapi/linux/if.h
+@@ -33,6 +33,7 @@
+ #define	IFNAMSIZ	16
+ #endif /* __UAPI_DEF_IF_IFNAMSIZ */
+ #define	IFALIASZ	256
++#define	ALTIFNAMSIZ	128
+ #include <linux/hdlc/ioctl.h>
+ 
+ /* For glibc compatibility. An empty enum does not compile. */
+diff --git a/net/ethtool/netlink.c b/net/ethtool/netlink.c
+index 59e1ebde2f15..aef882e0c3f5 100644
+--- a/net/ethtool/netlink.c
++++ b/net/ethtool/netlink.c
+@@ -1,8 +1,174 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ 
++#include <net/sock.h>
+ #include <linux/ethtool_netlink.h>
+ #include "netlink.h"
+ 
++static struct genl_family ethtool_genl_family;
++
++static const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_MAX + 1] = {
++	[ETHTOOL_A_HEADER_UNSPEC]	= { .type = NLA_REJECT },
++	[ETHTOOL_A_HEADER_DEV_INDEX]	= { .type = NLA_U32 },
++	[ETHTOOL_A_HEADER_DEV_NAME]	= { .type = NLA_NUL_STRING,
++					    .len = ALTIFNAMSIZ - 1 },
++	[ETHTOOL_A_HEADER_FLAGS]	= { .type = NLA_U32 },
++};
++
++/**
++ * ethnl_parse_header() - parse request header
++ * @req_info:    structure to put results into
++ * @header:      nest attribute with request header
++ * @net:         request netns
++ * @extack:      netlink extack for error reporting
++ * @require_dev: fail if no device identified in header
++ *
++ * Parse request header in nested attribute @nest and puts results into
++ * the structure pointed to by @req_info. Extack from @info is used for error
++ * reporting. If req_info->dev is not null on return, reference to it has
++ * been taken. If error is returned, *req_info is null initialized and no
++ * reference is held.
++ *
++ * Return: 0 on success or negative error code
++ */
++int ethnl_parse_header(struct ethnl_req_info *req_info,
++		       const struct nlattr *header, struct net *net,
++		       struct netlink_ext_ack *extack, bool require_dev)
++{
++	struct nlattr *tb[ETHTOOL_A_HEADER_MAX + 1];
++	const struct nlattr *devname_attr;
++	struct net_device *dev = NULL;
++	int ret;
++
++	if (!header) {
++		NL_SET_ERR_MSG(extack, "request header missing");
++		return -EINVAL;
++	}
++	ret = nla_parse_nested(tb, ETHTOOL_A_HEADER_MAX, header,
++			       ethnl_header_policy, extack);
++	if (ret < 0)
++		return ret;
++	devname_attr = tb[ETHTOOL_A_HEADER_DEV_NAME];
++
++	if (tb[ETHTOOL_A_HEADER_DEV_INDEX]) {
++		u32 ifindex = nla_get_u32(tb[ETHTOOL_A_HEADER_DEV_INDEX]);
++
++		dev = dev_get_by_index(net, ifindex);
++		if (!dev) {
++			NL_SET_ERR_MSG_ATTR(extack,
++					    tb[ETHTOOL_A_HEADER_DEV_INDEX],
++					    "no device matches ifindex");
++			return -ENODEV;
++		}
++		/* if both ifindex and ifname are passed, they must match */
++		if (devname_attr &&
++		    strncmp(dev->name, nla_data(devname_attr), IFNAMSIZ)) {
++			dev_put(dev);
++			NL_SET_ERR_MSG_ATTR(extack, header,
++					    "ifindex and name do not match");
++			return -ENODEV;
++		}
++	} else if (devname_attr) {
++		dev = dev_get_by_name(net, nla_data(devname_attr));
++		if (!dev) {
++			NL_SET_ERR_MSG_ATTR(extack, devname_attr,
++					    "no device matches name");
++			return -ENODEV;
++		}
++	} else if (require_dev) {
++		NL_SET_ERR_MSG_ATTR(extack, header,
++				    "neither ifindex nor name specified");
++		return -EINVAL;
++	}
++
++	if (dev && !netif_device_present(dev)) {
++		dev_put(dev);
++		NL_SET_ERR_MSG(extack, "device not present");
++		return -ENODEV;
++	}
++
++	req_info->dev = dev;
++	if (tb[ETHTOOL_A_HEADER_FLAGS])
++		req_info->flags = nla_get_u32(tb[ETHTOOL_A_HEADER_FLAGS]);
++
++	return 0;
++}
++
++/**
++ * ethnl_fill_reply_header() - Put common header into a reply message
++ * @skb:      skb with the message
++ * @dev:      network device to describe in header
++ * @attrtype: attribute type to use for the nest
++ *
++ * Create a nested attribute with attributes describing given network device.
++ *
++ * Return: 0 on success, error value (-EMSGSIZE only) on error
++ */
++int ethnl_fill_reply_header(struct sk_buff *skb, struct net_device *dev,
++			    u16 attrtype)
++{
++	struct nlattr *nest;
++
++	if (!dev)
++		return 0;
++	nest = nla_nest_start(skb, attrtype);
++	if (!nest)
++		return -EMSGSIZE;
++
++	if (nla_put_u32(skb, ETHTOOL_A_HEADER_DEV_INDEX, (u32)dev->ifindex) ||
++	    nla_put_string(skb, ETHTOOL_A_HEADER_DEV_NAME, dev->name))
++		goto nla_put_failure;
++	/* If more attributes are put into reply header, ethnl_header_size()
++	 * must be updated to account for them.
++	 */
++
++	nla_nest_end(skb, nest);
++	return 0;
++
++nla_put_failure:
++	nla_nest_cancel(skb, nest);
++	return -EMSGSIZE;
++}
++
++/**
++ * ethnl_reply_init() - Create skb for a reply and fill device identification
++ * @payload: payload length (without netlink and genetlink header)
++ * @dev:     device the reply is about (may be null)
++ * @cmd:     ETHTOOL_MSG_* message type for reply
++ * @info:    genetlink info of the received packet we respond to
++ * @ehdrp:   place to store payload pointer returned by genlmsg_new()
++ *
++ * Return: pointer to allocated skb on success, NULL on error
++ */
++struct sk_buff *ethnl_reply_init(size_t payload, struct net_device *dev, u8 cmd,
++				 u16 hdr_attrtype, struct genl_info *info,
++				 void **ehdrp)
++{
++	struct sk_buff *skb;
++
++	skb = genlmsg_new(payload, GFP_KERNEL);
++	if (!skb)
++		goto err;
++	*ehdrp = genlmsg_put_reply(skb, info, &ethtool_genl_family, 0, cmd);
++	if (!*ehdrp)
++		goto err_free;
++
++	if (dev) {
++		int ret;
++
++		ret = ethnl_fill_reply_header(skb, dev, hdr_attrtype);
++		if (ret < 0)
++			goto err_free;
++	}
++	return skb;
++
++err_free:
++	nlmsg_free(skb);
++err:
++	if (info)
++		GENL_SET_ERR_MSG(info, "failed to setup reply message");
++	return NULL;
++}
++
+ /* genetlink setup */
+ 
+ static const struct genl_ops ethtool_genl_ops[] = {
+diff --git a/net/ethtool/netlink.h b/net/ethtool/netlink.h
+index e4220780d368..05d7183da894 100644
+--- a/net/ethtool/netlink.h
++++ b/net/ethtool/netlink.h
+@@ -6,5 +6,210 @@
+ #include <linux/ethtool_netlink.h>
+ #include <linux/netdevice.h>
+ #include <net/genetlink.h>
++#include <net/sock.h>
++
++struct ethnl_req_info;
++
++int ethnl_parse_header(struct ethnl_req_info *req_info,
++		       const struct nlattr *nest, struct net *net,
++		       struct netlink_ext_ack *extack, bool require_dev);
++int ethnl_fill_reply_header(struct sk_buff *skb, struct net_device *dev,
++			    u16 attrtype);
++struct sk_buff *ethnl_reply_init(size_t payload, struct net_device *dev, u8 cmd,
++				 u16 hdr_attrtype, struct genl_info *info,
++				 void **ehdrp);
++
++/**
++ * ethnl_strz_size() - calculate attribute length for fixed size string
++ * @s: ETH_GSTRING_LEN sized string (may not be null terminated)
++ *
++ * Return: total length of an attribute with null terminated string from @s
++ */
++static inline int ethnl_strz_size(const char *s)
++{
++	return nla_total_size(strnlen(s, ETH_GSTRING_LEN) + 1);
++}
++
++/**
++ * ethnl_put_strz() - put string attribute with fixed size string
++ * @skb:     skb with the message
++ * @attrype: attribute type
++ * @s:       ETH_GSTRING_LEN sized string (may not be null terminated)
++ *
++ * Puts an attribute with null terminated string from @s into the message.
++ *
++ * Return: 0 on success, negative error code on failure
++ */
++static inline int ethnl_put_strz(struct sk_buff *skb, u16 attrtype,
++				 const char *s)
++{
++	unsigned int len = strnlen(s, ETH_GSTRING_LEN);
++	struct nlattr *attr;
++
++	attr = nla_reserve(skb, attrtype, len + 1);
++	if (!attr)
++		return -EMSGSIZE;
++
++	memcpy(nla_data(attr), s, len);
++	((char *)nla_data(attr))[len] = '\0';
++	return 0;
++}
++
++/**
++ * ethnl_update_u32() - update u32 value from NLA_U32 attribute
++ * @dst:  value to update
++ * @attr: netlink attribute with new value or null
++ * @mod:  pointer to bool for modification tracking
++ *
++ * Copy the u32 value from NLA_U32 netlink attribute @attr into variable
++ * pointed to by @dst; do nothing if @attr is null. Bool pointed to by @mod
++ * is set to true if this function changed the value of *dst, otherwise it
++ * is left as is.
++ */
++static inline void ethnl_update_u32(u32 *dst, const struct nlattr *attr,
++				    bool *mod)
++{
++	u32 val;
++
++	if (!attr)
++		return;
++	val = nla_get_u32(attr);
++	if (*dst == val)
++		return;
++
++	*dst = val;
++	*mod = true;
++}
++
++/**
++ * ethnl_update_u8() - update u8 value from NLA_U8 attribute
++ * @dst:  value to update
++ * @attr: netlink attribute with new value or null
++ * @mod:  pointer to bool for modification tracking
++ *
++ * Copy the u8 value from NLA_U8 netlink attribute @attr into variable
++ * pointed to by @dst; do nothing if @attr is null. Bool pointed to by @mod
++ * is set to true if this function changed the value of *dst, otherwise it
++ * is left as is.
++ */
++static inline void ethnl_update_u8(u8 *dst, const struct nlattr *attr,
++				   bool *mod)
++{
++	u8 val;
++
++	if (!attr)
++		return;
++	val = nla_get_u8(attr);
++	if (*dst == val)
++		return;
++
++	*dst = val;
++	*mod = true;
++}
++
++/**
++ * ethnl_update_bool32() - update u32 used as bool from NLA_U8 attribute
++ * @dst:  value to update
++ * @attr: netlink attribute with new value or null
++ * @mod:  pointer to bool for modification tracking
++ *
++ * Use the u8 value from NLA_U8 netlink attribute @attr to set u32 variable
++ * pointed to by @dst to 0 (if zero) or 1 (if not); do nothing if @attr is
++ * null. Bool pointed to by @mod is set to true if this function changed the
++ * logical value of *dst, otherwise it is left as is.
++ */
++static inline void ethnl_update_bool32(u32 *dst, const struct nlattr *attr,
++				       bool *mod)
++{
++	u8 val;
++
++	if (!attr)
++		return;
++	val = !!nla_get_u8(attr);
++	if (!!*dst == val)
++		return;
++
++	*dst = val;
++	*mod = true;
++}
++
++/**
++ * ethnl_update_binary() - update binary data from NLA_BINARY atribute
++ * @dst:  value to update
++ * @len:  destination buffer length
++ * @attr: netlink attribute with new value or null
++ * @mod:  pointer to bool for modification tracking
++ *
++ * Use the u8 value from NLA_U8 netlink attribute @attr to rewrite data block
++ * of length @len at @dst by attribute payload; do nothing if @attr is null.
++ * Bool pointed to by @mod is set to true if this function changed the logical
++ * value of *dst, otherwise it is left as is.
++ */
++static inline void ethnl_update_binary(void *dst, unsigned int len,
++				       const struct nlattr *attr, bool *mod)
++{
++	if (!attr)
++		return;
++	if (nla_len(attr) < len)
++		len = nla_len(attr);
++	if (!memcmp(dst, nla_data(attr), len))
++		return;
++
++	memcpy(dst, nla_data(attr), len);
++	*mod = true;
++}
++
++/**
++ * ethnl_update_bitfield32() - update u32 value from NLA_BITFIELD32 attribute
++ * @dst:  value to update
++ * @attr: netlink attribute with new value or null
++ * @mod:  pointer to bool for modification tracking
++ *
++ * Update bits in u32 value which are set in attribute's mask to values from
++ * attribute's value. Do nothing if @attr is null or the value wouldn't change;
++ * otherwise, set bool pointed to by @mod to true.
++ */
++static inline void ethnl_update_bitfield32(u32 *dst, const struct nlattr *attr,
++					   bool *mod)
++{
++	struct nla_bitfield32 change;
++	u32 newval;
++
++	if (!attr)
++		return;
++	change = nla_get_bitfield32(attr);
++	newval = (*dst & ~change.selector) | (change.value & change.selector);
++	if (*dst == newval)
++		return;
++
++	*dst = newval;
++	*mod = true;
++}
++
++/**
++ * ethnl_reply_header_size() - total size of reply header
++ *
++ * This is an upper estimate so that we do not need to hold RTNL lock longer
++ * than necessary (to prevent rename between size estimate and composing the
++ * message). Accounts only for device ifindex and name as those are the only
++ * attributes ethnl_fill_reply_header() puts into the reply header.
++ */
++static inline unsigned int ethnl_reply_header_size(void)
++{
++	return nla_total_size(nla_total_size(sizeof(u32)) +
++			      nla_total_size(IFNAMSIZ));
++}
++
++/**
++ * struct ethnl_req_info - base type of request information for GET requests
++ * @dev:   network device the request is for (may be null)
++ * @flags: request flags common for all request types
++ *
++ * This is a common base, additional members may follow after this structure.
++ */
++struct ethnl_req_info {
++	struct net_device	*dev;
++	u32			flags;
++};
+ 
+ #endif /* _NET_ETHTOOL_NETLINK_H */
+-- 
+2.34.1
+
diff --git a/patches/0524-ethtool-provide-ring-sizes-with-RINGS_GET-request.patch b/patches/0524-ethtool-provide-ring-sizes-with-RINGS_GET-request.patch
new file mode 100644
index 0000000..dc33008
--- /dev/null
+++ b/patches/0524-ethtool-provide-ring-sizes-with-RINGS_GET-request.patch
@@ -0,0 +1,1342 @@
+From 1421bb3e1bcf8b136d2e53885dfe5f7257b5fa48 Mon Sep 17 00:00:00 2001
+From: Michal Kubecek <mkubecek@suse.cz>
+Date: Thu, 12 Mar 2020 21:08:23 +0100
+Subject: [PATCH 163/283] ethtool: provide ring sizes with RINGS_GET request
+
+mainline inclusion
+from mainline-v5.7-rc1
+commit e4a1717b677c5cb285e9b425c569e261084a484c
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e4a1717b677c5cb285e9b425c569e261084a484c
+
+--------------------------------
+
+Implement RINGS_GET request to get ring sizes of a network device. These
+are traditionally available via ETHTOOL_GRINGPARAM ioctl request.
+
+Omit attributes for ring types which are not supported by driver or device
+(zero reported for maximum).
+
+v2: (all suggested by Jakub Kicinski)
+  - minor cleanup in rings_prepare_data()
+  - more descriptive rings_reply_size()
+  - omit attributes with zero max size
+
+Signed-off-by: Michal Kubecek <mkubecek@suse.cz>
+Reviewed-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	Documentation/networking/ethtool-netlink.rst
+	include/uapi/linux/ethtool_netlink.h
+	net/ethtool/Makefile
+	net/ethtool/netlink.c
+	net/ethtool/netlink.h
+---
+ Documentation/networking/ethtool-netlink.rst |  38 +-
+ include/linux/ethtool_netlink.h              |   4 +
+ include/linux/netlink.h                      |  14 +
+ include/uapi/linux/ethtool_netlink.h         | 239 +++++++-
+ net/ethtool/Makefile                         |   2 +-
+ net/ethtool/netlink.c                        | 601 +++++++++++++++++++
+ net/ethtool/netlink.h                        | 118 ++++
+ net/ethtool/rings.c                          | 108 ++++
+ net/netlink/af_netlink.c                     |  12 +-
+ 9 files changed, 1132 insertions(+), 4 deletions(-)
+ create mode 100644 net/ethtool/rings.c
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+index fc550a3e82b1..32a92edfec14 100644
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -175,6 +175,18 @@ according to message purpose:
+   ``_NTF``          kernel notification
+   ==============    ======================================
+ 
++Userspace to kernel:
++
++  ===================================== ================================
++  ``ETHTOOL_MSG_RINGS_GET``             get ring sizes
++  ===================================== ================================
++
++Kernel to userspace:
++
++  ===================================== =================================
++  ``ETHTOOL_MSG_RINGS_GET_REPLY``       ring sizes
++  ===================================== =================================
++
+ ``GET`` requests are sent by userspace applications to retrieve device
+ information. They usually do not contain any message specific attributes.
+ Kernel replies with corresponding "GET_REPLY" message. For most types, ``GET``
+@@ -205,6 +217,30 @@ an ``ACT_REPLY`` message. Performing an action also triggers a notification
+ 
+ Later sections describe the format and semantics of these messages.
+ 
++RINGS_GET
++=========
++
++Gets ring sizes like ``ETHTOOL_GRINGPARAM`` ioctl request.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_RINGS_HEADER``            nested  request header
++  ====================================  ======  ==========================
++
++Kernel response contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_RINGS_HEADER``            nested  reply header
++  ``ETHTOOL_A_RINGS_RX_MAX``            u32     max size of RX ring
++  ``ETHTOOL_A_RINGS_RX_MINI_MAX``       u32     max size of RX mini ring
++  ``ETHTOOL_A_RINGS_RX_JUMBO_MAX``      u32     max size of RX jumbo ring
++  ``ETHTOOL_A_RINGS_TX_MAX``            u32     max size of TX ring
++  ``ETHTOOL_A_RINGS_RX``                u32     size of RX ring
++  ``ETHTOOL_A_RINGS_RX_MINI``           u32     size of RX mini ring
++  ``ETHTOOL_A_RINGS_RX_JUMBO``          u32     size of RX jumbo ring
++  ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
++  ====================================  ======  ==========================
+ 
+ Request translation
+ ===================
+@@ -230,7 +266,7 @@ have their netlink replacement yet.
+   ``ETHTOOL_SEEPROM``                 n/a
+   ``ETHTOOL_GCOALESCE``               n/a
+   ``ETHTOOL_SCOALESCE``               n/a
+-  ``ETHTOOL_GRINGPARAM``              n/a
++  ``ETHTOOL_GRINGPARAM``              ``ETHTOOL_MSG_RINGS_GET``
+   ``ETHTOOL_SRINGPARAM``              n/a
+   ``ETHTOOL_GPAUSEPARAM``             n/a
+   ``ETHTOOL_SPAUSEPARAM``             n/a
+diff --git a/include/linux/ethtool_netlink.h b/include/linux/ethtool_netlink.h
+index f27e92b5f344..dd9a51057c6f 100644
+--- a/include/linux/ethtool_netlink.h
++++ b/include/linux/ethtool_netlink.h
+@@ -6,4 +6,8 @@
+ #include <uapi/linux/ethtool_netlink.h>
+ #include <linux/ethtool.h>
+ 
++enum ethtool_multicast_groups {
++	ETHNL_MCGRP_MONITOR,
++};
++
+ #endif /* _LINUX_ETHTOOL_NETLINK_H_ */
+diff --git a/include/linux/netlink.h b/include/linux/netlink.h
+index 71f121b66ca8..b25b2f427127 100644
+--- a/include/linux/netlink.h
++++ b/include/linux/netlink.h
+@@ -176,10 +176,24 @@ struct netlink_callback {
+ 	void			*data;
+ 	/* the module that dump function belong to */
+ 	struct module		*module;
++#ifndef __GENKSYMS__
++	struct netlink_ext_ack  *extack;
++#endif
+ 	u16			family;
+ 	u16			min_dump_alloc;
+ 	unsigned int		prev_seq, seq;
++#ifdef __GENKSYMS__
+ 	long			args[6];
++#else
++	union {
++		u8              ctx[48];
++
++		/* args is deprecated. Cast a struct over ctx instead
++		 * for proper type safety.
++		 */
++		long            args[6];
++	};
++#endif
+ };
+ 
+ struct netlink_notify {
+diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
+index 82fc3b5f41c9..496e1d4805ee 100644
+--- a/include/uapi/linux/ethtool_netlink.h
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -14,6 +14,21 @@
+ /* message types - userspace to kernel */
+ enum {
+ 	ETHTOOL_MSG_USER_NONE,
++	ETHTOOL_MSG_STRSET_GET,
++	ETHTOOL_MSG_LINKINFO_GET,
++	ETHTOOL_MSG_LINKINFO_SET,
++	ETHTOOL_MSG_LINKMODES_GET,
++	ETHTOOL_MSG_LINKMODES_SET,
++	ETHTOOL_MSG_LINKSTATE_GET,
++	ETHTOOL_MSG_DEBUG_GET,
++	ETHTOOL_MSG_DEBUG_SET,
++	ETHTOOL_MSG_WOL_GET,
++	ETHTOOL_MSG_WOL_SET,
++	ETHTOOL_MSG_FEATURES_GET,
++	ETHTOOL_MSG_FEATURES_SET,
++	ETHTOOL_MSG_PRIVFLAGS_GET,
++	ETHTOOL_MSG_PRIVFLAGS_SET,
++	ETHTOOL_MSG_RINGS_GET,
+ 
+ 	/* add new constants above here */
+ 	__ETHTOOL_MSG_USER_CNT,
+@@ -23,7 +38,23 @@ enum {
+ /* message types - kernel to userspace */
+ enum {
+ 	ETHTOOL_MSG_KERNEL_NONE,
+-
++	ETHTOOL_MSG_STRSET_GET_REPLY,
++	ETHTOOL_MSG_LINKINFO_GET_REPLY,
++	ETHTOOL_MSG_LINKINFO_NTF,
++	ETHTOOL_MSG_LINKMODES_GET_REPLY,
++	ETHTOOL_MSG_LINKMODES_NTF,
++	ETHTOOL_MSG_LINKSTATE_GET_REPLY,
++	ETHTOOL_MSG_DEBUG_GET_REPLY,
++	ETHTOOL_MSG_DEBUG_NTF,
++	ETHTOOL_MSG_WOL_GET_REPLY,
++	ETHTOOL_MSG_WOL_NTF,
++	ETHTOOL_MSG_FEATURES_GET_REPLY,
++	ETHTOOL_MSG_FEATURES_SET_REPLY,
++	ETHTOOL_MSG_FEATURES_NTF,
++	ETHTOOL_MSG_PRIVFLAGS_GET_REPLY,
++	ETHTOOL_MSG_PRIVFLAGS_NTF,
++	ETHTOOL_MSG_RINGS_GET_REPLY,
++	ETHTOOL_MSG_RINGS_NTF,
+ 	/* add new constants above here */
+ 	__ETHTOOL_MSG_KERNEL_CNT,
+ 	ETHTOOL_MSG_KERNEL_MAX = __ETHTOOL_MSG_KERNEL_CNT - 1
+@@ -50,8 +81,214 @@ enum {
+ 	ETHTOOL_A_HEADER_MAX = __ETHTOOL_A_HEADER_CNT - 1
+ };
+ 
++/* bit sets */
++
++enum {
++	ETHTOOL_A_BITSET_BIT_UNSPEC,
++	ETHTOOL_A_BITSET_BIT_INDEX,		/* u32 */
++	ETHTOOL_A_BITSET_BIT_NAME,		/* string */
++	ETHTOOL_A_BITSET_BIT_VALUE,		/* flag */
++
++	/* add new constants above here */
++	__ETHTOOL_A_BITSET_BIT_CNT,
++	ETHTOOL_A_BITSET_BIT_MAX = __ETHTOOL_A_BITSET_BIT_CNT - 1
++};
++
++enum {
++	ETHTOOL_A_BITSET_BITS_UNSPEC,
++	ETHTOOL_A_BITSET_BITS_BIT,		/* nest - _A_BITSET_BIT_* */
++
++	/* add new constants above here */
++	__ETHTOOL_A_BITSET_BITS_CNT,
++	ETHTOOL_A_BITSET_BITS_MAX = __ETHTOOL_A_BITSET_BITS_CNT - 1
++};
++
++enum {
++	ETHTOOL_A_BITSET_UNSPEC,
++	ETHTOOL_A_BITSET_NOMASK,		/* flag */
++	ETHTOOL_A_BITSET_SIZE,			/* u32 */
++	ETHTOOL_A_BITSET_BITS,			/* nest - _A_BITSET_BITS_* */
++	ETHTOOL_A_BITSET_VALUE,			/* binary */
++	ETHTOOL_A_BITSET_MASK,			/* binary */
++
++	/* add new constants above here */
++	__ETHTOOL_A_BITSET_CNT,
++	ETHTOOL_A_BITSET_MAX = __ETHTOOL_A_BITSET_CNT - 1
++};
++
++/* string sets */
++
++enum {
++	ETHTOOL_A_STRING_UNSPEC,
++	ETHTOOL_A_STRING_INDEX,			/* u32 */
++	ETHTOOL_A_STRING_VALUE,			/* string */
++
++	/* add new constants above here */
++	__ETHTOOL_A_STRING_CNT,
++	ETHTOOL_A_STRING_MAX = __ETHTOOL_A_STRING_CNT - 1
++};
++
++enum {
++	ETHTOOL_A_STRINGS_UNSPEC,
++	ETHTOOL_A_STRINGS_STRING,		/* nest - _A_STRINGS_* */
++
++	/* add new constants above here */
++	__ETHTOOL_A_STRINGS_CNT,
++	ETHTOOL_A_STRINGS_MAX = __ETHTOOL_A_STRINGS_CNT - 1
++};
++
++enum {
++	ETHTOOL_A_STRINGSET_UNSPEC,
++	ETHTOOL_A_STRINGSET_ID,			/* u32 */
++	ETHTOOL_A_STRINGSET_COUNT,		/* u32 */
++	ETHTOOL_A_STRINGSET_STRINGS,		/* nest - _A_STRINGS_* */
++
++	/* add new constants above here */
++	__ETHTOOL_A_STRINGSET_CNT,
++	ETHTOOL_A_STRINGSET_MAX = __ETHTOOL_A_STRINGSET_CNT - 1
++};
++
++enum {
++	ETHTOOL_A_STRINGSETS_UNSPEC,
++	ETHTOOL_A_STRINGSETS_STRINGSET,		/* nest - _A_STRINGSET_* */
++
++	/* add new constants above here */
++	__ETHTOOL_A_STRINGSETS_CNT,
++	ETHTOOL_A_STRINGSETS_MAX = __ETHTOOL_A_STRINGSETS_CNT - 1
++};
++
++/* STRSET */
++
++enum {
++	ETHTOOL_A_STRSET_UNSPEC,
++	ETHTOOL_A_STRSET_HEADER,		/* nest - _A_HEADER_* */
++	ETHTOOL_A_STRSET_STRINGSETS,		/* nest - _A_STRINGSETS_* */
++	ETHTOOL_A_STRSET_COUNTS_ONLY,		/* flag */
++
++	/* add new constants above here */
++	__ETHTOOL_A_STRSET_CNT,
++	ETHTOOL_A_STRSET_MAX = __ETHTOOL_A_STRSET_CNT - 1
++};
++
++/* LINKINFO */
++
++enum {
++	ETHTOOL_A_LINKINFO_UNSPEC,
++	ETHTOOL_A_LINKINFO_HEADER,		/* nest - _A_HEADER_* */
++	ETHTOOL_A_LINKINFO_PORT,		/* u8 */
++	ETHTOOL_A_LINKINFO_PHYADDR,		/* u8 */
++	ETHTOOL_A_LINKINFO_TP_MDIX,		/* u8 */
++	ETHTOOL_A_LINKINFO_TP_MDIX_CTRL,	/* u8 */
++	ETHTOOL_A_LINKINFO_TRANSCEIVER,		/* u8 */
++
++	/* add new constants above here */
++	__ETHTOOL_A_LINKINFO_CNT,
++	ETHTOOL_A_LINKINFO_MAX = __ETHTOOL_A_LINKINFO_CNT - 1
++};
++
++/* LINKMODES */
++
++enum {
++	ETHTOOL_A_LINKMODES_UNSPEC,
++	ETHTOOL_A_LINKMODES_HEADER,		/* nest - _A_HEADER_* */
++	ETHTOOL_A_LINKMODES_AUTONEG,		/* u8 */
++	ETHTOOL_A_LINKMODES_OURS,		/* bitset */
++	ETHTOOL_A_LINKMODES_PEER,		/* bitset */
++	ETHTOOL_A_LINKMODES_SPEED,		/* u32 */
++	ETHTOOL_A_LINKMODES_DUPLEX,		/* u8 */
++
++	/* add new constants above here */
++	__ETHTOOL_A_LINKMODES_CNT,
++	ETHTOOL_A_LINKMODES_MAX = __ETHTOOL_A_LINKMODES_CNT - 1
++};
++
++/* LINKSTATE */
++
++enum {
++	ETHTOOL_A_LINKSTATE_UNSPEC,
++	ETHTOOL_A_LINKSTATE_HEADER,		/* nest - _A_HEADER_* */
++	ETHTOOL_A_LINKSTATE_LINK,		/* u8 */
++
++	/* add new constants above here */
++	__ETHTOOL_A_LINKSTATE_CNT,
++	ETHTOOL_A_LINKSTATE_MAX = __ETHTOOL_A_LINKSTATE_CNT - 1
++};
++
++/* DEBUG */
++
++enum {
++	ETHTOOL_A_DEBUG_UNSPEC,
++	ETHTOOL_A_DEBUG_HEADER,			/* nest - _A_HEADER_* */
++	ETHTOOL_A_DEBUG_MSGMASK,		/* bitset */
++
++	/* add new constants above here */
++	__ETHTOOL_A_DEBUG_CNT,
++	ETHTOOL_A_DEBUG_MAX = __ETHTOOL_A_DEBUG_CNT - 1
++};
++
++/* WOL */
++
++enum {
++	ETHTOOL_A_WOL_UNSPEC,
++	ETHTOOL_A_WOL_HEADER,			/* nest - _A_HEADER_* */
++	ETHTOOL_A_WOL_MODES,			/* bitset */
++	ETHTOOL_A_WOL_SOPASS,			/* binary */
++
++	/* add new constants above here */
++	__ETHTOOL_A_WOL_CNT,
++	ETHTOOL_A_WOL_MAX = __ETHTOOL_A_WOL_CNT - 1
++};
++
++/* FEATURES */
++
++enum {
++	ETHTOOL_A_FEATURES_UNSPEC,
++	ETHTOOL_A_FEATURES_HEADER,			/* nest - _A_HEADER_* */
++	ETHTOOL_A_FEATURES_HW,				/* bitset */
++	ETHTOOL_A_FEATURES_WANTED,			/* bitset */
++	ETHTOOL_A_FEATURES_ACTIVE,			/* bitset */
++	ETHTOOL_A_FEATURES_NOCHANGE,			/* bitset */
++
++	/* add new constants above here */
++	__ETHTOOL_A_FEATURES_CNT,
++	ETHTOOL_A_FEATURES_MAX = __ETHTOOL_A_FEATURES_CNT - 1
++};
++
++/* PRIVFLAGS */
++
++enum {
++	ETHTOOL_A_PRIVFLAGS_UNSPEC,
++	ETHTOOL_A_PRIVFLAGS_HEADER,			/* nest - _A_HEADER_* */
++	ETHTOOL_A_PRIVFLAGS_FLAGS,			/* bitset */
++
++	/* add new constants above here */
++	__ETHTOOL_A_PRIVFLAGS_CNT,
++	ETHTOOL_A_PRIVFLAGS_MAX = __ETHTOOL_A_PRIVFLAGS_CNT - 1
++};
++
++/* RINGS */
++
++enum {
++	ETHTOOL_A_RINGS_UNSPEC,
++	ETHTOOL_A_RINGS_HEADER,				/* nest - _A_HEADER_* */
++	ETHTOOL_A_RINGS_RX_MAX,				/* u32 */
++	ETHTOOL_A_RINGS_RX_MINI_MAX,			/* u32 */
++	ETHTOOL_A_RINGS_RX_JUMBO_MAX,			/* u32 */
++	ETHTOOL_A_RINGS_TX_MAX,				/* u32 */
++	ETHTOOL_A_RINGS_RX,				/* u32 */
++	ETHTOOL_A_RINGS_RX_MINI,			/* u32 */
++	ETHTOOL_A_RINGS_RX_JUMBO,			/* u32 */
++	ETHTOOL_A_RINGS_TX,				/* u32 */
++
++	/* add new constants above here */
++	__ETHTOOL_A_RINGS_CNT,
++	ETHTOOL_A_RINGS_MAX = (__ETHTOOL_A_RINGS_CNT - 1)
++};
++
+ /* generic netlink info */
+ #define ETHTOOL_GENL_NAME "ethtool"
+ #define ETHTOOL_GENL_VERSION 1
+ 
++#define ETHTOOL_MCGRP_MONITOR_NAME "monitor"
++
+ #endif /* _UAPI_LINUX_ETHTOOL_NETLINK_H_ */
+diff --git a/net/ethtool/Makefile b/net/ethtool/Makefile
+index 59d5ee230c29..6f1cdf8a57b3 100644
+--- a/net/ethtool/Makefile
++++ b/net/ethtool/Makefile
+@@ -4,4 +4,4 @@ obj-y				+= ioctl.o common.o
+ 
+ obj-$(CONFIG_ETHTOOL_NETLINK)	+= ethtool_nl.o
+ 
+-ethtool_nl-y	:= netlink.o
++ethtool_nl-y	:= netlink.o rings.o
+diff --git a/net/ethtool/netlink.c b/net/ethtool/netlink.c
+index aef882e0c3f5..778bbeb517f5 100644
+--- a/net/ethtool/netlink.c
++++ b/net/ethtool/netlink.c
+@@ -6,6 +6,9 @@
+ 
+ static struct genl_family ethtool_genl_family;
+ 
++static bool ethnl_ok __read_mostly;
++static u32 ethnl_bcast_seq;
++
+ static const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_MAX + 1] = {
+ 	[ETHTOOL_A_HEADER_UNSPEC]	= { .type = NLA_REJECT },
+ 	[ETHTOOL_A_HEADER_DEV_INDEX]	= { .type = NLA_U32 },
+@@ -14,6 +17,85 @@ static const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_MAX + 1] = {
+ 	[ETHTOOL_A_HEADER_FLAGS]	= { .type = NLA_U32 },
+ };
+ 
++/**
++ * ethnl_parse_header_dev_get() - parse request header
++ * @req_info:    structure to put results into
++ * @header:      nest attribute with request header
++ * @net:         request netns
++ * @extack:      netlink extack for error reporting
++ * @require_dev: fail if no device identified in header
++ *
++ * Parse request header in nested attribute @nest and puts results into
++ * the structure pointed to by @req_info. Extack from @info is used for error
++ * reporting. If req_info->dev is not null on return, reference to it has
++ * been taken. If error is returned, *req_info is null initialized and no
++ * reference is held.
++ *
++ * Return: 0 on success or negative error code
++ */
++int ethnl_parse_header_dev_get(struct ethnl_req_info *req_info,
++			       const struct nlattr *header, struct net *net,
++			       struct netlink_ext_ack *extack, bool require_dev)
++{
++	struct nlattr *tb[ETHTOOL_A_HEADER_MAX + 1];
++	const struct nlattr *devname_attr;
++	struct net_device *dev = NULL;
++	int ret;
++
++	if (!header) {
++		NL_SET_ERR_MSG(extack, "request header missing");
++		return -EINVAL;
++	}
++	ret = nla_parse_nested(tb, ETHTOOL_A_HEADER_MAX, header,
++			       ethnl_header_policy, extack);
++	if (ret < 0)
++		return ret;
++	devname_attr = tb[ETHTOOL_A_HEADER_DEV_NAME];
++
++	if (tb[ETHTOOL_A_HEADER_DEV_INDEX]) {
++		u32 ifindex = nla_get_u32(tb[ETHTOOL_A_HEADER_DEV_INDEX]);
++
++		dev = dev_get_by_index(net, ifindex);
++		if (!dev) {
++			NL_SET_ERR_MSG_ATTR(extack,
++					    tb[ETHTOOL_A_HEADER_DEV_INDEX],
++					    "no device matches ifindex");
++			return -ENODEV;
++		}
++		/* if both ifindex and ifname are passed, they must match */
++		if (devname_attr &&
++		    strncmp(dev->name, nla_data(devname_attr), IFNAMSIZ)) {
++			dev_put(dev);
++			NL_SET_ERR_MSG_ATTR(extack, header,
++					    "ifindex and name do not match");
++			return -ENODEV;
++		}
++	} else if (devname_attr) {
++		dev = dev_get_by_name(net, nla_data(devname_attr));
++		if (!dev) {
++			NL_SET_ERR_MSG_ATTR(extack, devname_attr,
++					    "no device matches name");
++			return -ENODEV;
++		}
++	} else if (require_dev) {
++		NL_SET_ERR_MSG_ATTR(extack, header,
++				    "neither ifindex nor name specified");
++		return -EINVAL;
++	}
++
++	if (dev && !netif_device_present(dev)) {
++		dev_put(dev);
++		NL_SET_ERR_MSG(extack, "device not present");
++		return -ENODEV;
++	}
++
++	req_info->dev = dev;
++	if (tb[ETHTOOL_A_HEADER_FLAGS])
++		req_info->flags = nla_get_u32(tb[ETHTOOL_A_HEADER_FLAGS]);
++
++	return 0;
++}
++
+ /**
+  * ethnl_parse_header() - parse request header
+  * @req_info:    structure to put results into
+@@ -169,9 +251,528 @@ struct sk_buff *ethnl_reply_init(size_t payload, struct net_device *dev, u8 cmd,
+ 	return NULL;
+ }
+ 
++static void *ethnl_bcastmsg_put(struct sk_buff *skb, u8 cmd)
++{
++	return genlmsg_put(skb, 0, ++ethnl_bcast_seq, &ethtool_genl_family, 0,
++			   cmd);
++}
++
++static int ethnl_multicast(struct sk_buff *skb, struct net_device *dev)
++{
++	return genlmsg_multicast_netns(&ethtool_genl_family, dev_net(dev), skb,
++				       0, ETHNL_MCGRP_MONITOR, GFP_KERNEL);
++}
++
++/* GET request helpers */
++
++/**
++ * struct ethnl_dump_ctx - context structure for generic dumpit() callback
++ * @ops:        request ops of currently processed message type
++ * @req_info:   parsed request header of processed request
++ * @reply_data: data needed to compose the reply
++ * @pos_hash:   saved iteration position - hashbucket
++ * @pos_idx:    saved iteration position - index
++ *
++ * These parameters are kept in struct netlink_callback as context preserved
++ * between iterations. They are initialized by ethnl_default_start() and used
++ * in ethnl_default_dumpit() and ethnl_default_done().
++ */
++struct ethnl_dump_ctx {
++	const struct ethnl_request_ops	*ops;
++	struct ethnl_req_info		*req_info;
++	struct ethnl_reply_data		*reply_data;
++	int				pos_hash;
++	int				pos_idx;
++};
++
++static const struct ethnl_request_ops *
++ethnl_default_requests[__ETHTOOL_MSG_USER_CNT] = {
++	[ETHTOOL_MSG_RINGS_GET]		= &ethnl_rings_request_ops,
++};
++
++static struct ethnl_dump_ctx *ethnl_dump_context(struct netlink_callback *cb)
++{
++	return (struct ethnl_dump_ctx *)cb->ctx;
++}
++
++/**
++ * ethnl_default_parse() - Parse request message
++ * @req_info:    pointer to structure to put data into
++ * @nlhdr:       pointer to request message header
++ * @net:         request netns
++ * @request_ops: struct request_ops for request type
++ * @extack:      netlink extack for error reporting
++ * @require_dev: fail if no device identified in header
++ *
++ * Parse universal request header and call request specific ->parse_request()
++ * callback (if defined) to parse the rest of the message.
++ *
++ * Return: 0 on success or negative error code
++ */
++static int ethnl_default_parse(struct ethnl_req_info *req_info,
++			       const struct nlmsghdr *nlhdr, struct net *net,
++			       const struct ethnl_request_ops *request_ops,
++			       struct netlink_ext_ack *extack, bool require_dev)
++{
++	struct nlattr **tb;
++	int ret;
++
++	tb = kmalloc_array(request_ops->max_attr + 1, sizeof(tb[0]),
++			   GFP_KERNEL);
++	if (!tb)
++		return -ENOMEM;
++
++	ret = nlmsg_parse(nlhdr, GENL_HDRLEN, tb, request_ops->max_attr,
++			  request_ops->request_policy, extack);
++	if (ret < 0)
++		goto out;
++	ret = ethnl_parse_header_dev_get(req_info, tb[request_ops->hdr_attr],
++					 net, extack, require_dev);
++	if (ret < 0)
++		goto out;
++
++	if (request_ops->parse_request) {
++		ret = request_ops->parse_request(req_info, tb, extack);
++		if (ret < 0)
++			goto out;
++	}
++
++	ret = 0;
++out:
++	kfree(tb);
++	return ret;
++}
++
++/**
++ * ethnl_init_reply_data() - Initialize reply data for GET request
++ * @reply_data: pointer to embedded struct ethnl_reply_data
++ * @ops:        instance of struct ethnl_request_ops describing the layout
++ * @dev:        network device to initialize the reply for
++ *
++ * Fills the reply data part with zeros and sets the dev member. Must be called
++ * before calling the ->fill_reply() callback (for each iteration when handling
++ * dump requests).
++ */
++static void ethnl_init_reply_data(struct ethnl_reply_data *reply_data,
++				  const struct ethnl_request_ops *ops,
++				  struct net_device *dev)
++{
++	memset(reply_data, 0, ops->reply_data_size);
++	reply_data->dev = dev;
++}
++
++/* default ->doit() handler for GET type requests */
++static int ethnl_default_doit(struct sk_buff *skb, struct genl_info *info)
++{
++	struct ethnl_reply_data *reply_data = NULL;
++	struct ethnl_req_info *req_info = NULL;
++	const u8 cmd = info->genlhdr->cmd;
++	const struct ethnl_request_ops *ops;
++	struct sk_buff *rskb;
++	void *reply_payload;
++	int reply_len;
++	int ret;
++
++	ops = ethnl_default_requests[cmd];
++	if (WARN_ONCE(!ops, "cmd %u has no ethnl_request_ops\n", cmd))
++		return -EOPNOTSUPP;
++	req_info = kzalloc(ops->req_info_size, GFP_KERNEL);
++	if (!req_info)
++		return -ENOMEM;
++	reply_data = kmalloc(ops->reply_data_size, GFP_KERNEL);
++	if (!reply_data) {
++		kfree(req_info);
++		return -ENOMEM;
++	}
++
++	ret = ethnl_default_parse(req_info, info->nlhdr,
++				  genl_info_net(info), ops,
++				  info->extack, !ops->allow_nodev_do);
++	if (ret < 0)
++		goto err_dev;
++	ethnl_init_reply_data(reply_data, ops, req_info->dev);
++
++	rtnl_lock();
++	ret = ops->prepare_data(req_info, reply_data, info);
++	rtnl_unlock();
++	if (ret < 0)
++		goto err_cleanup;
++	ret = ops->reply_size(req_info, reply_data);
++	if (ret < 0)
++		goto err_cleanup;
++	reply_len = ret;
++	ret = -ENOMEM;
++	rskb = ethnl_reply_init(reply_len, req_info->dev, ops->reply_cmd,
++				ops->hdr_attr, info, &reply_payload);
++	if (!rskb)
++		goto err_cleanup;
++	ret = ops->fill_reply(rskb, req_info, reply_data);
++	if (ret < 0)
++		goto err_msg;
++	if (ops->cleanup_data)
++		ops->cleanup_data(reply_data);
++
++	genlmsg_end(rskb, reply_payload);
++	if (req_info->dev)
++		dev_put(req_info->dev);
++	kfree(reply_data);
++	kfree(req_info);
++	return genlmsg_reply(rskb, info);
++
++err_msg:
++	WARN_ONCE(ret == -EMSGSIZE,
++		  "calculated message payload length (%d) not sufficient\n",
++		  reply_len);
++	nlmsg_free(rskb);
++err_cleanup:
++	if (ops->cleanup_data)
++		ops->cleanup_data(reply_data);
++err_dev:
++	if (req_info->dev)
++		dev_put(req_info->dev);
++	kfree(reply_data);
++	kfree(req_info);
++	return ret;
++}
++
++static int ethnl_default_dump_one(struct sk_buff *skb, struct net_device *dev,
++				  const struct ethnl_dump_ctx *ctx)
++{
++	int ret;
++
++	ethnl_init_reply_data(ctx->reply_data, ctx->ops, dev);
++	rtnl_lock();
++	ret = ctx->ops->prepare_data(ctx->req_info, ctx->reply_data, NULL);
++	rtnl_unlock();
++	if (ret < 0)
++		goto out;
++	ret = ethnl_fill_reply_header(skb, dev, ctx->ops->hdr_attr);
++	if (ret < 0)
++		goto out;
++	ret = ctx->ops->fill_reply(skb, ctx->req_info, ctx->reply_data);
++
++out:
++	if (ctx->ops->cleanup_data)
++		ctx->ops->cleanup_data(ctx->reply_data);
++	ctx->reply_data->dev = NULL;
++	return ret;
++}
++
++/* Default ->dumpit() handler for GET requests. Device iteration copied from
++ * rtnl_dump_ifinfo(); we have to be more careful about device hashtable
++ * persistence as we cannot guarantee to hold RTNL lock through the whole
++ * function as rtnetnlink does.
++ */
++static int ethnl_default_dumpit(struct sk_buff *skb,
++				struct netlink_callback *cb)
++{
++	struct ethnl_dump_ctx *ctx = ethnl_dump_context(cb);
++	struct net *net = sock_net(skb->sk);
++	int s_idx = ctx->pos_idx;
++	int h, idx = 0;
++	int ret = 0;
++	void *ehdr;
++
++	rtnl_lock();
++	for (h = ctx->pos_hash; h < NETDEV_HASHENTRIES; h++, s_idx = 0) {
++		struct hlist_head *head;
++		struct net_device *dev;
++		unsigned int seq;
++
++		head = &net->dev_index_head[h];
++
++restart_chain:
++		seq = net->dev_base_seq;
++		cb->seq = seq;
++		idx = 0;
++		hlist_for_each_entry(dev, head, index_hlist) {
++			if (idx < s_idx)
++				goto cont;
++			dev_hold(dev);
++			rtnl_unlock();
++
++			ehdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid,
++					   cb->nlh->nlmsg_seq,
++					   &ethtool_genl_family, 0,
++					   ctx->ops->reply_cmd);
++			if (!ehdr) {
++				dev_put(dev);
++				ret = -EMSGSIZE;
++				goto out;
++			}
++			ret = ethnl_default_dump_one(skb, dev, ctx);
++			dev_put(dev);
++			if (ret < 0) {
++				genlmsg_cancel(skb, ehdr);
++				if (ret == -EOPNOTSUPP)
++					goto lock_and_cont;
++				if (likely(skb->len))
++					ret = skb->len;
++				goto out;
++			}
++			genlmsg_end(skb, ehdr);
++lock_and_cont:
++			rtnl_lock();
++			if (net->dev_base_seq != seq) {
++				s_idx = idx + 1;
++				goto restart_chain;
++			}
++cont:
++			idx++;
++		}
++	}
++	rtnl_unlock();
++
++out:
++	ctx->pos_hash = h;
++	ctx->pos_idx = idx;
++	nl_dump_check_consistent(cb, nlmsg_hdr(skb));
++
++	return ret;
++}
++
++/* generic ->start() handler for GET requests */
++static int ethnl_default_start(struct netlink_callback *cb)
++{
++	struct ethnl_dump_ctx *ctx = ethnl_dump_context(cb);
++	struct ethnl_reply_data *reply_data;
++	const struct ethnl_request_ops *ops;
++	struct ethnl_req_info *req_info;
++	struct genlmsghdr *ghdr;
++	int ret;
++
++	BUILD_BUG_ON(sizeof(*ctx) > sizeof(cb->ctx));
++
++	ghdr = nlmsg_data(cb->nlh);
++	ops = ethnl_default_requests[ghdr->cmd];
++	if (WARN_ONCE(!ops, "cmd %u has no ethnl_request_ops\n", ghdr->cmd))
++		return -EOPNOTSUPP;
++	req_info = kzalloc(ops->req_info_size, GFP_KERNEL);
++	if (!req_info)
++		return -ENOMEM;
++	reply_data = kmalloc(ops->reply_data_size, GFP_KERNEL);
++	if (!reply_data) {
++		ret = -ENOMEM;
++		goto free_req_info;
++	}
++
++	ret = ethnl_default_parse(req_info, cb->nlh, sock_net(cb->skb->sk), ops,
++				  cb->extack, false);
++	if (req_info->dev) {
++		/* We ignore device specification in dump requests but as the
++		 * same parser as for non-dump (doit) requests is used, it
++		 * would take reference to the device if it finds one
++		 */
++		dev_put(req_info->dev);
++		req_info->dev = NULL;
++	}
++	if (ret < 0)
++		goto free_reply_data;
++
++	ctx->ops = ops;
++	ctx->req_info = req_info;
++	ctx->reply_data = reply_data;
++	ctx->pos_hash = 0;
++	ctx->pos_idx = 0;
++
++	return 0;
++
++free_reply_data:
++	kfree(reply_data);
++free_req_info:
++	kfree(req_info);
++
++	return ret;
++}
++
++/* default ->done() handler for GET requests */
++static int ethnl_default_done(struct netlink_callback *cb)
++{
++	struct ethnl_dump_ctx *ctx = ethnl_dump_context(cb);
++
++	kfree(ctx->reply_data);
++	kfree(ctx->req_info);
++
++	return 0;
++}
++
++static const struct ethnl_request_ops *
++ethnl_default_notify_ops[ETHTOOL_MSG_KERNEL_MAX + 1] = {
++	[ETHTOOL_MSG_RINGS_NTF]		= &ethnl_rings_request_ops,
++};
++
++/* default notification handler */
++static void ethnl_default_notify(struct net_device *dev, unsigned int cmd,
++				 const void *data)
++{
++	struct ethnl_reply_data *reply_data;
++	const struct ethnl_request_ops *ops;
++	struct ethnl_req_info *req_info;
++	struct sk_buff *skb;
++	void *reply_payload;
++	int reply_len;
++	int ret;
++
++	if (WARN_ONCE(cmd > ETHTOOL_MSG_KERNEL_MAX ||
++		      !ethnl_default_notify_ops[cmd],
++		      "unexpected notification type %u\n", cmd))
++		return;
++	ops = ethnl_default_notify_ops[cmd];
++	req_info = kzalloc(ops->req_info_size, GFP_KERNEL);
++	if (!req_info)
++		return;
++	reply_data = kmalloc(ops->reply_data_size, GFP_KERNEL);
++	if (!reply_data) {
++		kfree(req_info);
++		return;
++	}
++
++	req_info->dev = dev;
++	req_info->flags |= ETHTOOL_FLAG_COMPACT_BITSETS;
++
++	ethnl_init_reply_data(reply_data, ops, dev);
++	ret = ops->prepare_data(req_info, reply_data, NULL);
++	if (ret < 0)
++		goto err_cleanup;
++	ret = ops->reply_size(req_info, reply_data);
++	if (ret < 0)
++		goto err_cleanup;
++	reply_len = ret;
++	ret = -ENOMEM;
++	skb = genlmsg_new(reply_len, GFP_KERNEL);
++	if (!skb)
++		goto err_cleanup;
++	reply_payload = ethnl_bcastmsg_put(skb, cmd);
++	if (!reply_payload)
++		goto err_skb;
++	ret = ethnl_fill_reply_header(skb, dev, ops->hdr_attr);
++	if (ret < 0)
++		goto err_msg;
++	ret = ops->fill_reply(skb, req_info, reply_data);
++	if (ret < 0)
++		goto err_msg;
++	if (ops->cleanup_data)
++		ops->cleanup_data(reply_data);
++
++	genlmsg_end(skb, reply_payload);
++	kfree(reply_data);
++	kfree(req_info);
++	ethnl_multicast(skb, dev);
++	return;
++
++err_msg:
++	WARN_ONCE(ret == -EMSGSIZE,
++		  "calculated message payload length (%d) not sufficient\n",
++		  reply_len);
++err_skb:
++	nlmsg_free(skb);
++err_cleanup:
++	if (ops->cleanup_data)
++		ops->cleanup_data(reply_data);
++	kfree(reply_data);
++	kfree(req_info);
++}
++
++/* notifications */
++
++typedef void (*ethnl_notify_handler_t)(struct net_device *dev, unsigned int cmd,
++				       const void *data);
++
++static const ethnl_notify_handler_t ethnl_notify_handlers[] = {
++	[ETHTOOL_MSG_LINKINFO_NTF]	= ethnl_default_notify,
++	[ETHTOOL_MSG_LINKMODES_NTF]	= ethnl_default_notify,
++	[ETHTOOL_MSG_DEBUG_NTF]		= ethnl_default_notify,
++	[ETHTOOL_MSG_WOL_NTF]		= ethnl_default_notify,
++	[ETHTOOL_MSG_FEATURES_NTF]	= ethnl_default_notify,
++	[ETHTOOL_MSG_PRIVFLAGS_NTF]	= ethnl_default_notify,
++};
++
++void ethtool_notify(struct net_device *dev, unsigned int cmd, const void *data)
++{
++	if (unlikely(!ethnl_ok))
++		return;
++	ASSERT_RTNL();
++
++	if (likely(cmd < ARRAY_SIZE(ethnl_notify_handlers) &&
++		   ethnl_notify_handlers[cmd]))
++		ethnl_notify_handlers[cmd](dev, cmd, data);
++	else
++		WARN_ONCE(1, "notification %u not implemented (dev=%s)\n",
++			  cmd, netdev_name(dev));
++}
++EXPORT_SYMBOL(ethtool_notify);
++
+ /* genetlink setup */
+ 
+ static const struct genl_ops ethtool_genl_ops[] = {
++	{
++		.cmd	= ETHTOOL_MSG_STRSET_GET,
++		.doit	= ethnl_default_doit,
++		.start	= ethnl_default_start,
++		.dumpit	= ethnl_default_dumpit,
++		.done	= ethnl_default_done,
++	},
++	{
++		.cmd	= ETHTOOL_MSG_LINKINFO_GET,
++		.doit	= ethnl_default_doit,
++		.start	= ethnl_default_start,
++		.dumpit	= ethnl_default_dumpit,
++		.done	= ethnl_default_done,
++	},
++	{
++		.cmd	= ETHTOOL_MSG_LINKMODES_GET,
++		.doit	= ethnl_default_doit,
++		.start	= ethnl_default_start,
++		.dumpit	= ethnl_default_dumpit,
++		.done	= ethnl_default_done,
++	},
++	{
++		.cmd	= ETHTOOL_MSG_LINKSTATE_GET,
++		.doit	= ethnl_default_doit,
++		.start	= ethnl_default_start,
++		.dumpit	= ethnl_default_dumpit,
++		.done	= ethnl_default_done,
++	},
++	{
++		.cmd	= ETHTOOL_MSG_DEBUG_GET,
++		.doit	= ethnl_default_doit,
++		.start	= ethnl_default_start,
++		.dumpit	= ethnl_default_dumpit,
++		.done	= ethnl_default_done,
++	},
++	{
++		.cmd	= ETHTOOL_MSG_WOL_GET,
++		.flags	= GENL_UNS_ADMIN_PERM,
++		.doit	= ethnl_default_doit,
++		.start	= ethnl_default_start,
++		.dumpit	= ethnl_default_dumpit,
++		.done	= ethnl_default_done,
++	},
++	{
++		.cmd	= ETHTOOL_MSG_FEATURES_GET,
++		.doit	= ethnl_default_doit,
++		.start	= ethnl_default_start,
++		.dumpit	= ethnl_default_dumpit,
++		.done	= ethnl_default_done,
++	},
++	{
++		.cmd	= ETHTOOL_MSG_PRIVFLAGS_GET,
++		.doit	= ethnl_default_doit,
++		.start	= ethnl_default_start,
++		.dumpit	= ethnl_default_dumpit,
++		.done	= ethnl_default_done,
++	},
++	{
++		.cmd	= ETHTOOL_MSG_RINGS_GET,
++		.doit	= ethnl_default_doit,
++		.start	= ethnl_default_start,
++		.dumpit	= ethnl_default_dumpit,
++		.done	= ethnl_default_done,
++	},
++};
++
++static const struct genl_multicast_group ethtool_nl_mcgrps[] = {
++	[ETHNL_MCGRP_MONITOR] = { .name = ETHTOOL_MCGRP_MONITOR_NAME },
+ };
+ 
+ static struct genl_family ethtool_genl_family = {
+diff --git a/net/ethtool/netlink.h b/net/ethtool/netlink.h
+index 05d7183da894..c89b1f6254ba 100644
+--- a/net/ethtool/netlink.h
++++ b/net/ethtool/netlink.h
+@@ -212,4 +212,122 @@ struct ethnl_req_info {
+ 	u32			flags;
+ };
+ 
++/**
++ * struct ethnl_reply_data - base type of reply data for GET requests
++ * @dev:       device for current reply message; in single shot requests it is
++ *             equal to &ethnl_req_info.dev; in dumps it's different for each
++ *             reply message
++ *
++ * This is a common base for request specific structures holding data for
++ * kernel reply message. These always embed struct ethnl_reply_data at zero
++ * offset.
++ */
++struct ethnl_reply_data {
++	struct net_device		*dev;
++};
++
++static inline int ethnl_ops_begin(struct net_device *dev)
++{
++	if (dev && dev->ethtool_ops->begin)
++		return dev->ethtool_ops->begin(dev);
++	else
++		return 0;
++}
++
++static inline void ethnl_ops_complete(struct net_device *dev)
++{
++	if (dev && dev->ethtool_ops->complete)
++		dev->ethtool_ops->complete(dev);
++}
++
++/**
++ * struct ethnl_request_ops - unified handling of GET requests
++ * @request_cmd:      command id for request (GET)
++ * @reply_cmd:        command id for reply (GET_REPLY)
++ * @hdr_attr:         attribute type for request header
++ * @max_attr:         maximum (top level) attribute type
++ * @req_info_size:    size of request info
++ * @reply_data_size:  size of reply data
++ * @request_policy:   netlink policy for message contents
++ * @allow_nodev_do:   allow non-dump request with no device identification
++ * @parse_request:
++ *	Parse request except common header (struct ethnl_req_info). Common
++ *	header is already filled on entry, the rest up to @repdata_offset
++ *	is zero initialized. This callback should only modify type specific
++ *	request info by parsed attributes from request message.
++ * @prepare_data:
++ *	Retrieve and prepare data needed to compose a reply message. Calls to
++ *	ethtool_ops handlers are limited to this callback. Common reply data
++ *	(struct ethnl_reply_data) is filled on entry, type specific part after
++ *	it is zero initialized. This callback should only modify the type
++ *	specific part of reply data. Device identification from struct
++ *	ethnl_reply_data is to be used as for dump requests, it iterates
++ *	through network devices while dev member of struct ethnl_req_info
++ *	points to the device from client request.
++ * @reply_size:
++ *	Estimate reply message size. Returned value must be sufficient for
++ *	message payload without common reply header. The callback may returned
++ *	estimate higher than actual message size if exact calculation would
++ *	not be worth the saved memory space.
++ * @fill_reply:
++ *	Fill reply message payload (except for common header) from reply data.
++ *	The callback must not generate more payload than previously called
++ *	->reply_size() estimated.
++ * @cleanup_data:
++ *	Optional cleanup called when reply data is no longer needed. Can be
++ *	used e.g. to free any additional data structures outside the main
++ *	structure which were allocated by ->prepare_data(). When processing
++ *	dump requests, ->cleanup() is called for each message.
++ *
++ * Description of variable parts of GET request handling when using the
++ * unified infrastructure. When used, a pointer to an instance of this
++ * structure is to be added to &ethnl_default_requests array and generic
++ * handlers ethnl_default_doit(), ethnl_default_dumpit(),
++ * ethnl_default_start() and ethnl_default_done() used in @ethtool_genl_ops;
++ * ethnl_default_notify() can be used in @ethnl_notify_handlers to send
++ * notifications of the corresponding type.
++ */
++struct ethnl_request_ops {
++	u8			request_cmd;
++	u8			reply_cmd;
++	u16			hdr_attr;
++	unsigned int		max_attr;
++	unsigned int		req_info_size;
++	unsigned int		reply_data_size;
++	const struct nla_policy *request_policy;
++	bool			allow_nodev_do;
++
++	int (*parse_request)(struct ethnl_req_info *req_info,
++			     struct nlattr **tb,
++			     struct netlink_ext_ack *extack);
++	int (*prepare_data)(const struct ethnl_req_info *req_info,
++			    struct ethnl_reply_data *reply_data,
++			    struct genl_info *info);
++	int (*reply_size)(const struct ethnl_req_info *req_info,
++			  const struct ethnl_reply_data *reply_data);
++	int (*fill_reply)(struct sk_buff *skb,
++			  const struct ethnl_req_info *req_info,
++			  const struct ethnl_reply_data *reply_data);
++	void (*cleanup_data)(struct ethnl_reply_data *reply_data);
++};
++
++/* request handlers */
++
++extern const struct ethnl_request_ops ethnl_strset_request_ops;
++extern const struct ethnl_request_ops ethnl_linkinfo_request_ops;
++extern const struct ethnl_request_ops ethnl_linkmodes_request_ops;
++extern const struct ethnl_request_ops ethnl_linkstate_request_ops;
++extern const struct ethnl_request_ops ethnl_debug_request_ops;
++extern const struct ethnl_request_ops ethnl_wol_request_ops;
++extern const struct ethnl_request_ops ethnl_features_request_ops;
++extern const struct ethnl_request_ops ethnl_privflags_request_ops;
++extern const struct ethnl_request_ops ethnl_rings_request_ops;
++
++int ethnl_set_linkinfo(struct sk_buff *skb, struct genl_info *info);
++int ethnl_set_linkmodes(struct sk_buff *skb, struct genl_info *info);
++int ethnl_set_debug(struct sk_buff *skb, struct genl_info *info);
++int ethnl_set_wol(struct sk_buff *skb, struct genl_info *info);
++int ethnl_set_features(struct sk_buff *skb, struct genl_info *info);
++int ethnl_set_privflags(struct sk_buff *skb, struct genl_info *info);
++
+ #endif /* _NET_ETHTOOL_NETLINK_H */
+diff --git a/net/ethtool/rings.c b/net/ethtool/rings.c
+new file mode 100644
+index 000000000000..d3129d8a252d
+--- /dev/null
++++ b/net/ethtool/rings.c
+@@ -0,0 +1,108 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include "netlink.h"
++#include "common.h"
++
++struct rings_req_info {
++	struct ethnl_req_info		base;
++};
++
++struct rings_reply_data {
++	struct ethnl_reply_data		base;
++	struct ethtool_ringparam	ringparam;
++};
++
++#define RINGS_REPDATA(__reply_base) \
++	container_of(__reply_base, struct rings_reply_data, base)
++
++static const struct nla_policy
++rings_get_policy[ETHTOOL_A_RINGS_MAX + 1] = {
++	[ETHTOOL_A_RINGS_UNSPEC]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_HEADER]		= { .type = NLA_NESTED },
++	[ETHTOOL_A_RINGS_RX_MAX]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_RX_MINI_MAX]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_RX_JUMBO_MAX]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_TX_MAX]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_RX]			= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_RX_MINI]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_RX_JUMBO]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_TX]			= { .type = NLA_REJECT },
++};
++
++static int rings_prepare_data(const struct ethnl_req_info *req_base,
++			      struct ethnl_reply_data *reply_base,
++			      struct genl_info *info)
++{
++	struct rings_reply_data *data = RINGS_REPDATA(reply_base);
++	struct net_device *dev = reply_base->dev;
++	int ret;
++
++	if (!dev->ethtool_ops->get_ringparam)
++		return -EOPNOTSUPP;
++	ret = ethnl_ops_begin(dev);
++	if (ret < 0)
++		return ret;
++	dev->ethtool_ops->get_ringparam(dev, &data->ringparam);
++	ethnl_ops_complete(dev);
++
++	return 0;
++}
++
++static int rings_reply_size(const struct ethnl_req_info *req_base,
++			    const struct ethnl_reply_data *reply_base)
++{
++	return nla_total_size(sizeof(u32)) +	/* _RINGS_RX_MAX */
++	       nla_total_size(sizeof(u32)) +	/* _RINGS_RX_MINI_MAX */
++	       nla_total_size(sizeof(u32)) +	/* _RINGS_RX_JUMBO_MAX */
++	       nla_total_size(sizeof(u32)) +	/* _RINGS_TX_MAX */
++	       nla_total_size(sizeof(u32)) +	/* _RINGS_RX */
++	       nla_total_size(sizeof(u32)) +	/* _RINGS_RX_MINI */
++	       nla_total_size(sizeof(u32)) +	/* _RINGS_RX_JUMBO */
++	       nla_total_size(sizeof(u32));	/* _RINGS_TX */
++}
++
++static int rings_fill_reply(struct sk_buff *skb,
++			    const struct ethnl_req_info *req_base,
++			    const struct ethnl_reply_data *reply_base)
++{
++	const struct rings_reply_data *data = RINGS_REPDATA(reply_base);
++	const struct ethtool_ringparam *ringparam = &data->ringparam;
++
++	if ((ringparam->rx_max_pending &&
++	     (nla_put_u32(skb, ETHTOOL_A_RINGS_RX_MAX,
++			  ringparam->rx_max_pending) ||
++	      nla_put_u32(skb, ETHTOOL_A_RINGS_RX,
++			  ringparam->rx_pending))) ||
++	    (ringparam->rx_mini_max_pending &&
++	     (nla_put_u32(skb, ETHTOOL_A_RINGS_RX_MINI_MAX,
++			  ringparam->rx_mini_max_pending) ||
++	      nla_put_u32(skb, ETHTOOL_A_RINGS_RX_MINI,
++			  ringparam->rx_mini_pending))) ||
++	    (ringparam->rx_jumbo_max_pending &&
++	     (nla_put_u32(skb, ETHTOOL_A_RINGS_RX_JUMBO_MAX,
++			  ringparam->rx_jumbo_max_pending) ||
++	      nla_put_u32(skb, ETHTOOL_A_RINGS_RX_JUMBO,
++			  ringparam->rx_jumbo_pending))) ||
++	    (ringparam->tx_max_pending &&
++	     (nla_put_u32(skb, ETHTOOL_A_RINGS_TX_MAX,
++			  ringparam->tx_max_pending) ||
++	      nla_put_u32(skb, ETHTOOL_A_RINGS_TX,
++			  ringparam->tx_pending))))
++		return -EMSGSIZE;
++
++	return 0;
++}
++
++const struct ethnl_request_ops ethnl_rings_request_ops = {
++	.request_cmd		= ETHTOOL_MSG_RINGS_GET,
++	.reply_cmd		= ETHTOOL_MSG_RINGS_GET_REPLY,
++	.hdr_attr		= ETHTOOL_A_RINGS_HEADER,
++	.max_attr		= ETHTOOL_A_RINGS_MAX,
++	.req_info_size		= sizeof(struct rings_req_info),
++	.reply_data_size	= sizeof(struct rings_reply_data),
++	.request_policy		= rings_get_policy,
++
++	.prepare_data		= rings_prepare_data,
++	.reply_size		= rings_reply_size,
++	.fill_reply		= rings_fill_reply,
++};
+diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c
+index 6b5be7a426ac..135b658f060d 100644
+--- a/net/netlink/af_netlink.c
++++ b/net/netlink/af_netlink.c
+@@ -2198,6 +2198,7 @@ EXPORT_SYMBOL(__nlmsg_put);
+ static int netlink_dump(struct sock *sk)
+ {
+ 	struct netlink_sock *nlk = nlk_sk(sk);
++	struct netlink_ext_ack extack = {};
+ 	struct netlink_callback *cb;
+ 	struct sk_buff *skb = NULL;
+ 	struct nlmsghdr *nlh;
+@@ -2256,8 +2257,11 @@ static int netlink_dump(struct sock *sk)
+ 
+ 	netlink_skb_set_owner_r(skb, sk);
+ 
+-	if (nlk->dump_done_errno > 0)
++	if (nlk->dump_done_errno > 0) {
++		cb->extack = &extack;
+ 		nlk->dump_done_errno = cb->dump(skb, cb);
++		cb->extack = NULL;
++	}
+ 
+ 	if (nlk->dump_done_errno > 0 ||
+ 	    skb_tailroom(skb) < nlmsg_total_size(sizeof(nlk->dump_done_errno))) {
+@@ -2280,6 +2284,12 @@ static int netlink_dump(struct sock *sk)
+ 	memcpy(nlmsg_data(nlh), &nlk->dump_done_errno,
+ 	       sizeof(nlk->dump_done_errno));
+ 
++	if (extack._msg && nlk->flags & NETLINK_F_EXT_ACK) {
++		nlh->nlmsg_flags |= NLM_F_ACK_TLVS;
++		if (!nla_put_string(skb, NLMSGERR_ATTR_MSG, extack._msg))
++			nlmsg_end(skb, nlh);
++	}
++
+ 	if (sk_filter(sk, skb))
+ 		kfree_skb(skb);
+ 	else
+-- 
+2.34.1
+
diff --git a/patches/0525-ethtool-set-device-ring-sizes-with-RINGS_SET-request.patch b/patches/0525-ethtool-set-device-ring-sizes-with-RINGS_SET-request.patch
new file mode 100644
index 0000000..01b5534
--- /dev/null
+++ b/patches/0525-ethtool-set-device-ring-sizes-with-RINGS_SET-request.patch
@@ -0,0 +1,239 @@
+From 01034b37673db2bea84b073d5d5f4a4e1c1a2b53 Mon Sep 17 00:00:00 2001
+From: Michal Kubecek <mkubecek@suse.cz>
+Date: Thu, 12 Mar 2020 21:08:28 +0100
+Subject: [PATCH 164/283] ethtool: set device ring sizes with RINGS_SET request
+
+mainline inclusion
+from mainline-v5.7-rc1
+commit 2fc2929e807211a9535a6541f24b57fa1c469728
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2fc2929e807211a9535a6541f24b57fa1c469728
+
+--------------------------------
+
+Implement RINGS_SET netlink request to set ring sizes of a network device.
+These are traditionally set with ETHTOOL_SRINGPARAM ioctl request.
+
+Like the ioctl implementation, the generic ethtool code checks if supplied
+values do not exceed driver defined limits; if they do, first offending
+attribute is reported using extack.
+
+v2:
+  - fix netdev reference leak in error path (found by Jakub Kicinsky)
+
+Signed-off-by: Michal Kubecek <mkubecek@suse.cz>
+Reviewed-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	Documentation/networking/ethtool-netlink.rst
+---
+ Documentation/networking/ethtool-netlink.rst | 24 +++++-
+ include/uapi/linux/ethtool_netlink.h         |  1 +
+ net/ethtool/netlink.c                        |  5 ++
+ net/ethtool/netlink.h                        |  5 ++
+ net/ethtool/rings.c                          | 89 ++++++++++++++++++++
+ 5 files changed, 123 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+index 32a92edfec14..6ed5a806054a 100644
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -179,6 +179,7 @@ Userspace to kernel:
+ 
+   ===================================== ================================
+   ``ETHTOOL_MSG_RINGS_GET``             get ring sizes
++  ``ETHTOOL_MSG_RINGS_SET``             set ring sizes
+   ===================================== ================================
+ 
+ Kernel to userspace:
+@@ -242,6 +243,27 @@ Kernel response contents:
+   ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
+   ====================================  ======  ==========================
+ 
++
++RINGS_SET
++=========
++
++Sets ring sizes like ``ETHTOOL_SRINGPARAM`` ioctl request.
++
++Request contents:
++
++  ====================================  ======  ==========================
++  ``ETHTOOL_A_RINGS_HEADER``            nested  reply header
++  ``ETHTOOL_A_RINGS_RX``                u32     size of RX ring
++  ``ETHTOOL_A_RINGS_RX_MINI``           u32     size of RX mini ring
++  ``ETHTOOL_A_RINGS_RX_JUMBO``          u32     size of RX jumbo ring
++  ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
++  ====================================  ======  ==========================
++
++Kernel checks that requested ring sizes do not exceed limits reported by
++driver. Driver may impose additional constraints and may not suspport all
++attributes.
++
++
+ Request translation
+ ===================
+ 
+@@ -267,7 +289,7 @@ have their netlink replacement yet.
+   ``ETHTOOL_GCOALESCE``               n/a
+   ``ETHTOOL_SCOALESCE``               n/a
+   ``ETHTOOL_GRINGPARAM``              ``ETHTOOL_MSG_RINGS_GET``
+-  ``ETHTOOL_SRINGPARAM``              n/a
++  ``ETHTOOL_SRINGPARAM``              ``ETHTOOL_MSG_RINGS_SET``
+   ``ETHTOOL_GPAUSEPARAM``             n/a
+   ``ETHTOOL_SPAUSEPARAM``             n/a
+   ``ETHTOOL_GRXCSUM``                 n/a
+diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
+index 496e1d4805ee..aa543c783529 100644
+--- a/include/uapi/linux/ethtool_netlink.h
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -29,6 +29,7 @@ enum {
+ 	ETHTOOL_MSG_PRIVFLAGS_GET,
+ 	ETHTOOL_MSG_PRIVFLAGS_SET,
+ 	ETHTOOL_MSG_RINGS_GET,
++	ETHTOOL_MSG_RINGS_SET,
+ 
+ 	/* add new constants above here */
+ 	__ETHTOOL_MSG_USER_CNT,
+diff --git a/net/ethtool/netlink.c b/net/ethtool/netlink.c
+index 778bbeb517f5..7ac8a4524376 100644
+--- a/net/ethtool/netlink.c
++++ b/net/ethtool/netlink.c
+@@ -769,6 +769,11 @@ static const struct genl_ops ethtool_genl_ops[] = {
+ 		.dumpit	= ethnl_default_dumpit,
+ 		.done	= ethnl_default_done,
+ 	},
++	{
++		.cmd	= ETHTOOL_MSG_RINGS_SET,
++		.flags	= GENL_UNS_ADMIN_PERM,
++		.doit	= ethnl_set_rings,
++	},
+ };
+ 
+ static const struct genl_multicast_group ethtool_nl_mcgrps[] = {
+diff --git a/net/ethtool/netlink.h b/net/ethtool/netlink.h
+index c89b1f6254ba..a862bad9dd06 100644
+--- a/net/ethtool/netlink.h
++++ b/net/ethtool/netlink.h
+@@ -10,6 +10,10 @@
+ 
+ struct ethnl_req_info;
+ 
++int ethnl_parse_header_dev_get(struct ethnl_req_info *req_info,
++			       const struct nlattr *nest, struct net *net,
++			       struct netlink_ext_ack *extack,
++			       bool require_dev);
+ int ethnl_parse_header(struct ethnl_req_info *req_info,
+ 		       const struct nlattr *nest, struct net *net,
+ 		       struct netlink_ext_ack *extack, bool require_dev);
+@@ -329,5 +333,6 @@ int ethnl_set_debug(struct sk_buff *skb, struct genl_info *info);
+ int ethnl_set_wol(struct sk_buff *skb, struct genl_info *info);
+ int ethnl_set_features(struct sk_buff *skb, struct genl_info *info);
+ int ethnl_set_privflags(struct sk_buff *skb, struct genl_info *info);
++int ethnl_set_rings(struct sk_buff *skb, struct genl_info *info);
+ 
+ #endif /* _NET_ETHTOOL_NETLINK_H */
+diff --git a/net/ethtool/rings.c b/net/ethtool/rings.c
+index d3129d8a252d..93f428e9a6c2 100644
+--- a/net/ethtool/rings.c
++++ b/net/ethtool/rings.c
+@@ -106,3 +106,92 @@ const struct ethnl_request_ops ethnl_rings_request_ops = {
+ 	.reply_size		= rings_reply_size,
+ 	.fill_reply		= rings_fill_reply,
+ };
++
++/* RINGS_SET */
++
++static const struct nla_policy
++rings_set_policy[ETHTOOL_A_RINGS_MAX + 1] = {
++	[ETHTOOL_A_RINGS_UNSPEC]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_HEADER]		= { .type = NLA_NESTED },
++	[ETHTOOL_A_RINGS_RX_MAX]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_RX_MINI_MAX]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_RX_JUMBO_MAX]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_TX_MAX]		= { .type = NLA_REJECT },
++	[ETHTOOL_A_RINGS_RX]			= { .type = NLA_U32 },
++	[ETHTOOL_A_RINGS_RX_MINI]		= { .type = NLA_U32 },
++	[ETHTOOL_A_RINGS_RX_JUMBO]		= { .type = NLA_U32 },
++	[ETHTOOL_A_RINGS_TX]			= { .type = NLA_U32 },
++};
++
++int ethnl_set_rings(struct sk_buff *skb, struct genl_info *info)
++{
++	struct nlattr *tb[ETHTOOL_A_RINGS_MAX + 1];
++	struct ethtool_ringparam ringparam = {};
++	struct ethnl_req_info req_info = {};
++	const struct nlattr *err_attr;
++	const struct ethtool_ops *ops;
++	struct net_device *dev;
++	bool mod = false;
++	int ret;
++
++	ret = nlmsg_parse(info->nlhdr, GENL_HDRLEN, tb,
++			  ETHTOOL_A_RINGS_MAX, rings_set_policy,
++			  info->extack);
++	if (ret < 0)
++		return ret;
++	ret = ethnl_parse_header_dev_get(&req_info,
++					 tb[ETHTOOL_A_RINGS_HEADER],
++					 genl_info_net(info), info->extack,
++					 true);
++	if (ret < 0)
++		return ret;
++	dev = req_info.dev;
++	ops = dev->ethtool_ops;
++	ret = -EOPNOTSUPP;
++	if (!ops->get_ringparam || !ops->set_ringparam)
++		goto out_dev;
++
++	rtnl_lock();
++	ret = ethnl_ops_begin(dev);
++	if (ret < 0)
++		goto out_rtnl;
++	ops->get_ringparam(dev, &ringparam);
++
++	ethnl_update_u32(&ringparam.rx_pending, tb[ETHTOOL_A_RINGS_RX], &mod);
++	ethnl_update_u32(&ringparam.rx_mini_pending,
++			 tb[ETHTOOL_A_RINGS_RX_MINI], &mod);
++	ethnl_update_u32(&ringparam.rx_jumbo_pending,
++			 tb[ETHTOOL_A_RINGS_RX_JUMBO], &mod);
++	ethnl_update_u32(&ringparam.tx_pending, tb[ETHTOOL_A_RINGS_TX], &mod);
++	ret = 0;
++	if (!mod)
++		goto out_ops;
++
++	/* ensure new ring parameters are within limits */
++	if (ringparam.rx_pending > ringparam.rx_max_pending)
++		err_attr = tb[ETHTOOL_A_RINGS_RX];
++	else if (ringparam.rx_mini_pending > ringparam.rx_mini_max_pending)
++		err_attr = tb[ETHTOOL_A_RINGS_RX_MINI];
++	else if (ringparam.rx_jumbo_pending > ringparam.rx_jumbo_max_pending)
++		err_attr = tb[ETHTOOL_A_RINGS_RX_JUMBO];
++	else if (ringparam.tx_pending > ringparam.tx_max_pending)
++		err_attr = tb[ETHTOOL_A_RINGS_TX];
++	else
++		err_attr = NULL;
++	if (err_attr) {
++		ret = -EINVAL;
++		NL_SET_ERR_MSG_ATTR(info->extack, err_attr,
++				    "requested ring size exceeeds maximum");
++		goto out_ops;
++	}
++
++	ret = dev->ethtool_ops->set_ringparam(dev, &ringparam);
++
++out_ops:
++	ethnl_ops_complete(dev);
++out_rtnl:
++	rtnl_unlock();
++out_dev:
++	dev_put(dev);
++	return ret;
++}
+-- 
+2.34.1
+
diff --git a/patches/0526-ethtool-add-support-to-set-get-tx-copybreak-buf-size.patch b/patches/0526-ethtool-add-support-to-set-get-tx-copybreak-buf-size.patch
new file mode 100644
index 0000000..ba8cf48
--- /dev/null
+++ b/patches/0526-ethtool-add-support-to-set-get-tx-copybreak-buf-size.patch
@@ -0,0 +1,72 @@
+From 7b83388f0cf848c90462b2459db89db09c8a4530 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Mon, 27 Dec 2021 19:41:38 +0800
+Subject: [PATCH 165/283] ethtool: add support to set/get tx copybreak buf size
+ via ethtool
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit 448f413a8bdc727d25d9a786ccbdb974fb85d973
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=448f413a8bdc727d25d9a786ccbdb974fb85d973
+
+----------------------------------------------------------------------
+
+Add support for ethtool to set/get tx copybreak buf size.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Acked-by: Xie XiuQi <xiexiuqi@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ include/uapi/linux/ethtool.h | 1 +
+ net/ethtool/common.c         | 1 +
+ net/ethtool/ioctl.c          | 1 +
+ 3 files changed, 3 insertions(+)
+
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index e519138e2a38..047f880edff9 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -225,6 +225,7 @@ enum tunable_id {
+ 	ETHTOOL_RX_COPYBREAK,
+ 	ETHTOOL_TX_COPYBREAK,
+ 	ETHTOOL_PFC_PREVENTION_TOUT, /* timeout in msecs */
++	ETHTOOL_TX_COPYBREAK_BUF_SIZE,
+ 	/*
+ 	 * Add your fresh new tunable attribute above and remember to update
+ 	 * tunable_strings[] in net/core/ethtool.c
+diff --git a/net/ethtool/common.c b/net/ethtool/common.c
+index 11a12af88165..61f326eb844e 100644
+--- a/net/ethtool/common.c
++++ b/net/ethtool/common.c
+@@ -74,6 +74,7 @@ tunable_strings[__ETHTOOL_TUNABLE_COUNT][ETH_GSTRING_LEN] = {
+ 	[ETHTOOL_RX_COPYBREAK]	= "rx-copybreak",
+ 	[ETHTOOL_TX_COPYBREAK]	= "tx-copybreak",
+ 	[ETHTOOL_PFC_PREVENTION_TOUT] = "pfc-prevention-tout",
++	[ETHTOOL_TX_COPYBREAK_BUF_SIZE] = "tx-copybreak-buf-size",
+ };
+ 
+ const char
+diff --git a/net/ethtool/ioctl.c b/net/ethtool/ioctl.c
+index 7799062c2b97..4fdfb3e40dea 100644
+--- a/net/ethtool/ioctl.c
++++ b/net/ethtool/ioctl.c
+@@ -2270,6 +2270,7 @@ static int ethtool_tunable_valid(const struct ethtool_tunable *tuna)
+ 	switch (tuna->id) {
+ 	case ETHTOOL_RX_COPYBREAK:
+ 	case ETHTOOL_TX_COPYBREAK:
++	case ETHTOOL_TX_COPYBREAK_BUF_SIZE:
+ 		if (tuna->len != sizeof(u32) ||
+ 		    tuna->type_id != ETHTOOL_TUNABLE_U32)
+ 			return -EINVAL;
+-- 
+2.34.1
+
diff --git a/patches/0527-net-hns3-add-support-to-set-get-tx-copybreak-buf-siz.patch b/patches/0527-net-hns3-add-support-to-set-get-tx-copybreak-buf-siz.patch
new file mode 100644
index 0000000..2b3943a
--- /dev/null
+++ b/patches/0527-net-hns3-add-support-to-set-get-tx-copybreak-buf-siz.patch
@@ -0,0 +1,163 @@
+From 45cf3372a56d4606fbd6e0483be31c4c819cd56c Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Mon, 27 Dec 2021 19:41:39 +0800
+Subject: [PATCH 166/283] net: hns3: add support to set/get tx copybreak buf
+ size via ethtool for hns3 driver
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit e445f08af2b15035474439fbbb8649f466ad2501
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e445f08af2b15035474439fbbb8649f466ad2501
+
+----------------------------------------------------------------------
+
+Tx copybreak buf size is used for tx copybreak feature, the feature is
+used for small size packet or frag. It adds a queue based tx shared
+bounce buffer to memcpy the small packet when the len of xmitted skb is
+below tx_copybreak(value to distinguish small size and normal size),
+and reduce the overhead of dma map and unmap when IOMMU is on.
+
+Support setting it via ethtool --set-tunable parameter and getting
+it via ethtool --get-tunable parameter.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  4 +-
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  2 +
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 56 +++++++++++++++++++
+ 3 files changed, 60 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 6cf947cd96eb..363b92e6298c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -5165,8 +5165,8 @@ static int hns3_reset_notify_uninit_enet(struct hnae3_handle *handle)
+ 	return ret;
+ }
+ 
+-static int hns3_reset_notify(struct hnae3_handle *handle,
+-			     enum hnae3_reset_notify_type type)
++int hns3_reset_notify(struct hnae3_handle *handle,
++		      enum hnae3_reset_notify_type type)
+ {
+ 	int ret = 0;
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 433422fda7b8..f889ec9fc24e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -695,6 +695,8 @@ void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
+ 				    u32 ql_value);
+ 
+ void hns3_request_update_promisc_mode(struct hnae3_handle *handle);
++int hns3_reset_notify(struct hnae3_handle *handle,
++		      enum hnae3_reset_notify_type type);
+ 
+ #ifdef CONFIG_HNS3_DCB
+ void hns3_dcbnl_setup(struct hnae3_handle *handle);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index f7bb9c85e243..8da002d6d0b9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1681,6 +1681,7 @@ static int hns3_get_tunable(struct net_device *netdev,
+ 			    void *data)
+ {
+ 	struct hns3_nic_priv *priv = netdev_priv(netdev);
++	struct hnae3_handle *h = priv->ae_handle;
+ 	int ret = 0;
+ 
+ 	switch (tuna->id) {
+@@ -1691,6 +1692,9 @@ static int hns3_get_tunable(struct net_device *netdev,
+ 	case ETHTOOL_RX_COPYBREAK:
+ 		*(u32 *)data = priv->rx_copybreak;
+ 		break;
++	case ETHTOOL_TX_COPYBREAK_BUF_SIZE:
++		*(u32 *)data = h->kinfo.tx_spare_buf_size;
++		break;
+ 	default:
+ 		ret = -EOPNOTSUPP;
+ 		break;
+@@ -1699,11 +1703,43 @@ static int hns3_get_tunable(struct net_device *netdev,
+ 	return ret;
+ }
+ 
++static int hns3_set_tx_spare_buf_size(struct net_device *netdev,
++				      u32 data)
++{
++	struct hns3_nic_priv *priv = netdev_priv(netdev);
++	struct hnae3_handle *h = priv->ae_handle;
++	int ret;
++
++	if (hns3_nic_resetting(netdev))
++		return -EBUSY;
++
++	h->kinfo.tx_spare_buf_size = data;
++
++	ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
++	if (ret)
++		return ret;
++
++	ret = hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
++	if (ret)
++		return ret;
++
++	ret = hns3_reset_notify(h, HNAE3_INIT_CLIENT);
++	if (ret)
++		return ret;
++
++	ret = hns3_reset_notify(h, HNAE3_UP_CLIENT);
++	if (ret)
++		hns3_reset_notify(h, HNAE3_UNINIT_CLIENT);
++
++	return ret;
++}
++
+ static int hns3_set_tunable(struct net_device *netdev,
+ 			    const struct ethtool_tunable *tuna,
+ 			    const void *data)
+ {
+ 	struct hns3_nic_priv *priv = netdev_priv(netdev);
++	u32 old_tx_spare_buf_size, new_tx_spare_buf_size;
+ 	struct hnae3_handle *h = priv->ae_handle;
+ 	int i, ret = 0;
+ 
+@@ -1721,6 +1757,26 @@ static int hns3_set_tunable(struct net_device *netdev,
+ 		for (i = h->kinfo.num_tqps; i < h->kinfo.num_tqps * 2; i++)
+ 			priv->ring[i].rx_copybreak = priv->rx_copybreak;
+ 
++		break;
++	case ETHTOOL_TX_COPYBREAK_BUF_SIZE:
++		old_tx_spare_buf_size = h->kinfo.tx_spare_buf_size;
++		new_tx_spare_buf_size = *(u32 *)data;
++		ret = hns3_set_tx_spare_buf_size(netdev, new_tx_spare_buf_size);
++		if (ret) {
++			int ret1;
++
++			netdev_warn(netdev,
++				    "change tx spare buf size fail, revert to old value\n");
++			ret1 = hns3_set_tx_spare_buf_size(netdev,
++							  old_tx_spare_buf_size);
++			if (ret1) {
++				netdev_err(netdev,
++					   "revert to old tx spare buf size fail\n");
++				return ret1;
++			}
++
++			return ret;
++		}
+ 		break;
+ 	default:
+ 		ret = -EOPNOTSUPP;
+-- 
+2.34.1
+
diff --git a/patches/0528-ethtool-add-support-to-set-get-rx-buf-len-via-ethtoo.patch b/patches/0528-ethtool-add-support-to-set-get-rx-buf-len-via-ethtoo.patch
new file mode 100644
index 0000000..102cbec
--- /dev/null
+++ b/patches/0528-ethtool-add-support-to-set-get-rx-buf-len-via-ethtoo.patch
@@ -0,0 +1,348 @@
+From adc45e25377473ec6b3303fbe15bb63e29f4b9c8 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Mon, 27 Dec 2021 19:41:40 +0800
+Subject: [PATCH 167/283] ethtool: add support to set/get rx buf len via
+ ethtool
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit 0b70c256eba8448b072d25c95ee65e59da8970de
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0b70c256eba8448b072d25c95ee65e59da8970de
+
+----------------------------------------------------------------------
+
+Add support to set rx buf len via ethtool -G parameter and get
+rx buf len via ethtool -g parameter.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+(fix conflicts: remove extend link modes)
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	include/linux/ethtool.h
+	net/ethtool/netlink.h
+	net/ethtool/rings.c
+---
+ Documentation/networking/ethtool-netlink.rst | 10 ++--
+ include/linux/ethtool.h                      | 26 ++++++----
+ include/net/netlink.h                        | 50 +++++++++++++++++++-
+ include/uapi/linux/ethtool_netlink.h         |  1 +
+ net/ethtool/netlink.c                        |  2 +-
+ net/ethtool/netlink.h                        | 23 +++++++++
+ net/ethtool/rings.c                          | 24 +++++++++-
+ 7 files changed, 120 insertions(+), 16 deletions(-)
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+index 6ed5a806054a..1cf07b28382d 100644
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -231,7 +231,7 @@ Request contents:
+ 
+ Kernel response contents:
+ 
+-  ====================================  ======  ==========================
++  ====================================  ======  ===========================
+   ``ETHTOOL_A_RINGS_HEADER``            nested  reply header
+   ``ETHTOOL_A_RINGS_RX_MAX``            u32     max size of RX ring
+   ``ETHTOOL_A_RINGS_RX_MINI_MAX``       u32     max size of RX mini ring
+@@ -241,7 +241,8 @@ Kernel response contents:
+   ``ETHTOOL_A_RINGS_RX_MINI``           u32     size of RX mini ring
+   ``ETHTOOL_A_RINGS_RX_JUMBO``          u32     size of RX jumbo ring
+   ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
+-  ====================================  ======  ==========================
++  ``ETHTOOL_A_RINGS_RX_BUF_LEN``        u32     size of buffers on the ring
++  ====================================  ======  ===========================
+ 
+ 
+ RINGS_SET
+@@ -251,13 +252,14 @@ Sets ring sizes like ``ETHTOOL_SRINGPARAM`` ioctl request.
+ 
+ Request contents:
+ 
+-  ====================================  ======  ==========================
++  ====================================  ======  ===========================
+   ``ETHTOOL_A_RINGS_HEADER``            nested  reply header
+   ``ETHTOOL_A_RINGS_RX``                u32     size of RX ring
+   ``ETHTOOL_A_RINGS_RX_MINI``           u32     size of RX mini ring
+   ``ETHTOOL_A_RINGS_RX_JUMBO``          u32     size of RX jumbo ring
+   ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
+-  ====================================  ======  ==========================
++  ``ETHTOOL_A_RINGS_RX_BUF_LEN``        u32     size of buffers on the ring
++  ====================================  ======  ===========================
+ 
+ Kernel checks that requested ring sizes do not exceed limits reported by
+ driver. Driver may impose additional constraints and may not suspport all
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 4154522d8497..812026982640 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -71,6 +71,22 @@ enum {
+ 	ETH_RSS_HASH_FUNCS_COUNT
+ };
+ 
++/**
++ * struct kernel_ethtool_ringparam - RX/TX ring configuration
++ * @rx_buf_len: Current length of buffers on the rx ring.
++ */
++struct kernel_ethtool_ringparam {
++	u32	rx_buf_len;
++};
++
++/**
++ * enum ethtool_supported_ring_param - indicator caps for setting ring params
++ * @ETHTOOL_RING_USE_RX_BUF_LEN: capture for setting rx_buf_len
++ */
++enum ethtool_supported_ring_param {
++	ETHTOOL_RING_USE_RX_BUF_LEN = BIT(0),
++};
++
+ #define __ETH_RSS_HASH_BIT(bit)	((u32)1 << (bit))
+ #define __ETH_RSS_HASH(name)	__ETH_RSS_HASH_BIT(ETH_RSS_HASH_##name##_BIT)
+ 
+@@ -234,14 +250,7 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+ /**
+  * struct ethtool_ops - optional netdev operations
+  * @supported_coalesce_params: supported types of interrupt coalescing.
+- * @get_settings: DEPRECATED, use %get_link_ksettings/%set_link_ksettings
+- *	API. Get various device settings including Ethernet link
+- *	settings. The @cmd parameter is expected to have been cleared
+- *	before get_settings is called. Returns a negative error code
+- *	or zero.
+- * @set_settings: DEPRECATED, use %get_link_ksettings/%set_link_ksettings
+- *	API. Set various device settings including Ethernet link
+- *	settings.  Returns a negative error code or zero.
++ * @supported_ring_params: supported ring params.
+  * @get_drvinfo: Report driver/device information.  Should only set the
+  *	@driver, @version, @fw_version and @bus_info fields.  If not
+  *	implemented, the @driver and @bus_info fields will be filled in
+@@ -384,6 +393,7 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+ struct ethtool_ops {
+ #ifndef __GENKSYMS__
+ 	u32     supported_coalesce_params;
++	u32     supported_ring_params;
+ #endif
+ 	int	(*get_settings)(struct net_device *, struct ethtool_cmd *);
+ 	int	(*set_settings)(struct net_device *, struct ethtool_cmd *);
+diff --git a/include/net/netlink.h b/include/net/netlink.h
+index d6e48d6ad67d..f30598d66eec 100644
+--- a/include/net/netlink.h
++++ b/include/net/netlink.h
+@@ -191,6 +191,17 @@ enum {
+ 
+ #define NLA_TYPE_MAX (__NLA_TYPE_MAX - 1)
+ 
++enum nla_policy_validation {
++	NLA_VALIDATE_NONE,
++	NLA_VALIDATE_RANGE,
++	NLA_VALIDATE_RANGE_WARN_TOO_LONG,
++	NLA_VALIDATE_MIN,
++	NLA_VALIDATE_MAX,
++	NLA_VALIDATE_MASK,
++	NLA_VALIDATE_RANGE_PTR,
++	NLA_VALIDATE_FUNCTION,
++};
++
+ /**
+  * struct nla_policy - attribute validation policy
+  * @type: Type of attribute or NLA_UNSPEC
+@@ -228,9 +239,46 @@ enum {
+ struct nla_policy {
+ 	u16		type;
+ 	u16		len;
+-	void            *validation_data;
++	void		*validation_data;
++#ifndef __GENKSYMS__
++	u8		validation_type;
++	union {
++		const u32 bitfield32_valid;
++		const u32 mask;
++		const char *reject_message;
++		const struct nla_policy *nested_policy;
++		struct netlink_range_validation *range;
++		struct netlink_range_validation_signed *range_signed;
++		struct {
++			s16 min, max;
++		};
++		int (*validate)(const struct nlattr *attr,
++				struct netlink_ext_ack *extack);
++		u16 strict_start_type;
++	};
++#endif
+ };
+ 
++#define __NLA_IS_UINT_TYPE(tp)						\
++	(tp == NLA_U8 || tp == NLA_U16 || tp == NLA_U32 || tp == NLA_U64)
++#define __NLA_IS_SINT_TYPE(tp)						\
++	(tp == NLA_S8 || tp == NLA_S16 || tp == NLA_S32 || tp == NLA_S64)
++
++#define __NLA_ENSURE(condition) BUILD_BUG_ON_ZERO(!(condition))
++
++#define NLA_ENSURE_INT_OR_BINARY_TYPE(tp)		\
++	(__NLA_ENSURE(__NLA_IS_UINT_TYPE(tp) ||		\
++		      __NLA_IS_SINT_TYPE(tp) ||		\
++		      tp == NLA_MSECS ||		\
++		      tp == NLA_BINARY) + tp)
++
++
++#define NLA_POLICY_MIN(tp, _min) {			\
++	.type = NLA_ENSURE_INT_OR_BINARY_TYPE(tp),	\
++	.validation_type = NLA_VALIDATE_MIN,		\
++	.min = _min,					\
++}
++
+ /**
+  * struct nl_info - netlink source information
+  * @nlh: Netlink message header of original request
+diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
+index aa543c783529..4eed3507a005 100644
+--- a/include/uapi/linux/ethtool_netlink.h
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -280,6 +280,7 @@ enum {
+ 	ETHTOOL_A_RINGS_RX_MINI,			/* u32 */
+ 	ETHTOOL_A_RINGS_RX_JUMBO,			/* u32 */
+ 	ETHTOOL_A_RINGS_TX,				/* u32 */
++	ETHTOOL_A_RINGS_RX_BUF_LEN,                     /* u32 */
+ 
+ 	/* add new constants above here */
+ 	__ETHTOOL_A_RINGS_CNT,
+diff --git a/net/ethtool/netlink.c b/net/ethtool/netlink.c
+index 7ac8a4524376..d86613309591 100644
+--- a/net/ethtool/netlink.c
++++ b/net/ethtool/netlink.c
+@@ -9,7 +9,7 @@ static struct genl_family ethtool_genl_family;
+ static bool ethnl_ok __read_mostly;
+ static u32 ethnl_bcast_seq;
+ 
+-static const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_MAX + 1] = {
++const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_MAX + 1] = {
+ 	[ETHTOOL_A_HEADER_UNSPEC]	= { .type = NLA_REJECT },
+ 	[ETHTOOL_A_HEADER_DEV_INDEX]	= { .type = NLA_U32 },
+ 	[ETHTOOL_A_HEADER_DEV_NAME]	= { .type = NLA_NUL_STRING,
+diff --git a/net/ethtool/netlink.h b/net/ethtool/netlink.h
+index a862bad9dd06..bc2b83877e01 100644
+--- a/net/ethtool/netlink.h
++++ b/net/ethtool/netlink.h
+@@ -326,6 +326,29 @@ extern const struct ethnl_request_ops ethnl_wol_request_ops;
+ extern const struct ethnl_request_ops ethnl_features_request_ops;
+ extern const struct ethnl_request_ops ethnl_privflags_request_ops;
+ extern const struct ethnl_request_ops ethnl_rings_request_ops;
++extern const struct ethnl_request_ops ethnl_channels_request_ops;
++extern const struct ethnl_request_ops ethnl_coalesce_request_ops;
++extern const struct ethnl_request_ops ethnl_pause_request_ops;
++extern const struct ethnl_request_ops ethnl_eee_request_ops;
++extern const struct ethnl_request_ops ethnl_tsinfo_request_ops;
++
++extern const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_FLAGS + 1];
++extern const struct nla_policy ethnl_header_policy_stats[ETHTOOL_A_HEADER_FLAGS + 1];
++extern const struct nla_policy ethnl_strset_get_policy[ETHTOOL_A_STRSET_COUNTS_ONLY + 1];
++extern const struct nla_policy ethnl_linkinfo_get_policy[ETHTOOL_A_LINKINFO_HEADER + 1];
++extern const struct nla_policy ethnl_linkinfo_set_policy[ETHTOOL_A_LINKINFO_TP_MDIX_CTRL + 1];
++extern const struct nla_policy ethnl_linkmodes_get_policy[ETHTOOL_A_LINKMODES_HEADER + 1];
++extern const struct nla_policy ethnl_linkstate_get_policy[ETHTOOL_A_LINKSTATE_HEADER + 1];
++extern const struct nla_policy ethnl_debug_get_policy[ETHTOOL_A_DEBUG_HEADER + 1];
++extern const struct nla_policy ethnl_debug_set_policy[ETHTOOL_A_DEBUG_MSGMASK + 1];
++extern const struct nla_policy ethnl_wol_get_policy[ETHTOOL_A_WOL_HEADER + 1];
++extern const struct nla_policy ethnl_wol_set_policy[ETHTOOL_A_WOL_SOPASS + 1];
++extern const struct nla_policy ethnl_features_get_policy[ETHTOOL_A_FEATURES_HEADER + 1];
++extern const struct nla_policy ethnl_features_set_policy[ETHTOOL_A_FEATURES_WANTED + 1];
++extern const struct nla_policy ethnl_privflags_get_policy[ETHTOOL_A_PRIVFLAGS_HEADER + 1];
++extern const struct nla_policy ethnl_privflags_set_policy[ETHTOOL_A_PRIVFLAGS_FLAGS + 1];
++extern const struct nla_policy ethnl_rings_get_policy[ETHTOOL_A_RINGS_HEADER + 1];
++extern const struct nla_policy ethnl_rings_set_policy[ETHTOOL_A_RINGS_RX_BUF_LEN + 1];
+ 
+ int ethnl_set_linkinfo(struct sk_buff *skb, struct genl_info *info);
+ int ethnl_set_linkmodes(struct sk_buff *skb, struct genl_info *info);
+diff --git a/net/ethtool/rings.c b/net/ethtool/rings.c
+index 93f428e9a6c2..128e15b10883 100644
+--- a/net/ethtool/rings.c
++++ b/net/ethtool/rings.c
+@@ -10,6 +10,7 @@ struct rings_req_info {
+ struct rings_reply_data {
+ 	struct ethnl_reply_data		base;
+ 	struct ethtool_ringparam	ringparam;
++	struct kernel_ethtool_ringparam	kernel_ringparam;
+ };
+ 
+ #define RINGS_REPDATA(__reply_base) \
+@@ -58,7 +59,8 @@ static int rings_reply_size(const struct ethnl_req_info *req_base,
+ 	       nla_total_size(sizeof(u32)) +	/* _RINGS_RX */
+ 	       nla_total_size(sizeof(u32)) +	/* _RINGS_RX_MINI */
+ 	       nla_total_size(sizeof(u32)) +	/* _RINGS_RX_JUMBO */
+-	       nla_total_size(sizeof(u32));	/* _RINGS_TX */
++	       nla_total_size(sizeof(u32)) +	/* _RINGS_TX */
++	       nla_total_size(sizeof(u32));     /* _RINGS_RX_BUF_LEN */
+ }
+ 
+ static int rings_fill_reply(struct sk_buff *skb,
+@@ -66,6 +68,8 @@ static int rings_fill_reply(struct sk_buff *skb,
+ 			    const struct ethnl_reply_data *reply_base)
+ {
+ 	const struct rings_reply_data *data = RINGS_REPDATA(reply_base);
++	const struct kernel_ethtool_ringparam *kernel_ringparam =
++						&data->kernel_ringparam;
+ 	const struct ethtool_ringparam *ringparam = &data->ringparam;
+ 
+ 	if ((ringparam->rx_max_pending &&
+@@ -87,7 +91,10 @@ static int rings_fill_reply(struct sk_buff *skb,
+ 	     (nla_put_u32(skb, ETHTOOL_A_RINGS_TX_MAX,
+ 			  ringparam->tx_max_pending) ||
+ 	      nla_put_u32(skb, ETHTOOL_A_RINGS_TX,
+-			  ringparam->tx_pending))))
++			  ringparam->tx_pending)))  ||
++	    (kernel_ringparam->rx_buf_len &&
++	     (nla_put_u32(skb, ETHTOOL_A_RINGS_RX_BUF_LEN,
++			  kernel_ringparam->rx_buf_len))))
+ 		return -EMSGSIZE;
+ 
+ 	return 0;
+@@ -121,11 +128,13 @@ rings_set_policy[ETHTOOL_A_RINGS_MAX + 1] = {
+ 	[ETHTOOL_A_RINGS_RX_MINI]		= { .type = NLA_U32 },
+ 	[ETHTOOL_A_RINGS_RX_JUMBO]		= { .type = NLA_U32 },
+ 	[ETHTOOL_A_RINGS_TX]			= { .type = NLA_U32 },
++	[ETHTOOL_A_RINGS_RX_BUF_LEN]            = NLA_POLICY_MIN(NLA_U32, 1),
+ };
+ 
+ int ethnl_set_rings(struct sk_buff *skb, struct genl_info *info)
+ {
+ 	struct nlattr *tb[ETHTOOL_A_RINGS_MAX + 1];
++	struct kernel_ethtool_ringparam kernel_ringparam = {};
+ 	struct ethtool_ringparam ringparam = {};
+ 	struct ethnl_req_info req_info = {};
+ 	const struct nlattr *err_attr;
+@@ -163,6 +172,8 @@ int ethnl_set_rings(struct sk_buff *skb, struct genl_info *info)
+ 	ethnl_update_u32(&ringparam.rx_jumbo_pending,
+ 			 tb[ETHTOOL_A_RINGS_RX_JUMBO], &mod);
+ 	ethnl_update_u32(&ringparam.tx_pending, tb[ETHTOOL_A_RINGS_TX], &mod);
++	ethnl_update_u32(&kernel_ringparam.rx_buf_len,
++			 tb[ETHTOOL_A_RINGS_RX_BUF_LEN], &mod);
+ 	ret = 0;
+ 	if (!mod)
+ 		goto out_ops;
+@@ -185,6 +196,15 @@ int ethnl_set_rings(struct sk_buff *skb, struct genl_info *info)
+ 		goto out_ops;
+ 	}
+ 
++	if (kernel_ringparam.rx_buf_len != 0 &&
++	    !(ops->supported_ring_params & ETHTOOL_RING_USE_RX_BUF_LEN)) {
++		ret = -EOPNOTSUPP;
++		NL_SET_ERR_MSG_ATTR(info->extack,
++				    tb[ETHTOOL_A_RINGS_RX_BUF_LEN],
++				    "setting rx buf len not supported");
++		goto out_ops;
++	}
++
+ 	ret = dev->ethtool_ops->set_ringparam(dev, &ringparam);
+ 
+ out_ops:
+-- 
+2.34.1
+
diff --git a/patches/0529-net-hns3-add-support-to-set-get-rx-buf-len-via-ethto.patch b/patches/0529-net-hns3-add-support-to-set-get-rx-buf-len-via-ethto.patch
new file mode 100644
index 0000000..10fb5fd
--- /dev/null
+++ b/patches/0529-net-hns3-add-support-to-set-get-rx-buf-len-via-ethto.patch
@@ -0,0 +1,183 @@
+From ee9b56e619331100993c4682ba0d344ce959a44a Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Mon, 27 Dec 2021 19:41:42 +0800
+Subject: [PATCH 168/283] net: hns3: add support to set/get rx buf len via
+ ethtool for hns3 driver
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit e65a0231d2caf7d30548964c7bba4c3016dea1d2
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e65a0231d2caf7d30548964c7bba4c3016dea1d2
+
+----------------------------------------------------------------------
+
+Rx buf len is for rx BD buffer size, support setting it via ethtool -G
+parameter and getting it via ethtool -g parameter.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+---
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 52 ++++++++++++++++---
+ 1 file changed, 44 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 8da002d6d0b9..752cc41f529e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -655,7 +655,7 @@ static void hns3_get_ringparam(struct net_device *netdev,
+ {
+ 	struct hns3_nic_priv *priv = netdev_priv(netdev);
+ 	struct hnae3_handle *h = priv->ae_handle;
+-	int queue_num = h->kinfo.num_tqps;
++	int rx_queue_index = h->kinfo.num_tqps;
+ 
+ 	if (hns3_nic_resetting(netdev)) {
+ 		netdev_err(netdev, "dev resetting!");
+@@ -666,7 +666,8 @@ static void hns3_get_ringparam(struct net_device *netdev,
+ 	param->rx_max_pending = HNS3_RING_MAX_PENDING;
+ 
+ 	param->tx_pending = priv->ring[0].desc_num;
+-	param->rx_pending = priv->ring[queue_num].desc_num;
++	param->rx_pending = priv->ring[rx_queue_index].desc_num;
++	kernel_param->rx_buf_len = priv->ring[rx_queue_index].buf_size;
+ }
+ 
+ static void hns3_get_pauseparam(struct net_device *netdev,
+@@ -1065,14 +1066,23 @@ static struct hns3_enet_ring *hns3_backup_ringparam(struct hns3_nic_priv *priv)
+ }
+ 
+ static int hns3_check_ringparam(struct net_device *ndev,
+-				struct ethtool_ringparam *param)
++				struct ethtool_ringparam *param,
++				struct kernel_ethtool_ringparam *kernel_param)
+ {
++#define RX_BUF_LEN_2K 2048
++#define RX_BUF_LEN_4K 4096
+ 	if (hns3_nic_resetting(ndev))
+ 		return -EBUSY;
+ 
+ 	if (param->rx_mini_pending || param->rx_jumbo_pending)
+ 		return -EINVAL;
+ 
++	if (kernel_param->rx_buf_len != RX_BUF_LEN_2K &&
++	    kernel_param->rx_buf_len != RX_BUF_LEN_4K) {
++		netdev_err(ndev, "Rx buf len only support 2048 and 4096\n");
++		return -EINVAL;
++	}
++
+ 	if (param->tx_pending > HNS3_RING_MAX_PENDING ||
+ 	    param->tx_pending < HNS3_RING_MIN_PENDING ||
+ 	    param->rx_pending > HNS3_RING_MAX_PENDING ||
+@@ -1085,6 +1095,22 @@ static int hns3_check_ringparam(struct net_device *ndev,
+ 	return 0;
+ }
+ 
++static int hns3_change_rx_buf_len(struct net_device *ndev, u32 rx_buf_len)
++{
++	struct hns3_nic_priv *priv = netdev_priv(ndev);
++	struct hnae3_handle *h = priv->ae_handle;
++	int i;
++
++	h->kinfo.rx_buf_len = rx_buf_len;
++
++	for (i = 0; i < h->kinfo.num_tqps; i++) {
++		h->kinfo.tqp[i]->buf_size = rx_buf_len;
++		priv->ring[i + h->kinfo.num_tqps].buf_size = rx_buf_len;
++	}
++
++	return 0;
++}
++
+ static int hns3_set_ringparam(struct net_device *ndev,
+ 			      struct ethtool_ringparam *param)
+ {
+@@ -1095,9 +1121,10 @@ static int hns3_set_ringparam(struct net_device *ndev,
+ 	u32 old_rx_desc_num, new_rx_desc_num;
+ 	u16 queue_num = h->kinfo.num_tqps;
+ 	struct hns3_enet_ring *tmp_rings;
++	u32 old_rx_buf_len;
+ 	int ret, i;
+ 
+-	ret = hns3_check_ringparam(ndev, param);
++	ret = hns3_check_ringparam(ndev, param, kernel_param);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -1106,8 +1133,10 @@ static int hns3_set_ringparam(struct net_device *ndev,
+ 	new_rx_desc_num = ALIGN(param->rx_pending, HNS3_RING_BD_MULTIPLE);
+ 	old_tx_desc_num = priv->ring[0].desc_num;
+ 	old_rx_desc_num = priv->ring[queue_num].desc_num;
++	old_rx_buf_len = priv->ring[queue_num].buf_size;
+ 	if (old_tx_desc_num == new_tx_desc_num &&
+-	    old_rx_desc_num == new_rx_desc_num)
++	    old_rx_desc_num == new_rx_desc_num &&
++	    kernel_param->rx_buf_len == old_rx_buf_len)
+ 		return 0;
+ 
+ 	tmp_rings = hns3_backup_ringparam(priv);
+@@ -1118,19 +1147,22 @@ static int hns3_set_ringparam(struct net_device *ndev,
+ 	}
+ 
+ 	netdev_info(ndev,
+-		    "Changing Tx/Rx ring depth from %u/%u to %u/%u\n",
++		    "Changing Tx/Rx ring depth from %u/%u to %u/%u, Changing rx buffer len from %d to %d\n",
+ 		    old_tx_desc_num, old_rx_desc_num,
+-		    new_tx_desc_num, new_rx_desc_num);
++		    new_tx_desc_num, new_rx_desc_num,
++		    old_rx_buf_len, kernel_param->rx_buf_len);
+ 
+ 	if (if_running)
+ 		ndev->netdev_ops->ndo_stop(ndev);
+ 
+ 	hns3_change_all_ring_bd_num(priv, new_tx_desc_num, new_rx_desc_num);
++	hns3_change_rx_buf_len(ndev, kernel_param->rx_buf_len);
+ 	ret = hns3_init_all_ring(priv);
+ 	if (ret) {
+-		netdev_err(ndev, "Change bd num fail, revert to old value(%d)\n",
++		netdev_err(ndev, "set ringparam fail, revert to old value(%d)\n",
+ 			   ret);
+ 
++		hns3_change_rx_buf_len(ndev, old_rx_buf_len);
+ 		hns3_change_all_ring_bd_num(priv, old_tx_desc_num,
+ 					    old_rx_desc_num);
+ 		for (i = 0; i < h->kinfo.num_tqps * 2; i++)
+@@ -1792,6 +1824,8 @@ static int hns3_set_tunable(struct net_device *netdev,
+ 				 ETHTOOL_COALESCE_TX_USECS_HIGH |	\
+ 				 ETHTOOL_COALESCE_MAX_FRAMES)
+ 
++#define HNS3_ETHTOOL_RING	ETHTOOL_RING_USE_RX_BUF_LEN
++
+ static int hns3_get_ts_info(struct net_device *netdev,
+ 			    struct ethtool_ts_info *info)
+ {
+@@ -1870,6 +1904,7 @@ static int hns3_get_link_ext_state(struct net_device *netdev,
+ 
+ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ 	.supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
++	.supported_ring_params = HNS3_ETHTOOL_RING,
+ 	.get_drvinfo = hns3_get_drvinfo,
+ 	.get_ringparam = hns3_get_ringparam,
+ 	.set_ringparam = hns3_set_ringparam,
+@@ -1901,6 +1936,7 @@ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ 
+ static const struct ethtool_ops hns3_ethtool_ops = {
+ 	.supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
++	.supported_ring_params = HNS3_ETHTOOL_RING,
+ 	.self_test = hns3_self_test,
+ 	.get_drvinfo = hns3_get_drvinfo,
+ 	.get_link = hns3_get_link,
+-- 
+2.34.1
+
diff --git a/patches/0530-net-hns3-remove-the-way-to-set-tx-spare-buf-via-modu.patch b/patches/0530-net-hns3-remove-the-way-to-set-tx-spare-buf-via-modu.patch
new file mode 100644
index 0000000..af8fc91
--- /dev/null
+++ b/patches/0530-net-hns3-remove-the-way-to-set-tx-spare-buf-via-modu.patch
@@ -0,0 +1,61 @@
+From 589d6121b792a8c81fa6e7dbb7c95d52440e0753 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Mon, 27 Dec 2021 19:41:43 +0800
+Subject: [PATCH 169/283] net: hns3: remove the way to set tx spare buf via
+ module parameter
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit e175eb5fb05462398452e31df5019d780badf45d
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e175eb5fb05462398452e31df5019d780badf45d
+
+----------------------------------------------------------------------
+
+The way to set tx spare buf via module parameter is not such
+convenient as the way to set it via ethtool.
+
+So,remove the way to set tx spare buf via module parameter.
+
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 363b92e6298c..f7f9a79d299f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -52,10 +52,6 @@ static int debug = -1;
+ module_param(debug, int, 0);
+ MODULE_PARM_DESC(debug, " Network interface message level setting");
+ 
+-static unsigned int tx_spare_buf_size;
+-module_param(tx_spare_buf_size, uint, 0400);
+-MODULE_PARM_DESC(tx_spare_buf_size, "Size used to allocate tx spare buffer");
+-
+ static unsigned int tx_sgl = 1;
+ module_param(tx_sgl, uint, 0600);
+ MODULE_PARM_DESC(tx_sgl, "Minimum number of frags when using dma_map_sg() to optimize the IOMMU mapping");
+@@ -745,8 +741,7 @@ static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
+ 	dma_addr_t dma;
+ 	int order;
+ 
+-	alloc_size = tx_spare_buf_size ? tx_spare_buf_size :
+-		     ring->tqp->handle->kinfo.tx_spare_buf_size;
++	alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
+ 	if (!alloc_size)
+ 		return;
+ 
+-- 
+2.34.1
+
diff --git a/patches/0531-net-hns3-debugfs-add-drop-packet-statistics-of-multi.patch b/patches/0531-net-hns3-debugfs-add-drop-packet-statistics-of-multi.patch
new file mode 100644
index 0000000..cc23592
--- /dev/null
+++ b/patches/0531-net-hns3-debugfs-add-drop-packet-statistics-of-multi.patch
@@ -0,0 +1,55 @@
+From 5403f80bad470858de567b32d9809ca843cdd73c Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Mon, 27 Dec 2021 19:41:46 +0800
+Subject: [PATCH 170/283] net: hns3: debugfs add drop packet statistics of
+ multicast and broadcast for igu
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit 8488e3c682147f60d592b03bc69eaea0fbe1ebcf
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8488e3c682147f60d592b03bc69eaea0fbe1ebcf
+
+----------------------------------------------------------------------
+
+Currently, there is no way to get drop packet number of multicast and
+broadcast in IGU hardware module, it is not convenient to find problem
+when multicast packet or broadcast packet is dropped in IGU, so this
+patch adds statistics for them in debugfs.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h    | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h
+index dab61afe3d33..3ea03d12b0d1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h
+@@ -340,10 +340,10 @@ static const struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = {
+ 	{true,	"IGU_RX_OUT_UDP0_PKT"},
+ 
+ 	{true,	"IGU_RX_IN_UDP0_PKT"},
+-	{false, "Reserved"},
+-	{false, "Reserved"},
+-	{false, "Reserved"},
+-	{false, "Reserved"},
++	{true,	"IGU_MC_CAR_DROP_PKT_L"},
++	{true,	"IGU_MC_CAR_DROP_PKT_H"},
++	{true,	"IGU_BC_CAR_DROP_PKT_L"},
++	{true,	"IGU_BC_CAR_DROP_PKT_H"},
+ 	{false, "Reserved"},
+ 
+ 	{true,	"IGU_RX_OVERSIZE_PKT_L"},
+-- 
+2.34.1
+
diff --git a/patches/0532-net-hns3-add-dql-info-when-tx-timeout.patch b/patches/0532-net-hns3-add-dql-info-when-tx-timeout.patch
new file mode 100644
index 0000000..ea079f7
--- /dev/null
+++ b/patches/0532-net-hns3-add-dql-info-when-tx-timeout.patch
@@ -0,0 +1,51 @@
+From 5b7345e485cda6e80e225d890d71b24026a4031b Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Mon, 27 Dec 2021 19:41:47 +0800
+Subject: [PATCH 171/283] net: hns3: add dql info when tx timeout
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit db596298edbf18c8a0d2778ca4d76ee09ed761f6
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=db596298edbf18c8a0d2778ca4d76ee09ed761f6
+
+----------------------------------------------------------------------
+
+When tx timeout occurs, the info of dql maybe helpful, so print
+these info to hns3_get_tx_timeo_queue_info().
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index f7f9a79d299f..19ba800afc6c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -2367,6 +2367,13 @@ bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
+ 		if (netif_xmit_stopped(q) &&
+ 		    time_after(jiffies,
+ 			       (trans_start + ndev->watchdog_timeo))) {
++#ifdef CONFIG_BQL
++			struct dql *dql = &q->dql;
++
++			netdev_info(ndev, "DQL info last_cnt: %u, queued: %u, adj_limit: %u, completed: %u\n",
++				    dql->last_obj_cnt, dql->num_queued,
++				    dql->adj_limit, dql->num_completed);
++#endif
+ 			timeout_queue = i;
+ 			netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
+ 				    q->state,
+-- 
+2.34.1
+
diff --git a/patches/0533-net-hns3-fix-incorrect-components-info-of-ethtool-re.patch b/patches/0533-net-hns3-fix-incorrect-components-info-of-ethtool-re.patch
new file mode 100644
index 0000000..8a66d2d
--- /dev/null
+++ b/patches/0533-net-hns3-fix-incorrect-components-info-of-ethtool-re.patch
@@ -0,0 +1,67 @@
+From 7583eb532f7e773691d2a04f98a4407333b06524 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Mon, 27 Dec 2021 19:41:51 +0800
+Subject: [PATCH 172/283] net: hns3: fix incorrect components info of ethtool
+ --reset command
+
+mainline inclusion
+from mainline-v5.16-rc3
+commit 82229c4dbb8a2780f05fa1bab29c97ef7bcd21bb
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=82229c4dbb8a2780f05fa1bab29c97ef7bcd21bb
+
+----------------------------------------------------------------------
+
+Currently, HNS3 driver doesn't clear the reset flags of components after
+successfully executing reset, it causes userspace info of
+"Components reset" and "Components not reset" is incorrect.
+
+So fix this problem by clear corresponding reset flag after reset process.
+
+Fixes: ddccc5e368a3 ("net: hns3: add support for triggering reset by ethtool")
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 752cc41f529e..a7f4820f6f8c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -993,6 +993,7 @@ static int hns3_set_reset(struct net_device *netdev, u32 *flags)
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(h->pdev);
+ 	const struct hnae3_ae_ops *ops = h->ae_algo->ops;
+ 	const struct hns3_reset_type_map *rst_type_map;
++	enum ethtool_reset_flags rst_flags;
+ 	u32 i, size;
+ 
+ 	if (ops->ae_dev_resetting && ops->ae_dev_resetting(h))
+@@ -1012,6 +1013,7 @@ static int hns3_set_reset(struct net_device *netdev, u32 *flags)
+ 	for (i = 0; i < size; i++) {
+ 		if (rst_type_map[i].rst_flags == *flags) {
+ 			rst_type = rst_type_map[i].rst_type;
++			rst_flags = rst_type_map[i].rst_flags;
+ 			break;
+ 		}
+ 	}
+@@ -1027,6 +1029,8 @@ static int hns3_set_reset(struct net_device *netdev, u32 *flags)
+ 
+ 	ops->reset_event(h->pdev, h);
+ 
++	*flags &= ~rst_flags;
++
+ 	return 0;
+ }
+ 
+-- 
+2.34.1
+
diff --git a/patches/0534-net-hns3-create-new-cmdq-hardware-description-struct.patch b/patches/0534-net-hns3-create-new-cmdq-hardware-description-struct.patch
new file mode 100644
index 0000000..3073c31
--- /dev/null
+++ b/patches/0534-net-hns3-create-new-cmdq-hardware-description-struct.patch
@@ -0,0 +1,154 @@
+From 46b0da78c7c1deae0bb38d5943ce717e1f967143 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:47 +0800
+Subject: [PATCH 173/283] net: hns3: create new cmdq hardware description
+ structure hclge_comm_hw
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit 0a7b6d221868be6aa3249c70ffab707a265b89d6
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0a7b6d221868be6aa3249c70ffab707a265b89d6
+
+----------------------------------------------------------------------
+
+Currently PF and VF cmdq APIs use struct hclge(vf)_hw to describe cmdq
+hardware information needed by hclge(vf)_cmd_send. There are a little
+differences between its child struct hclge_cmq_ring and hclgevf_cmq_ring.
+It is redundent to use two sets of structures to support same functions.
+
+So this patch creates new set of common cmdq hardware description
+structures(hclge_comm_hw) to unify PF and VF cmdq functions. The struct
+hclge_desc is still kept to avoid too many meaningless replacement.
+
+These new structures will be used to unify hclge(vf)_hw structures in PF
+and VF cmdq APIs in next patches.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/Makefile
+---
+ drivers/net/ethernet/hisilicon/hns3/Makefile  |  3 +-
+ .../hns3/hns3_common/hclge_comm_cmd.h         | 55 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  9 +--
+ 3 files changed, 58 insertions(+), 9 deletions(-)
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile
+index c012979b86be..70bf49da5591 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/Makefile
+@@ -13,7 +13,8 @@ ccflags-y += 	-I$(PWD) \
+ 		-I$(PWD)/hns3_extension \
+ 		-I$(PWD)/hns3_extension/hns3pf \
+ 		-I$(PWD)/hns3vf \
+-		-I$(PWD)/hns3_cae
++		-I$(PWD)/hns3_cae \
++		-I$(PWD)/hns3_common
+ 
+ #### compile hnae3.ko
+ obj-$(CONFIG_HNS3) += hnae3.o
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+new file mode 100644
+index 000000000000..f1e39003ceeb
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -0,0 +1,55 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++// Copyright (c) 2021-2021 Hisilicon Limited.
++
++#ifndef __HCLGE_COMM_CMD_H
++#define __HCLGE_COMM_CMD_H
++#include <linux/types.h>
++
++#include "hnae3.h"
++
++#define HCLGE_DESC_DATA_LEN		6
++struct hclge_desc {
++	__le16 opcode;
++	__le16 flag;
++	__le16 retval;
++	__le16 rsv;
++	__le32 data[HCLGE_DESC_DATA_LEN];
++};
++
++struct hclge_comm_cmq_ring {
++	dma_addr_t desc_dma_addr;
++	struct hclge_desc *desc;
++	struct pci_dev *pdev;
++	u32 head;
++	u32 tail;
++
++	u16 buf_size;
++	u16 desc_num;
++	int next_to_use;
++	int next_to_clean;
++	u8 ring_type; /* cmq ring type */
++	spinlock_t lock; /* Command queue lock */
++};
++
++enum hclge_comm_cmd_status {
++	HCLGE_COMM_STATUS_SUCCESS	= 0,
++	HCLGE_COMM_ERR_CSQ_FULL		= -1,
++	HCLGE_COMM_ERR_CSQ_TIMEOUT	= -2,
++	HCLGE_COMM_ERR_CSQ_ERROR	= -3,
++};
++
++struct hclge_comm_cmq {
++	struct hclge_comm_cmq_ring csq;
++	struct hclge_comm_cmq_ring crq;
++	u16 tx_timeout;
++	enum hclge_comm_cmd_status last_status;
++};
++
++struct hclge_comm_hw {
++	void __iomem *io_base;
++	void __iomem *mem_base;
++	struct hclge_comm_cmq cmq;
++	unsigned long comm_state;
++};
++
++#endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 882e14a15128..52e8f318fd96 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -7,24 +7,17 @@
+ #include <linux/types.h>
+ #include <linux/io.h>
+ #include "hnae3.h"
++#include "hclge_comm_cmd.h"
+ 
+ #define HCLGE_CMDQ_TX_TIMEOUT		30000
+ #define HCLGE_CMDQ_CLEAR_WAIT_TIME	200
+ #define HCLGE_DESC_DATA_LEN		6
+ 
+ struct hclge_dev;
+-struct hclge_desc {
+-	__le16 opcode;
+ 
+ #define HCLGE_CMDQ_RX_INVLD_B		0
+ #define HCLGE_CMDQ_RX_OUTVLD_B		1
+ 
+-	__le16 flag;
+-	__le16 retval;
+-	__le16 rsv;
+-	__le32 data[HCLGE_DESC_DATA_LEN];
+-};
+-
+ struct hclge_cmq_ring {
+ 	dma_addr_t desc_dma_addr;
+ 	struct hclge_desc *desc;
+-- 
+2.34.1
+
diff --git a/patches/0535-net-hns3-use-struct-hclge_desc-to-replace-hclgevf_de.patch b/patches/0535-net-hns3-use-struct-hclge_desc-to-replace-hclgevf_de.patch
new file mode 100644
index 0000000..b948ea3
--- /dev/null
+++ b/patches/0535-net-hns3-use-struct-hclge_desc-to-replace-hclgevf_de.patch
@@ -0,0 +1,304 @@
+From e5088761e0c437bedc1e54d84927026f8717a6a9 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:48 +0800
+Subject: [PATCH 174/283] net: hns3: use struct hclge_desc to replace
+ hclgevf_desc in VF cmdq module
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit 6befad603d79be43cfece9f41309e5cc9546beba
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6befad603d79be43cfece9f41309e5cc9546beba
+
+----------------------------------------------------------------------
+
+This patch use new common struct hclge_desc to replace struct hclgevf_desc
+in VF cmdq module and then delete the old struct hclgevf_desc.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+---
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       | 22 +++++++++----------
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       | 15 ++++---------
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 22 +++++++++----------
+ .../hisilicon/hns3/hns3vf/hclgevf_mbx.c       |  4 ++--
+ 4 files changed, 28 insertions(+), 35 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 12b241c0db0a..b0fc21fe3c82 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -138,7 +138,7 @@ static void hclgevf_cmd_clear_regs(struct hclgevf_hw *hw)
+ 
+ static int hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring *ring)
+ {
+-	int size = ring->desc_num * sizeof(struct hclgevf_desc);
++	int size = ring->desc_num * sizeof(struct hclge_desc);
+ 
+ 	ring->desc = dma_zalloc_coherent(cmq_ring_to_dev(ring),
+ 					 size, &ring->desc_dma_addr,
+@@ -151,7 +151,7 @@ static int hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring *ring)
+ 
+ static void hclgevf_free_cmd_desc(struct hclgevf_cmq_ring *ring)
+ {
+-	int size  = ring->desc_num * sizeof(struct hclgevf_desc);
++	int size  = ring->desc_num * sizeof(struct hclge_desc);
+ 
+ 	if (ring->desc) {
+ 		dma_free_coherent(cmq_ring_to_dev(ring), size,
+@@ -179,10 +179,10 @@ static int hclgevf_alloc_cmd_queue(struct hclgevf_dev *hdev, int ring_type)
+ 	return ret;
+ }
+ 
+-void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
++void hclgevf_cmd_setup_basic_desc(struct hclge_desc *desc,
+ 				  enum hclgevf_opcode_type opcode, bool is_read)
+ {
+-	memset(desc, 0, sizeof(struct hclgevf_desc));
++	memset(desc, 0, sizeof(struct hclge_desc));
+ 	desc->opcode = cpu_to_le16(opcode);
+ 	desc->flag = cpu_to_le16(HCLGEVF_CMD_FLAG_NO_INTR |
+ 				 HCLGEVF_CMD_FLAG_IN);
+@@ -198,9 +198,9 @@ struct vf_errcode {
+ };
+ 
+ static void hclgevf_cmd_copy_desc(struct hclgevf_hw *hw,
+-				  struct hclgevf_desc *desc, int num)
++				  struct hclge_desc *desc, int num)
+ {
+-	struct hclgevf_desc *desc_to_use;
++	struct hclge_desc *desc_to_use;
+ 	int handle = 0;
+ 
+ 	while (handle < num) {
+@@ -240,7 +240,7 @@ static int hclgevf_cmd_convert_err_code(u16 desc_ret)
+ }
+ 
+ static int hclgevf_cmd_check_retval(struct hclgevf_hw *hw,
+-				    struct hclgevf_desc *desc, int num, int ntc)
++				    struct hclge_desc *desc, int num, int ntc)
+ {
+ 	u16 opcode, desc_ret;
+ 	int handle;
+@@ -263,7 +263,7 @@ static int hclgevf_cmd_check_retval(struct hclgevf_hw *hw,
+ }
+ 
+ static int hclgevf_cmd_check_result(struct hclgevf_hw *hw,
+-				    struct hclgevf_desc *desc, int num, int ntc)
++				    struct hclge_desc *desc, int num, int ntc)
+ {
+ 	struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
+ 	bool is_completed = false;
+@@ -307,7 +307,7 @@ static int hclgevf_cmd_check_result(struct hclgevf_hw *hw,
+  * This is the main send command for command queue, it
+  * sends the queue, cleans the queue, etc
+  */
+-int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
++int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num)
+ {
+ 	struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
+ 	struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
+@@ -384,7 +384,7 @@ static int hclgevf_cmd_query_version_and_capability(struct hclgevf_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct hclgevf_query_version_cmd *resp;
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	int status;
+ 
+ 	resp = (struct hclgevf_query_version_cmd *)desc.data;
+@@ -448,7 +448,7 @@ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
+ static int hclgevf_firmware_compat_config(struct hclgevf_dev *hdev, bool en)
+ {
+ 	struct hclgevf_firmware_compat_cmd *req;
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	u32 compat = 0;
+ 
+ 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_IMP_COMPAT_CFG, false);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 6d0540c15487..96a41f0e2991 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -6,6 +6,7 @@
+ #include <linux/io.h>
+ #include <linux/types.h>
+ #include "hnae3.h"
++#include "hclge_comm_cmd.h"
+ 
+ #define HCLGEVF_CMDQ_TX_TIMEOUT		30000
+ #define HCLGEVF_CMDQ_CLEAR_WAIT_TIME	200
+@@ -21,14 +22,6 @@ struct hclgevf_firmware_compat_cmd {
+ 	u8 rsv[20];
+ };
+ 
+-struct hclgevf_desc {
+-	__le16 opcode;
+-	__le16 flag;
+-	__le16 retval;
+-	__le16 rsv;
+-	__le32 data[6];
+-};
+-
+ struct hclgevf_desc_cb {
+ 	dma_addr_t dma;
+ 	void *va;
+@@ -37,7 +30,7 @@ struct hclgevf_desc_cb {
+ 
+ struct hclgevf_cmq_ring {
+ 	dma_addr_t desc_dma_addr;
+-	struct hclgevf_desc *desc;
++	struct hclge_desc *desc;
+ 	struct hclgevf_desc_cb *desc_cb;
+ 	struct hclgevf_dev  *dev;
+ 	u32 head;
+@@ -326,8 +319,8 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev);
+ void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
+ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
+ 
+-int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num);
+-void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
++int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num);
++void hclgevf_cmd_setup_basic_desc(struct hclge_desc *desc,
+ 				  enum hclgevf_opcode_type opcode,
+ 				  bool is_read);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 2457feb0e95f..ffac4a4aa66a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -105,7 +105,7 @@ static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
+ {
+ 	struct hnae3_knic_private_info *kinfo = &handle->kinfo;
+ 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	struct hclgevf_tqp *tqp;
+ 	int status;
+ 	int i;
+@@ -593,7 +593,7 @@ static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
+ {
+ 	struct hclgevf_rss_config_cmd *req;
+ 	unsigned int key_offset = 0;
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	int key_counts;
+ 	int key_size;
+ 	int ret;
+@@ -642,7 +642,7 @@ static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
+ {
+ 	const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
+ 	struct hclgevf_rss_indirection_table_cmd *req;
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	int status;
+ 	int i, j;
+ 
+@@ -677,7 +677,7 @@ static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev,  u16 rss_size)
+ 	u16 tc_offset[HCLGEVF_MAX_TC_NUM];
+ 	u16 tc_valid[HCLGEVF_MAX_TC_NUM];
+ 	u16 tc_size[HCLGEVF_MAX_TC_NUM];
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	u16 roundup_size;
+ 	unsigned int i;
+ 	int status;
+@@ -889,7 +889,7 @@ static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
+ 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
+ 	struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
+ 	struct hclgevf_rss_input_tuple_cmd *req;
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	u8 tuple_sets;
+ 	int ret;
+ 
+@@ -1039,7 +1039,7 @@ static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
+ 				       struct hclgevf_rss_cfg *rss_cfg)
+ {
+ 	struct hclgevf_rss_input_tuple_cmd *req;
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	int ret;
+ 
+ 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
+@@ -1238,7 +1238,7 @@ static int hclgevf_tqp_enable_cmd_send(struct hclgevf_dev *hdev, u16 tqp_id,
+ 				       u16 stream_id, bool enable)
+ {
+ 	struct hclgevf_cfg_com_tqp_queue_cmd *req;
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 
+ 	req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
+ 
+@@ -2498,7 +2498,7 @@ static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
+ static int hclgevf_config_gro(struct hclgevf_dev *hdev)
+ {
+ 	struct hclgevf_cfg_gro_status_cmd *req;
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	int ret;
+ 
+ 	if (!hnae3_dev_gro_supported(hdev))
+@@ -3034,7 +3034,7 @@ static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
+ static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
+ {
+ 	struct hclgevf_query_res_cmd *req;
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	int ret;
+ 
+ 	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
+@@ -3096,7 +3096,7 @@ static void hclgevf_set_default_dev_specs(struct hclgevf_dev *hdev)
+ }
+ 
+ static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
+-				    struct hclgevf_desc *desc)
++				    struct hclge_desc *desc)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct hclgevf_dev_specs_0_cmd *req0;
+@@ -3115,7 +3115,7 @@ static void hclgevf_parse_dev_specs(struct hclgevf_dev *hdev,
+ 
+ static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
+ {
+-	struct hclgevf_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];
++	struct hclge_desc desc[HCLGEVF_QUERY_DEV_SPECS_BD_NUM];
+ 	int ret;
+ 	int i;
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+index 510d9826e998..5e43289d714a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+@@ -122,7 +122,7 @@ int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev,
+ 			 u8 *resp_data, u16 resp_len)
+ {
+ 	struct hclge_mbx_vf_to_pf_cmd *req;
+-	struct hclgevf_desc desc;
++	struct hclge_desc desc;
+ 	int status;
+ 
+ 	req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
+@@ -238,7 +238,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
+ {
+ 	struct hclge_mbx_pf_to_vf_cmd *req;
+ 	struct hclgevf_cmq_ring *crq;
+-	struct hclgevf_desc *desc;
++	struct hclge_desc *desc;
+ 	u16 flag;
+ 
+ 	crq = &hdev->hw.cmq.crq;
+-- 
+2.34.1
+
diff --git a/patches/0536-net-hns3-create-new-set-of-unified-hclge_comm_cmd_se.patch b/patches/0536-net-hns3-create-new-set-of-unified-hclge_comm_cmd_se.patch
new file mode 100644
index 0000000..82a81a6
--- /dev/null
+++ b/patches/0536-net-hns3-create-new-set-of-unified-hclge_comm_cmd_se.patch
@@ -0,0 +1,388 @@
+From 64214f889cf9be67c0972f913b16c338e38f5a5d Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:49 +0800
+Subject: [PATCH 175/283] net: hns3: create new set of unified
+ hclge_comm_cmd_send APIs
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit 8d307f8e8cf195921b10939dde673f1f039bd732
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8d307f8e8cf195921b10939dde673f1f039bd732
+
+----------------------------------------------------------------------
+
+This patch create new set of unified hclge_comm_cmd_send APIs for PF and VF
+cmdq module. Subfunctions called by hclge_comm_cmd_send are also created
+include cmdq result check, cmdq return code conversion and ring space
+opertaion APIs.
+
+These new common cmdq APIs will be used to replace the old PF and VF cmdq
+APIs in next patches.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hns3/hns3_common/hclge_comm_cmd.c         | 259 ++++++++++++++++++
+ .../hns3/hns3_common/hclge_comm_cmd.h         |  66 +++++
+ 2 files changed, 325 insertions(+)
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+new file mode 100644
+index 000000000000..89e999248b9a
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -0,0 +1,259 @@
++// SPDX-License-Identifier: GPL-2.0+
++// Copyright (c) 2021-2021 Hisilicon Limited.
++
++#include "hnae3.h"
++#include "hclge_comm_cmd.h"
++
++static bool hclge_is_elem_in_array(const u16 *spec_opcode, u32 size, u16 opcode)
++{
++	u32 i;
++
++	for (i = 0; i < size; i++) {
++		if (spec_opcode[i] == opcode)
++			return true;
++	}
++
++	return false;
++}
++
++static const u16 pf_spec_opcode[] = { HCLGE_COMM_OPC_STATS_64_BIT,
++				      HCLGE_COMM_OPC_STATS_32_BIT,
++				      HCLGE_COMM_OPC_STATS_MAC,
++				      HCLGE_COMM_OPC_STATS_MAC_ALL,
++				      HCLGE_COMM_OPC_QUERY_32_BIT_REG,
++				      HCLGE_COMM_OPC_QUERY_64_BIT_REG,
++				      HCLGE_COMM_QUERY_CLEAR_MPF_RAS_INT,
++				      HCLGE_COMM_QUERY_CLEAR_PF_RAS_INT,
++				      HCLGE_COMM_QUERY_CLEAR_ALL_MPF_MSIX_INT,
++				      HCLGE_COMM_QUERY_CLEAR_ALL_PF_MSIX_INT,
++				      HCLGE_COMM_QUERY_ALL_ERR_INFO };
++
++static const u16 vf_spec_opcode[] = { HCLGE_COMM_OPC_STATS_64_BIT,
++				      HCLGE_COMM_OPC_STATS_32_BIT,
++				      HCLGE_COMM_OPC_STATS_MAC };
++
++static bool hclge_comm_is_special_opcode(u16 opcode, bool is_pf)
++{
++	/* these commands have several descriptors,
++	 * and use the first one to save opcode and return value
++	 */
++	const u16 *spec_opcode = is_pf ? pf_spec_opcode : vf_spec_opcode;
++	u32 size = is_pf ? ARRAY_SIZE(pf_spec_opcode) :
++				ARRAY_SIZE(vf_spec_opcode);
++
++	return hclge_is_elem_in_array(spec_opcode, size, opcode);
++}
++
++static int hclge_comm_ring_space(struct hclge_comm_cmq_ring *ring)
++{
++	int ntc = ring->next_to_clean;
++	int ntu = ring->next_to_use;
++	int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
++
++	return ring->desc_num - used - 1;
++}
++
++static void hclge_comm_cmd_copy_desc(struct hclge_comm_hw *hw,
++				     struct hclge_desc *desc, int num)
++{
++	struct hclge_desc *desc_to_use;
++	int handle = 0;
++
++	while (handle < num) {
++		desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
++		*desc_to_use = desc[handle];
++		(hw->cmq.csq.next_to_use)++;
++		if (hw->cmq.csq.next_to_use >= hw->cmq.csq.desc_num)
++			hw->cmq.csq.next_to_use = 0;
++		handle++;
++	}
++}
++
++static int hclge_comm_is_valid_csq_clean_head(struct hclge_comm_cmq_ring *ring,
++					      int head)
++{
++	int ntc = ring->next_to_clean;
++	int ntu = ring->next_to_use;
++
++	if (ntu > ntc)
++		return head >= ntc && head <= ntu;
++
++	return head >= ntc || head <= ntu;
++}
++
++static int hclge_comm_cmd_csq_clean(struct hclge_comm_hw *hw)
++{
++	struct hclge_comm_cmq_ring *csq = &hw->cmq.csq;
++	int clean;
++	u32 head;
++
++	head = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG);
++	rmb(); /* Make sure head is ready before touch any data */
++
++	if (!hclge_comm_is_valid_csq_clean_head(csq, head)) {
++		dev_warn(&hw->cmq.csq.pdev->dev, "wrong cmd head (%u, %d-%d)\n",
++			 head, csq->next_to_use, csq->next_to_clean);
++		dev_warn(&hw->cmq.csq.pdev->dev,
++			 "Disabling any further commands to IMP firmware\n");
++		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state);
++		dev_warn(&hw->cmq.csq.pdev->dev,
++			 "IMP firmware watchdog reset soon expected!\n");
++		return -EIO;
++	}
++
++	clean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num;
++	csq->next_to_clean = head;
++	return clean;
++}
++
++static int hclge_comm_cmd_csq_done(struct hclge_comm_hw *hw)
++{
++	u32 head = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG);
++	return head == hw->cmq.csq.next_to_use;
++}
++
++static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw,
++				     bool *is_completed)
++{
++	u32 timeout = 0;
++
++	do {
++		if (hclge_comm_cmd_csq_done(hw)) {
++			*is_completed = true;
++			break;
++		}
++		udelay(1);
++		timeout++;
++	} while (timeout < hw->cmq.tx_timeout);
++}
++
++static int hclge_comm_cmd_convert_err_code(u16 desc_ret)
++{
++	struct hclge_comm_errcode hclge_comm_cmd_errcode[] = {
++		{ HCLGE_COMM_CMD_EXEC_SUCCESS, 0 },
++		{ HCLGE_COMM_CMD_NO_AUTH, -EPERM },
++		{ HCLGE_COMM_CMD_NOT_SUPPORTED, -EOPNOTSUPP },
++		{ HCLGE_COMM_CMD_QUEUE_FULL, -EXFULL },
++		{ HCLGE_COMM_CMD_NEXT_ERR, -ENOSR },
++		{ HCLGE_COMM_CMD_UNEXE_ERR, -ENOTBLK },
++		{ HCLGE_COMM_CMD_PARA_ERR, -EINVAL },
++		{ HCLGE_COMM_CMD_RESULT_ERR, -ERANGE },
++		{ HCLGE_COMM_CMD_TIMEOUT, -ETIME },
++		{ HCLGE_COMM_CMD_HILINK_ERR, -ENOLINK },
++		{ HCLGE_COMM_CMD_QUEUE_ILLEGAL, -ENXIO },
++		{ HCLGE_COMM_CMD_INVALID, -EBADR },
++	};
++	u32 errcode_count = ARRAY_SIZE(hclge_comm_cmd_errcode);
++	u32 i;
++
++	for (i = 0; i < errcode_count; i++)
++		if (hclge_comm_cmd_errcode[i].imp_errcode == desc_ret)
++			return hclge_comm_cmd_errcode[i].common_errno;
++
++	return -EIO;
++}
++
++static int hclge_comm_cmd_check_retval(struct hclge_comm_hw *hw,
++				       struct hclge_desc *desc, int num,
++				       int ntc, bool is_pf)
++{
++	u16 opcode, desc_ret;
++	int handle;
++
++	opcode = le16_to_cpu(desc[0].opcode);
++	for (handle = 0; handle < num; handle++) {
++		desc[handle] = hw->cmq.csq.desc[ntc];
++		ntc++;
++		if (ntc >= hw->cmq.csq.desc_num)
++			ntc = 0;
++	}
++	if (likely(!hclge_comm_is_special_opcode(opcode, is_pf)))
++		desc_ret = le16_to_cpu(desc[num - 1].retval);
++	else
++		desc_ret = le16_to_cpu(desc[0].retval);
++
++	hw->cmq.last_status = desc_ret;
++
++	return hclge_comm_cmd_convert_err_code(desc_ret);
++}
++
++static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw,
++				       struct hclge_desc *desc,
++				       int num, int ntc, bool is_pf)
++{
++	bool is_completed = false;
++	int handle, ret;
++
++	/* If the command is sync, wait for the firmware to write back,
++	 * if multi descriptors to be sent, use the first one to check
++	 */
++	if (HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag)))
++		hclge_comm_wait_for_resp(hw, &is_completed);
++
++	if (!is_completed)
++		ret = -EBADE;
++	else
++		ret = hclge_comm_cmd_check_retval(hw, desc, num, ntc, is_pf);
++
++	/* Clean the command send queue */
++	handle = hclge_comm_cmd_csq_clean(hw);
++	if (handle < 0)
++		ret = handle;
++	else if (handle != num)
++		dev_warn(&hw->cmq.csq.pdev->dev,
++			 "cleaned %d, need to clean %d\n", handle, num);
++	return ret;
++}
++
++/**
++ * hclge_comm_cmd_send - send command to command queue
++ * @hw: pointer to the hw struct
++ * @desc: prefilled descriptor for describing the command
++ * @num : the number of descriptors to be sent
++ * @is_pf: bool to judge pf/vf module
++ *
++ * This is the main send command for command queue, it
++ * sends the queue, cleans the queue, etc
++ **/
++int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
++			int num, bool is_pf)
++{
++	struct hclge_comm_cmq_ring *csq = &hw->cmq.csq;
++	int ret;
++	int ntc;
++
++	spin_lock_bh(&hw->cmq.csq.lock);
++
++	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state)) {
++		spin_unlock_bh(&hw->cmq.csq.lock);
++		return -EBUSY;
++	}
++
++	if (num > hclge_comm_ring_space(&hw->cmq.csq)) {
++		/* If CMDQ ring is full, SW HEAD and HW HEAD may be different,
++		 * need update the SW HEAD pointer csq->next_to_clean
++		 */
++		csq->next_to_clean =
++			hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG);
++		spin_unlock_bh(&hw->cmq.csq.lock);
++		return -EBUSY;
++	}
++
++	/**
++	 * Record the location of desc in the ring for this time
++	 * which will be use for hardware to write back
++	 */
++	ntc = hw->cmq.csq.next_to_use;
++
++	hclge_comm_cmd_copy_desc(hw, desc, num);
++
++	/* Write to hardware */
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_TAIL_REG,
++			     hw->cmq.csq.next_to_use);
++
++	ret = hclge_comm_cmd_check_result(hw, desc, num, ntc, is_pf);
++
++	spin_unlock_bh(&hw->cmq.csq.lock);
++
++	return ret;
++}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index f1e39003ceeb..5164c666cae7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -7,6 +7,52 @@
+ 
+ #include "hnae3.h"
+ 
++#define HCLGE_COMM_CMD_FLAG_NO_INTR		BIT(4)
++
++#define HCLGE_COMM_SEND_SYNC(flag) \
++	((flag) & HCLGE_COMM_CMD_FLAG_NO_INTR)
++
++#define HCLGE_COMM_NIC_CSQ_TAIL_REG		0x27010
++#define HCLGE_COMM_NIC_CSQ_HEAD_REG		0x27014
++
++enum hclge_comm_cmd_return_status {
++	HCLGE_COMM_CMD_EXEC_SUCCESS	= 0,
++	HCLGE_COMM_CMD_NO_AUTH		= 1,
++	HCLGE_COMM_CMD_NOT_SUPPORTED	= 2,
++	HCLGE_COMM_CMD_QUEUE_FULL	= 3,
++	HCLGE_COMM_CMD_NEXT_ERR		= 4,
++	HCLGE_COMM_CMD_UNEXE_ERR	= 5,
++	HCLGE_COMM_CMD_PARA_ERR		= 6,
++	HCLGE_COMM_CMD_RESULT_ERR	= 7,
++	HCLGE_COMM_CMD_TIMEOUT		= 8,
++	HCLGE_COMM_CMD_HILINK_ERR	= 9,
++	HCLGE_COMM_CMD_QUEUE_ILLEGAL	= 10,
++	HCLGE_COMM_CMD_INVALID		= 11,
++};
++
++enum hclge_comm_special_cmd {
++	HCLGE_COMM_OPC_STATS_64_BIT		= 0x0030,
++	HCLGE_COMM_OPC_STATS_32_BIT		= 0x0031,
++	HCLGE_COMM_OPC_STATS_MAC		= 0x0032,
++	HCLGE_COMM_OPC_STATS_MAC_ALL		= 0x0034,
++	HCLGE_COMM_OPC_QUERY_32_BIT_REG		= 0x0041,
++	HCLGE_COMM_OPC_QUERY_64_BIT_REG		= 0x0042,
++	HCLGE_COMM_QUERY_CLEAR_MPF_RAS_INT	= 0x1511,
++	HCLGE_COMM_QUERY_CLEAR_PF_RAS_INT	= 0x1512,
++	HCLGE_COMM_QUERY_CLEAR_ALL_MPF_MSIX_INT	= 0x1514,
++	HCLGE_COMM_QUERY_CLEAR_ALL_PF_MSIX_INT	= 0x1515,
++	HCLGE_COMM_QUERY_ALL_ERR_INFO		= 0x1517,
++};
++
++enum hclge_comm_cmd_state {
++	HCLGE_COMM_STATE_CMD_DISABLE,
++};
++
++struct hclge_comm_errcode {
++	u32 imp_errcode;
++	int common_errno;
++};
++
+ #define HCLGE_DESC_DATA_LEN		6
+ struct hclge_desc {
+ 	__le16 opcode;
+@@ -52,4 +98,24 @@ struct hclge_comm_hw {
+ 	unsigned long comm_state;
+ };
+ 
++static inline void hclge_comm_write_reg(void __iomem *base, u32 reg, u32 value)
++{
++	writel(value, base + reg);
++}
++
++static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg)
++{
++	u8 __iomem *reg_addr = READ_ONCE(base);
++
++	return readl(reg_addr + reg);
++}
++
++#define hclge_comm_write_dev(a, reg, value) \
++	hclge_comm_write_reg((a)->io_base, reg, value)
++#define hclge_comm_read_dev(a, reg) \
++	hclge_comm_read_reg((a)->io_base, reg)
++
++int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
++			int num, bool is_pf);
++
+ #endif
+-- 
+2.34.1
+
diff --git a/patches/0537-net-hns3-add-support-for-TX-push-mode.patch b/patches/0537-net-hns3-add-support-for-TX-push-mode.patch
new file mode 100644
index 0000000..2f413fd
--- /dev/null
+++ b/patches/0537-net-hns3-add-support-for-TX-push-mode.patch
@@ -0,0 +1,333 @@
+From d7106b08a3618f542ba1beb3ceeda96c85878e03 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Mon, 17 Jan 2022 21:07:58 +0800
+Subject: [PATCH 176/283] net: hns3: add support for TX push mode
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+----------------------------------------------------------------------
+
+For the device that supports the TX push capability, the BD can
+be directly copied to the device memory. However, due to hardware
+restrictions, the push mode can be used only when there are no
+more than two BDs, otherwise, the doorbell mode based on device
+memory is used.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  1 +
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 82 +++++++++++++++++--
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  4 +
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  2 +
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  9 ++
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  9 ++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |  9 ++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.h      | 13 ++-
+ include/asm-generic/barrier.h                 |  4 +
+ 9 files changed, 123 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 4f77d80b01f4..60918a9c3953 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -167,6 +167,7 @@ struct hnae3_handle;
+ 
+ struct hnae3_queue {
+ 	void __iomem *io_base;
++	void __iomem *mem_base;
+ 	struct hnae3_ae_algo *ae_algo;
+ 	struct hnae3_handle *handle;
+ 	int tqp_index;		/* index in a handle */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 19ba800afc6c..43b38e267e5b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -1709,9 +1709,73 @@ static int hns3_fill_skb_to_desc(struct hns3_enet_ring *ring,
+ 	return bd_num;
+ }
+ 
++static void hns3_tx_push_bd(struct hns3_enet_ring *ring, int num)
++{
++#define HNS3_BYTES_PER_64BIT		8
++
++	struct hns3_desc desc[HNS3_MAX_PUSH_BD_NUM] = {};
++	int offset = 0;
++
++	/* make sure everything is visible to device before
++	 * excuting tx push or updating doorbell
++	 */
++	dma_wmb();
++
++	do {
++		int idx = (ring->next_to_use - num + ring->desc_num) %
++			  ring->desc_num;
++
++		u64_stats_update_begin(&ring->syncp);
++		ring->stats.tx_push++;
++		u64_stats_update_end(&ring->syncp);
++		memcpy(&desc[offset], &ring->desc[idx],
++		       sizeof(struct hns3_desc));
++		offset++;
++	} while (--num);
++
++	__iowrite64_copy(ring->tqp->mem_base, desc,
++			 (sizeof(struct hns3_desc) * HNS3_MAX_PUSH_BD_NUM) /
++			 HNS3_BYTES_PER_64BIT);
++
++	io_stop_wc();
++}
++
++static void hns3_tx_mem_doorbell(struct hns3_enet_ring *ring)
++{
++#define HNS3_MEM_DOORBELL_OFFSET	64
++
++	__le64 bd_num = cpu_to_le64((u64)ring->pending_buf);
++
++	/* make sure everything is visible to device before
++	 * excuting tx push or updating doorbell
++	 */
++	dma_wmb();
++
++	__iowrite64_copy(ring->tqp->mem_base + HNS3_MEM_DOORBELL_OFFSET,
++			 &bd_num, 1);
++	u64_stats_update_begin(&ring->syncp);
++	ring->stats.tx_mem_doorbell += ring->pending_buf;
++	u64_stats_update_end(&ring->syncp);
++
++	io_stop_wc();
++}
++
+ static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
+ 			     bool doorbell)
+ {
++	struct net_device *netdev = ring_to_netdev(ring);
++	struct hns3_nic_priv *priv = netdev_priv(netdev);
++
++	/* when tx push is enabled, the packet whose number of BD below
++	 * HNS3_MAX_PUSH_BD_NUM can be pushed directly.
++	 */
++	if (test_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state) && num &&
++	    !ring->pending_buf && num <= HNS3_MAX_PUSH_BD_NUM && doorbell) {
++		hns3_tx_push_bd(ring, num);
++		WRITE_ONCE(ring->last_to_use, ring->next_to_use);
++		return;
++	}
++
+ 	ring->pending_buf += num;
+ 
+ 	if (!doorbell) {
+@@ -1721,17 +1785,14 @@ static void hns3_tx_doorbell(struct hns3_enet_ring *ring, int num,
+ 		return;
+ 	}
+ 
+-	if (!ring->pending_buf)
+-		return;
+-
+-	/* This smp_store_release() pairs with smp_load_aquire() in
+-	 * hns3_nic_reclaim_desc(). Ensure that the BD valid bit is updated.
+-	 */
+-	smp_store_release(&ring->last_to_use, ring->next_to_use);
++	if (ring->tqp->mem_base)
++		hns3_tx_mem_doorbell(ring);
++	else
++		writel(ring->pending_buf,
++		       ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
+ 
+-	writel(ring->pending_buf,
+-	       ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
+ 	ring->pending_buf = 0;
++	WRITE_ONCE(ring->last_to_use, ring->next_to_use);
+ }
+ 
+ static void hns3_tsyn(struct net_device *netdev, struct sk_buff *skb,
+@@ -4694,6 +4755,9 @@ static void hns3_state_init(struct hnae3_handle *handle)
+ 
+ 	set_bit(HNS3_NIC_STATE_INITED, &priv->state);
+ 
++	if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
++		set_bit(HNS3_NIC_STATE_TX_PUSH_ENABLE, &priv->state);
++
+ 	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3)
+ 		set_bit(HNAE3_PFLAG_LIMIT_PROMISC, &handle->supported_pflags);
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index f889ec9fc24e..2377e69818a5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -24,6 +24,8 @@ enum hns3_nic_state {
+ 	HNS3_NIC_STATE_MAX
+ };
+ 
++#define HNS3_MAX_PUSH_BD_NUM		2
++
+ #define HNS3_RING_RX_RING_BASEADDR_L_REG	0x00000
+ #define HNS3_RING_RX_RING_BASEADDR_H_REG	0x00004
+ #define HNS3_RING_RX_RING_BD_NUM_REG		0x00008
+@@ -397,6 +399,8 @@ struct ring_stats {
+ 			u64 tx_pkts;
+ 			u64 tx_bytes;
+ 			u64 tx_more;
++			u64 tx_push;
++			u64 tx_mem_doorbell;
+ 			u64 restart_queue;
+ 			u64 tx_busy;
+ 			u64 tx_copy;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index a7f4820f6f8c..3646738ef4bc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -27,6 +27,8 @@ static const struct hns3_stats hns3_txq_stats[] = {
+ 	HNS3_TQP_STAT("packets", tx_pkts),
+ 	HNS3_TQP_STAT("bytes", tx_bytes),
+ 	HNS3_TQP_STAT("more", tx_more),
++	HNS3_TQP_STAT("push", tx_push),
++	HNS3_TQP_STAT("mem_doorbell", tx_mem_doorbell),
+ 	HNS3_TQP_STAT("wake", restart_queue),
+ 	HNS3_TQP_STAT("busy", tx_busy),
+ 	HNS3_TQP_STAT("copy", tx_copy),
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 3ff2eb9fcf5f..691fbbb77619 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1683,6 +1683,7 @@ static int hclge_config_gro(struct hclge_dev *hdev)
+ static int hclge_alloc_tqps(struct hclge_dev *hdev)
+ {
+ 	struct hclge_tqp *tqp;
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	int i;
+ 
+ 	hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
+@@ -1703,6 +1704,14 @@ static int hclge_alloc_tqps(struct hclge_dev *hdev)
+ 		tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
+ 			i * HCLGE_TQP_REG_SIZE;
+ 
++		/* when device supports tx push and has device memory,
++		 * the queue can execute push mode or doorbell mode on
++		 * device memory.
++		 */
++		if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
++			tqp->q.mem_base = hdev->hw.hw.mem_base +
++					  HCLGE_TQP_MEM_OFFSET(hdev, i);
++
+ 		tqp++;
+ 	}
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 7ba42bbcf370..973b4f3de627 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -196,6 +196,14 @@ enum HLCGE_PORT_TYPE {
+ #define HCLGE_VECTOR0_ALL_MSIX_ERR_B	6U
+ #define HCLGE_TRIGGER_IMP_RESET_B	7U
+ 
++#define HCLGE_TQP_MEM_SIZE		0x10000
++#define HCLGE_MEM_BAR			4
++/* in the bar4, the first half is for roce, and the second half is for nic */
++#define HCLGE_NIC_MEM_OFFSET(hdev)	\
++	(pci_resource_len((hdev)->pdev, HCLGE_MEM_BAR) >> 1)
++#define HCLGE_TQP_MEM_OFFSET(hdev, i)	\
++	(HCLGE_NIC_MEM_OFFSET(hdev) + HCLGE_TQP_MEM_SIZE * (i))
++
+ #define HCLGE_MAC_DEFAULT_FRAME \
+ 	(ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
+ #define HCLGE_MAC_MIN_FRAME		64
+@@ -296,6 +304,7 @@ struct hclge_mac {
+ };
+ 
+ struct hclge_hw {
++	struct hclge_comm_hw hw;
+ 	void __iomem *io_base;
+ 	void __iomem *mem_base;
+ 	struct hclge_mac mac;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index ffac4a4aa66a..4dbfd2daa7e2 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -394,6 +394,7 @@ static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)
+ static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
+ {
+ 	struct hclgevf_tqp *tqp;
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	int i;
+ 
+ 	hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
+@@ -414,6 +415,14 @@ static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
+ 		tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
+ 			i * HCLGEVF_TQP_REG_SIZE;
+ 
++		/* when device supports tx push and has device memory,
++		 * the queue can execute push mode or doorbell mode on
++		 * device memory.
++		 */
++		if (test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, ae_dev->caps))
++			tqp->q.mem_base = hdev->hw.hw.mem_base +
++					  HCLGEVF_TQP_MEM_OFFSET(hdev, i);
++
+ 		tqp++;
+ 	}
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index a9624b9adcfd..97e9834c6de5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -126,6 +126,16 @@
+ #define HCLGEVF_RSS_INPUT_TUPLE_SCTP6 \
+ 	(HCLGEVF_D_IP_BIT | HCLGEVF_S_IP_BIT | HCLGEVF_V_TAG_BIT)
+ 
++#define HCLGEVF_TQP_MEM_SIZE		0x10000
++#define HCLGEVF_MEM_BAR			4
++/* in the bar4, the first half is for roce, and the second half is for nic */
++#define HCLGEVF_NIC_MEM_OFFSET(hdev)	\
++	(pci_resource_len((hdev)->pdev, HCLGEVF_MEM_BAR) >> 1)
++#define HCLGEVF_TQP_MEM_OFFSET(hdev, i)		\
++	(HCLGEVF_NIC_MEM_OFFSET(hdev) + HCLGEVF_TQP_MEM_SIZE * (i))
++
++#define HCLGEVF_MAC_MAX_FRAME		9728
++
+ #define HCLGEVF_STATS_TIMER_INTERVAL	36U
+ 
+ enum hclgevf_evt_cause {
+@@ -167,12 +177,13 @@ struct hclgevf_mac {
+ };
+ 
+ struct hclgevf_hw {
++	struct hclge_comm_hw hw;
+ 	void __iomem *io_base;
+ 	void __iomem *mem_base;
+ 	int num_vec;
+ 	struct hclgevf_cmq cmq;
+ 	struct hclgevf_mac mac;
+-	void *hdev; /* hchgevf device it is part of */
++	void *hdev; /* hclgevf device it is par of */
+ };
+ 
+ /* TQP stats */
+diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h
+index 2cafdbb9ae4c..ad7f17434dfc 100644
+--- a/include/asm-generic/barrier.h
++++ b/include/asm-generic/barrier.h
+@@ -261,5 +261,9 @@ do {									\
+ })
+ #endif
+ 
++#ifndef io_stop_wc
++#define io_stop_wc() do { } while (0)
++#endif
++
+ #endif /* !__ASSEMBLY__ */
+ #endif /* __ASM_GENERIC_BARRIER_H */
+-- 
+2.34.1
+
diff --git a/patches/0538-net-hns3-handle-empty-unknown-interrupt-for-VF.patch b/patches/0538-net-hns3-handle-empty-unknown-interrupt-for-VF.patch
new file mode 100644
index 0000000..5e50f7a
--- /dev/null
+++ b/patches/0538-net-hns3-handle-empty-unknown-interrupt-for-VF.patch
@@ -0,0 +1,51 @@
+From 8294bb0096acee531586cc5364273763fc658b5b Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Thu, 7 Apr 2022 16:12:44 +0800
+Subject: [PATCH 177/283] net: hns3: handle empty unknown interrupt for VF
+
+mainline inclusion
+from mainline-v5.17-rc2
+commit 2f61353cd2f789a4229b6f5c1c24a40a613357bb
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/commit/?id=2f61353cd2f789a4229b6f5c1c24a40a613357bb
+
+----------------------------------------------------------------------
+
+Since some interrupt states may be cleared by hardware, the driver
+may receive an empty interrupt. Currently, the VF driver directly
+disables the vector0 interrupt in this case. As a result, the VF
+is unavailable. Therefore, the vector0 interrupt should be enabled
+in this case.
+
+Fixes: b90fcc5bd904 ("net: hns3: add reset handling for VF when doing Core/Global/IMP reset")
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Acked-by: Xie XiuQi <xiexiuqi@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 4dbfd2daa7e2..d03d6c22b051 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -2430,8 +2430,7 @@ static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
+ 		break;
+ 	}
+ 
+-	if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER)
+-		hclgevf_enable_vector(&hdev->misc_vector, true);
++	hclgevf_enable_vector(&hdev->misc_vector, true);
+ 
+ 	return IRQ_HANDLED;
+ }
+-- 
+2.34.1
+
diff --git a/patches/0539-net-hns3-fix-software-vlan-talbe-of-vlan-0-inconsist.patch b/patches/0539-net-hns3-fix-software-vlan-talbe-of-vlan-0-inconsist.patch
new file mode 100644
index 0000000..64859c1
--- /dev/null
+++ b/patches/0539-net-hns3-fix-software-vlan-talbe-of-vlan-0-inconsist.patch
@@ -0,0 +1,58 @@
+From 275383264471b2e77bc0b57083942e7c0990e697 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 14 Jun 2022 17:47:17 +0800
+Subject: [PATCH 178/283] net: hns3: fix software vlan talbe of vlan 0
+ inconsistent with hardware
+
+mainline inclusion
+from mainline-v5.18-rc1
+commit 7ed258f12ec5ce855f15cdfb5710361dc82fe899
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7ed258f12ec5ce855f15cdfb5710361dc82fe899
+
+----------------------------------------------------------------------
+
+When user delete vlan 0, as driver will not delete vlan 0 for hardware in
+function hclge_set_vlan_filter_hw(), so vlan 0 in software vlan talbe should
+not be deleted.
+
+Fixes: fe4144d47eef ("net: hns3: sync VLAN filter entries when kill VLAN ID failed")
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 691fbbb77619..7ae0194bcda2 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -9926,11 +9926,11 @@ int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
+ 	}
+ 
+ 	if (!ret) {
+-		if (is_kill && vlan_id != 0)
+-			hclge_rm_vport_vlan_table(vport, vlan_id, false);
+-		else
++		if (!is_kill)
+ 			hclge_add_vport_vlan_table(vport, vlan_id,
+ 						   writen_to_tbl);
++		else if (is_kill && vlan_id != 0)
++			hclge_rm_vport_vlan_table(vport, vlan_id, false);
+ 	} else if (is_kill) {
+ 		/* when remove hw vlan filter failed, record the vlan id,
+ 		 * and try to remove it from hw later, to be consistence
+-- 
+2.34.1
+
diff --git a/patches/0540-net-hns3-add-querying-fec-ability-from-firmware.patch b/patches/0540-net-hns3-add-querying-fec-ability-from-firmware.patch
new file mode 100644
index 0000000..342ae14
--- /dev/null
+++ b/patches/0540-net-hns3-add-querying-fec-ability-from-firmware.patch
@@ -0,0 +1,140 @@
+From a41dcb72565235863e31f72032208b2d712c1eb3 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 11 Oct 2022 23:14:12 +0800
+Subject: [PATCH 179/283] net: hns3: add querying fec ability from firmware
+
+mainline inclusion
+from mainline-v6.0-rc2
+commit eaf83ae59e18a3480afe222daf9537d58165e052
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=eaf83ae59e18
+
+----------------------------------------------------------------------
+
+For some new devices, driver can queries fec ability from firmware to
+decide which FEC mode can be supported.
+
+If devices of old version which not support querying fec ability, driver
+sets fixed ability according to current speed.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  3 +-
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 33 ++++++++++++++-----
+ 2 files changed, 26 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 52e8f318fd96..991d6de9009c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -694,7 +694,8 @@ struct hclge_sfp_info_cmd {
+ 	u8 autoneg_ability; /* whether support autoneg */
+ 	__le32 speed_ability; /* speed ability for current media */
+ 	__le32 module_type;
+-	u8 rsv[8];
++	u8 fec_ability;
++	u8 rsv[7];
+ };
+ 
+ #define HCLGE_MAC_CFG_FEC_AUTO_EN_B	0
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 7ae0194bcda2..330483b99c01 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1072,6 +1072,19 @@ static int hclge_check_port_speed(struct hnae3_handle *handle, u32 speed)
+ 	return -EINVAL;
+ }
+ 
++static void hclge_update_fec_support(struct hclge_mac *mac)
++{
++	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported);
++	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
++
++	if (mac->fec_ability & BIT(HNAE3_FEC_BASER))
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
++				 mac->supported);
++	if (mac->fec_ability & BIT(HNAE3_FEC_RS))
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
++				 mac->supported);
++}
++
+ static void hclge_convert_setting_sr(u16 speed_ability,
+ 				     unsigned long *link_mode)
+ {
+@@ -1170,36 +1183,33 @@ static void hclge_convert_setting_kr(u16 speed_ability,
+ 
+ static void hclge_convert_setting_fec(struct hclge_mac *mac)
+ {
+-	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported);
+-	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
++/* If firmware has reported fec_ability, don't need to convert by speed */
++	if (mac->fec_ability)
++		goto out;
+ 
+ 	switch (mac->speed) {
+ 	case HCLGE_MAC_SPEED_10G:
+ 	case HCLGE_MAC_SPEED_40G:
+-		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
+-				 mac->supported);
+ 		mac->fec_ability =
+ 			BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO);
+ 		break;
+ 	case HCLGE_MAC_SPEED_25G:
+ 	case HCLGE_MAC_SPEED_50G:
+-		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
+-				 mac->supported);
+-		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
+-				 mac->supported);
+ 		mac->fec_ability =
+ 			BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) |
+ 			BIT(HNAE3_FEC_AUTO);
+ 		break;
+ 	case HCLGE_MAC_SPEED_100G:
+ 	case HCLGE_MAC_SPEED_200G:
+-		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
+ 		mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO);
+ 		break;
+ 	default:
+ 		mac->fec_ability = 0;
+ 		break;
+ 	}
++
++out:
++	hclge_update_fec_support(mac);
+ }
+ 
+ static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
+@@ -3166,6 +3176,7 @@ static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac)
+ 			mac->fec_mode = 0;
+ 		else
+ 			mac->fec_mode = BIT(resp->active_fec);
++		mac->fec_ability = resp->fec_ability;
+ 	} else {
+ 		mac->speed_type = QUERY_SFP_SPEED;
+ 	}
+@@ -11049,6 +11060,10 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	if (ret)
+ 		goto err_mdiobus_unreg;
+ 
++	ret = hclge_update_port_info(hdev);
++	if (ret)
++		goto err_mdiobus_unreg;
++
+ 	INIT_KFIFO(hdev->mac_tnl_log);
+ 
+ 	hclge_dcb_ops_set(hdev);
+-- 
+2.34.1
+
diff --git a/patches/0541-net-hns3-add-querying-and-setting-fec-llrs-mode-from.patch b/patches/0541-net-hns3-add-querying-and-setting-fec-llrs-mode-from.patch
new file mode 100644
index 0000000..f194e84
--- /dev/null
+++ b/patches/0541-net-hns3-add-querying-and-setting-fec-llrs-mode-from.patch
@@ -0,0 +1,196 @@
+From fb7e7586b438f7eebcbcf758b5aacb7cde09cfad Mon Sep 17 00:00:00 2001
+From: Hao Lan <lanhao@huawei.com>
+Date: Tue, 11 Oct 2022 23:14:13 +0800
+Subject: [PATCH 180/283] net: hns3: add querying and setting fec llrs mode
+ from firmware
+
+mainline inclusion
+from mainline-v6.0-rc2
+commit 5c4f72842d1df19337b171fd4677239d2e11d047
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=5c4f72842d1d
+
+----------------------------------------------------------------------
+
+This patch supports llrs fec mode in speed 200G for some new devices, and
+suppoprts querying llrs fec ability from firmware.
+
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  1 +
+ .../hns3/hns3_common/hclge_comm_cmd.h         | 19 +++++++++++++++++++
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  4 ++++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  1 +
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 15 ++++++++++++++-
+ include/uapi/linux/ethtool.h                  |  2 ++
+ 6 files changed, 41 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 60918a9c3953..5a1d6cb7b2eb 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -219,6 +219,7 @@ enum hnae3_fec_mode {
+ 	HNAE3_FEC_AUTO = 0,
+ 	HNAE3_FEC_BASER,
+ 	HNAE3_FEC_RS,
++	HNAE3_FEC_LLRS,
+ 	HNAE3_FEC_USER_DEF,
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 5164c666cae7..52fc4b830772 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -12,6 +12,25 @@
+ #define HCLGE_COMM_SEND_SYNC(flag) \
+ 	((flag) & HCLGE_COMM_CMD_FLAG_NO_INTR)
+ 
++#define HCLGE_COMM_LINK_EVENT_REPORT_EN_B	0
++#define HCLGE_COMM_NCSI_ERROR_REPORT_EN_B	1
++#define HCLGE_COMM_PHY_IMP_EN_B			2
++#define HCLGE_COMM_MAC_STATS_EXT_EN_B		3
++#define HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B	4
++#define HCLGE_COMM_LLRS_FEC_EN_B		5
++
++#define hclge_comm_dev_phy_imp_supported(ae_dev) \
++	test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (ae_dev)->caps)
++
++#define HCLGE_COMM_TYPE_CRQ			0
++#define HCLGE_COMM_TYPE_CSQ			1
++
++#define HCLGE_COMM_CMDQ_CLEAR_WAIT_TIME		200
++
++/* bar registers for cmdq */
++#define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG	0x27000
++#define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG	0x27004
++#define HCLGE_COMM_NIC_CSQ_DEPTH_REG		0x27008
+ #define HCLGE_COMM_NIC_CSQ_TAIL_REG		0x27010
+ #define HCLGE_COMM_NIC_CSQ_HEAD_REG		0x27014
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 3646738ef4bc..18a60e8fa746 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1524,6 +1524,8 @@ static unsigned int loc_to_eth_fec(u8 loc_fec)
+ 		eth_fec |= ETHTOOL_FEC_AUTO;
+ 	if (loc_fec & BIT(HNAE3_FEC_RS))
+ 		eth_fec |= ETHTOOL_FEC_RS;
++	if (loc_fec & BIT(HNAE3_FEC_LLRS))
++		eth_fec |= ETHTOOL_FEC_LLRS;
+ 	if (loc_fec & BIT(HNAE3_FEC_BASER))
+ 		eth_fec |= ETHTOOL_FEC_BASER;
+ 
+@@ -1546,6 +1548,8 @@ static unsigned int eth_to_loc_fec(unsigned int eth_fec)
+ 		loc_fec |= BIT(HNAE3_FEC_AUTO);
+ 	if (eth_fec & ETHTOOL_FEC_RS)
+ 		loc_fec |= BIT(HNAE3_FEC_RS);
++	if (eth_fec & ETHTOOL_FEC_LLRS)
++		loc_fec |= BIT(HNAE3_FEC_LLRS);
+ 	if (eth_fec & ETHTOOL_FEC_BASER)
+ 		loc_fec |= BIT(HNAE3_FEC_BASER);
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 991d6de9009c..234647cd6a4c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -707,6 +707,7 @@ struct hclge_sfp_info_cmd {
+ #define HCLGE_MAC_FEC_OFF		0
+ #define HCLGE_MAC_FEC_BASER		1
+ #define HCLGE_MAC_FEC_RS		2
++#define HCLGE_MAC_FEC_LLRS		3
+ struct hclge_config_fec_cmd {
+ 	u8 fec_mode;
+ 	u8 default_config;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 330483b99c01..8029fdf580b7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1076,6 +1076,7 @@ static void hclge_update_fec_support(struct hclge_mac *mac)
+ {
+ 	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported);
+ 	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
++	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported);
+ 
+ 	if (mac->fec_ability & BIT(HNAE3_FEC_BASER))
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
+@@ -1083,6 +1084,9 @@ static void hclge_update_fec_support(struct hclge_mac *mac)
+ 	if (mac->fec_ability & BIT(HNAE3_FEC_RS))
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
+ 				 mac->supported);
++	if (mac->fec_ability & BIT(HNAE3_FEC_LLRS))
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
++				 mac->supported);
+ }
+ 
+ static void hclge_convert_setting_sr(u16 speed_ability,
+@@ -1200,9 +1204,12 @@ static void hclge_convert_setting_fec(struct hclge_mac *mac)
+ 			BIT(HNAE3_FEC_AUTO);
+ 		break;
+ 	case HCLGE_MAC_SPEED_100G:
+-	case HCLGE_MAC_SPEED_200G:
+ 		mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO);
+ 		break;
++	case HCLGE_MAC_SPEED_200G:
++		mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
++				   BIT(HNAE3_FEC_LLRS);
++		break;
+ 	default:
+ 		mac->fec_ability = 0;
+ 		break;
+@@ -2795,6 +2802,9 @@ static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode)
+ 	if (fec_mode & BIT(HNAE3_FEC_RS))
+ 		hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
+ 				HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_RS);
++	if (fec_mode & BIT(HNAE3_FEC_LLRS))
++		hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
++				HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_LLRS);
+ 	if (fec_mode & BIT(HNAE3_FEC_BASER))
+ 		hnae3_set_field(req->fec_mode, HCLGE_MAC_CFG_FEC_MODE_M,
+ 				HCLGE_MAC_CFG_FEC_MODE_S, HCLGE_MAC_FEC_BASER);
+@@ -3040,6 +3050,9 @@ static void hclge_update_fec_advertising(struct hclge_mac *mac)
+ 	if (mac->fec_mode & BIT(HNAE3_FEC_RS))
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT,
+ 				 mac->advertising);
++	else if (mac->fec_mode & BIT(HNAE3_FEC_LLRS))
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
++				 mac->advertising);
+ 	else if (mac->fec_mode & BIT(HNAE3_FEC_BASER))
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
+ 				 mac->advertising);
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index 047f880edff9..e57b68fad155 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -1372,6 +1372,7 @@ enum ethtool_fec_config_bits {
+ 	ETHTOOL_FEC_OFF_BIT,
+ 	ETHTOOL_FEC_RS_BIT,
+ 	ETHTOOL_FEC_BASER_BIT,
++	ETHTOOL_FEC_LLRS_BIT,
+ };
+ 
+ #define ETHTOOL_FEC_NONE		(1 << ETHTOOL_FEC_NONE_BIT)
+@@ -1379,6 +1380,7 @@ enum ethtool_fec_config_bits {
+ #define ETHTOOL_FEC_OFF			(1 << ETHTOOL_FEC_OFF_BIT)
+ #define ETHTOOL_FEC_RS			(1 << ETHTOOL_FEC_RS_BIT)
+ #define ETHTOOL_FEC_BASER		(1 << ETHTOOL_FEC_BASER_BIT)
++#define ETHTOOL_FEC_LLRS		(1 << ETHTOOL_FEC_LLRS_BIT)
+ 
+ /* CMDs currently supported */
+ #define ETHTOOL_GSET		0x00000001 /* DEPRECATED, Get settings.
+-- 
+2.34.1
+
diff --git a/patches/0542-net-hns3-net-hns3-add-querying-and-setting-fec-off-m.patch b/patches/0542-net-hns3-net-hns3-add-querying-and-setting-fec-off-m.patch
new file mode 100644
index 0000000..f885048
--- /dev/null
+++ b/patches/0542-net-hns3-net-hns3-add-querying-and-setting-fec-off-m.patch
@@ -0,0 +1,131 @@
+From 11b27963cfd8b3fd103dfc960ab380639d58a4c9 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 11 Oct 2022 23:14:14 +0800
+Subject: [PATCH 181/283] net: hns3: net: hns3: add querying and setting fec
+ off mode from firmware
+
+mainline inclusion
+from mainline-v6.0-rc2
+commit 08aa17a0c18562a08981e5b103105c1798fa2bfd
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=08aa17a0c185
+
+----------------------------------------------------------------------
+
+For some new devices, the FEC mode can not be set to OFF in speed 200G.
+In order to flexibly adapt to all types of devices, driver queries
+fec ability from firmware to decide whether OFF mode can be supported.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h      |  1 +
+ .../net/ethernet/hisilicon/hns3/hns3_ethtool.c   | 11 +++++------
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c  | 16 ++++++++++------
+ 3 files changed, 16 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 5a1d6cb7b2eb..4d35bce95147 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -220,6 +220,7 @@ enum hnae3_fec_mode {
+ 	HNAE3_FEC_BASER,
+ 	HNAE3_FEC_RS,
+ 	HNAE3_FEC_LLRS,
++	HNAE3_FEC_NONE,
+ 	HNAE3_FEC_USER_DEF,
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 18a60e8fa746..c9a24d010260 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1528,10 +1528,8 @@ static unsigned int loc_to_eth_fec(u8 loc_fec)
+ 		eth_fec |= ETHTOOL_FEC_LLRS;
+ 	if (loc_fec & BIT(HNAE3_FEC_BASER))
+ 		eth_fec |= ETHTOOL_FEC_BASER;
+-
+-	/* if nothing is set, then FEC is off */
+-	if (!eth_fec)
+-		eth_fec = ETHTOOL_FEC_OFF;
++	if (loc_fec & BIT(HNAE3_FEC_NONE))
++		eth_fec |= ETHTOOL_FEC_OFF;
+ 
+ 	return eth_fec;
+ }
+@@ -1542,8 +1540,7 @@ static unsigned int eth_to_loc_fec(unsigned int eth_fec)
+ 	u32 loc_fec = 0;
+ 
+ 	if (eth_fec & ETHTOOL_FEC_OFF)
+-		return loc_fec;
+-
++		loc_fec |= BIT(HNAE3_FEC_NONE);
+ 	if (eth_fec & ETHTOOL_FEC_AUTO)
+ 		loc_fec |= BIT(HNAE3_FEC_AUTO);
+ 	if (eth_fec & ETHTOOL_FEC_RS)
+@@ -1575,6 +1572,8 @@ static int hns3_get_fecparam(struct net_device *netdev,
+ 
+ 	fec->fec = loc_to_eth_fec(fec_ability);
+ 	fec->active_fec = loc_to_eth_fec(fec_mode);
++	if (!fec->active_fec)
++		fec->active_fec = ETHTOOL_FEC_OFF;
+ 
+ 	return 0;
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 8029fdf580b7..ee10aea14eb1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1077,6 +1077,7 @@ static void hclge_update_fec_support(struct hclge_mac *mac)
+ 	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, mac->supported);
+ 	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, mac->supported);
+ 	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, mac->supported);
++	linkmode_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, mac->supported);
+ 
+ 	if (mac->fec_ability & BIT(HNAE3_FEC_BASER))
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT,
+@@ -1087,6 +1088,9 @@ static void hclge_update_fec_support(struct hclge_mac *mac)
+ 	if (mac->fec_ability & BIT(HNAE3_FEC_LLRS))
+ 		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
+ 				 mac->supported);
++	if (mac->fec_ability & BIT(HNAE3_FEC_NONE))
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT,
++				 mac->supported);
+ }
+ 
+ static void hclge_convert_setting_sr(u16 speed_ability,
+@@ -1194,17 +1198,17 @@ static void hclge_convert_setting_fec(struct hclge_mac *mac)
+ 	switch (mac->speed) {
+ 	case HCLGE_MAC_SPEED_10G:
+ 	case HCLGE_MAC_SPEED_40G:
+-		mac->fec_ability =
+-			BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO);
++		mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_AUTO) |
++				   BIT(HNAE3_FEC_NONE);
+ 		break;
+ 	case HCLGE_MAC_SPEED_25G:
+ 	case HCLGE_MAC_SPEED_50G:
+-		mac->fec_ability =
+-			BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) |
+-			BIT(HNAE3_FEC_AUTO);
++		mac->fec_ability = BIT(HNAE3_FEC_BASER) | BIT(HNAE3_FEC_RS) |
++				   BIT(HNAE3_FEC_AUTO) | BIT(HNAE3_FEC_NONE);
+ 		break;
+ 	case HCLGE_MAC_SPEED_100G:
+-		mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO);
++		mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
++				   BIT(HNAE3_FEC_NONE);
+ 		break;
+ 	case HCLGE_MAC_SPEED_200G:
+ 		mac->fec_ability = BIT(HNAE3_FEC_RS) | BIT(HNAE3_FEC_AUTO) |
+-- 
+2.34.1
+
diff --git a/patches/0543-net-hns3-add-support-for-external-loopback-test.patch b/patches/0543-net-hns3-add-support-for-external-loopback-test.patch
new file mode 100644
index 0000000..91de543
--- /dev/null
+++ b/patches/0543-net-hns3-add-support-for-external-loopback-test.patch
@@ -0,0 +1,349 @@
+From 59d968eb403e67c339cdfdc1ad156aff70ceda31 Mon Sep 17 00:00:00 2001
+From: Yonglong Liu <liuyonglong@huawei.com>
+Date: Tue, 11 Oct 2022 23:14:19 +0800
+Subject: [PATCH 182/283] net: hns3: add support for external loopback test
+
+mainline inclusion
+from mainline-v6.0-rc4
+commit 04b6ba143521f4485b7f2c36c655b262a79dae97
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=04b6ba143521
+
+----------------------------------------------------------------------
+
+This patch add support for external loopback test.
+The successful test need the link is up with duplex full. The
+driver do external loopback first, and then the whole offline
+test.
+
+Signed-off-by: Yonglong Liu <liuyonglong@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  2 +
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 51 +++++++++++++++
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  3 +
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 63 ++++++++++++++-----
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 26 +++++---
+ 5 files changed, 121 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 4d35bce95147..2963f3d816fd 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -183,6 +183,7 @@ struct hns3_mac_stats {
+ 
+ /* hnae3 loop mode */
+ enum hnae3_loop {
++	HNAE3_LOOP_EXTERNAL,
+ 	HNAE3_LOOP_APP,
+ 	HNAE3_LOOP_SERIAL_SERDES,
+ 	HNAE3_LOOP_PARALLEL_SERDES,
+@@ -865,6 +866,7 @@ struct hnae3_unic_private_info {
+ #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK	BIT(2)
+ #define HNAE3_SUPPORT_VF	      BIT(3)
+ #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK	BIT(4)
++#define HNAE3_SUPPORT_EXTERNAL_LOOPBACK	BIT(5)
+ 
+ #define HNAE3_USER_UPE		BIT(0)	/* unicast promisc enabled by user */
+ #define HNAE3_USER_MPE		BIT(1)	/* mulitcast promisc enabled by user */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 43b38e267e5b..66fd6c870cc3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -5346,6 +5346,57 @@ int hns3_set_channels(struct net_device *netdev,
+ 	return 0;
+ }
+ 
++void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
++{
++	struct hns3_nic_priv *priv = netdev_priv(ndev);
++	struct hnae3_handle *h = priv->ae_handle;
++	int i;
++
++	if (!if_running)
++		return;
++
++	netif_carrier_off(ndev);
++	netif_tx_disable(ndev);
++
++	for (i = 0; i < priv->vector_num; i++)
++		hns3_vector_disable(&priv->tqp_vector[i]);
++
++	for (i = 0; i < h->kinfo.num_tqps; i++)
++		hns3_tqp_disable(h->kinfo.tqp[i]);
++
++	/* delay ring buffer clearing to hns3_reset_notify_uninit_enet
++	 * during reset process, because driver may not be able
++	 * to disable the ring through firmware when downing the netdev.
++	 */
++	if (!hns3_nic_resetting(ndev))
++		hns3_nic_reset_all_ring(priv->ae_handle);
++
++	hns3_reset_tx_queue(priv->ae_handle);
++}
++
++void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
++{
++	struct hns3_nic_priv *priv = netdev_priv(ndev);
++	struct hnae3_handle *h = priv->ae_handle;
++	int i;
++
++	if (!if_running)
++		return;
++
++	hns3_nic_reset_all_ring(priv->ae_handle);
++
++	for (i = 0; i < priv->vector_num; i++)
++		hns3_vector_enable(&priv->tqp_vector[i]);
++
++	for (i = 0; i < h->kinfo.num_tqps; i++)
++		hns3_tqp_enable(h->kinfo.tqp[i]);
++
++	netif_tx_wake_all_queues(ndev);
++
++	if (h->ae_algo->ops->get_status(h))
++		netif_carrier_on(ndev);
++}
++
+ static const struct hns3_hw_error_info hns3_hw_err[] = {
+ 	{ .type = HNAE3_PPU_POISON_ERROR,
+ 	  .msg = "PPU poison" },
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 2377e69818a5..f2d5adb54cdc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -714,4 +714,7 @@ void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
+ void hns3_dbg_unregister_debugfs(void);
+ void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size);
+ u16 hns3_get_max_available_channels(struct hnae3_handle *h);
++
++void hns3_external_lb_prepare(struct net_device *ndev, bool if_running);
++void hns3_external_lb_restore(struct net_device *ndev, bool if_running);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index c9a24d010260..568cc9e57c9c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -72,7 +72,6 @@ static const struct hns3_stats hns3_rxq_stats[] = {
+ 
+ #define HNS3_TQP_STATS_COUNT (HNS3_TXQ_STATS_COUNT + HNS3_RXQ_STATS_COUNT)
+ 
+-#define HNS3_SELF_TEST_TYPE_NUM         4
+ #define HNS3_NIC_LB_TEST_PKT_NUM	1
+ #define HNS3_NIC_LB_TEST_RING_ID	0
+ #define HNS3_NIC_LB_TEST_PACKET_SIZE	128
+@@ -98,6 +97,7 @@ static int hns3_lp_setup(struct net_device *ndev, enum hnae3_loop loop, bool en)
+ 	case HNAE3_LOOP_PARALLEL_SERDES:
+ 	case HNAE3_LOOP_APP:
+ 	case HNAE3_LOOP_PHY:
++	case HNAE3_LOOP_EXTERNAL:
+ 		ret = h->ae_algo->ops->set_loopback(h, loop, en);
+ 		break;
+ 	default:
+@@ -312,6 +312,10 @@ static int hns3_lp_run_test(struct net_device *ndev, enum hnae3_loop mode)
+ 
+ static void hns3_set_selftest_param(struct hnae3_handle *h, int (*st_param)[2])
+ {
++	st_param[HNAE3_LOOP_EXTERNAL][0] = HNAE3_LOOP_EXTERNAL;
++	st_param[HNAE3_LOOP_EXTERNAL][1] =
++			h->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK;
++
+ 	st_param[HNAE3_LOOP_APP][0] = HNAE3_LOOP_APP;
+ 	st_param[HNAE3_LOOP_APP][1] =
+ 			h->flags & HNAE3_SUPPORT_APP_LOOPBACK;
+@@ -330,17 +334,11 @@ static void hns3_set_selftest_param(struct hnae3_handle *h, int (*st_param)[2])
+ 			h->flags & HNAE3_SUPPORT_PHY_LOOPBACK;
+ }
+ 
+-static void hns3_selftest_prepare(struct net_device *ndev,
+-				  bool if_running, int (*st_param)[2])
++static void hns3_selftest_prepare(struct net_device *ndev, bool if_running)
+ {
+ 	struct hns3_nic_priv *priv = netdev_priv(ndev);
+ 	struct hnae3_handle *h = priv->ae_handle;
+ 
+-	if (netif_msg_ifdown(h))
+-		netdev_info(ndev, "self test start\n");
+-
+-	hns3_set_selftest_param(h, st_param);
+-
+ 	if (if_running)
+ 		ndev->netdev_ops->ndo_stop(ndev);
+ 
+@@ -379,18 +377,15 @@ static void hns3_selftest_restore(struct net_device *ndev, bool if_running)
+ 
+ 	if (if_running)
+ 		ndev->netdev_ops->ndo_open(ndev);
+-
+-	if (netif_msg_ifdown(h))
+-		netdev_info(ndev, "self test end\n");
+ }
+ 
+ static void hns3_do_selftest(struct net_device *ndev, int (*st_param)[2],
+ 			     struct ethtool_test *eth_test, u64 *data)
+ {
+-	int test_index = 0;
++	int test_index = HNAE3_LOOP_APP;
+ 	u32 i;
+ 
+-	for (i = 0; i < HNS3_SELF_TEST_TYPE_NUM; i++) {
++	for (i = HNAE3_LOOP_APP; i < HNAE3_LOOP_NONE; i++) {
+ 		enum hnae3_loop loop_type = (enum hnae3_loop)st_param[i][0];
+ 
+ 		if (!st_param[i][1])
+@@ -409,6 +404,22 @@ static void hns3_do_selftest(struct net_device *ndev, int (*st_param)[2],
+ 	}
+ }
+ 
++static void hns3_do_external_lb(struct net_device *ndev,
++				struct ethtool_test *eth_test, u64 *data)
++{
++	data[HNAE3_LOOP_EXTERNAL] = hns3_lp_up(ndev, HNAE3_LOOP_EXTERNAL);
++	if (!data[HNAE3_LOOP_EXTERNAL])
++		data[HNAE3_LOOP_EXTERNAL] = (
++		hns3_lp_run_test(ndev, HNAE3_LOOP_EXTERNAL)
++		);
++	hns3_lp_down(ndev, HNAE3_LOOP_EXTERNAL);
++
++	if (data[HNAE3_LOOP_EXTERNAL])
++		eth_test->flags |= ETH_TEST_FL_FAILED;
++
++	eth_test->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
++}
++
+ /**
+  * hns3_nic_self_test - self test
+  * @ndev: net device
+@@ -418,7 +429,9 @@ static void hns3_do_selftest(struct net_device *ndev, int (*st_param)[2],
+ static void hns3_self_test(struct net_device *ndev,
+ 			   struct ethtool_test *eth_test, u64 *data)
+ {
+-	int st_param[HNS3_SELF_TEST_TYPE_NUM][2];
++	struct hns3_nic_priv *priv = netdev_priv(ndev);
++	struct hnae3_handle *h = priv->ae_handle;
++	int st_param[HNAE3_LOOP_NONE][2];
+ 	bool if_running = netif_running(ndev);
+ 
+ 	if (hns3_nic_resetting(ndev)) {
+@@ -426,13 +439,29 @@ static void hns3_self_test(struct net_device *ndev,
+ 		return;
+ 	}
+ 
+-	/* Only do offline selftest, or pass by default */
+-	if (eth_test->flags != ETH_TEST_FL_OFFLINE)
++	if (!(eth_test->flags & ETH_TEST_FL_OFFLINE))
+ 		return;
+ 
+-	hns3_selftest_prepare(ndev, if_running, st_param);
++	if (netif_msg_ifdown(h))
++		netdev_info(ndev, "self test start\n");
++
++	hns3_set_selftest_param(h, st_param);
++
++	/* external loopback test requires that the link is up and the duplex is
++	 * full, do external test first to reduce the whole test time
++	 */
++	if (eth_test->flags & ETH_TEST_FL_EXTERNAL_LB) {
++		hns3_external_lb_prepare(ndev, if_running);
++		hns3_do_external_lb(ndev, eth_test, data);
++		hns3_external_lb_restore(ndev, if_running);
++	}
++
++	hns3_selftest_prepare(ndev, if_running);
+ 	hns3_do_selftest(ndev, st_param, eth_test, data);
+ 	hns3_selftest_restore(ndev, if_running);
++
++	if (netif_msg_ifdown(h))
++		netdev_info(ndev, "self test end\n");
+ }
+ 
+ static void hns3_update_limit_promisc_mode(struct net_device *netdev,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index ee10aea14eb1..aeb776403ff0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -144,10 +144,11 @@ static const u32 tqp_intr_reg_addr_list[] = {HCLGE_TQP_INTR_CTRL_REG,
+ 					     HCLGE_TQP_INTR_RL_REG};
+ 
+ static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
+-	"App    Loopback test",
+-	"Serdes serial Loopback test",
+-	"Serdes parallel Loopback test",
+-	"Phy    Loopback test"
++	"External Loopback test",
++	"App      Loopback test",
++	"Serdes   serial Loopback test",
++	"Serdes   parallel Loopback test",
++	"Phy      Loopback test"
+ };
+ 
+ static const struct hclge_comm_stats_str g_mac_stats_string[] = {
+@@ -785,7 +786,8 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
+ #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK | \
+ 		HNAE3_SUPPORT_PHY_LOOPBACK | \
+ 		HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK | \
+-		HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
++		HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK | \
++		HNAE3_SUPPORT_EXTERNAL_LOOPBACK)
+ 
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+@@ -807,9 +809,12 @@ static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
+ 			handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
+ 		}
+ 
+-		count += 2;
++		count += 1;
+ 		handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
++		count += 1;
+ 		handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
++		count += 1;
++		handle->flags |= HNAE3_SUPPORT_EXTERNAL_LOOPBACK;
+ 
+ 		if ((hdev->hw.mac.phydev && hdev->hw.mac.phydev->drv &&
+ 		     hdev->hw.mac.phydev->drv->set_loopback) ||
+@@ -840,6 +845,11 @@ static void hclge_get_strings(struct hnae3_handle *handle, u32 stringset,
+ 					   size, p);
+ 		p = hclge_tqps_get_strings(handle, p);
+ 	} else if (stringset == ETH_SS_TEST) {
++		if (handle->flags & HNAE3_SUPPORT_EXTERNAL_LOOPBACK) {
++			memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_EXTERNAL],
++			       ETH_GSTRING_LEN);
++			p += ETH_GSTRING_LEN;
++		}
+ 		if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
+ 			memcpy(p, hns3_nic_test_strs[HNAE3_LOOP_APP],
+ 			       ETH_GSTRING_LEN);
+@@ -7467,7 +7477,7 @@ static int hclge_set_loopback(struct hnae3_handle *handle,
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+-	int ret;
++	int ret = 0;
+ 
+ 	/* Loopback can be enabled in three places: SSU, MAC, and serdes. By
+ 	 * default, SSU loopback is enabled, so if the SMAC and the DMAC are
+@@ -7494,6 +7504,8 @@ static int hclge_set_loopback(struct hnae3_handle *handle,
+ 	case HNAE3_LOOP_PHY:
+ 		ret = hclge_set_phy_loopback(hdev, en);
+ 		break;
++	case HNAE3_LOOP_EXTERNAL:
++		break;
+ 	default:
+ 		ret = -ENOTSUPP;
+ 		dev_err(&hdev->pdev->dev,
+-- 
+2.34.1
+
diff --git a/patches/0544-net-hns3-fix-setting-incorrect-phy-link-ksettings-fo.patch b/patches/0544-net-hns3-fix-setting-incorrect-phy-link-ksettings-fo.patch
new file mode 100644
index 0000000..3f3e914
--- /dev/null
+++ b/patches/0544-net-hns3-fix-setting-incorrect-phy-link-ksettings-fo.patch
@@ -0,0 +1,66 @@
+From 1557f33214d6f7b9d345a32a43646da0ce3c5fe3 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Mon, 14 Nov 2022 16:20:48 +0800
+Subject: [PATCH 183/283] net: hns3: fix setting incorrect phy link ksettings
+ for firmware in resetting process
+
+mainline inclusion
+from mainline-v6.1-rc6
+commit 510d7b6ae842e59ee00d57e5f07ac15131b6d899
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=510d7b6ae842e59ee00d57e5f07ac15131b6d899
+
+----------------------------------------------------------------------
+
+Currently, if driver is in phy-imp(phy controlled by imp firmware) mode, as
+driver did not update phy link ksettings after initialization process or
+not update advertising when getting phy link ksettings from firmware, it
+may set incorrect phy link ksettings for firmware in resetting process.
+So fix it.
+
+Fixes: f5f2b3e4dcc0 ("net: hns3: add support for imp-controlled PHYs")
+Fixes: c5ef83cbb1e9 ("net: hns3: fix for phy_addr error in hclge_mac_mdio_config")
+Fixes: 2312e050f42b ("net: hns3: Fix for deadlock problem occurring when unregistering ae_algo")
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c    | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index aeb776403ff0..62b60e559137 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3327,6 +3327,7 @@ static int hclge_update_tp_port_info(struct hclge_dev *hdev)
+ 	hdev->hw.mac.autoneg = cmd.base.autoneg;
+ 	hdev->hw.mac.speed = cmd.base.speed;
+ 	hdev->hw.mac.duplex = cmd.base.duplex;
++	linkmode_copy(hdev->hw.mac.advertising, cmd.link_modes.advertising);
+ 
+ 	return 0;
+ }
+@@ -11026,9 +11027,12 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	if (ret)
+ 		goto err_msi_irq_uninit;
+ 
+-	if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER &&
+-	    !hnae3_dev_phy_imp_supported(hdev)) {
+-		ret = hclge_mac_mdio_config(hdev);
++	if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
++		if (hnae3_dev_phy_imp_supported(hdev))
++			ret = hclge_update_tp_port_info(hdev);
++		else
++			ret = hclge_mac_mdio_config(hdev);
++
+ 		if (ret)
+ 			goto err_msi_irq_uninit;
+ 	}
+-- 
+2.34.1
+
diff --git a/patches/0545-net-hns3-refine-the-handling-for-VF-heartbeat.patch b/patches/0545-net-hns3-refine-the-handling-for-VF-heartbeat.patch
new file mode 100644
index 0000000..802e262
--- /dev/null
+++ b/patches/0545-net-hns3-refine-the-handling-for-VF-heartbeat.patch
@@ -0,0 +1,856 @@
+From e6642c8c809905f91653b25325c0fbdcf20c5952 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Wed, 30 Nov 2022 18:23:31 +0800
+Subject: [PATCH 184/283] net: hns3: refine the handling for VF heartbeat
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+----------------------------------------------------------------------
+
+Currently, the PF check the VF alive by the KEEP_ALVE
+mailbox from VF. VF keep sending the mailbox per 2
+seconds. Once PF lost the mailbox for more than 8
+seconds, it will regards the VF is abnormal, and stop
+notifying the state change to VF, include link state,
+vf mac, reset, even though it receives the KEEP_ALIVE
+mailbox again. It's inreasonable.
+
+This patch fixes it. PF will record the state change which
+need to notify VF when lost the VF's KEEP_ALIVE mailbox.
+And notify VF when receive the mailbox again. Introduce a
+new flag HCLGE_VPORT_STATE_INITED, used to distinguish the
+case whether VF driver loaded or not. For VF will query
+these states when initializing, so it's unnecessary to
+notify it in this case.
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+---
+ .../net/ethernet/hisilicon/hns3/hclge_mbx.h   |  13 +-
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  60 ++-
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   8 +-
+ .../hisilicon/hns3/hns3pf/hclge_mbx.c         | 510 ++++++++++++------
+ 4 files changed, 393 insertions(+), 198 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
+index 98045a4649e8..05a1b789c9ab 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
+@@ -24,7 +24,7 @@ enum HCLGE_MBX_OPCODE {
+ 	HCLGE_MBX_GET_RETA,		/* (VF -> PF) get RETA */
+ 	HCLGE_MBX_GET_RSS_KEY,		/* (VF -> PF) get RSS key */
+ 	HCLGE_MBX_GET_MAC_ADDR,		/* (VF -> PF) get MAC addr */
+-	HCLGE_MBX_PF_VF_RESP,		/* (PF -> VF) generate respone to VF */
++	HCLGE_MBX_PF_VF_RESP,		/* (PF -> VF) generate response to VF */
+ 	HCLGE_MBX_GET_BDNUM,		/* (VF -> PF) get BD num */
+ 	HCLGE_MBX_GET_BUFSIZE,		/* (VF -> PF) get buffer size */
+ 	HCLGE_MBX_GET_STREAMID,		/* (VF -> PF) get stream id */
+@@ -47,6 +47,8 @@ enum HCLGE_MBX_OPCODE {
+ 	HCLGE_MBX_VF_UNINIT,            /* (VF -> PF) vf is unintializing */
+ 	HCLGE_MBX_HANDLE_VF_TBL,	/* (VF -> PF) store/clear hw table */
+ 	HCLGE_MBX_GET_RING_VECTOR_MAP,	/* (VF -> PF) get ring-to-vector map */
++	HCLGE_MBX_SET_QB = 0x28,        /* (VF -> PF) set queue bonding */
++	HCLGE_MBX_PUSH_QB_STATE,        /* (PF -> VF) push qb state */
+ 
+ 	HCLGE_MBX_GET_VF_FLR_STATUS = 200, /* (M7 -> PF) get vf flr status */
+ 	HCLGE_MBX_PUSH_LINK_STATUS,	/* (M7 -> PF) get port link status */
+@@ -186,6 +188,15 @@ struct hclgevf_mbx_arq_ring {
+ 	u16 msg_q[HCLGE_MBX_MAX_ARQ_MSG_NUM][HCLGE_MBX_MAX_ARQ_MSG_SIZE];
+ };
+ 
++#define HCLGE_MBX_OPCODE_MAX 256
++struct hclge_mbx_ops_param {
++	struct hclge_vport *vport;
++	struct hclge_mbx_vf_to_pf_cmd *req;
++	struct hclge_respond_to_vf_msg *resp_msg;
++};
++
++typedef int (*hclge_mbx_ops_fn)(struct hclge_mbx_ops_param *param);
++
+ #define hclge_mbx_ring_ptr_move_crq(crq) \
+ 	(crq->next_to_use = (crq->next_to_use + 1) % crq->desc_num)
+ #define hclge_mbx_tail_ptr_move_arq(arq) \
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 62b60e559137..14e70efd44c8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -3797,9 +3797,17 @@ static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
+ 			return ret;
+ 		}
+ 
+-		if (!reset || !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
++		if (!reset ||
++		    !test_bit(HCLGE_VPORT_STATE_INITED, &vport->state))
+ 			continue;
+ 
++		if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state) &&
++		    hdev->reset_type == HNAE3_FUNC_RESET) {
++			set_bit(HCLGE_VPORT_NEED_NOTIFY_RESET,
++				&vport->need_notify);
++			continue;
++		}
++
+ 		/* Inform VF to process the reset.
+ 		 * hclge_inform_reset_assert_to_vf may fail if VF
+ 		 * driver is not loaded.
+@@ -4520,20 +4528,15 @@ static void hclge_update_vport_alive(struct hclge_dev *hdev)
+ 	for (i = 1; i < hdev->num_alloc_vport; i++) {
+ 		struct hclge_vport *vport = &hdev->vport[i];
+ 
+-		/* vf keeps sending alive msg to pf per 2s, if pf doesn't
+-		 * receive a vf's alive msg for 8s, regards the vf is offline
+-		 */
+-		if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ))
+-			if (test_and_clear_bit(HCLGE_VPORT_STATE_ALIVE,
+-					       &vport->state))
+-				dev_info(&hdev->pdev->dev,
+-					 "VF %u keep alive lost!",
+-					 vport->vport_id -
+-					 HCLGE_VF_VPORT_START_NUM);
+-
+-		/* If vf is not alive, set to default value */
+-		if (!test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
+-			vport->mps = HCLGE_MAC_DEFAULT_FRAME;
++		if (!test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) ||
++		    !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
++			continue;
++		if (time_after(jiffies, vport->last_active_jiffies + 8 * HZ)) {
++			clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
++			dev_warn(&hdev->pdev->dev,
++				 "vf %u heartbeat timeout\n",
++				 i - HCLGE_VF_VPORT_START_NUM);
++		}
+ 	}
+ }
+ 
+@@ -7645,11 +7648,11 @@ int hclge_vport_start(struct hclge_vport *vport)
+ {
+ 	struct hclge_dev *hdev = vport->back;
+ 
++	set_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
+ 	set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
+ 	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
+ 	vport->last_active_jiffies = jiffies;
+-	set_bit(HCLGE_VPORT_STATE_START, &vport->state);
+-	set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
++	vport->need_notify = 0;
+ 
+ 	if (test_bit(vport->vport_id, hdev->vport_config_block)) {
+ 		if (vport->vport_id) {
+@@ -7666,8 +7669,9 @@ int hclge_vport_start(struct hclge_vport *vport)
+ 
+ void hclge_vport_stop(struct hclge_vport *vport)
+ {
+-	clear_bit(HCLGE_VPORT_STATE_START, &vport->state);
++	clear_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
+ 	clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
++	vport->need_notify = 0;
+ }
+ 
+ static int hclge_client_start(struct hnae3_handle *handle)
+@@ -8723,7 +8727,8 @@ static int hclge_set_vf_mac(struct hnae3_handle *handle, int vf,
+ 		return 0;
+ 	}
+ 
+-	dev_info(&hdev->pdev->dev, "MAC of VF %d has been set to %s\n",
++	dev_info(&hdev->pdev->dev,
++		 "MAC of VF %d has been set to %s, will be active after vf reset\n",
+ 		 vf, format_mac_addr);
+ 	return 0;
+ }
+@@ -9866,6 +9871,7 @@ static u16 hclge_get_port_base_vlan_state(struct hclge_vport *vport,
+ static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
+ 				    u16 vlan, u8 qos, __be16 proto)
+ {
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+ 	struct hclge_vlan_info vlan_info;
+@@ -9907,10 +9913,16 @@ static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
+ 	 * cause send mailbox fail, but it doesn't matter, VF will
+ 	 * query it when reinit.
+ 	 */
+-	if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
+-		(void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
+-							vport->vport_id,
+-							state, &vlan_info);
++	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3) {
++		if (test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state))
++			(void)hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
++								vport->vport_id,
++								state,
++								&vlan_info);
++		else
++			set_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN,
++				&vport->need_notify);
++	}
+ 	return 0;
+ }
+ 
+@@ -11376,7 +11388,7 @@ static void hclge_reset_vport_state(struct hclge_dev *hdev)
+ 	int i;
+ 
+ 	for (i = 0; i < hdev->num_alloc_vport; i++) {
+-		hclge_vport_stop(vport);
++		clear_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
+ 		vport++;
+ 	}
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 973b4f3de627..b7b4d922711e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -973,10 +973,15 @@ enum HCLGE_VPORT_STATE {
+ 	HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
+ 	HCLGE_VPORT_STATE_PROMISC_CHANGE,
+ 	HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
+-	HCLGE_VPORT_STATE_START,
++	HCLGE_VPORT_STATE_INITED,
+ 	HCLGE_VPORT_STATE_MAX
+ };
+ 
++enum HCLGE_VPORT_NEED_NOTIFY {
++	HCLGE_VPORT_NEED_NOTIFY_RESET,
++	HCLGE_VPORT_NEED_NOTIFY_VF_VLAN,
++};
++
+ struct hclge_vlan_info {
+ 	u16 vlan_proto; /* so far support 802.1Q only */
+ 	u16 qos;
+@@ -1032,6 +1037,7 @@ struct hclge_vport {
+ 	struct hnae3_handle roce;
+ 
+ 	unsigned long state;
++	unsigned long need_notify;
+ 	unsigned long last_active_jiffies;
+ 	int mps; /* Max packet size */
+ 	struct hclge_vf_info vf_info;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+index 7b27a012bbd1..ec84f81fff92 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+@@ -117,17 +117,26 @@ static int hclge_send_mbx_msg(struct hclge_vport *vport, u8 *msg, u16 msg_len,
+ 	return status;
+ }
+ 
++static int hclge_inform_vf_reset(struct hclge_vport *vport, u16 reset_type)
++{
++	__le16 msg_data;
++	u8 dest_vfid;
++
++	dest_vfid = (u8)vport->vport_id;
++	msg_data = cpu_to_le16(reset_type);
++
++	/* send this requested info to VF */
++	return hclge_send_mbx_msg(vport, (u8 *)&msg_data, sizeof(msg_data),
++				  HCLGE_MBX_ASSERTING_RESET, dest_vfid);
++}
++
+ int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport)
+ {
+ 	struct hclge_dev *hdev = vport->back;
+ 	u16 reset_type;
+-	u8 msg_data[2];
+-	u8 dest_vfid;
+ 
+ 	BUILD_BUG_ON(HNAE3_MAX_RESET > U16_MAX);
+ 
+-	dest_vfid = (u8)vport->vport_id;
+-
+ 	if (hdev->reset_type == HNAE3_FUNC_RESET)
+ 		reset_type = HNAE3_VF_PF_FUNC_RESET;
+ 	else if (hdev->reset_type == HNAE3_FLR_RESET)
+@@ -135,11 +144,7 @@ int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport)
+ 	else
+ 		reset_type = HNAE3_VF_FUNC_RESET;
+ 
+-	memcpy(&msg_data[0], &reset_type, sizeof(u16));
+-
+-	/* send this requested info to VF */
+-	return hclge_send_mbx_msg(vport, msg_data, sizeof(msg_data),
+-				  HCLGE_MBX_ASSERTING_RESET, dest_vfid);
++	return hclge_inform_vf_reset(vport, reset_type);
+ }
+ 
+ static void hclge_free_vector_ring_chain(struct hnae3_ring_chain_node *head)
+@@ -639,31 +644,55 @@ static int hclge_reset_vf(struct hclge_vport *vport)
+ 	return hclge_func_reset_cmd(hdev, vport->vport_id);
+ }
+ 
+-static void hclge_vf_keep_alive(struct hclge_vport *vport)
++static void hclge_notify_vf_config(struct hclge_vport *vport)
+ {
+ 	struct hclge_dev *hdev = vport->back;
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	struct hclge_port_base_vlan_config *vlan_cfg;
+ 	int ret;
+ 
++	hclge_push_vf_link_status(vport);
++	if (test_bit(HCLGE_VPORT_NEED_NOTIFY_RESET, &vport->need_notify)) {
++		ret = hclge_inform_vf_reset(vport, HNAE3_VF_PF_FUNC_RESET);
++		if (ret) {
++			dev_err(&hdev->pdev->dev,
++				"failed to inform VF %u reset!",
++				vport->vport_id - HCLGE_VF_VPORT_START_NUM);
++			return;
++		}
++		vport->need_notify = 0;
++		return;
++	}
++
++	if (ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3 &&
++	    test_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, &vport->need_notify)) {
++		vlan_cfg = &vport->port_base_vlan_cfg;
++		ret = hclge_push_vf_port_base_vlan_info(&hdev->vport[0],
++							vport->vport_id,
++							vlan_cfg->state,
++							&vlan_cfg->vlan_info);
++		if (ret) {
++			dev_err(&hdev->pdev->dev,
++				"failed to inform VF %u port base vlan!",
++				vport->vport_id - HCLGE_VF_VPORT_START_NUM);
++			return;
++		}
++		clear_bit(HCLGE_VPORT_NEED_NOTIFY_VF_VLAN, &vport->need_notify);
++	}
++}
++
++static void hclge_vf_keep_alive(struct hclge_vport *vport)
++{
++	struct hclge_dev *hdev = vport->back;
++
+ 	vport->last_active_jiffies = jiffies;
+ 
+-	if (test_bit(HCLGE_VPORT_STATE_START, &vport->state) &&
++	if (test_bit(HCLGE_VPORT_STATE_INITED, &vport->state) &&
+ 	    !test_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state)) {
+ 		set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
+-
+-		dev_info(&hdev->pdev->dev, "VF %u keep alive resume!",
++		dev_info(&hdev->pdev->dev, "VF %u is alive!",
+ 			 vport->vport_id - HCLGE_VF_VPORT_START_NUM);
+-
+-		/* if vf support push link, need to push link status after keep
+-		 * alive restore, because the vf will not fetch the link status
+-		 * of it's own.
+-		 */
+-		ret = hclge_push_vf_link_status(vport);
+-		if (ret) {
+-			dev_err(&hdev->pdev->dev,
+-				"failed to push link status to vf%u, ret=%d\n",
+-				vport->vport_id - HCLGE_VF_VPORT_START_NUM,
+-				ret);
+-		}
++		hclge_notify_vf_config(vport);
+ 	}
+ }
+ 
+@@ -677,7 +706,7 @@ static int hclge_set_vf_mtu(struct hclge_vport *vport,
+ 	return hclge_set_vport_mtu(vport, mtu);
+ }
+ 
+-static void hclge_get_queue_id_in_pf(struct hclge_vport *vport,
++static int hclge_get_queue_id_in_pf(struct hclge_vport *vport,
+ 				     struct hclge_mbx_vf_to_pf_cmd *mbx_req,
+ 				     struct hclge_respond_to_vf_msg *resp_msg)
+ {
+@@ -689,17 +718,19 @@ static void hclge_get_queue_id_in_pf(struct hclge_vport *vport,
+ 	if (queue_id >= handle->kinfo.num_tqps) {
+ 		dev_err(&hdev->pdev->dev, "Invalid queue id(%u) from VF %u\n",
+ 			queue_id, mbx_req->mbx_src_vfid);
+-		return;
++		return -EINVAL;
+ 	}
+ 
+ 	qid_in_pf = hclge_covert_handle_qid_global(&vport->nic, queue_id);
+ 	memcpy(resp_msg->data, &qid_in_pf, sizeof(qid_in_pf));
+ 	resp_msg->len = sizeof(qid_in_pf);
++
++	return 0;
+ }
+ 
+-static void hclge_get_rss_key(struct hclge_vport *vport,
+-			      struct hclge_mbx_vf_to_pf_cmd *mbx_req,
+-			      struct hclge_respond_to_vf_msg *resp_msg)
++static int hclge_get_rss_key(struct hclge_vport *vport,
++			     struct hclge_mbx_vf_to_pf_cmd *mbx_req,
++			     struct hclge_respond_to_vf_msg *resp_msg)
+ {
+ #define HCLGE_RSS_MBX_RESP_LEN	8
+ 	struct hclge_dev *hdev = vport->back;
+@@ -719,13 +750,15 @@ static void hclge_get_rss_key(struct hclge_vport *vport,
+ 		dev_warn(&hdev->pdev->dev,
+ 			 "failed to get the rss hash key, the index(%u) invalid !\n",
+ 			 index);
+-		return;
++		return -EINVAL;
+ 	}
+ 
+ 	memcpy(resp_msg->data,
+ 	       &hdev->vport[0].rss_hash_key[index * HCLGE_RSS_MBX_RESP_LEN],
+ 	       HCLGE_RSS_MBX_RESP_LEN);
+ 	resp_msg->len = HCLGE_RSS_MBX_RESP_LEN;
++
++	return 0;
+ }
+ 
+ static void hclge_link_fail_parse(struct hclge_dev *hdev, u8 link_fail_code)
+@@ -789,17 +822,285 @@ static void hclge_handle_vf_tbl(struct hclge_vport *vport,
+ 	}
+ }
+ 
++static int
++hclge_mbx_map_ring_to_vector_handler(struct hclge_mbx_ops_param *param)
++{
++	return hclge_map_unmap_ring_to_vf_vector(param->vport, true,
++						 param->req);
++}
++
++static int
++hclge_mbx_unmap_ring_to_vector_handler(struct hclge_mbx_ops_param *param)
++{
++	return hclge_map_unmap_ring_to_vf_vector(param->vport, false,
++						 param->req);
++}
++
++static int
++hclge_mbx_get_ring_vector_map_handler(struct hclge_mbx_ops_param *param)
++{
++	int ret;
++
++	ret = hclge_get_vf_ring_vector_map(param->vport, param->req,
++					   param->resp_msg);
++	if (ret)
++		dev_err(&param->vport->back->pdev->dev,
++			"PF fail(%d) to get VF ring vector map\n",
++			ret);
++	return ret;
++}
++
++static int hclge_mbx_set_promisc_mode_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_set_vf_promisc_mode(param->vport, param->req);
++	return 0;
++}
++
++static int hclge_mbx_set_unicast_handler(struct hclge_mbx_ops_param *param)
++{
++	int ret;
++
++	ret = hclge_set_vf_uc_mac_addr(param->vport, param->req);
++	if (ret)
++		dev_err(&param->vport->back->pdev->dev,
++			"PF fail(%d) to set VF UC MAC Addr\n",
++			ret);
++	return ret;
++}
++
++static int hclge_mbx_set_multicast_handler(struct hclge_mbx_ops_param *param)
++{
++	int ret;
++
++	ret = hclge_set_vf_mc_mac_addr(param->vport, param->req);
++	if (ret)
++		dev_err(&param->vport->back->pdev->dev,
++			"PF fail(%d) to set VF MC MAC Addr\n",
++			ret);
++	return ret;
++}
++
++static int hclge_mbx_set_vlan_handler(struct hclge_mbx_ops_param *param)
++{
++	int ret;
++
++	ret = hclge_set_vf_vlan_cfg(param->vport, param->req, param->resp_msg);
++	if (ret)
++		dev_err(&param->vport->back->pdev->dev,
++			"PF failed(%d) to config VF's VLAN\n",
++			ret);
++	return ret;
++}
++
++static int hclge_mbx_set_alive_handler(struct hclge_mbx_ops_param *param)
++{
++	int ret;
++
++	ret = hclge_set_vf_alive(param->vport, param->req);
++	if (ret)
++		dev_err(&param->vport->back->pdev->dev,
++			"PF failed(%d) to set VF's ALIVE\n",
++			ret);
++	return ret;
++}
++
++static int hclge_mbx_get_qinfo_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_get_vf_queue_info(param->vport, param->resp_msg);
++	return 0;
++}
++
++static int hclge_mbx_get_qdepth_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_get_vf_queue_depth(param->vport, param->resp_msg);
++	return 0;
++}
++
++static int hclge_mbx_get_basic_info_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_get_basic_info(param->vport, param->resp_msg);
++	return 0;
++}
++
++static int hclge_mbx_get_link_status_handler(struct hclge_mbx_ops_param *param)
++{
++	int ret;
++
++	ret = hclge_push_vf_link_status(param->vport);
++	if (ret)
++		dev_err(&param->vport->back->pdev->dev,
++			"failed to inform link stat to VF, ret = %d\n",
++			ret);
++	return ret;
++}
++
++static int hclge_mbx_queue_reset_handler(struct hclge_mbx_ops_param *param)
++{
++	return hclge_mbx_reset_vf_queue(param->vport, param->req,
++					param->resp_msg);
++}
++
++static int hclge_mbx_reset_handler(struct hclge_mbx_ops_param *param)
++{
++	return hclge_reset_vf(param->vport);
++}
++
++static int hclge_mbx_keep_alive_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_vf_keep_alive(param->vport);
++	return 0;
++}
++
++static int hclge_mbx_set_mtu_handler(struct hclge_mbx_ops_param *param)
++{
++	int ret;
++
++	ret = hclge_set_vf_mtu(param->vport, param->req);
++	if (ret)
++		dev_err(&param->vport->back->pdev->dev,
++			"VF fail(%d) to set mtu\n", ret);
++	return ret;
++}
++
++static int hclge_mbx_get_qid_in_pf_handler(struct hclge_mbx_ops_param *param)
++{
++	return hclge_get_queue_id_in_pf(param->vport, param->req,
++					param->resp_msg);
++}
++
++static int hclge_mbx_get_rss_key_handler(struct hclge_mbx_ops_param *param)
++{
++	return hclge_get_rss_key(param->vport, param->req, param->resp_msg);
++}
++
++static int hclge_mbx_get_link_mode_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_get_link_mode(param->vport, param->req);
++	return 0;
++}
++
++static int
++hclge_mbx_get_vf_flr_status_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_rm_vport_all_mac_table(param->vport, false,
++				     HCLGE_MAC_ADDR_UC);
++	hclge_rm_vport_all_mac_table(param->vport, false,
++				     HCLGE_MAC_ADDR_MC);
++	hclge_rm_vport_all_vlan_table(param->vport, false);
++	return 0;
++}
++
++static int hclge_mbx_vf_uninit_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_rm_vport_all_mac_table(param->vport, true,
++				     HCLGE_MAC_ADDR_UC);
++	hclge_rm_vport_all_mac_table(param->vport, true,
++				     HCLGE_MAC_ADDR_MC);
++	hclge_rm_vport_all_vlan_table(param->vport, true);
++	param->vport->mps = 0;
++	return 0;
++}
++
++static int hclge_mbx_get_media_type_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_get_vf_media_type(param->vport, param->resp_msg);
++	return 0;
++}
++
++static int hclge_mbx_push_link_status_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_handle_link_change_event(param->vport->back, param->req);
++	return 0;
++}
++
++static int hclge_mbx_get_mac_addr_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_get_vf_mac_addr(param->vport, param->resp_msg);
++	return 0;
++}
++
++static int hclge_mbx_ncsi_error_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_handle_ncsi_error(param->vport->back);
++	return 0;
++}
++
++static int hclge_mbx_handle_vf_tbl_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_handle_vf_tbl(param->vport, param->req);
++	return 0;
++}
++
++static const hclge_mbx_ops_fn hclge_mbx_ops_list[HCLGE_MBX_OPCODE_MAX] = {
++	[HCLGE_MBX_RESET]   = hclge_mbx_reset_handler,
++	[HCLGE_MBX_SET_UNICAST] = hclge_mbx_set_unicast_handler,
++	[HCLGE_MBX_SET_MULTICAST] = hclge_mbx_set_multicast_handler,
++	[HCLGE_MBX_SET_VLAN] = hclge_mbx_set_vlan_handler,
++	[HCLGE_MBX_MAP_RING_TO_VECTOR] = hclge_mbx_map_ring_to_vector_handler,
++	[HCLGE_MBX_UNMAP_RING_TO_VECTOR] = hclge_mbx_unmap_ring_to_vector_handler,
++	[HCLGE_MBX_SET_PROMISC_MODE] = hclge_mbx_set_promisc_mode_handler,
++	[HCLGE_MBX_GET_QINFO] = hclge_mbx_get_qinfo_handler,
++	[HCLGE_MBX_GET_QDEPTH] = hclge_mbx_get_qdepth_handler,
++	[HCLGE_MBX_GET_BASIC_INFO] = hclge_mbx_get_basic_info_handler,
++	[HCLGE_MBX_GET_RSS_KEY] = hclge_mbx_get_rss_key_handler,
++	[HCLGE_MBX_GET_MAC_ADDR] = hclge_mbx_get_mac_addr_handler,
++	[HCLGE_MBX_GET_LINK_STATUS] = hclge_mbx_get_link_status_handler,
++	[HCLGE_MBX_QUEUE_RESET] = hclge_mbx_queue_reset_handler,
++	[HCLGE_MBX_KEEP_ALIVE] = hclge_mbx_keep_alive_handler,
++	[HCLGE_MBX_SET_ALIVE] = hclge_mbx_set_alive_handler,
++	[HCLGE_MBX_SET_MTU] = hclge_mbx_set_mtu_handler,
++	[HCLGE_MBX_GET_QID_IN_PF] = hclge_mbx_get_qid_in_pf_handler,
++	[HCLGE_MBX_GET_LINK_MODE] = hclge_mbx_get_link_mode_handler,
++	[HCLGE_MBX_GET_MEDIA_TYPE] = hclge_mbx_get_media_type_handler,
++	[HCLGE_MBX_VF_UNINIT] = hclge_mbx_vf_uninit_handler,
++	[HCLGE_MBX_HANDLE_VF_TBL] = hclge_mbx_handle_vf_tbl_handler,
++	[HCLGE_MBX_GET_RING_VECTOR_MAP] = hclge_mbx_get_ring_vector_map_handler,
++	[HCLGE_MBX_GET_VF_FLR_STATUS] = hclge_mbx_get_vf_flr_status_handler,
++	[HCLGE_MBX_PUSH_LINK_STATUS] = hclge_mbx_push_link_status_handler,
++	[HCLGE_MBX_NCSI_ERROR] = hclge_mbx_ncsi_error_handler,
++};
++
++static void hclge_mbx_request_handling(struct hclge_mbx_ops_param *param)
++{
++	hclge_mbx_ops_fn cmd_func = NULL;
++	struct hclge_dev *hdev;
++	int ret = 0;
++
++	hdev = param->vport->back;
++	cmd_func = hclge_mbx_ops_list[param->req->msg.code];
++	if (cmd_func)
++		ret = cmd_func(param);
++	else
++		dev_err(&hdev->pdev->dev,
++			"un-supported mailbox message, code = %u\n",
++			param->req->msg.code);
++
++	/* PF driver should not reply IMP */
++	if (hnae3_get_bit(param->req->mbx_need_resp, HCLGE_MBX_NEED_RESP_B) &&
++	    param->req->msg.code < HCLGE_MBX_GET_VF_FLR_STATUS) {
++		param->resp_msg->status = ret;
++		if (time_is_before_jiffies(hdev->last_mbx_scheduled +
++					   HCLGE_MBX_SCHED_TIMEOUT))
++			dev_warn(&hdev->pdev->dev,
++				 "resp vport%u mbx(%u,%u) late\n",
++				 param->req->mbx_src_vfid,
++				 param->req->msg.code,
++				 param->req->msg.subcode);
++
++		hclge_gen_resp_to_vf(param->vport, param->req, param->resp_msg);
++	}
++}
++
+ void hclge_mbx_handler(struct hclge_dev *hdev)
+ {
+ 	struct hclge_cmq_ring *crq = &hdev->hw.cmq.crq;
+ 	struct hclge_respond_to_vf_msg resp_msg;
+ 	struct hclge_mbx_vf_to_pf_cmd *req;
+-	struct hclge_vport *vport;
++	struct hclge_mbx_ops_param param;
+ 	struct hclge_desc *desc;
+-	bool is_del = false;
+ 	unsigned int flag;
+-	int ret = 0;
+ 
++	param.resp_msg = &resp_msg;
+ 	/* handle all the mailbox requests in the queue */
+ 	while (!hclge_cmd_crq_empty(&hdev->hw)) {
+ 		if (test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) {
+@@ -823,152 +1124,17 @@ void hclge_mbx_handler(struct hclge_dev *hdev)
+ 			continue;
+ 		}
+ 
+-		vport = &hdev->vport[req->mbx_src_vfid];
+-
+ 		trace_hclge_pf_mbx_get(hdev, req);
+ 
+ 		/* clear the resp_msg before processing every mailbox message */
+ 		memset(&resp_msg, 0, sizeof(resp_msg));
+ 
+-		switch (req->msg.code) {
+-		case HCLGE_MBX_MAP_RING_TO_VECTOR:
+-			ret = hclge_map_unmap_ring_to_vf_vector(vport, true,
+-								req);
+-			break;
+-		case HCLGE_MBX_UNMAP_RING_TO_VECTOR:
+-			ret = hclge_map_unmap_ring_to_vf_vector(vport, false,
+-								req);
+-			break;
+-		case HCLGE_MBX_GET_RING_VECTOR_MAP:
+-			ret = hclge_get_vf_ring_vector_map(vport, req,
+-							   &resp_msg);
+-			if (ret)
+-				dev_err(&hdev->pdev->dev,
+-					"PF fail(%d) to get VF ring vector map\n",
+-					ret);
+-			break;
+-		case HCLGE_MBX_SET_PROMISC_MODE:
+-			hclge_set_vf_promisc_mode(vport, req);
+-			break;
+-		case HCLGE_MBX_SET_UNICAST:
+-			ret = hclge_set_vf_uc_mac_addr(vport, req);
+-			if (ret)
+-				dev_err(&hdev->pdev->dev,
+-					"PF fail(%d) to set VF UC MAC Addr\n",
+-					ret);
+-			break;
+-		case HCLGE_MBX_SET_MULTICAST:
+-			ret = hclge_set_vf_mc_mac_addr(vport, req);
+-			if (ret)
+-				dev_err(&hdev->pdev->dev,
+-					"PF fail(%d) to set VF MC MAC Addr\n",
+-					ret);
+-			break;
+-		case HCLGE_MBX_SET_VLAN:
+-			ret = hclge_set_vf_vlan_cfg(vport, req, &resp_msg);
+-			if (ret)
+-				dev_err(&hdev->pdev->dev,
+-					"PF failed(%d) to config VF's VLAN\n",
+-					ret);
+-			break;
+-		case HCLGE_MBX_SET_ALIVE:
+-			ret = hclge_set_vf_alive(vport, req);
+-			if (ret)
+-				dev_err(&hdev->pdev->dev,
+-					"PF failed(%d) to set VF's ALIVE\n",
+-					ret);
+-			break;
+-		case HCLGE_MBX_GET_QINFO:
+-			hclge_get_vf_queue_info(vport, &resp_msg);
+-			break;
+-		case HCLGE_MBX_GET_QDEPTH:
+-			hclge_get_vf_queue_depth(vport, &resp_msg);
+-			break;
+-		case HCLGE_MBX_GET_BASIC_INFO:
+-			hclge_get_basic_info(vport, &resp_msg);
+-			break;
+-		case HCLGE_MBX_GET_LINK_STATUS:
+-			ret = hclge_push_vf_link_status(vport);
+-			if (ret)
+-				dev_err(&hdev->pdev->dev,
+-					"failed to inform link stat to VF, ret = %d\n",
+-					ret);
+-			break;
+-		case HCLGE_MBX_QUEUE_RESET:
+-			ret = hclge_mbx_reset_vf_queue(vport, req, &resp_msg);
+-			break;
+-		case HCLGE_MBX_RESET:
+-			ret = hclge_reset_vf(vport);
+-			break;
+-		case HCLGE_MBX_KEEP_ALIVE:
+-			hclge_vf_keep_alive(vport);
+-			break;
+-		case HCLGE_MBX_SET_MTU:
+-			ret = hclge_set_vf_mtu(vport, req);
+-			if (ret)
+-				dev_err(&hdev->pdev->dev,
+-					"VF fail(%d) to set mtu\n", ret);
+-			break;
+-		case HCLGE_MBX_GET_QID_IN_PF:
+-			hclge_get_queue_id_in_pf(vport, req, &resp_msg);
+-			break;
+-		case HCLGE_MBX_GET_RSS_KEY:
+-			hclge_get_rss_key(vport, req, &resp_msg);
+-			break;
+-		case HCLGE_MBX_GET_LINK_MODE:
+-			hclge_get_link_mode(vport, req);
+-			break;
+-		case HCLGE_MBX_GET_VF_FLR_STATUS:
+-		case HCLGE_MBX_VF_UNINIT:
+-			is_del = req->msg.code == HCLGE_MBX_VF_UNINIT;
+-			hclge_rm_vport_all_mac_table(vport, is_del,
+-						     HCLGE_MAC_ADDR_UC);
+-			hclge_rm_vport_all_mac_table(vport, is_del,
+-						     HCLGE_MAC_ADDR_MC);
+-			hclge_rm_vport_all_vlan_table(vport, is_del);
+-			break;
+-		case HCLGE_MBX_GET_MEDIA_TYPE:
+-			hclge_get_vf_media_type(vport, &resp_msg);
+-			break;
+-		case HCLGE_MBX_PUSH_LINK_STATUS:
+-			hclge_handle_link_change_event(hdev, req);
+-			break;
+-		case HCLGE_MBX_GET_MAC_ADDR:
+-			hclge_get_vf_mac_addr(vport, &resp_msg);
+-			break;
+-		case HCLGE_MBX_NCSI_ERROR:
+-			hclge_handle_ncsi_error(hdev);
+-			break;
+-		case HCLGE_MBX_HANDLE_VF_TBL:
+-			hclge_handle_vf_tbl(vport, req);
+-			break;
+-		default:
+-			dev_err(&hdev->pdev->dev,
+-				"un-supported mailbox message, code = %u\n",
+-				req->msg.code);
+-			break;
+-		}
+-
+-		/* PF driver should not reply IMP */
+-		if (hnae3_get_bit(req->mbx_need_resp, HCLGE_MBX_NEED_RESP_B) &&
+-		    req->msg.code < HCLGE_MBX_GET_VF_FLR_STATUS) {
+-			resp_msg.status = ret;
+-			if (time_is_before_jiffies(hdev->last_mbx_scheduled +
+-						   HCLGE_MBX_SCHED_TIMEOUT))
+-				dev_warn(&hdev->pdev->dev,
+-					 "resp vport%u mbx(%u,%u) late\n",
+-					 req->mbx_src_vfid,
+-					 req->msg.code,
+-					 req->msg.subcode);
+-
+-			hclge_gen_resp_to_vf(vport, req, &resp_msg);
+-		}
++		param.vport = &hdev->vport[req->mbx_src_vfid];
++		param.req = req;
++		hclge_mbx_request_handling(&param);
+ 
+ 		crq->desc[crq->next_to_use].flag = 0;
+ 		hclge_mbx_ring_ptr_move_crq(crq);
+-
+-		/* reinitialize ret after complete the mbx message processing */
+-		ret = 0;
+ 	}
+ 
+ 	/* Write back CMDQ_RQ header pointer, M7 need this pointer */
+-- 
+2.34.1
+
diff --git a/patches/0546-net-hns3-add-support-for-queue-bonding-mode-of-flow-.patch b/patches/0546-net-hns3-add-support-for-queue-bonding-mode-of-flow-.patch
new file mode 100644
index 0000000..cc70a66
--- /dev/null
+++ b/patches/0546-net-hns3-add-support-for-queue-bonding-mode-of-flow-.patch
@@ -0,0 +1,693 @@
+From db6fc1265c32f538007028c888d92f3eba756448 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Wed, 30 Nov 2022 18:23:32 +0800
+Subject: [PATCH 185/283] net: hns3: add support for queue bonding mode of flow
+ director
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+----------------------------------------------------------------------
+
+For device version V3, it supports queue bonding, which can
+identify the tuple information of TCP stream, and create flow
+director rules automatically, in order to keep the tx and rx
+packets are in the same queue pair. The driver set FD_ADD
+field of TX BD for TCP SYN packet, and set FD_DEL filed for
+TCP FIN or RST packet. The hardware create or remove a fd rule
+according to the TX BD, and it also support to age-out a rule
+if not hit for a long time.
+
+The queue bonding mode is default to be disabled, and can be
+enabled/disabled with ethtool priv-flags command.
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |   8 +
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    |   4 +-
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 228 +++++++++++++-----
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  20 +-
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  30 ++-
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |   7 +
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 109 +++++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   4 +
+ 8 files changed, 346 insertions(+), 64 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 2963f3d816fd..07db6d16abbe 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -549,6 +549,10 @@ struct hnae3_ae_dev {
+  *   Check if any cls flower rule exist
+  * dbg_read_cmd
+  *   Execute debugfs read command.
++ * request_flush_qb_config
++ *   Request to update queue bonding configuration
++ * query_fd_qb_state
++ *   Query whether hw queue bonding enabled
+  * set_tx_hwts_info
+  *   Save information for 1588 tx packet
+  * get_rx_hwts
+@@ -741,6 +745,8 @@ struct hnae3_ae_ops {
+ 				      struct ethtool_link_ksettings *cmd);
+ 	int (*set_phy_link_ksettings)(struct hnae3_handle *handle,
+ 				      const struct ethtool_link_ksettings *cmd);
++	void (*request_flush_qb_config)(struct hnae3_handle *handle);
++	bool (*query_fd_qb_state)(struct hnae3_handle *handle);
+ 	bool (*set_tx_hwts_info)(struct hnae3_handle *handle,
+ 				 struct sk_buff *skb);
+ 	void (*get_rx_hwts)(struct hnae3_handle *handle, struct sk_buff *skb,
+@@ -880,6 +886,8 @@ struct hnae3_unic_private_info {
+ 
+ enum hnae3_pflag {
+ 	HNAE3_PFLAG_LIMIT_PROMISC,
++	HNAE3_PFLAG_PUSH_ENABLE,
++	HNAE3_PFLAG_FD_QB_ENABLE,
+ 	HNAE3_PFLAG_MAX
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index f535b7ea39c0..f2a11eaa7161 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -844,7 +844,7 @@ static const struct hns3_dbg_item tx_bd_info_items[] = {
+ 	{ "OT_VLAN_TAG", 3 },
+ 	{ "TV", 5 },
+ 	{ "OLT_VLAN_LEN", 2 },
+-	{ "PAYLEN_OL4CS", 2 },
++	{ "PAYLEN_FDOP_OL4CS", 2 },
+ 	{ "BD_FE_SC_VLD", 2 },
+ 	{ "MSS_HW_CSUM", 0 },
+ };
+@@ -864,7 +864,7 @@ static void hns3_dump_tx_bd_info(struct hns3_nic_priv *priv,
+ 	sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.tv));
+ 	sprintf(result[j++], "%10u",
+ 		le32_to_cpu(desc->tx.ol_type_vlan_len_msec));
+-	sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen));
++	sprintf(result[j++], "%#x", le32_to_cpu(desc->tx.paylen_fdop_ol4cs));
+ 	sprintf(result[j++], "%#x", le16_to_cpu(desc->tx.bdtp_fe_sc_vld_ra_ri));
+ 	sprintf(result[j++], "%5u", le16_to_cpu(desc->tx.mss_hw_csum));
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 66fd6c870cc3..42932052ccaf 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -1235,6 +1235,73 @@ static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
+ 	return 0;
+ }
+ 
++static bool hns3_query_fd_qb_state(struct hnae3_handle *handle)
++{
++	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
++
++	if (!test_bit(HNAE3_PFLAG_FD_QB_ENABLE, &handle->priv_flags))
++		return false;
++
++	if (!ops->query_fd_qb_state)
++		return false;
++
++	return ops->query_fd_qb_state(handle);
++}
++
++/* fd_op is the field of tx bd indicates hw whether to add or delete
++ * a qb rule or do nothing.
++ */
++static u8 hns3_fd_qb_handle(struct hns3_enet_ring *ring, struct sk_buff *skb)
++{
++	struct hnae3_handle *handle = ring->tqp->handle;
++	union l4_hdr_info l4;
++	union l3_hdr_info l3;
++	u8 l4_proto_tmp = 0;
++	__be16 frag_off;
++	u8 ip_version;
++	u8 fd_op = 0;
++
++	if (!hns3_query_fd_qb_state(handle))
++		return 0;
++
++	if (skb->encapsulation) {
++		ip_version = inner_ip_hdr(skb)->version;
++		l3.hdr = skb_inner_network_header(skb);
++		l4.hdr = skb_inner_transport_header(skb);
++	} else {
++		ip_version = ip_hdr(skb)->version;
++		l3.hdr = skb_network_header(skb);
++		l4.hdr = skb_transport_header(skb);
++	}
++
++	if (ip_version == IP_VERSION_IPV6) {
++		unsigned char *exthdr;
++
++		exthdr = l3.hdr + sizeof(*l3.v6);
++		l4_proto_tmp = l3.v6->nexthdr;
++		if (l4.hdr != exthdr)
++			ipv6_skip_exthdr(skb, exthdr - skb->data,
++					 &l4_proto_tmp, &frag_off);
++	} else if (ip_version == IP_VERSION_IPV4) {
++		l4_proto_tmp = l3.v4->protocol;
++	}
++
++	if (l4_proto_tmp != IPPROTO_TCP)
++		return 0;
++
++	ring->fd_qb_tx_sample++;
++	if (l4.tcp->fin || l4.tcp->rst) {
++		hnae3_set_bit(fd_op, HNS3_TXD_FD_DEL_B, 1);
++		ring->fd_qb_tx_sample = 0;
++	} else if (l4.tcp->syn ||
++		   ring->fd_qb_tx_sample >= HNS3_FD_QB_FORCE_CNT_MAX) {
++		hnae3_set_bit(fd_op, HNS3_TXD_FD_ADD_B, 1);
++		ring->fd_qb_tx_sample = 0;
++	}
++
++	return fd_op;
++}
++
+ /* check if the hardware is capable of checksum offloading */
+ static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
+ {
+@@ -1251,16 +1318,29 @@ static bool hns3_check_hw_tx_csum(struct sk_buff *skb)
+ 	return true;
+ }
+ 
+-static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
+-			      struct sk_buff *skb, struct hns3_desc *desc,
+-			      struct hns3_desc_cb *desc_cb)
++struct hns3_desc_param {
++	u32 paylen_fdop_ol4cs;
++	u32 ol_type_vlan_len_msec;
++	u32 type_cs_vlan_tso;
++	u16 mss_hw_csum;
++	u16 inner_vtag;
++	u16 out_vtag;
++};
++
++static void hns3_init_desc_data(struct sk_buff *skb, struct hns3_desc_param *pa)
++{
++	pa->paylen_fdop_ol4cs = skb->len;
++	pa->ol_type_vlan_len_msec = 0;
++	pa->type_cs_vlan_tso = 0;
++	pa->mss_hw_csum = 0;
++	pa->inner_vtag = 0;
++	pa->out_vtag = 0;
++}
++
++static int hns3_handle_vlan_info(struct hns3_enet_ring *ring,
++				 struct sk_buff *skb,
++				 struct hns3_desc_param *param)
+ {
+-	u32 ol_type_vlan_len_msec = 0;
+-	u32 type_cs_vlan_tso = 0;
+-	u32 paylen = skb->len;
+-	u16 mss_hw_csum = 0;
+-	u16 inner_vtag = 0;
+-	u16 out_vtag = 0;
+ 	int ret;
+ 
+ 	ret = hns3_handle_vtags(ring, skb);
+@@ -1270,73 +1350,97 @@ static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
+ 		u64_stats_update_end(&ring->syncp);
+ 		return ret;
+ 	} else if (ret == HNS3_INNER_VLAN_TAG) {
+-		inner_vtag = skb_vlan_tag_get(skb);
+-		inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
++		param->inner_vtag = skb_vlan_tag_get(skb);
++		param->inner_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
+ 				VLAN_PRIO_MASK;
+-		hns3_set_field(type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
++		hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_VLAN_B, 1);
+ 	} else if (ret == HNS3_OUTER_VLAN_TAG) {
+-		out_vtag = skb_vlan_tag_get(skb);
+-		out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
++		param->out_vtag = skb_vlan_tag_get(skb);
++		param->out_vtag |= (skb->priority << VLAN_PRIO_SHIFT) &
+ 				VLAN_PRIO_MASK;
+-		hns3_set_field(ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
++		hns3_set_field(param->ol_type_vlan_len_msec, HNS3_TXD_OVLAN_B,
+ 			       1);
+ 	}
++	return 0;
++}
++
++static int hns3_handle_csum_partial(struct hns3_enet_ring *ring,
++				    struct sk_buff *skb,
++				    struct hns3_desc_cb *desc_cb,
++				    struct hns3_desc_param *param)
++{
++	u8 ol4_proto, il4_proto;
++	int ret;
++
++	if (hns3_check_hw_tx_csum(skb)) {
++		/* set checksum start and offset, defined in 2 Bytes */
++		hns3_set_field(param->type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
++			       skb_checksum_start_offset(skb) >> 1);
++		hns3_set_field(param->ol_type_vlan_len_msec,
++			       HNS3_TXD_CSUM_OFFSET_S,
++			       skb->csum_offset >> 1);
++		param->mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
++		return 0;
++	}
+ 
+-	desc_cb->send_bytes = skb->len;
++	skb_reset_mac_len(skb);
+ 
+-	if (skb->ip_summed == CHECKSUM_PARTIAL) {
+-		u8 ol4_proto, il4_proto;
+-
+-		if (hns3_check_hw_tx_csum(skb)) {
+-			/* set checksum start and offset, defined in 2 Bytes */
+-			hns3_set_field(type_cs_vlan_tso, HNS3_TXD_CSUM_START_S,
+-				       skb_checksum_start_offset(skb) >> 1);
+-			hns3_set_field(ol_type_vlan_len_msec,
+-				       HNS3_TXD_CSUM_OFFSET_S,
+-				       skb->csum_offset >> 1);
+-			mss_hw_csum |= BIT(HNS3_TXD_HW_CS_B);
+-			goto out_hw_tx_csum;
+-		}
++	ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
++	if (unlikely(ret < 0)) {
++		hns3_ring_stats_update(ring, tx_l4_proto_err);
++		return ret;
++	}
+ 
+-		skb_reset_mac_len(skb);
++	ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
++			      &param->type_cs_vlan_tso,
++			      &param->ol_type_vlan_len_msec);
++	if (unlikely(ret < 0)) {
++		hns3_ring_stats_update(ring, tx_l2l3l4_err);
++		return ret;
++	}
+ 
+-		ret = hns3_get_l4_protocol(skb, &ol4_proto, &il4_proto);
+-		if (unlikely(ret < 0)) {
+-			u64_stats_update_begin(&ring->syncp);
+-			ring->stats.tx_l4_proto_err++;
+-			u64_stats_update_end(&ring->syncp);
+-			return ret;
+-		}
++	ret = hns3_set_tso(skb, &param->paylen_fdop_ol4cs, &param->mss_hw_csum,
++			   &param->type_cs_vlan_tso, &desc_cb->send_bytes);
++	if (unlikely(ret < 0)) {
++		hns3_ring_stats_update(ring, tx_tso_err);
++		return ret;
++	}
++	return 0;
++}
+ 
+-		ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
+-				      &type_cs_vlan_tso,
+-				      &ol_type_vlan_len_msec);
+-		if (unlikely(ret < 0)) {
+-			u64_stats_update_begin(&ring->syncp);
+-			ring->stats.tx_l2l3l4_err++;
+-			u64_stats_update_end(&ring->syncp);
+-			return ret;
+-		}
++static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
++			      struct sk_buff *skb, struct hns3_desc *desc,
++			      struct hns3_desc_cb *desc_cb)
++{
++	struct hns3_desc_param param;
++	u8 fd_op;
++	int ret;
+ 
+-		ret = hns3_set_tso(skb, &paylen, &mss_hw_csum,
+-				   &type_cs_vlan_tso, &desc_cb->send_bytes);
+-		if (unlikely(ret < 0)) {
+-			u64_stats_update_begin(&ring->syncp);
+-			ring->stats.tx_tso_err++;
+-			u64_stats_update_end(&ring->syncp);
++	hns3_init_desc_data(skb, &param);
++	ret = hns3_handle_vlan_info(ring, skb, &param);
++	if (unlikely(ret < 0))
++		return ret;
++
++	desc_cb->send_bytes = skb->len;
++
++	if (skb->ip_summed == CHECKSUM_PARTIAL) {
++		ret = hns3_handle_csum_partial(ring, skb, desc_cb, &param);
++		if (ret)
+ 			return ret;
+-		}
+ 	}
+ 
+-out_hw_tx_csum:
++	fd_op = hns3_fd_qb_handle(ring, skb);
++	hnae3_set_field(param.paylen_fdop_ol4cs, HNS3_TXD_FD_OP_M,
++			HNS3_TXD_FD_OP_S, fd_op);
++
+ 	/* Set txbd */
+ 	desc->tx.ol_type_vlan_len_msec =
+-		cpu_to_le32(ol_type_vlan_len_msec);
+-	desc->tx.type_cs_vlan_tso_len = cpu_to_le32(type_cs_vlan_tso);
+-	desc->tx.paylen = cpu_to_le32(paylen);
+-	desc->tx.mss_hw_csum = cpu_to_le16(mss_hw_csum);
+-	desc->tx.vlan_tag = cpu_to_le16(inner_vtag);
+-	desc->tx.outer_vlan_tag = cpu_to_le16(out_vtag);
++		cpu_to_le32(param.ol_type_vlan_len_msec);
++	desc->tx.type_cs_vlan_tso_len = cpu_to_le32(param.type_cs_vlan_tso);
++	desc->tx.paylen_fdop_ol4cs = cpu_to_le32(param.paylen_fdop_ol4cs);
++	desc->tx.mss_hw_csum = cpu_to_le16(param.mss_hw_csum);
++	desc->tx.vlan_tag = cpu_to_le16(param.inner_vtag);
++	desc->tx.outer_vlan_tag = cpu_to_le16(param.out_vtag);
+ 
+ 	return 0;
+ }
+@@ -4766,11 +4870,15 @@ static void hns3_state_init(struct hnae3_handle *handle)
+ 
+ 	if (hnae3_ae_dev_rxd_adv_layout_supported(ae_dev))
+ 		set_bit(HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE, &priv->state);
++
++	if (test_bit(HNAE3_DEV_SUPPORT_QB_B, ae_dev->caps))
++		set_bit(HNAE3_PFLAG_FD_QB_ENABLE, &handle->supported_pflags);
+ }
+ 
+ static int hns3_client_init(struct hnae3_handle *handle)
+ {
+ 	struct pci_dev *pdev = handle->pdev;
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
+ 	u16 alloc_tqps, max_rss_size;
+ 	struct hns3_nic_priv *priv;
+ 	struct net_device *netdev;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index f2d5adb54cdc..b71d06ab6dba 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -174,6 +174,13 @@ enum hns3_nic_state {
+ #define HNS3_TXD_DECTTL_S			12
+ #define HNS3_TXD_DECTTL_M			(0xf << HNS3_TXD_DECTTL_S)
+ 
++#define HNS3_TXD_FD_ADD_B			1
++#define HNS3_TXD_FD_DEL_B			0
++#define HNS3_TXD_FD_OP_M			GENMASK(21, 20)
++#define HNS3_TXD_FD_OP_S			20
++
++#define HNS3_TXD_OL4CS_B			22
++
+ #define HNS3_TXD_MSS_S				0
+ #define HNS3_TXD_MSS_M				(0x3fff << HNS3_TXD_MSS_S)
+ #define HNS3_TXD_HW_CS_B			14
+@@ -200,6 +207,14 @@ enum hns3_nic_state {
+ 
+ #define HNS3_RING_EN_B				0
+ 
++#define HNS3_GL0_CQ_MODE_REG			0x20d00
++#define HNS3_GL1_CQ_MODE_REG			0x20d04
++#define HNS3_GL2_CQ_MODE_REG			0x20d08
++#define HNS3_CQ_MODE_EQE			1U
++#define HNS3_CQ_MODE_CQE			0U
++
++#define HNS3_FD_QB_FORCE_CNT_MAX		20
++
+ enum hns3_pkt_l2t_type {
+ 	HNS3_L2_TYPE_UNICAST,
+ 	HNS3_L2_TYPE_MULTICAST,
+@@ -271,7 +286,7 @@ struct __packed hns3_desc {
+ 			};
+ 		};
+ 
+-			__le32 paylen;
++			__le32 paylen_fdop_ol4cs;
+ 			__le16 bdtp_fe_sc_vld_ra_ri;
+ 			__le16 mss_hw_csum;
+ 		} tx;
+@@ -383,6 +398,9 @@ enum hns3_pkt_ol4type {
+ 	HNS3_OL4_TYPE_UNKNOWN
+ };
+ 
++#define IP_VERSION_IPV4		0x4
++#define IP_VERSION_IPV6		0x6
++
+ struct hns3_rx_ptype {
+ 	u32 ptype : 8;
+ 	u32 csum_level : 2;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 568cc9e57c9c..c2c7e94d0467 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -477,8 +477,36 @@ static void hns3_update_limit_promisc_mode(struct net_device *netdev,
+ 	hns3_request_update_promisc_mode(handle);
+ }
+ 
++static void hns3_update_fd_qb_state(struct net_device *netdev, bool enable)
++{
++	struct hnae3_handle *handle = hns3_get_handle(netdev);
++
++	if (!handle->ae_algo->ops->request_flush_qb_config)
++		return;
++
++	handle->ae_algo->ops->request_flush_qb_config(handle);
++}
++
++static void hns3_update_state(struct net_device *netdev,
++			      enum hns3_nic_state state, bool enable)
++{
++	struct hns3_nic_priv *priv = netdev_priv(netdev);
++
++	if (enable)
++		set_bit(state, &priv->state);
++	else
++		clear_bit(state, &priv->state);
++}
++
++static void hns3_update_push_state(struct net_device *netdev, bool enable)
++{
++	hns3_update_state(netdev, HNS3_NIC_STATE_TX_PUSH_ENABLE, enable);
++}
++
+ static const struct hns3_pflag_desc hns3_priv_flags[HNAE3_PFLAG_MAX] = {
+-	{ "limit_promisc",	hns3_update_limit_promisc_mode }
++	{ "limit_promisc",	hns3_update_limit_promisc_mode },
++	{ "tx_push_enable",	hns3_update_push_state },
++	{ "qb_enable",		hns3_update_fd_qb_state },
+ };
+ 
+ static int hns3_get_sset_count(struct net_device *netdev, int stringset)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 234647cd6a4c..d06307c0199e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -245,6 +245,7 @@ enum hclge_opcode_type {
+ 	HCLGE_OPC_FD_AD_OP		= 0x1204,
+ 	HCLGE_OPC_FD_CNT_OP		= 0x1205,
+ 	HCLGE_OPC_FD_USER_DEF_OP	= 0x1207,
++	HCLGE_OPC_FD_QB_CTRL		= 0x1210,
+ 
+ 	/* MDIO command */
+ 	HCLGE_OPC_MDIO_CONFIG		= 0x1900,
+@@ -1108,6 +1109,12 @@ struct hclge_fd_ad_cnt_read_cmd {
+ 	u8 rsv2[8];
+ };
+ 
++struct hclge_fd_qb_cfg_cmd {
++	u8 en;
++	u8 vf_id;
++	u8 rsv[22];
++};
++
+ #define HCLGE_FD_USER_DEF_OFT_S		0
+ #define HCLGE_FD_USER_DEF_OFT_M		GENMASK(14, 0)
+ #define HCLGE_FD_USER_DEF_EN_B		15
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 14e70efd44c8..5fcae2b54ac7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -4540,6 +4540,95 @@ static void hclge_update_vport_alive(struct hclge_dev *hdev)
+ 	}
+ }
+ 
++static int hclge_set_fd_qb(struct hclge_dev *hdev, u8 vf_id, bool enable)
++{
++	struct hclge_fd_qb_cfg_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_QB_CTRL, false);
++	req = (struct hclge_fd_qb_cfg_cmd *)desc.data;
++	req->en = enable;
++	req->vf_id = vf_id;
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to %s qb config for vport %u, ret = %d.\n",
++			enable ? "enable" : "disable", vf_id, ret);
++	return ret;
++}
++
++static int hclge_sync_pf_qb_mode(struct hclge_dev *hdev)
++{
++	struct hclge_vport *vport = &hdev->vport[0];
++	struct hnae3_handle *handle = &vport->nic;
++	bool request_enable = true;
++	int ret;
++
++	if (!test_and_clear_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state))
++		return 0;
++
++	spin_lock_bh(&hdev->fd_rule_lock);
++	if (hdev->fd_active_type == HCLGE_FD_EP_ACTIVE ||
++	    hdev->fd_active_type == HCLGE_FD_TC_FLOWER_ACTIVE ||
++	    !test_bit(HNAE3_PFLAG_FD_QB_ENABLE, &handle->priv_flags))
++		request_enable = false;
++
++	if (request_enable ==
++		test_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state)) {
++		spin_unlock_bh(&hdev->fd_rule_lock);
++		return 0;
++	}
++
++	if (request_enable)
++		hclge_clear_arfs_rules(handle);
++
++	ret = hclge_set_fd_qb(hdev, vport->vport_id, request_enable);
++	if (!ret) {
++		if (request_enable) {
++			set_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state);
++			hdev->fd_active_type = HCLGE_FD_QB_ACTIVE;
++		} else {
++			clear_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state);
++			hdev->fd_active_type = HCLGE_FD_RULE_NONE;
++		}
++	} else {
++		set_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state);
++	}
++	spin_unlock_bh(&hdev->fd_rule_lock);
++
++	return ret;
++}
++
++static int hclge_disable_fd_qb_mode(struct hclge_dev *hdev)
++{
++	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
++	int ret;
++
++	if (!test_bit(HNAE3_DEV_SUPPORT_QB_B, ae_dev->caps) ||
++	    !test_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state))
++		return 0;
++
++	ret = hclge_set_fd_qb(hdev, 0, false);
++	if (ret)
++		return ret;
++
++	clear_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state);
++
++	return 0;
++}
++
++static void hclge_sync_fd_qb_mode(struct hclge_dev *hdev)
++{
++	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
++
++	if (!test_bit(HNAE3_DEV_SUPPORT_QB_B, ae_dev->caps))
++		return;
++
++	hclge_sync_pf_qb_mode(hdev);
++}
++
+ static void hclge_periodic_service_task(struct hclge_dev *hdev)
+ {
+ 	unsigned long delta = round_jiffies_relative(HZ);
+@@ -4553,6 +4642,7 @@ static void hclge_periodic_service_task(struct hclge_dev *hdev)
+ 	hclge_update_link_status(hdev);
+ 	hclge_sync_mac_table(hdev);
+ 	hclge_sync_promisc_mode(hdev);
++	hclge_sync_fd_qb_mode(hdev);
+ 
+ 	if (time_is_after_jiffies(hdev->last_serv_processed + HZ)) {
+ 		delta = jiffies - hdev->last_serv_processed;
+@@ -5456,6 +5546,21 @@ static void hclge_request_update_promisc_mode(struct hnae3_handle *handle)
+ 	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
+ }
+ 
++static bool hclge_query_fd_qb_state(struct hnae3_handle *handle)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_dev *hdev = vport->back;
++
++	return test_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state);
++}
++
++static void hclge_flush_qb_config(struct hnae3_handle *handle)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++
++	set_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state);
++}
++
+ static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
+ {
+ 	struct hclge_get_fd_mode_cmd *req;
+@@ -7650,6 +7755,7 @@ int hclge_vport_start(struct hclge_vport *vport)
+ 
+ 	set_bit(HCLGE_VPORT_STATE_INITED, &vport->state);
+ 	set_bit(HCLGE_VPORT_STATE_ALIVE, &vport->state);
++	set_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state);
+ 	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
+ 	vport->last_active_jiffies = jiffies;
+ 	vport->need_notify = 0;
+@@ -9701,6 +9807,7 @@ static void hclge_restore_hw_table(struct hclge_dev *hdev)
+ 	hclge_restore_vport_port_base_vlan_config(hdev);
+ 	hclge_restore_vport_vlan_table(vport);
+ 	set_bit(HCLGE_STATE_FD_USER_DEF_CHANGED, &hdev->state);
++	clear_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state);
+ 	hclge_restore_fd_entries(handle);
+ }
+ 
+@@ -12391,6 +12498,8 @@ struct hnae3_ae_ops hclge_ops = {
+ 	.put_vector = hclge_put_vector,
+ 	.set_promisc_mode = hclge_set_promisc_mode,
+ 	.request_update_promisc_mode = hclge_request_update_promisc_mode,
++	.request_flush_qb_config = hclge_flush_qb_config,
++	.query_fd_qb_state = hclge_query_fd_qb_state,
+ 	.set_loopback = hclge_set_loopback,
+ 	.start = hclge_ae_start,
+ 	.stop = hclge_ae_stop,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index b7b4d922711e..65c7b8a534aa 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -242,6 +242,7 @@ enum HCLGE_DEV_STATE {
+ 	HCLGE_STATE_FD_TBL_CHANGED,
+ 	HCLGE_STATE_FD_CLEAR_ALL,
+ 	HCLGE_STATE_FD_USER_DEF_CHANGED,
++	HCLGE_STATE_HW_QB_ENABLE,
+ 	HCLGE_STATE_PTP_EN,
+ 	HCLGE_STATE_PTP_TX_HANDLING,
+ 	HCLGE_STATE_MAX
+@@ -636,6 +637,8 @@ enum HCLGE_FD_ACTIVE_RULE_TYPE {
+ 	HCLGE_FD_RULE_NONE,
+ 	HCLGE_FD_ARFS_ACTIVE,
+ 	HCLGE_FD_EP_ACTIVE,
++	HCLGE_FD_TC_FLOWER_ACTIVE,
++	HCLGE_FD_QB_ACTIVE,
+ };
+ 
+ enum HCLGE_FD_PACKET_TYPE {
+@@ -971,6 +974,7 @@ struct hclge_rss_tuple_cfg {
+ enum HCLGE_VPORT_STATE {
+ 	HCLGE_VPORT_STATE_ALIVE,
+ 	HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
++	HCLGE_VPORT_STATE_QB_CHANGE,
+ 	HCLGE_VPORT_STATE_PROMISC_CHANGE,
+ 	HCLGE_VPORT_STATE_VLAN_FLTR_CHANGE,
+ 	HCLGE_VPORT_STATE_INITED,
+-- 
+2.34.1
+
diff --git a/patches/0547-net-hns3-add-queue-bonding-mode-support-for-VF.patch b/patches/0547-net-hns3-add-queue-bonding-mode-support-for-VF.patch
new file mode 100644
index 0000000..3c83511
--- /dev/null
+++ b/patches/0547-net-hns3-add-queue-bonding-mode-support-for-VF.patch
@@ -0,0 +1,412 @@
+From 274e8e310c46db5cf2e04f41960adf1696b5374b Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Wed, 30 Nov 2022 18:23:33 +0800
+Subject: [PATCH 186/283] net: hns3: add queue bonding mode support for VF
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+----------------------------------------------------------------------
+
+For device version V3, the hardware supports queue bonding
+mode. VF can not enable queue bond mode unless PF enables it.
+So VF needs to query whether PF support queue bonding mode
+when initializing, and query whether PF enables queue bonding
+mode periodically. For the resource limited, to avoid a VF
+occupy to many FD rule space, only trust VF is allowed to enable
+queue bonding mode.
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+---
+ .../net/ethernet/hisilicon/hns3/hclge_mbx.h   |  6 ++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 50 ++++++++++++-
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  2 +
+ .../hisilicon/hns3/hns3pf/hclge_mbx.c         | 37 ++++++++++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 74 +++++++++++++++++++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.h      |  8 ++
+ .../hisilicon/hns3/hns3vf/hclgevf_mbx.c       | 17 +++++
+ 7 files changed, 193 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
+index 05a1b789c9ab..cb6e3c40471a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
+@@ -79,6 +79,12 @@ enum hclge_mbx_tbl_cfg_subcode {
+ 	HCLGE_MBX_VPORT_LIST_CLEAR,
+ };
+ 
++enum hclge_mbx_qb_cfg_subcode {
++	HCLGE_MBX_QB_CHECK_CAPS = 0,	/* query whether support qb */
++	HCLGE_MBX_QB_ENABLE,		/* request pf enable qb */
++	HCLGE_MBX_QB_GET_STATE		/* query whether qb enabled */
++};
++
+ #define HCLGE_MBX_MAX_MSG_SIZE	14
+ #define HCLGE_MBX_MAX_RESP_DATA_SIZE	8U
+ #define HCLGE_MBX_MAX_RING_CHAIN_PARAM_NUM	4
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 5fcae2b54ac7..c6bebf2a9e31 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -4565,6 +4565,7 @@ static int hclge_sync_pf_qb_mode(struct hclge_dev *hdev)
+ 	struct hnae3_handle *handle = &vport->nic;
+ 	bool request_enable = true;
+ 	int ret;
++	u16 i;
+ 
+ 	if (!test_and_clear_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state))
+ 		return 0;
+@@ -4593,6 +4594,11 @@ static int hclge_sync_pf_qb_mode(struct hclge_dev *hdev)
+ 			clear_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state);
+ 			hdev->fd_active_type = HCLGE_FD_RULE_NONE;
+ 		}
++
++		for (i = 1; i < hdev->num_alloc_vport; i++) {
++			vport = &hdev->vport[i];
++			set_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state);
++		}
+ 	} else {
+ 		set_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state);
+ 	}
+@@ -4601,10 +4607,33 @@ static int hclge_sync_pf_qb_mode(struct hclge_dev *hdev)
+ 	return ret;
+ }
+ 
++static int hclge_sync_vf_qb_mode(struct hclge_vport *vport)
++{
++	struct hclge_dev *hdev = vport->back;
++	bool request_enable = false;
++	int ret;
++
++	if (!test_and_clear_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state))
++		return 0;
++
++	if (vport->vf_info.trusted && vport->vf_info.request_qb_en &&
++	    test_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state))
++		request_enable = true;
++
++	ret = hclge_set_fd_qb(hdev, vport->vport_id, request_enable);
++	if (ret)
++		set_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state);
++	vport->vf_info.qb_en = request_enable ? 1 : 0;
++
++	return ret;
++}
++
+ static int hclge_disable_fd_qb_mode(struct hclge_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
++	struct hclge_vport *vport;
+ 	int ret;
++	u16 i;
+ 
+ 	if (!test_bit(HNAE3_DEV_SUPPORT_QB_B, ae_dev->caps) ||
+ 	    !test_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state))
+@@ -4616,17 +4645,35 @@ static int hclge_disable_fd_qb_mode(struct hclge_dev *hdev)
+ 
+ 	clear_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state);
+ 
++	for (i = 1; i < hdev->num_alloc_vport; i++) {
++		vport = &hdev->vport[i];
++		set_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state);
++	}
++
+ 	return 0;
+ }
+ 
+ static void hclge_sync_fd_qb_mode(struct hclge_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
++	struct hclge_vport *vport;
++	int ret;
++	u16 i;
+ 
+ 	if (!test_bit(HNAE3_DEV_SUPPORT_QB_B, ae_dev->caps))
+ 		return;
+ 
+-	hclge_sync_pf_qb_mode(hdev);
++	ret = hclge_sync_pf_qb_mode(hdev);
++	if (ret)
++		return;
++
++	for (i = 1; i < hdev->num_alloc_vport; i++) {
++		vport = &hdev->vport[i];
++
++		ret = hclge_sync_vf_qb_mode(vport);
++		if (ret)
++			return;
++	}
+ }
+ 
+ static void hclge_periodic_service_task(struct hclge_dev *hdev)
+@@ -11392,6 +11439,7 @@ static int hclge_set_vf_trust(struct hnae3_handle *handle, int vf, bool enable)
+ 
+ 	vport->vf_info.trusted = new_trusted;
+ 
++	set_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state);
+ 	set_bit(HCLGE_VPORT_STATE_PROMISC_CHANGE, &vport->state);
+ 	hclge_task_schedule(hdev, 0);
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 65c7b8a534aa..4924aaad757d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -1005,6 +1005,8 @@ struct hclge_vf_info {
+ 	u32 spoofchk;
+ 	u32 max_tx_rate;
+ 	u32 trusted;
++	u8 request_qb_en;
++	u8 qb_en;
+ 	u8 request_uc_en;
+ 	u8 request_mc_en;
+ 	u8 request_bc_en;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+index ec84f81fff92..305f11c854bf 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+@@ -822,6 +822,36 @@ static void hclge_handle_vf_tbl(struct hclge_vport *vport,
+ 	}
+ }
+ 
++static void hclge_handle_vf_qb(struct hclge_vport *vport,
++			       struct hclge_mbx_vf_to_pf_cmd *mbx_req,
++			       struct hclge_respond_to_vf_msg *resp_msg)
++{
++	struct hclge_dev *hdev = vport->back;
++
++	if (mbx_req->msg.subcode == HCLGE_MBX_QB_CHECK_CAPS) {
++		struct hnae3_handle *handle = &hdev->vport[0].nic;
++
++		resp_msg->data[0] = test_bit(HNAE3_PFLAG_FD_QB_ENABLE,
++					     &handle->supported_pflags);
++		resp_msg->len = sizeof(u8);
++	} else if (mbx_req->msg.subcode == HCLGE_MBX_QB_ENABLE) {
++		vport->vf_info.request_qb_en = mbx_req->msg.data[0];
++		set_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state);
++	} else if (mbx_req->msg.subcode == HCLGE_MBX_QB_GET_STATE) {
++		u16 msg_data = vport->vf_info.qb_en;
++		int ret;
++
++		ret = hclge_send_mbx_msg(vport, (u8 *)&msg_data,
++					 sizeof(msg_data),
++					 HCLGE_MBX_PUSH_QB_STATE,
++					 vport->vport_id);
++		if (ret)
++			dev_err(&hdev->pdev->dev,
++				"failed to inform qb state to vport %u, ret = %d\n",
++				vport->vport_id, ret);
++	}
++}
++
+ static int
+ hclge_mbx_map_ring_to_vector_handler(struct hclge_mbx_ops_param *param)
+ {
+@@ -1031,6 +1061,12 @@ static int hclge_mbx_handle_vf_tbl_handler(struct hclge_mbx_ops_param *param)
+ 	return 0;
+ }
+ 
++static int hclge_mbx_handle_vf_qb_handler(struct hclge_mbx_ops_param *param)
++{
++	hclge_handle_vf_qb(param->vport, param->req, param->resp_msg);
++	return 0;
++}
++
+ static const hclge_mbx_ops_fn hclge_mbx_ops_list[HCLGE_MBX_OPCODE_MAX] = {
+ 	[HCLGE_MBX_RESET]   = hclge_mbx_reset_handler,
+ 	[HCLGE_MBX_SET_UNICAST] = hclge_mbx_set_unicast_handler,
+@@ -1055,6 +1091,7 @@ static const hclge_mbx_ops_fn hclge_mbx_ops_list[HCLGE_MBX_OPCODE_MAX] = {
+ 	[HCLGE_MBX_VF_UNINIT] = hclge_mbx_vf_uninit_handler,
+ 	[HCLGE_MBX_HANDLE_VF_TBL] = hclge_mbx_handle_vf_tbl_handler,
+ 	[HCLGE_MBX_GET_RING_VECTOR_MAP] = hclge_mbx_get_ring_vector_map_handler,
++	[HCLGE_MBX_SET_QB] = hclge_mbx_handle_vf_qb_handler,
+ 	[HCLGE_MBX_GET_VF_FLR_STATUS] = hclge_mbx_get_vf_flr_status_handler,
+ 	[HCLGE_MBX_PUSH_LINK_STATUS] = hclge_mbx_push_link_status_handler,
+ 	[HCLGE_MBX_NCSI_ERROR] = hclge_mbx_ncsi_error_handler,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index d03d6c22b051..8bd2d8019425 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -472,6 +472,74 @@ static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
+ 	return 0;
+ }
+ 
++static void hclgevf_update_fd_qb_state(struct hclgevf_dev *hdev)
++{
++	struct hnae3_handle *handle = &hdev->nic;
++	struct hclge_vf_to_pf_msg send_msg;
++	int ret;
++
++	if (!hdev->qb_cfg.pf_support_qb ||
++	    !test_bit(HNAE3_PFLAG_FD_QB_ENABLE, &handle->priv_flags))
++		return;
++
++	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_QB,
++			       HCLGE_MBX_QB_GET_STATE);
++	ret = hclgevf_send_mbx_msg(hdev, &send_msg, false, NULL, 0);
++	if (ret)
++		dev_err(&hdev->pdev->dev, "failed to get qb state, ret = %d",
++			ret);
++}
++
++static void hclgevf_get_pf_qb_caps(struct hclgevf_dev *hdev)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	struct hclge_vf_to_pf_msg send_msg;
++	u8 resp_msg;
++	int ret;
++
++	if (!test_bit(HNAE3_DEV_SUPPORT_QB_B, ae_dev->caps))
++		return;
++
++	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_QB,
++			       HCLGE_MBX_QB_CHECK_CAPS);
++	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
++				   sizeof(resp_msg));
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get qb caps from PF, ret = %d", ret);
++		return;
++	}
++
++	hdev->qb_cfg.pf_support_qb = resp_msg > 0;
++}
++
++static void hclgevf_set_fd_qb(struct hnae3_handle *handle)
++{
++#define HCLGEVF_QB_MBX_STATE_OFFSET	0
++
++	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
++	struct hclge_vf_to_pf_msg send_msg;
++	u8 resp_msg;
++	int ret;
++
++	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_SET_QB,
++			       HCLGE_MBX_QB_ENABLE);
++	send_msg.data[HCLGEVF_QB_MBX_STATE_OFFSET] =
++		test_bit(HNAE3_PFLAG_FD_QB_ENABLE, &handle->priv_flags) ? 1 : 0;
++	ret = hclgevf_send_mbx_msg(hdev, &send_msg, true, &resp_msg,
++				   sizeof(resp_msg));
++	if (ret)
++		dev_err(&hdev->pdev->dev, "failed to set qb state, ret = %d",
++			ret);
++}
++
++static bool hclgevf_query_fd_qb_state(struct hnae3_handle *handle)
++{
++	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
++
++	return hdev->qb_cfg.hw_qb_en;
++}
++
+ static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
+ {
+ 	struct hclge_vf_to_pf_msg send_msg;
+@@ -2328,6 +2396,8 @@ static void hclgevf_periodic_service_task(struct hclgevf_dev *hdev)
+ 
+ 	hclgevf_sync_promisc_mode(hdev);
+ 
++	hclgevf_update_fd_qb_state(hdev);
++
+ 	hdev->last_serv_processed = jiffies;
+ 
+ out:
+@@ -3328,6 +3398,8 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
+ 		goto err_config;
+ 	}
+ 
++	hclgevf_get_pf_qb_caps(hdev);
++
+ 	set_bit(HCLGEVF_STATE_SERVICE_INITED, &hdev->state);
+ 
+ 	hdev->last_reset_time = jiffies;
+@@ -3769,6 +3841,8 @@ static const struct hnae3_ae_ops hclgevf_ops = {
+ 	.get_link_mode = hclgevf_get_link_mode,
+ 	.set_promisc_mode = hclgevf_set_promisc_mode,
+ 	.request_update_promisc_mode = hclgevf_request_update_promisc_mode,
++	.request_flush_qb_config = hclgevf_set_fd_qb,
++	.query_fd_qb_state = hclgevf_query_fd_qb_state,
+ };
+ 
+ static struct hnae3_ae_algo ae_algovf = {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index 97e9834c6de5..a8366fbf394a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -272,6 +272,11 @@ struct hclgevf_mac_table_cfg {
+ 	struct list_head mc_mac_list;
+ };
+ 
++struct hclgevf_qb_cfg {
++	bool pf_support_qb;
++	bool hw_qb_en;
++};
++
+ struct hclgevf_dev {
+ 	struct pci_dev *pdev;
+ 	struct hnae3_ae_dev *ae_dev;
+@@ -338,6 +343,9 @@ struct hclgevf_dev {
+ 	u32 flag;
+ 	unsigned long serv_processed_cnt;
+ 	unsigned long last_serv_processed;
++
++	struct hclgevf_qb_cfg qb_cfg;
++	struct devlink *devlink;
+ };
+ 
+ static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+index 5e43289d714a..ccd45b3c532d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+@@ -281,6 +281,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
+ 		case HCLGE_MBX_LINK_STAT_MODE:
+ 		case HCLGE_MBX_PUSH_VLAN_INFO:
+ 		case HCLGE_MBX_PUSH_PROMISC_INFO:
++		case HCLGE_MBX_PUSH_QB_STATE:
+ 			hclgevf_handle_mbx_msg(hdev, req);
+ 			break;
+ 		default:
+@@ -306,6 +307,19 @@ static void hclgevf_parse_promisc_info(struct hclgevf_dev *hdev,
+ 			 "Promisc mode is closed by host for being untrusted.\n");
+ }
+ 
++static void hclgevf_parse_qb_info(struct hclgevf_dev *hdev, u16 qb_state)
++{
++#define HCLGEVF_HW_QB_ON       1
++#define HCLGEVF_HW_QB_OFF      0
++
++	if (qb_state > HCLGEVF_HW_QB_ON) {
++		dev_warn(&hdev->pdev->dev, "Invalid state, ignored.\n");
++		return;
++	}
++
++	hdev->qb_cfg.hw_qb_en = qb_state > HCLGEVF_HW_QB_OFF;
++}
++
+ void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev)
+ {
+ 	enum hnae3_reset_type reset_type;
+@@ -375,6 +389,9 @@ void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev)
+ 		case HCLGE_MBX_PUSH_PROMISC_INFO:
+ 			hclgevf_parse_promisc_info(hdev, msg_q[1]);
+ 			break;
++		case HCLGE_MBX_PUSH_QB_STATE:
++			hclgevf_parse_qb_info(hdev, msg_q[1]);
++			break;
+ 		default:
+ 			dev_err(&hdev->pdev->dev,
+ 				"fetched unsupported(%u) message from arq\n",
+-- 
+2.34.1
+
diff --git a/patches/0548-net-hns3-allocate-fd-counter-for-queue-bonding.patch b/patches/0548-net-hns3-allocate-fd-counter-for-queue-bonding.patch
new file mode 100644
index 0000000..db0a93f
--- /dev/null
+++ b/patches/0548-net-hns3-allocate-fd-counter-for-queue-bonding.patch
@@ -0,0 +1,150 @@
+From 8ec2a17ca6273d9586f726876d4de9dc7426d715 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Wed, 30 Nov 2022 18:23:34 +0800
+Subject: [PATCH 187/283] net: hns3: allocate fd counter for queue bonding
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+----------------------------------------------------------------------
+
+For the fd rule of queue bonding is created by hardware
+automatically, the driver needs to specify the fd counter
+for each function, then it's available to query how many
+times the queue bonding fd rules hit.
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         | 13 ++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 64 +++++++++++--------
+ 2 files changed, 52 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index d06307c0199e..71cf6ad71427 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -246,6 +246,7 @@ enum hclge_opcode_type {
+ 	HCLGE_OPC_FD_CNT_OP		= 0x1205,
+ 	HCLGE_OPC_FD_USER_DEF_OP	= 0x1207,
+ 	HCLGE_OPC_FD_QB_CTRL		= 0x1210,
++	HCLGE_OPC_FD_QB_AD_OP		= 0x1211,
+ 
+ 	/* MDIO command */
+ 	HCLGE_OPC_MDIO_CONFIG		= 0x1900,
+@@ -1115,6 +1116,18 @@ struct hclge_fd_qb_cfg_cmd {
+ 	u8 rsv[22];
+ };
+ 
++#define HCLGE_FD_QB_AD_RULE_ID_VLD_B	0
++#define HCLGE_FD_QB_AD_COUNTER_VLD_B	1
++struct hclge_fd_qb_ad_cmd {
++	u8 vf_id;
++	u8 rsv1;
++	u8 ad_sel;
++	u8 rsv2;
++	__le16 hit_rule_id;
++	u8 counter_id;
++	u8 rsv3[17];
++};
++
+ #define HCLGE_FD_USER_DEF_OFT_S		0
+ #define HCLGE_FD_USER_DEF_OFT_M		GENMASK(14, 0)
+ #define HCLGE_FD_USER_DEF_EN_B		15
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index c6bebf2a9e31..970012a36c14 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -4540,6 +4540,40 @@ static void hclge_update_vport_alive(struct hclge_dev *hdev)
+ 	}
+ }
+ 
++static int hclge_set_fd_qb_counter(struct hclge_dev *hdev, u8 vf_id)
++{
++	struct hclge_fd_qb_ad_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_QB_AD_OP, false);
++	req = (struct hclge_fd_qb_ad_cmd *)desc.data;
++	req->vf_id = vf_id;
++	hnae3_set_bit(req->ad_sel, HCLGE_FD_QB_AD_COUNTER_VLD_B, 1);
++	req->counter_id = vf_id % hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1];
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_warn(&hdev->pdev->dev,
++			 "failed to set qb counter for vport %u, ret = %d.\n",
++			 vf_id, ret);
++	return ret;
++}
++
++static void hclge_init_fd_qb_counter(struct hclge_dev *hdev)
++{
++	int ret;
++	u16 i;
++
++	if (!test_bit(HNAE3_DEV_SUPPORT_QB_B, hdev->ae_dev->caps))
++		return;
++
++	for (i = 0; i < hdev->num_alloc_vport; i++) {
++		ret = hclge_set_fd_qb_counter(hdev, i);
++		if (ret)
++			return;
++	}
++}
++
+ static int hclge_set_fd_qb(struct hclge_dev *hdev, u8 vf_id, bool enable)
+ {
+ 	struct hclge_fd_qb_cfg_cmd *req;
+@@ -4628,31 +4662,6 @@ static int hclge_sync_vf_qb_mode(struct hclge_vport *vport)
+ 	return ret;
+ }
+ 
+-static int hclge_disable_fd_qb_mode(struct hclge_dev *hdev)
+-{
+-	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
+-	struct hclge_vport *vport;
+-	int ret;
+-	u16 i;
+-
+-	if (!test_bit(HNAE3_DEV_SUPPORT_QB_B, ae_dev->caps) ||
+-	    !test_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state))
+-		return 0;
+-
+-	ret = hclge_set_fd_qb(hdev, 0, false);
+-	if (ret)
+-		return ret;
+-
+-	clear_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state);
+-
+-	for (i = 1; i < hdev->num_alloc_vport; i++) {
+-		vport = &hdev->vport[i];
+-		set_bit(HCLGE_VPORT_STATE_QB_CHANGE, &vport->state);
+-	}
+-
+-	return 0;
+-}
+-
+ static void hclge_sync_fd_qb_mode(struct hclge_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
+@@ -5743,6 +5752,11 @@ static int hclge_init_fd_config(struct hclge_dev *hdev)
+ 	if (ret)
+ 		return ret;
+ 
++	if (!hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1])
++		hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1] = 1;
++
++	hclge_init_fd_qb_counter(hdev);
++
+ 	return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
+ }
+ 
+-- 
+2.34.1
+
diff --git a/patches/0549-net-hns3-refactor-the-debugfs-for-dumping-FD-tcam.patch b/patches/0549-net-hns3-refactor-the-debugfs-for-dumping-FD-tcam.patch
new file mode 100644
index 0000000..f455bf4
--- /dev/null
+++ b/patches/0549-net-hns3-refactor-the-debugfs-for-dumping-FD-tcam.patch
@@ -0,0 +1,255 @@
+From 4639dc08250c9f77bbbad67f81f3039d4d057519 Mon Sep 17 00:00:00 2001
+From: liaoguojia <liaoguojia@huawei.com>
+Date: Wed, 30 Nov 2022 18:23:36 +0800
+Subject: [PATCH 188/283] net: hns3: refactor the debugfs for dumping FD tcam
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+
+----------------------------------------------------------------------
+
+On version HNAE3_DEVICE_VERSION_V2, the tcam table entry of the FD is
+obtained by traversing the list recorded by the driver.
+
+On version HNAE3_DEVICE_VERSION_V3, a new usage mode of FD is supported,
+called Queue bond mode. In this mode, the hardware automatically creates
+rules and the driver does not record the flow table entry.
+
+So we needs to check the validity of the entry by traversing the entire
+hardware entry to dump out the QB tcam table.
+
+Signed-off-by: liaoguojia <liaoguojia@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |   3 +
+ .../hns3/hns3_common/hclge_comm_cmd.h         |   3 +
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     | 115 +++++++++++++++---
+ 3 files changed, 106 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 07db6d16abbe..f016bf08f297 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -101,6 +101,9 @@ enum HNAE3_DEV_CAP_BITS {
+ 	HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
+ };
+ 
++#define hnae3_ae_dev_fd_supported(ae_dev) \
++		test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps)
++
+ #define hnae3_dev_fd_supported(hdev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps)
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 52fc4b830772..ea30d94c081c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -7,6 +7,9 @@
+ 
+ #include "hnae3.h"
+ 
++#define HCLGE_COMM_CMD_FLAG_IN			BIT(0)
++#define HCLGE_COMM_CMD_FLAG_NEXT		BIT(2)
++#define HCLGE_COMM_CMD_FLAG_WR			BIT(3)
+ #define HCLGE_COMM_CMD_FLAG_NO_INTR		BIT(4)
+ 
+ #define HCLGE_COMM_SEND_SYNC(flag) \
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index 985e6677ea27..63cc42060a31 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -1525,8 +1525,7 @@ static int hclge_dbg_dump_mng_table(struct hclge_dev *hdev, char *buf, int len)
+ #define HCLGE_DBG_TCAM_BUF_SIZE 256
+ 
+ static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, bool sel_x,
+-				  char *tcam_buf,
+-				  struct hclge_dbg_tcam_msg tcam_msg)
++				  char *tcam_buf, u8 stage, u32 loc)
+ {
+ 	struct hclge_fd_tcam_config_1_cmd *req1;
+ 	struct hclge_fd_tcam_config_2_cmd *req2;
+@@ -1546,9 +1545,9 @@ static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, bool sel_x,
+ 	req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
+ 	req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
+ 
+-	req1->stage  = tcam_msg.stage;
++	req1->stage  = stage;
+ 	req1->xy_sel = sel_x ? 1 : 0;
+-	req1->index  = cpu_to_le32(tcam_msg.loc);
++	req1->index  = cpu_to_le32(loc);
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, desc, 3);
+ 	if (ret)
+@@ -1556,7 +1555,7 @@ static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, bool sel_x,
+ 
+ 	pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos,
+ 			 "read result tcam key %s(%u):\n", sel_x ? "x" : "y",
+-			 tcam_msg.loc);
++			 loc);
+ 
+ 	/* tcam_data0 ~ tcam_data1 */
+ 	req = (u32 *)req1->tcam_data;
+@@ -1601,7 +1600,6 @@ static int hclge_dbg_get_rules_location(struct hclge_dev *hdev, u16 *rule_locs)
+ static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len)
+ {
+ 	u32 rule_num = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
+-	struct hclge_dbg_tcam_msg tcam_msg;
+ 	int i, ret, rule_cnt;
+ 	u16 *rule_locs;
+ 	char *tcam_buf;
+@@ -1636,10 +1634,8 @@ static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len)
+ 
+ 	ret = 0;
+ 	for (i = 0; i < rule_cnt; i++) {
+-		tcam_msg.stage = HCLGE_FD_STAGE_1;
+-		tcam_msg.loc = rule_locs[i];
+-
+-		ret = hclge_dbg_fd_tcam_read(hdev, true, tcam_buf, tcam_msg);
++		ret = hclge_dbg_fd_tcam_read(hdev, true, tcam_buf,
++					     HCLGE_FD_STAGE_1, rule_locs[i]);
+ 		if (ret) {
+ 			dev_err(&hdev->pdev->dev,
+ 				"failed to get fd tcam key x, ret = %d\n", ret);
+@@ -1648,7 +1644,8 @@ static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len)
+ 
+ 		pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf);
+ 
+-		ret = hclge_dbg_fd_tcam_read(hdev, false, tcam_buf, tcam_msg);
++		ret = hclge_dbg_fd_tcam_read(hdev, false, tcam_buf,
++					     HCLGE_FD_STAGE_1, rule_locs[i]);
+ 		if (ret) {
+ 			dev_err(&hdev->pdev->dev,
+ 				"failed to get fd tcam key y, ret = %d\n", ret);
+@@ -1664,6 +1661,86 @@ static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len)
+ 	return ret;
+ }
+ 
++static int hclge_query_rules_valid(struct hclge_dev *hdev, u8 stage, u32 loc)
++{
++#define HCLGE_TCAM_SELECTION_X	1
++	struct hclge_fd_tcam_config_1_cmd *req1;
++	struct hclge_fd_tcam_config_2_cmd *req2;
++	struct hclge_fd_tcam_config_3_cmd *req3;
++	struct hclge_desc desc[3];
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, true);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
++	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, true);
++	desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
++	hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, true);
++
++	req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
++	req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
++	req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
++
++	req1->stage = stage;
++	req1->xy_sel = HCLGE_TCAM_SELECTION_X;
++	req1->index = cpu_to_le32(loc);
++
++	ret = hclge_cmd_send(&hdev->hw, desc, 3);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to read tcam status, ret = %d\n", ret);
++		return ret;
++	}
++
++	return req1->entry_vld;
++}
++
++static int hclge_dbg_dump_qb_tcam(struct hclge_dev *hdev, char *buf, int len)
++{
++	char *tcam_buf;
++	int pos = 0;
++	int ret = 0;
++	int i;
++
++	if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
++		dev_err(&hdev->pdev->dev,
++			"Only FD-supported dev supports dump fd tcam\n");
++		return -EOPNOTSUPP;
++	}
++
++	tcam_buf = kzalloc(HCLGE_DBG_TCAM_BUF_SIZE, GFP_KERNEL);
++	if (!tcam_buf)
++		return -ENOMEM;
++
++	for (i = 0; i < hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; i++) {
++		if (hclge_query_rules_valid(hdev, HCLGE_FD_STAGE_1, i) <= 0)
++			continue;
++
++		ret = hclge_dbg_fd_tcam_read(hdev, true, tcam_buf,
++					     HCLGE_FD_STAGE_1, i);
++		if (ret) {
++			dev_err(&hdev->pdev->dev,
++				"failed to get qb tcam key x, ret = %d\n", ret);
++			goto out;
++		}
++
++		pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf);
++
++		ret = hclge_dbg_fd_tcam_read(hdev, false, tcam_buf,
++					     HCLGE_FD_STAGE_1, i);
++		if (ret) {
++			dev_err(&hdev->pdev->dev,
++				"failed to get qb tcam key y, ret = %d\n", ret);
++			goto out;
++		}
++
++		pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf);
++	}
++
++out:
++	kfree(tcam_buf);
++	return ret;
++}
++
+ static int hclge_dbg_dump_fd_counter(struct hclge_dev *hdev, char *buf, int len)
+ {
+ 	u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */
+@@ -2286,6 +2363,14 @@ static int hclge_dbg_dump_mac_uc(struct hclge_dev *hdev, char *buf, int len)
+ 	return 0;
+ }
+ 
++static int hclge_dbg_dump_tcam(struct hclge_dev *hdev, char *buf, int len)
++{
++	if (test_bit(HCLGE_STATE_HW_QB_ENABLE, &hdev->state))
++		return hclge_dbg_dump_qb_tcam(hdev, buf, len);
++	else
++		return hclge_dbg_dump_fd_tcam(hdev, buf, len);
++};
++
+ static int hclge_dbg_dump_mac_mc(struct hclge_dev *hdev, char *buf, int len)
+ {
+ 	hclge_dbg_dump_mac_list(hdev, buf, len, false);
+@@ -2440,14 +2525,14 @@ static const struct hclge_dbg_func hclge_dbg_cmd_func[] = {
+ 		.cmd = HNAE3_DBG_CMD_REG_DCB,
+ 		.dbg_dump = hclge_dbg_dump_dcb,
+ 	},
+-	{
+-		.cmd = HNAE3_DBG_CMD_FD_TCAM,
+-		.dbg_dump = hclge_dbg_dump_fd_tcam,
+-	},
+ 	{
+ 		.cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS,
+ 		.dbg_dump = hclge_dbg_dump_mac_tnl_status,
+ 	},
++	{
++		.cmd = HNAE3_DBG_CMD_FD_TCAM,
++		.dbg_dump = hclge_dbg_dump_tcam,
++	},
+ 	{
+ 		.cmd = HNAE3_DBG_CMD_SERV_INFO,
+ 		.dbg_dump = hclge_dbg_dump_serv_info,
+-- 
+2.34.1
+
diff --git a/patches/0550-net-hns3-support-wake-on-lan-configuration-and-query.patch b/patches/0550-net-hns3-support-wake-on-lan-configuration-and-query.patch
new file mode 100644
index 0000000..b5fcb6b
--- /dev/null
+++ b/patches/0550-net-hns3-support-wake-on-lan-configuration-and-query.patch
@@ -0,0 +1,815 @@
+From 4d398dd78ebd4841a22a53e3dec54d7eea153cc0 Mon Sep 17 00:00:00 2001
+From: Hao Lan <lanhao@huawei.com>
+Date: Wed, 30 Nov 2022 18:23:57 +0800
+Subject: [PATCH 189/283] net: hns3: support wake on lan configuration and
+ query
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+Implement configuration and query WOL by ethtool and
+added the needed device commands and structures to hns3.
+Add it do not support suspend resume interface.
+
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  29 +++
+ .../hns3/hns3_common/hclge_comm_cmd.c         | 219 +++++++++++++++++-
+ .../hns3/hns3_common/hclge_comm_cmd.h         |  89 +++++--
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  27 +++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  25 ++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 202 ++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  15 +-
+ 7 files changed, 591 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index f016bf08f297..d15038e8bcb5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -99,6 +99,10 @@ enum HNAE3_DEV_CAP_BITS {
+ 	HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
+ 	HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
+ 	HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
++	HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,
++	HNAE3_DEV_SUPPORT_CQ_B,
++	HNAE3_DEV_SUPPORT_LANE_NUM_B,
++	HNAE3_DEV_SUPPORT_WOL_B,
+ };
+ 
+ #define hnae3_ae_dev_fd_supported(ae_dev) \
+@@ -158,6 +162,18 @@ enum HNAE3_DEV_CAP_BITS {
+ #define hnae3_ae_dev_rxd_adv_layout_supported(ae_dev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, (ae_dev)->caps)
+ 
++#define hnae3_ae_dev_mc_mac_mng_supported(ae_dev) \
++	test_bit(HNAE3_DEV_SUPPORT_MC_MAC_MNG_B, (ae_dev)->caps)
++
++#define hnae3_ae_dev_cq_supported(ae_dev) \
++	test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)
++
++#define hnae3_ae_dev_lane_num_supported(ae_dev) \
++	test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)
++
++#define hnae3_ae_dev_wol_supported(ae_dev) \
++	test_bit(HNAE3_DEV_SUPPORT_WOL_B, (ae_dev)->caps)
++
+ enum HNAE3_PF_CAP_BITS {
+ 	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
+ };
+@@ -562,6 +578,12 @@ struct hnae3_ae_dev {
+  *   Get 1588 rx hwstamp
+  * get_ts_info
+  *   Get phc info
++ * clean_vf_config
++ *   Clean residual vf info after disable sriov
++ * get_wol
++ *   Get wake on lan info
++ * set_wol
++ *   Config wake on lan
+  */
+ struct hnae3_ae_ops {
+ 	int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev);
+@@ -758,6 +780,13 @@ struct hnae3_ae_ops {
+ 			   struct ethtool_ts_info *info);
+ 	int (*get_link_diagnosis_info)(struct hnae3_handle *handle,
+ 				       u32 *status_code);
++	void (*clean_vf_config)(struct hnae3_ae_dev *ae_dev, int num_vfs);
++	int (*get_dscp_prio)(struct hnae3_handle *handle, u8 dscp,
++			     u8 *tc_map_mode, u8 *priority);
++	void (*get_wol)(struct hnae3_handle *handle,
++			struct ethtool_wolinfo *wol);
++	int (*set_wol)(struct hnae3_handle *handle,
++		       struct ethtool_wolinfo *wol);
+ /* Notice! If the function is not for test, the definition must before
+  * CONFIG_HNS3_TEST! Because RoCE will use this head file, and it won't
+  * set CONFIG_HNS3_TEST, that may cause RoCE calling the wrong function.
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index 89e999248b9a..a899b4c535dd 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -6,7 +6,224 @@
+ 
+ static bool hclge_is_elem_in_array(const u16 *spec_opcode, u32 size, u16 opcode)
+ {
+-	u32 i;
++	dma_addr_t dma = ring->desc_dma_addr;
++	u32 reg_val;
++
++	if (ring->ring_type == HCLGE_COMM_TYPE_CSQ) {
++		hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG,
++				     lower_32_bits(dma));
++		hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG,
++				     upper_32_bits(dma));
++		reg_val = hclge_comm_read_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
++		reg_val &= HCLGE_COMM_NIC_SW_RST_RDY;
++		reg_val |= ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S;
++		hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);
++		hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG, 0);
++		hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_TAIL_REG, 0);
++	} else {
++		hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG,
++				     lower_32_bits(dma));
++		hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG,
++				     upper_32_bits(dma));
++		reg_val = ring->desc_num >> HCLGE_COMM_NIC_CMQ_DESC_NUM_S;
++		hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_DEPTH_REG, reg_val);
++		hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_HEAD_REG, 0);
++		hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG, 0);
++	}
++}
++
++void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw)
++{
++	hclge_comm_cmd_config_regs(hw, &hw->cmq.csq);
++	hclge_comm_cmd_config_regs(hw, &hw->cmq.crq);
++}
++
++void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
++{
++	desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR |
++				 HCLGE_COMM_CMD_FLAG_IN);
++	if (is_read)
++		desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR);
++	else
++		desc->flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_WR);
++}
++
++static void hclge_comm_set_default_capability(struct hnae3_ae_dev *ae_dev,
++					      bool is_pf)
++{
++	set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);
++	if (is_pf) {
++		set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
++		set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
++		set_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps);
++	}
++}
++
++void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
++				     enum hclge_opcode_type opcode,
++				     bool is_read)
++{
++	memset((void *)desc, 0, sizeof(struct hclge_desc));
++	desc->opcode = cpu_to_le16(opcode);
++	desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR |
++				 HCLGE_COMM_CMD_FLAG_IN);
++
++	if (is_read)
++		desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR);
++}
++
++int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,
++				      struct hclge_comm_hw *hw, bool en)
++{
++	struct hclge_comm_firmware_compat_cmd *req;
++	struct hclge_desc desc;
++	u32 compat = 0;
++
++	hclge_comm_cmd_setup_basic_desc(&desc, HCLGE_OPC_IMP_COMPAT_CFG, false);
++
++	if (en) {
++		req = (struct hclge_comm_firmware_compat_cmd *)desc.data;
++
++		hnae3_set_bit(compat, HCLGE_COMM_LINK_EVENT_REPORT_EN_B, 1);
++		hnae3_set_bit(compat, HCLGE_COMM_NCSI_ERROR_REPORT_EN_B, 1);
++		if (hclge_comm_dev_phy_imp_supported(ae_dev))
++			hnae3_set_bit(compat, HCLGE_COMM_PHY_IMP_EN_B, 1);
++		hnae3_set_bit(compat, HCLGE_COMM_MAC_STATS_EXT_EN_B, 1);
++		hnae3_set_bit(compat, HCLGE_COMM_SYNC_RX_RING_HEAD_EN_B, 1);
++		hnae3_set_bit(compat, HCLGE_COMM_LLRS_FEC_EN_B, 1);
++
++		req->compat = cpu_to_le32(compat);
++	}
++
++	return hclge_comm_cmd_send(hw, &desc, 1);
++}
++
++void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring)
++{
++	int size  = ring->desc_num * sizeof(struct hclge_desc);
++
++	if (!ring->desc)
++		return;
++
++	dma_free_coherent(&ring->pdev->dev, size,
++			  ring->desc, ring->desc_dma_addr);
++	ring->desc = NULL;
++}
++
++static int hclge_comm_alloc_cmd_desc(struct hclge_comm_cmq_ring *ring)
++{
++	int size  = ring->desc_num * sizeof(struct hclge_desc);
++
++	ring->desc = dma_alloc_coherent(&ring->pdev->dev,
++					size, &ring->desc_dma_addr, GFP_KERNEL);
++	if (!ring->desc)
++		return -ENOMEM;
++
++	return 0;
++}
++
++static __le32 hclge_comm_build_api_caps(void)
++{
++	u32 api_caps = 0;
++
++	hnae3_set_bit(api_caps, HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B, 1);
++
++	return cpu_to_le32(api_caps);
++}
++
++static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = {
++	{HCLGE_COMM_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
++	{HCLGE_COMM_CAP_PTP_B, HNAE3_DEV_SUPPORT_PTP_B},
++	{HCLGE_COMM_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
++	{HCLGE_COMM_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
++	{HCLGE_COMM_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
++	{HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
++	{HCLGE_COMM_CAP_FD_FORWARD_TC_B, HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B},
++	{HCLGE_COMM_CAP_FEC_B, HNAE3_DEV_SUPPORT_FEC_B},
++	{HCLGE_COMM_CAP_PAUSE_B, HNAE3_DEV_SUPPORT_PAUSE_B},
++	{HCLGE_COMM_CAP_PHY_IMP_B, HNAE3_DEV_SUPPORT_PHY_IMP_B},
++	{HCLGE_COMM_CAP_QB_B, HNAE3_DEV_SUPPORT_QB_B},
++	{HCLGE_COMM_CAP_TX_PUSH_B, HNAE3_DEV_SUPPORT_TX_PUSH_B},
++	{HCLGE_COMM_CAP_RAS_IMP_B, HNAE3_DEV_SUPPORT_RAS_IMP_B},
++	{HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
++	{HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B,
++	 HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B},
++	{HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B},
++	{HCLGE_COMM_CAP_CQ_B, HNAE3_DEV_SUPPORT_CQ_B},
++	{HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},
++	{HCLGE_COMM_CAP_FD_B, HNAE3_DEV_SUPPORT_FD_B},
++	{HCLGE_COMM_CAP_LANE_NUM_B, HNAE3_DEV_SUPPORT_LANE_NUM_B},
++	{HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},
++};
++
++static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
++	{HCLGE_COMM_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
++	{HCLGE_COMM_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
++	{HCLGE_COMM_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
++	{HCLGE_COMM_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
++	{HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
++	{HCLGE_COMM_CAP_QB_B, HNAE3_DEV_SUPPORT_QB_B},
++	{HCLGE_COMM_CAP_TX_PUSH_B, HNAE3_DEV_SUPPORT_TX_PUSH_B},
++	{HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
++	{HCLGE_COMM_CAP_CQ_B, HNAE3_DEV_SUPPORT_CQ_B},
++	{HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},
++};
++
++static void
++hclge_comm_parse_capability(struct hnae3_ae_dev *ae_dev, bool is_pf,
++			    struct hclge_comm_query_version_cmd *cmd)
++{
++	const struct hclge_comm_caps_bit_map *caps_map =
++				is_pf ? hclge_pf_cmd_caps : hclge_vf_cmd_caps;
++	u32 size = is_pf ? ARRAY_SIZE(hclge_pf_cmd_caps) :
++				ARRAY_SIZE(hclge_vf_cmd_caps);
++	u32 caps, i;
++
++	caps = __le32_to_cpu(cmd->caps[0]);
++	for (i = 0; i < size; i++)
++		if (hnae3_get_bit(caps, caps_map[i].imp_bit))
++			set_bit(caps_map[i].local_bit, ae_dev->caps);
++}
++
++int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type)
++{
++	struct hclge_comm_cmq_ring *ring =
++		(ring_type == HCLGE_COMM_TYPE_CSQ) ? &hw->cmq.csq :
++						     &hw->cmq.crq;
++	int ret;
++
++	ring->ring_type = ring_type;
++
++	ret = hclge_comm_alloc_cmd_desc(ring);
++	if (ret)
++		dev_err(&ring->pdev->dev, "descriptor %s alloc error %d\n",
++			(ring_type == HCLGE_COMM_TYPE_CSQ) ? "CSQ" : "CRQ",
++			ret);
++
++	return ret;
++}
++
++int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
++						struct hclge_comm_hw *hw,
++						u32 *fw_version, bool is_pf)
++{
++	struct hclge_comm_query_version_cmd *resp;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_comm_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);
++	resp = (struct hclge_comm_query_version_cmd *)desc.data;
++	resp->api_caps = hclge_comm_build_api_caps();
++
++	ret = hclge_comm_cmd_send(hw, &desc, 1);
++	if (ret)
++		return ret;
++
++	*fw_version = le32_to_cpu(resp->firmware);
++
++	ae_dev->dev_version = le32_to_cpu(resp->hardware) <<
++					 HNAE3_PCI_REVISION_BIT_SIZE;
++	ae_dev->dev_version |= ae_dev->pdev->revision;
+ 
+ 	for (i = 0; i < size; i++) {
+ 		if (spec_opcode[i] == opcode)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index ea30d94c081c..13562209f74d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -5,6 +5,7 @@
+ #define __HCLGE_COMM_CMD_H
+ #include <linux/types.h>
+ 
++#include "hclge_cmd.h"
+ #include "hnae3.h"
+ 
+ #define HCLGE_COMM_CMD_FLAG_IN			BIT(0)
+@@ -36,6 +37,27 @@
+ #define HCLGE_COMM_NIC_CSQ_DEPTH_REG		0x27008
+ #define HCLGE_COMM_NIC_CSQ_TAIL_REG		0x27010
+ #define HCLGE_COMM_NIC_CSQ_HEAD_REG		0x27014
++#define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG	0x27018
++#define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG	0x2701C
++#define HCLGE_COMM_NIC_CRQ_DEPTH_REG		0x27020
++#define HCLGE_COMM_NIC_CRQ_TAIL_REG		0x27024
++#define HCLGE_COMM_NIC_CRQ_HEAD_REG		0x27028
++/* Vector0 interrupt CMDQ event source register(RW) */
++#define HCLGE_COMM_VECTOR0_CMDQ_SRC_REG		0x27100
++/* Vector0 interrupt CMDQ event status register(RO) */
++#define HCLGE_COMM_VECTOR0_CMDQ_STATE_REG	0x27104
++#define HCLGE_COMM_CMDQ_INTR_EN_REG		0x27108
++#define HCLGE_COMM_CMDQ_INTR_GEN_REG		0x2710C
++#define HCLGE_COMM_CMDQ_INTR_STS_REG		0x27104
++
++/* this bit indicates that the driver is ready for hardware reset */
++#define HCLGE_COMM_NIC_SW_RST_RDY_B		16
++#define HCLGE_COMM_NIC_SW_RST_RDY		BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)
++#define HCLGE_COMM_NIC_CMQ_DESC_NUM_S		3
++#define HCLGE_COMM_NIC_CMQ_DESC_NUM		1024
++#define HCLGE_COMM_CMDQ_TX_TIMEOUT		30000
++
++enum hclge_opcode_type;
+ 
+ enum hclge_comm_cmd_return_status {
+ 	HCLGE_COMM_CMD_EXEC_SUCCESS	= 0,
+@@ -52,18 +74,49 @@ enum hclge_comm_cmd_return_status {
+ 	HCLGE_COMM_CMD_INVALID		= 11,
+ };
+ 
+-enum hclge_comm_special_cmd {
+-	HCLGE_COMM_OPC_STATS_64_BIT		= 0x0030,
+-	HCLGE_COMM_OPC_STATS_32_BIT		= 0x0031,
+-	HCLGE_COMM_OPC_STATS_MAC		= 0x0032,
+-	HCLGE_COMM_OPC_STATS_MAC_ALL		= 0x0034,
+-	HCLGE_COMM_OPC_QUERY_32_BIT_REG		= 0x0041,
+-	HCLGE_COMM_OPC_QUERY_64_BIT_REG		= 0x0042,
+-	HCLGE_COMM_QUERY_CLEAR_MPF_RAS_INT	= 0x1511,
+-	HCLGE_COMM_QUERY_CLEAR_PF_RAS_INT	= 0x1512,
+-	HCLGE_COMM_QUERY_CLEAR_ALL_MPF_MSIX_INT	= 0x1514,
+-	HCLGE_COMM_QUERY_CLEAR_ALL_PF_MSIX_INT	= 0x1515,
+-	HCLGE_COMM_QUERY_ALL_ERR_INFO		= 0x1517,
++enum HCLGE_COMM_CAP_BITS {
++	HCLGE_COMM_CAP_UDP_GSO_B,
++	HCLGE_COMM_CAP_QB_B,
++	HCLGE_COMM_CAP_FD_FORWARD_TC_B,
++	HCLGE_COMM_CAP_PTP_B,
++	HCLGE_COMM_CAP_INT_QL_B,
++	HCLGE_COMM_CAP_HW_TX_CSUM_B,
++	HCLGE_COMM_CAP_TX_PUSH_B,
++	HCLGE_COMM_CAP_PHY_IMP_B,
++	HCLGE_COMM_CAP_TQP_TXRX_INDEP_B,
++	HCLGE_COMM_CAP_HW_PAD_B,
++	HCLGE_COMM_CAP_STASH_B,
++	HCLGE_COMM_CAP_UDP_TUNNEL_CSUM_B,
++	HCLGE_COMM_CAP_RAS_IMP_B = 12,
++	HCLGE_COMM_CAP_FEC_B = 13,
++	HCLGE_COMM_CAP_PAUSE_B = 14,
++	HCLGE_COMM_CAP_RXD_ADV_LAYOUT_B = 15,
++	HCLGE_COMM_CAP_PORT_VLAN_BYPASS_B = 17,
++	HCLGE_COMM_CAP_CQ_B = 18,
++	HCLGE_COMM_CAP_GRO_B = 20,
++	HCLGE_COMM_CAP_FD_B = 21,
++	HCLGE_COMM_CAP_LANE_NUM_B = 27,
++	HCLGE_COMM_CAP_WOL_B = 28,
++};
++
++enum HCLGE_COMM_API_CAP_BITS {
++	HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B,
++};
++
++enum hclge_comm_opcode_type {
++	HCLGE_COMM_OPC_QUERY_FW_VER             = 0x0001,
++	HCLGE_COMM_OPC_IMP_COMPAT_CFG           = 0x701A,
++};
++
++/* capabilities bits map between imp firmware and local driver */
++struct hclge_comm_caps_bit_map {
++	u16 imp_bit;
++	u16 local_bit;
++};
++
++struct hclge_comm_firmware_compat_cmd {
++	__le32 compat;
++	u8 rsv[20];
+ };
+ 
+ enum hclge_comm_cmd_state {
+@@ -137,7 +190,17 @@ static inline u32 hclge_comm_read_reg(u8 __iomem *base, u32 reg)
+ #define hclge_comm_read_dev(a, reg) \
+ 	hclge_comm_read_reg((a)->io_base, reg)
+ 
++void hclge_comm_cmd_init_regs(struct hclge_comm_hw *hw);
++int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
++						struct hclge_comm_hw *hw,
++						u32 *fw_version, bool is_pf);
++int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type);
+ int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
+ 			int num, bool is_pf);
+-
++int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,
++				      struct hclge_comm_hw *hw, bool en);
++void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring);
++void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
++				     enum hclge_opcode_type opcode,
++				     bool is_read);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index c2c7e94d0467..52d448686a06 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1968,6 +1968,31 @@ static int hns3_get_link_ext_state(struct net_device *netdev,
+ 	return -ENODATA;
+ }
+ 
++static void hns3_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
++{
++	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
++	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
++
++	if (!hnae3_ae_dev_wol_supported(ae_dev) || !ops->get_wol)
++		return;
++
++	ops->get_wol(handle, wol);
++}
++
++static int hns3_set_wol(struct net_device *netdev,
++			struct ethtool_wolinfo *wol)
++{
++	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
++	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
++
++	if (!hnae3_ae_dev_wol_supported(ae_dev) || !ops->set_wol)
++		return -EOPNOTSUPP;
++
++	return ops->set_wol(handle, wol);
++}
++
+ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ 	.supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
+ 	.supported_ring_params = HNS3_ETHTOOL_RING,
+@@ -2042,6 +2067,8 @@ static const struct ethtool_ops hns3_ethtool_ops = {
+ 	.set_tunable = hns3_set_tunable,
+ 	.reset = hns3_set_reset,
+ 	.get_link_ext_state = hns3_get_link_ext_state,
++	.get_wol = hns3_get_wol,
++	.set_wol = hns3_set_wol,
+ };
+ 
+ void hns3_ethtool_set_ops(struct net_device *netdev)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 71cf6ad71427..1785eb6b0f33 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -312,6 +312,8 @@ enum hclge_opcode_type {
+ 	HCLGE_PPP_CMD1_INT_CMD		= 0x2101,
+ 	HCLGE_PPP_MAC_VLAN_IDX_RD	= 0x2104,
+ 	HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
++	HCLGE_OPC_WOL_CFG               = 0x2200,
++	HCLGE_OPC_WOL_GET_SUPPORTED_MODE        = 0x2201,
+ 	HCLGE_NCSI_INT_EN		= 0x2401,
+ 
+ 	/* PHY command */
+@@ -1275,6 +1277,29 @@ static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
+ 
+ #define HCLGE_SEND_SYNC(flag) \
+ 	((flag) & HCLGE_CMD_FLAG_NO_INTR)
++enum HCLGE_WOL_MODE {
++	HCLGE_WOL_PHY           = BIT(0),
++	HCLGE_WOL_UNICAST       = BIT(1),
++	HCLGE_WOL_MULTICAST     = BIT(2),
++	HCLGE_WOL_BROADCAST     = BIT(3),
++	HCLGE_WOL_ARP           = BIT(4),
++	HCLGE_WOL_MAGIC         = BIT(5),
++	HCLGE_WOL_MAGICSECURED  = BIT(6),
++	HCLGE_WOL_FILTER        = BIT(7),
++	HCLGE_WOL_DISABLE       = 0,
++};
++
++struct hclge_wol_cfg_cmd {
++	__le32 wake_on_lan_mode;
++	u8 sopass[SOPASS_MAX];
++	u8 sopass_size;
++	u8 rsv[13];
++};
++
++struct hclge_query_wol_supported_cmd {
++	__le32 supported_wake_mode;
++	u8 rsv[20];
++};
+ 
+ struct hclge_hw;
+ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 970012a36c14..bbc63c47d0df 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -11127,6 +11127,199 @@ static void hclge_clear_hw_resource(struct hclge_dev *hdev)
+ 			 "clear hw resource incomplete, ret = %d\n", ret);
+ }
+ 
++static __u32 hclge_wol_mode_to_ethtool(u32 mode)
++{
++	__u32 ret = 0;
++
++	if (mode & HCLGE_WOL_PHY)
++		ret |= WAKE_PHY;
++
++	if (mode & HCLGE_WOL_UNICAST)
++		ret |= WAKE_UCAST;
++
++	if (mode & HCLGE_WOL_MULTICAST)
++		ret |= WAKE_MCAST;
++
++	if (mode & HCLGE_WOL_BROADCAST)
++		ret |= WAKE_BCAST;
++
++	if (mode & HCLGE_WOL_ARP)
++		ret |= WAKE_ARP;
++
++	if (mode & HCLGE_WOL_MAGIC)
++		ret |= WAKE_MAGIC;
++
++	if (mode & HCLGE_WOL_MAGICSECURED)
++		ret |= WAKE_MAGICSECURE;
++
++	if (mode & HCLGE_WOL_FILTER)
++		ret |= WAKE_FILTER;
++
++	return ret;
++}
++
++static u32 hclge_wol_mode_from_ethtool(__u32 mode)
++{
++	u32 ret = HCLGE_WOL_DISABLE;
++
++	if (mode & WAKE_PHY)
++		ret |= HCLGE_WOL_PHY;
++
++	if (mode & WAKE_UCAST)
++		ret |= HCLGE_WOL_UNICAST;
++
++	if (mode & WAKE_MCAST)
++		ret |= HCLGE_WOL_MULTICAST;
++
++	if (mode & WAKE_BCAST)
++		ret |= HCLGE_WOL_BROADCAST;
++
++	if (mode & WAKE_ARP)
++		ret |= HCLGE_WOL_ARP;
++
++	if (mode & WAKE_MAGIC)
++		ret |= HCLGE_WOL_MAGIC;
++
++	if (mode & WAKE_MAGICSECURE)
++		ret |= HCLGE_WOL_MAGICSECURED;
++
++	if (mode & WAKE_FILTER)
++		ret |= HCLGE_WOL_FILTER;
++
++	return ret;
++}
++
++int hclge_get_wol_supported_mode(struct hclge_dev *hdev, u32 *wol_supported)
++{
++	struct hclge_query_wol_supported_cmd *wol_supported_cmd;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE,
++				   true);
++	wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)&desc.data;
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to query wol supported, ret = %d\n", ret);
++		return ret;
++	}
++
++	*wol_supported = le32_to_cpu(wol_supported_cmd->supported_wake_mode);
++
++	return 0;
++}
++
++int hclge_get_wol_cfg(struct hclge_dev *hdev, u32 *mode)
++{
++	struct hclge_wol_cfg_cmd *wol_cfg_cmd;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, true);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get wol config, ret = %d\n", ret);
++		return ret;
++	}
++
++	wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)&desc.data;
++	*mode = le32_to_cpu(wol_cfg_cmd->wake_on_lan_mode);
++
++	return 0;
++}
++
++static int hclge_set_wol_cfg(struct hclge_dev *hdev,
++			     struct hclge_wol_info *wol_info)
++{
++	struct hclge_wol_cfg_cmd *wol_cfg_cmd;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false);
++	wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)&desc.data;
++	wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode);
++	wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size;
++	memcpy(&wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to set wol config, ret = %d\n", ret);
++
++	return ret;
++}
++
++static int hclge_update_wol(struct hclge_dev *hdev)
++{
++	struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
++
++	if (!hnae3_ae_dev_wol_supported(hdev->ae_dev))
++		return 0;
++
++	return hclge_set_wol_cfg(hdev, wol_info);
++}
++
++static int hclge_init_wol(struct hclge_dev *hdev)
++{
++	struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
++	int ret;
++
++	if (!hnae3_ae_dev_wol_supported(hdev->ae_dev))
++		return 0;
++
++	memset(wol_info, 0, sizeof(struct hclge_wol_info));
++	ret = hclge_get_wol_supported_mode(hdev,
++					   &wol_info->wol_support_mode);
++	if (ret) {
++		wol_info->wol_support_mode = HCLGE_WOL_DISABLE;
++		return ret;
++	}
++
++	return hclge_update_wol(hdev);
++}
++
++static void hclge_get_wol(struct hnae3_handle *handle,
++			  struct ethtool_wolinfo *wol)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_dev *hdev = vport->back;
++	struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
++
++	wol->supported = hclge_wol_mode_to_ethtool(wol_info->wol_support_mode);
++	wol->wolopts =
++		hclge_wol_mode_to_ethtool(wol_info->wol_current_mode);
++	if (wol_info->wol_current_mode & HCLGE_WOL_MAGICSECURED)
++		memcpy(&wol->sopass, wol_info->wol_sopass, SOPASS_MAX);
++}
++
++static int hclge_set_wol(struct hnae3_handle *handle,
++			 struct ethtool_wolinfo *wol)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_dev *hdev = vport->back;
++	struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
++	u32 wol_supported;
++	u32 wol_mode;
++
++	wol_supported = hclge_wol_mode_from_ethtool(wol->supported);
++	wol_mode = hclge_wol_mode_from_ethtool(wol->wolopts);
++	if (wol_mode & ~wol_supported)
++		return -EINVAL;
++
++	wol_info->wol_current_mode = wol_mode;
++	if (wol_mode & HCLGE_WOL_MAGICSECURED) {
++		memcpy(wol_info->wol_sopass, &wol->sopass, SOPASS_MAX);
++		wol_info->wol_sopass_size = SOPASS_MAX;
++	} else {
++		wol_info->wol_sopass_size = 0;
++	}
++
++	return hclge_set_wol_cfg(hdev, wol_info);
++}
++
+ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ {
+ 	struct pci_dev *pdev = ae_dev->pdev;
+@@ -11313,6 +11506,11 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	/* Enable MISC vector(vector0) */
+ 	hclge_enable_vector(&hdev->misc_vector, true);
+ 
++	ret = hclge_init_wol(hdev);
++	if (ret)
++		dev_warn(&pdev->dev,
++			 "failed to wake on lan init, ret = %d\n", ret);
++
+ 	hclge_state_init(hdev);
+ 	hdev->last_reset_time = jiffies;
+ 
+@@ -11693,6 +11891,8 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 		ae_dev->ops->ext_reset_done(&hdev->vport->nic);
+ #endif
+ 
++	(void)hclge_update_wol(hdev);
++
+ 	dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
+ 		 HCLGE_DRIVER_NAME);
+ 
+@@ -12651,6 +12851,8 @@ struct hnae3_ae_ops hclge_ops = {
+ 	.get_rx_hwts = hclge_ptp_get_rx_hwts,
+ 	.get_ts_info = hclge_ptp_get_ts_info,
+ 	.get_link_diagnosis_info = hclge_get_link_diagnosis_info,
++	.get_wol = hclge_get_wol,
++	.set_wol = hclge_set_wol,
+ };
+ 
+ static struct hnae3_ae_algo ae_algo = {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 4924aaad757d..9d739033daab 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -277,6 +277,13 @@ enum HCLGE_MAC_DUPLEX {
+ #define QUERY_SFP_SPEED		0
+ #define QUERY_ACTIVE_SPEED	1
+ 
++struct hclge_wol_info {
++	u32 wol_support_mode; /* store the wake on lan info */
++	u32 wol_current_mode;
++	u8 wol_sopass[SOPASS_MAX];
++	u8 wol_sopass_size;
++};
++
+ struct hclge_mac {
+ 	u8 mac_id;
+ 	u8 phy_addr;
+@@ -296,7 +303,8 @@ struct hclge_mac {
+ 	u32 fec_mode; /* active fec mode */
+ 	u32 user_fec_mode;
+ 	u32 fec_ability;
+-	int link;	/* store the link status of mac & phy (if phy exit) */
++	int link;	/* store the link status of mac & phy (if phy exists) */
++	struct hclge_wol_info wol;
+ 	struct phy_device *phydev;
+ 	struct mii_bus *mdio_bus;
+ 	phy_interface_t phy_if;
+@@ -1155,4 +1163,9 @@ int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len);
+ int hclge_push_vf_link_status(struct hclge_vport *vport);
+ int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en);
+ int hclge_mac_update_stats(struct hclge_dev *hdev);
++int hclge_register_sysfs(struct hclge_dev *hdev);
++void hclge_unregister_sysfs(struct hclge_dev *hdev);
++int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, u8 duplex);
++int hclge_get_wol_supported_mode(struct hclge_dev *hdev, u32 *wol_supported);
++int hclge_get_wol_cfg(struct hclge_dev *hdev, u32 *mode);
+ #endif
+-- 
+2.34.1
+
diff --git a/patches/0551-net-hns3-fix-miss-L3E-checking-for-rx-packet.patch b/patches/0551-net-hns3-fix-miss-L3E-checking-for-rx-packet.patch
new file mode 100644
index 0000000..fd000c4
--- /dev/null
+++ b/patches/0551-net-hns3-fix-miss-L3E-checking-for-rx-packet.patch
@@ -0,0 +1,49 @@
+From 148ec1376bab4e262f3bcd354dac20140ad062b6 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Thu, 22 Dec 2022 14:43:42 +0800
+Subject: [PATCH 190/283] net: hns3: fix miss L3E checking for rx packet
+
+mainline inclusion
+from mainline-v6.2-rc3
+commit 7d89b53cea1a702f97117fb4361523519bb1e52c
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=7d89b53cea1a702f97117fb4361523519bb1e52c
+
+----------------------------------------------------------------------
+
+For device supports RXD advanced layout, the driver will
+return directly if the hardware finish the checksum
+calculate. It cause missing L3E checking for ip packets.
+Fixes it.
+
+Fixes: 1ddc028ac849 ("net: hns3: refactor out RX completion checksum")
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 42932052ccaf..2ca9e369c4bc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -3545,6 +3545,7 @@ static void hns3_rx_checksum(struct hns3_enet_ring *ring, struct sk_buff *skb,
+ 	if (unlikely(l234info & (BIT(HNS3_RXD_L3E_B) | BIT(HNS3_RXD_L4E_B) |
+ 				 BIT(HNS3_RXD_OL3E_B) |
+ 				 BIT(HNS3_RXD_OL4E_B)))) {
++		skb->ip_summed = CHECKSUM_NONE;
+ 		u64_stats_update_begin(&ring->syncp);
+ 		ring->stats.l3l4_csum_err++;
+ 		u64_stats_update_end(&ring->syncp);
+-- 
+2.34.1
+
diff --git a/patches/0552-net-hns3-add-support-customized-exception-handling-i.patch b/patches/0552-net-hns3-add-support-customized-exception-handling-i.patch
new file mode 100644
index 0000000..5c5b8c4
--- /dev/null
+++ b/patches/0552-net-hns3-add-support-customized-exception-handling-i.patch
@@ -0,0 +1,774 @@
+From 66962d2f2ca31c150b28b43e99654f6c85889357 Mon Sep 17 00:00:00 2001
+From: Tian Jiang <jiangtian6@h-partners.com>
+Date: Thu, 9 Mar 2023 10:59:36 +0800
+Subject: [PATCH 191/283] net: hns3: add support customized exception handling
+ interfaces.
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+Establish a framework to support customization requirement. Provides
+interfaces to register special processing functions. When the system
+is reset due to an abnormal interrupt, the registered handler is
+called first.
+
+Signed-off-by: Tian Jiang <jiangtian6@h-partners.com>
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/Makefile
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+---
+ drivers/net/ethernet/hisilicon/hns3/Makefile  |   3 +
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |   2 +
+ .../net/ethernet/hisilicon/hns3/hnae3_ext.h   |  32 ++++
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   |   5 +
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    |  76 ++++++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |  13 ++
+ .../hns3_extension/hns3pf/hclge_main_it.c     |  22 +--
+ .../hns3_extension/hns3pf/hclge_main_it.h     |  32 ----
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 178 ++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ext.h         |  43 +++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  45 ++---
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   5 +-
+ .../hisilicon/hns3/hns3pf/hclge_mbx.c         |   2 +-
+ 13 files changed, 382 insertions(+), 76 deletions(-)
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile
+index 70bf49da5591..d0f56781b558 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/Makefile
+@@ -26,6 +26,7 @@ HNS3_OBJS	=	hns3_enet.o \
+ HNS3_OBJS_IT	=	hns3_extension/hns3_enet_it.o
+ obj-$(CONFIG_HNS3_ENET) += hns3.o
+ hns3-objs = $(HNS3_OBJS) $(HNS3_OBJS_IT)
++hns3-objs += hns3_ext.o
+ 
+ hns3-$(CONFIG_HNS3_DCB) += hns3_dcbnl.o
+ 
+@@ -44,6 +45,8 @@ HCLGE_OBJ_IT_MAIN	=	hns3_extension/hns3pf/hclge_main_it.o \
+ 				hns3_extension/hns3pf/hclge_sysfs.o
+ obj-$(CONFIG_HNS3_HCLGE) += hclge.o
+ hclge-objs := $(HCLGE_OBJ) $(HCLGE_OBJ_IT_MAIN)
++hclge-objs += hns3pf/hclge_ext.o
++
+ hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o
+ #### compile hclgevf.ko
+ obj-$(CONFIG_HNS3_HCLGEVF) += hclgevf.o
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index d15038e8bcb5..970ef08ce9cc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -787,6 +787,8 @@ struct hnae3_ae_ops {
+ 			struct ethtool_wolinfo *wol);
+ 	int (*set_wol)(struct hnae3_handle *handle,
+ 		       struct ethtool_wolinfo *wol);
++	int (*priv_ops)(struct hnae3_handle *handle, int opcode,
++			void *data, size_t length);
+ /* Notice! If the function is not for test, the definition must before
+  * CONFIG_HNS3_TEST! Because RoCE will use this head file, and it won't
+  * set CONFIG_HNS3_TEST, that may cause RoCE calling the wrong function.
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+new file mode 100644
+index 000000000000..0b1fa53dfb41
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++// Copyright (c) 2023 Hisilicon Limited.
++
++#ifndef __HNAE3_EXT_H
++#define __HNAE3_EXT_H
++
++enum hnae3_event_type_custom {
++	HNAE3_VF_RESET_CUSTOM,
++	HNAE3_VF_FUNC_RESET_CUSTOM,
++	HNAE3_VF_PF_FUNC_RESET_CUSTOM,
++	HNAE3_VF_FULL_RESET_CUSTOM,
++	HNAE3_FLR_RESET_CUSTOM,
++	HNAE3_FUNC_RESET_CUSTOM,
++	HNAE3_GLOBAL_RESET_CUSTOM,
++	HNAE3_IMP_RESET_CUSTOM,
++	HNAE3_UNKNOWN_RESET_CUSTOM,
++	HNAE3_NONE_RESET_CUSTOM,
++	HNAE3_PORT_FAULT,
++	HNAE3_RESET_DONE_CUSTOM,
++	HNAE3_FUNC_RESET_FAIL_CUSTOM,
++	HNAE3_GLOBAL_RESET_FAIL_CUSTOM,
++	HNAE3_IMP_RESET_FAIL_CUSTOM,
++	HNAE3_PPU_POISON_CUSTOM,
++	HNAE3_IMP_RD_POISON_CUSTOM,
++	HNAE3_INVALID_EVENT_CUSTOM
++};
++
++enum hnae3_ext_opcode {
++	HNAE3_EXT_OPC_RESET,
++	HNAE3_EXT_OPC_EVENT_CALLBACK,
++};
++#endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 2ca9e369c4bc..72cc7f16aa7e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -23,6 +23,7 @@
+ 
+ #include "kcompat.h"
+ #include "hnae3.h"
++#include "hnae3_ext.h"
+ #include "hns3_enet.h"
+ /* All hns3 tracepoints are defined by the include below, which
+  * must be included exactly once across the whole kernel with
+@@ -5526,6 +5527,10 @@ static void hns3_process_hw_error(struct hnae3_handle *handle,
+ 		if (hns3_hw_err[i].type == type) {
+ 			dev_err(&handle->pdev->dev, "Detected %s!\n",
+ 				hns3_hw_err[i].msg);
++			if (handle->ae_algo->ops->priv_ops)
++				handle->ae_algo->ops->priv_ops(handle,
++					HNAE3_EXT_OPC_EVENT_CALLBACK, &type,
++					sizeof(type));
+ 			break;
+ 		}
+ 	}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+new file mode 100644
+index 000000000000..34aadd10feb8
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -0,0 +1,76 @@
++// SPDX-License-Identifier: GPL-2.0+
++// Copyright (c) 2023 Hisilicon Limited.
++
++#include "hns3_ext.h"
++
++int nic_netdev_match_check(struct net_device *ndev)
++{
++#define HNS3_DRIVER_NAME_LEN 5
++
++	struct ethtool_drvinfo drv_info;
++	struct hnae3_handle *h;
++
++	if (!ndev || !ndev->ethtool_ops ||
++	    !ndev->ethtool_ops->get_drvinfo)
++		return -EINVAL;
++
++	ndev->ethtool_ops->get_drvinfo(ndev, &drv_info);
++
++	if (strncmp(drv_info.driver, "hns3", HNS3_DRIVER_NAME_LEN))
++		return -EINVAL;
++
++	h = hns3_get_handle(ndev);
++	if (h->flags & HNAE3_SUPPORT_VF)
++		return -EINVAL;
++
++	return 0;
++}
++EXPORT_SYMBOL(nic_netdev_match_check);
++
++static int nic_invoke_pri_ops(struct net_device *ndev, int opcode,
++			      void *data, size_t length)
++
++{
++	struct hnae3_handle *h;
++	int ret;
++
++	if ((!data && length) || (data && !length)) {
++		netdev_err(ndev, "failed to check data and length");
++		return -EINVAL;
++	}
++
++	if (nic_netdev_match_check(ndev))
++		return -ENODEV;
++
++	h = hns3_get_handle(ndev);
++	if (!h->ae_algo->ops->priv_ops)
++		return -EOPNOTSUPP;
++
++	ret = h->ae_algo->ops->priv_ops(h, opcode, data, length);
++	if (ret)
++		netdev_err(ndev,
++			   "failed to invoke pri ops, opcode = %#x, ret = %d\n",
++			   opcode, ret);
++
++	return ret;
++}
++
++void nic_chip_recover_handler(struct net_device *ndev,
++			      enum hnae3_event_type_custom event_t)
++{
++	dev_info(&ndev->dev, "reset type is %d!!\n", event_t);
++
++	if (event_t == HNAE3_PPU_POISON_CUSTOM)
++		event_t = HNAE3_FUNC_RESET_CUSTOM;
++
++	if (event_t != HNAE3_FUNC_RESET_CUSTOM &&
++	    event_t != HNAE3_GLOBAL_RESET_CUSTOM &&
++	    event_t != HNAE3_IMP_RESET_CUSTOM) {
++		dev_err(&ndev->dev, "reset type err!!\n");
++		return;
++	}
++
++	nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_RESET,
++			   &event_t, sizeof(event_t));
++}
++EXPORT_SYMBOL(nic_chip_recover_handler);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+new file mode 100644
+index 000000000000..ce92a666db17
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/* Copyright (c) 2023 Hisilicon Limited. */
++
++#ifndef __HNS3_EXT_H
++#define __HNS3_EXT_H
++#include <linux/types.h>
++#include "hns3_enet.h"
++#include "hnae3_ext.h"
++
++int nic_netdev_match_check(struct net_device *netdev);
++void nic_chip_recover_handler(struct net_device *ndev,
++			      enum hnae3_event_type_custom event_t);
++#endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c
+index 0118b9577a66..37b121632ddc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c
+@@ -18,6 +18,7 @@
+ #include "hclge_main.h"
+ #include "hnae3.h"
+ #include "hclge_main_it.h"
++#include "hclge_ext.h"
+ #ifdef CONFIG_HNS3_TEST
+ #include "hclge_sysfs.h"
+ #endif
+@@ -27,27 +28,6 @@
+ 
+ static nic_event_fn_t nic_event_call;
+ 
+-int nic_register_event(nic_event_fn_t event_call)
+-{
+-	if (!event_call) {
+-		pr_err("register event handle is null.\n");
+-		return -EINVAL;
+-	}
+-
+-	nic_event_call = event_call;
+-
+-	pr_info("netdev register success.\n");
+-	return 0;
+-}
+-EXPORT_SYMBOL(nic_register_event);
+-
+-int nic_unregister_event(void)
+-{
+-	nic_event_call = NULL;
+-	return 0;
+-}
+-EXPORT_SYMBOL(nic_unregister_event);
+-
+ static void nic_call_event(struct net_device *netdev,
+ 			   enum hnae3_event_type_custom event_t)
+ {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.h b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.h
+index 343e036412d4..290c221f1807 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.h
+@@ -7,25 +7,6 @@
+ extern struct hnae3_ae_algo ae_algo;
+ extern struct hnae3_ae_ops hclge_ops;
+ 
+-enum hnae3_event_type_custom {
+-	HNAE3_VF_RESET_CUSTOM,
+-	HNAE3_VF_FUNC_RESET_CUSTOM,
+-	HNAE3_VF_PF_FUNC_RESET_CUSTOM,
+-	HNAE3_VF_FULL_RESET_CUSTOM,
+-	HNAE3_FLR_RESET_CUSTOM,
+-	HNAE3_FUNC_RESET_CUSTOM,
+-	HNAE3_GLOBAL_RESET_CUSTOM,
+-	HNAE3_IMP_RESET_CUSTOM,
+-	HNAE3_UNKNOWN_RESET_CUSTOM,
+-	HNAE3_NONE_RESET_CUSTOM,
+-	HNAE3_PORT_FAULT,
+-	HNAE3_RESET_DONE_CUSTOM,
+-	HNAE3_FUNC_RESET_FAIL_CUSTOM,
+-	HNAE3_GLOBAL_RESET_FAIL_CUSTOM,
+-	HNAE3_IMP_RESET_FAIL_CUSTOM,
+-	HNAE3_PPU_POISON_CUSTOM,
+-	HNAE3_IMP_RD_POISON_CUSTOM,
+-};
+ 
+ /**
+  * nic_event_fn_t - nic event handler prototype
+@@ -35,18 +16,5 @@ enum hnae3_event_type_custom {
+ typedef void (*nic_event_fn_t) (struct net_device *netdev,
+ 				enum hnae3_event_type_custom);
+ 
+-/**
+- * nic_register_event - register for nic event handling
+- * @event_call:	nic event handler
+- * return 0 - success , negative - fail
+- */
+-int nic_register_event(nic_event_fn_t event_call);
+-
+-/**
+- * nic_unregister_event - quit nic event handling
+- * return 0 - success , negative - fail
+- */
+-int nic_unregister_event(void);
+-
+ int hclge_init(void);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+new file mode 100644
+index 000000000000..52c7f5085cfb
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -0,0 +1,178 @@
++// SPDX-License-Identifier: GPL-2.0+
++// Copyright (c) 2023 Hisilicon Limited.
++
++#include "hclge_main.h"
++#include "hnae3.h"
++#include "hnae3_ext.h"
++#include "hclge_cmd.h"
++#include "hclge_ext.h"
++
++#define HCLGE_RESET_MAX_FAIL_CNT 5
++
++static nic_event_fn_t nic_event_call;
++
++/* We use a lock to ensure that the address of the nic_event_call function
++ * is valid when it is called. Avoid null pointer exceptions caused by
++ * external unregister during invoking.
++ */
++static DEFINE_MUTEX(hclge_nic_event_lock);
++
++static int hclge_set_reset_task(struct hclge_dev *hdev, void *data,
++				size_t length)
++{
++	u32 *reset_level = (u32 *)data;
++
++	if (length != sizeof(u32))
++		return -EINVAL;
++
++	dev_warn(&hdev->pdev->dev, "reset level is %u\n", *reset_level);
++
++	/* request reset & schedule reset task */
++	set_bit(*reset_level, &hdev->reset_request);
++	hclge_reset_task_schedule(hdev);
++	return 0;
++}
++
++int hclge_ext_call_event(struct hclge_dev *hdev,
++			 enum hnae3_event_type_custom event_t)
++{
++	if (event_t >= HNAE3_INVALID_EVENT_CUSTOM)
++		return -EINVAL;
++
++	mutex_lock(&hclge_nic_event_lock);
++	if (!nic_event_call) {
++		mutex_unlock(&hclge_nic_event_lock);
++		return -EOPNOTSUPP;
++	}
++
++	nic_event_call(hdev->vport[0].nic.netdev, event_t);
++	mutex_unlock(&hclge_nic_event_lock);
++	return 0;
++}
++
++int nic_register_event(nic_event_fn_t event_call)
++{
++	if (!event_call) {
++		pr_err("hns3: register event handle is null\n");
++		return -EINVAL;
++	}
++
++	mutex_lock(&hclge_nic_event_lock);
++	if (nic_event_call) {
++		mutex_unlock(&hclge_nic_event_lock);
++		pr_err("hns3: event already register\n");
++		return -EBUSY;
++	}
++
++	nic_event_call = event_call;
++
++	mutex_unlock(&hclge_nic_event_lock);
++	pr_info("hns3: event register success\n");
++	return 0;
++}
++EXPORT_SYMBOL(nic_register_event);
++
++int nic_unregister_event(void)
++{
++	mutex_lock(&hclge_nic_event_lock);
++	nic_event_call = NULL;
++
++	mutex_unlock(&hclge_nic_event_lock);
++	pr_info("hns3: event unregister success\n");
++	return 0;
++}
++EXPORT_SYMBOL(nic_unregister_event);
++
++static int hclge_nic_call_event(struct hclge_dev *hdev, void *data,
++				size_t length)
++{
++#define ERROR_EVENT_TYPE_NUM 3
++
++	u32 event_type[ERROR_EVENT_TYPE_NUM] = {
++		HNAE3_PPU_POISON_CUSTOM,
++		HNAE3_IMP_RESET_CUSTOM,
++		HNAE3_IMP_RD_POISON_CUSTOM
++	};
++	u32 *index = (u32 *)data;
++
++	if (length != sizeof(u32))
++		return -EINVAL;
++
++	if ((*index) >= ERROR_EVENT_TYPE_NUM)
++		return 0;
++
++	return hclge_ext_call_event(hdev, event_type[*index]);
++}
++
++static enum hnae3_event_type_custom
++hclge_get_reset_fail_type(enum hnae3_reset_type reset_type)
++{
++	const struct hclge_reset_fail_type_map fail_type_map[] = {
++		{HNAE3_FUNC_RESET, HNAE3_FUNC_RESET_FAIL_CUSTOM},
++		{HNAE3_GLOBAL_RESET, HNAE3_GLOBAL_RESET_FAIL_CUSTOM},
++		{HNAE3_IMP_RESET, HNAE3_IMP_RESET_FAIL_CUSTOM},
++	};
++	u32 i;
++
++	for (i = 0; i < ARRAY_SIZE(fail_type_map); i++)
++		if (fail_type_map[i].reset_type == reset_type)
++			return fail_type_map[i].custom_type;
++
++	return HNAE3_INVALID_EVENT_CUSTOM;
++}
++
++static void hclge_report_reset_fail_custom(struct hclge_dev *hdev)
++{
++#define HCLGE_RESET_MAX_FAIL_CNT_CUSTOM 1
++
++	u32 max_fail_custom_cnt = HCLGE_RESET_MAX_FAIL_CNT;
++
++	mutex_lock(&hclge_nic_event_lock);
++	if (nic_event_call)
++		max_fail_custom_cnt = HCLGE_RESET_MAX_FAIL_CNT_CUSTOM;
++	mutex_unlock(&hclge_nic_event_lock);
++
++	if (hdev->rst_stats.reset_fail_cnt < max_fail_custom_cnt)
++		return;
++
++	dev_err(&hdev->pdev->dev, "failed to report reset!\n");
++	hclge_ext_call_event(hdev, hclge_get_reset_fail_type(hdev->reset_type));
++}
++
++void hclge_ext_reset_end(struct hclge_dev *hdev, bool done)
++{
++	if (!done) {
++		hclge_report_reset_fail_custom(hdev);
++		return;
++	}
++
++	hclge_ext_call_event(hdev, HNAE3_RESET_DONE_CUSTOM);
++	dev_info(&hdev->pdev->dev, "report reset done!\n");
++}
++
++static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
++	[HNAE3_EXT_OPC_RESET] = hclge_set_reset_task,
++	[HNAE3_EXT_OPC_EVENT_CALLBACK] = hclge_nic_call_event,
++};
++
++int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
++			 void *data, size_t length)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	int cmd_num = ARRAY_SIZE(hclge_ext_func_arr);
++	struct hclge_dev *hdev = vport->back;
++	hclge_priv_ops_fn ext_opcode_func;
++
++	if (opcode >= cmd_num) {
++		dev_err(&hdev->pdev->dev, "invalid opcode %d\n", opcode);
++		return -EINVAL;
++	}
++
++	ext_opcode_func = hclge_ext_func_arr[opcode];
++	if (!ext_opcode_func) {
++		dev_err(&hdev->pdev->dev, "unsupported opcode %d\n", opcode);
++		return -EOPNOTSUPP;
++	}
++
++	return ext_opcode_func(hdev, data, length);
++}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+new file mode 100644
+index 000000000000..1c1b04765e7e
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -0,0 +1,43 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/* Copyright (c) 2016-2017 Hisilicon Limited. */
++
++#ifndef __HCLGE_EXT_H
++#define __HCLGE_EXT_H
++#include <linux/types.h>
++
++struct hclge_reset_fail_type_map {
++	enum hnae3_reset_type reset_type;
++	enum hnae3_event_type_custom custom_type;
++};
++
++typedef int (*hclge_priv_ops_fn)(struct hclge_dev *hdev, void *data,
++				 size_t length);
++
++/**
++ * nic_event_fn_t - nic event handler prototype
++ * @netdev:	net device
++ * @hnae3_event_type_custom:	nic device event type
++ */
++typedef void (*nic_event_fn_t) (struct net_device *netdev,
++				enum hnae3_event_type_custom);
++
++/**
++ * nic_register_event - register for nic event handling
++ * @event_call:	nic event handler
++ * return 0 - success , negative - fail
++ */
++int nic_register_event(nic_event_fn_t event_call);
++
++/**
++ * nic_unregister_event - unregister for nic event handling
++ * return 0 - success , negative - fail
++ */
++int nic_unregister_event(void);
++
++int hclge_ext_call_event(struct hclge_dev *hdev,
++			 enum hnae3_event_type_custom event_t);
++void hclge_ext_reset_end(struct hclge_dev *hdev, bool done);
++
++int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
++			 void *data, size_t length);
++#endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index bbc63c47d0df..3779181b8f59 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -18,6 +18,7 @@
+ #include "kcompat.h"
+ #include "hclge_cmd.h"
+ #include "hclge_dcb.h"
++#include "hclge_ext.h"
+ #include "hclge_main.h"
+ #include "hclge_mbx.h"
+ #include "hclge_mdio.h"
+@@ -34,7 +35,6 @@
+ #define BUF_MAX_PERCENT		100
+ #define BUF_RESERVE_PERCENT	90
+ 
+-#define HCLGE_RESET_MAX_FAIL_CNT	5
+ #define HCLGE_RESET_SYNC_TIME		100
+ #define HCLGE_PF_RESET_SYNC_TIME	20
+ #define HCLGE_PF_RESET_SYNC_CNT		1500
+@@ -55,6 +55,8 @@
+ 
+ #define HCLGE_LINK_STATUS_MS	10
+ 
++#define HCLGE_RESET_MAX_FAIL_CNT        5
++
+ static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
+ static int hclge_init_vlan_config(struct hclge_dev *hdev);
+ static void hclge_sync_vlan_filter(struct hclge_dev *hdev);
+@@ -67,6 +69,7 @@ static int hclge_set_default_loopback(struct hclge_dev *hdev);
+ static void hclge_sync_mac_table(struct hclge_dev *hdev);
+ static void hclge_restore_hw_table(struct hclge_dev *hdev);
+ static void hclge_sync_promisc_mode(struct hclge_dev *hdev);
++static void hclge_reset_end(struct hnae3_handle *handle, bool done);
+ 
+ static struct hnae3_ae_algo ae_algo;
+ 
+@@ -2916,7 +2919,7 @@ static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
+ 	}
+ }
+ 
+-static void hclge_reset_task_schedule(struct hclge_dev *hdev)
++void hclge_reset_task_schedule(struct hclge_dev *hdev)
+ {
+ 	if (!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
+ 	    test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state) &&
+@@ -3399,7 +3402,7 @@ static int hclge_get_status(struct hnae3_handle *handle)
+ 	return hdev->hw.mac.link;
+ }
+ 
+-static struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf)
++struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf)
+ {
+ 	if (!pci_num_vf(hdev->pdev)) {
+ 		dev_err(&hdev->pdev->dev,
+@@ -4142,8 +4145,7 @@ static bool hclge_reset_err_handle(struct hclge_dev *hdev)
+ 	/* recover the handshake status when reset fail */
+ 	hclge_reset_handshake(hdev, true);
+ 
+-	if (handle && handle->ae_algo->ops->reset_end)
+-		handle->ae_algo->ops->reset_end(handle, false);
++	hclge_reset_end(handle, false);
+ 
+ 	hclge_show_rst_info(hdev);
+ 
+@@ -4262,6 +4264,7 @@ static int hclge_reset_prepare(struct hclge_dev *hdev)
+ 
+ static int hclge_reset_rebuild(struct hclge_dev *hdev)
+ {
++	struct hnae3_handle *handle = &hdev->vport[0].nic;
+ 	int ret;
+ 
+ 	hdev->rst_stats.hw_reset_done_cnt++;
+@@ -4307,6 +4310,8 @@ static int hclge_reset_rebuild(struct hclge_dev *hdev)
+ 
+ 	hclge_update_reset_level(hdev);
+ 
++	hclge_reset_end(handle, true);
++
+ 	return 0;
+ }
+ 
+@@ -4328,10 +4333,11 @@ static void hclge_reset(struct hclge_dev *hdev)
+ 		hclge_reset_task_schedule(hdev);
+ }
+ 
+-static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
++void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
+ 	struct hclge_dev *hdev = ae_dev->priv;
++	int ret;
+ 
+ 	/* We might end up getting called broadly because of 2 below cases:
+ 	 * 1. Recoverable error was conveyed through APEI and only way to bring
+@@ -4366,9 +4372,12 @@ static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
+ 	dev_info(&hdev->pdev->dev, "received reset event, reset type is %d\n",
+ 		 hdev->reset_level);
+ 
+-	/* request reset & schedule reset task */
+-	set_bit(hdev->reset_level, &hdev->reset_request);
+-	hclge_reset_task_schedule(hdev);
++	ret = hclge_ext_call_event(hdev, hdev->reset_level);
++	if (ret) {
++		/* request reset & schedule reset task */
++		set_bit(hdev->reset_level, &hdev->reset_request);
++		hclge_reset_task_schedule(hdev);
++	}
+ 
+ 	if (hdev->reset_level < HNAE3_GLOBAL_RESET)
+ 		hdev->reset_level++;
+@@ -4385,7 +4394,6 @@ static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
+ static void hclge_reset_timer(struct timer_list *t)
+ {
+ 	struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 
+ 	/* if default_reset_request has no value, it means that this reset
+ 	 * request has already be handled, so just return here
+@@ -4395,20 +4403,15 @@ static void hclge_reset_timer(struct timer_list *t)
+ 
+ 	dev_info(&hdev->pdev->dev,
+ 		 "triggering reset in reset timer\n");
+-
+-	if (ae_dev->ops->reset_event)
+-		ae_dev->ops->reset_event(hdev->pdev, NULL);
++	hclge_reset_event(hdev->pdev, &hdev->vport[0].nic);
+ }
+ 
+-static bool hclge_reset_end(struct hnae3_handle *handle, bool done)
++static void hclge_reset_end(struct hnae3_handle *handle, bool done)
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+ 
+-	if (hdev->rst_stats.reset_fail_cnt >= HCLGE_RESET_MAX_FAIL_CNT)
+-		dev_err(&hdev->pdev->dev, "Reset fail!\n");
+-
+-	return done;
++	hclge_ext_reset_end(hdev, done);
+ }
+ 
+ static void hclge_reset_subtask(struct hclge_dev *hdev)
+@@ -4448,8 +4451,8 @@ static void hclge_handle_err_reset_request(struct hclge_dev *hdev)
+ 		hclge_set_def_reset_request(ae_dev, reset_type);
+ 	}
+ 
+-	if (hdev->default_reset_request && ae_dev->ops->reset_event)
+-		ae_dev->ops->reset_event(hdev->pdev, NULL);
++	if (hdev->default_reset_request)
++		hclge_reset_event(hdev->pdev, &hdev->vport[0].nic);
+ 
+ 	/* enable interrupt after error handling complete */
+ 	hclge_enable_vector(&hdev->misc_vector, true);
+@@ -12836,7 +12839,6 @@ struct hnae3_ae_ops hclge_ops = {
+ 	.set_timer_task = hclge_set_timer_task,
+ 	.mac_connect_phy = hclge_mac_connect_phy,
+ 	.mac_disconnect_phy = hclge_mac_disconnect_phy,
+-	.reset_end = hclge_reset_end,
+ 	.get_vf_config = hclge_get_vf_config,
+ 	.set_vf_link_state = hclge_set_vf_link_state,
+ 	.set_vf_spoofchk = hclge_set_vf_spoofchk,
+@@ -12853,6 +12855,7 @@ struct hnae3_ae_ops hclge_ops = {
+ 	.get_link_diagnosis_info = hclge_get_link_diagnosis_info,
+ 	.get_wol = hclge_get_wol,
+ 	.set_wol = hclge_set_wol,
++	.priv_ops = hclge_ext_ops_handle,
+ };
+ 
+ static struct hnae3_ae_algo ae_algo = {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 9d739033daab..f32c8b52f022 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -11,7 +11,7 @@
+ 
+ #include "hclge_cmd.h"
+ #include "hclge_ptp.h"
+-#include "hnae3.h"
++#include "hnae3_ext.h"
+ 
+ #define HCLGE_MOD_VERSION "23.7.1"
+ #define HCLGE_DRIVER_NAME "hclge"
+@@ -1168,4 +1168,7 @@ void hclge_unregister_sysfs(struct hclge_dev *hdev);
+ int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, u8 duplex);
+ int hclge_get_wol_supported_mode(struct hclge_dev *hdev, u32 *wol_supported);
+ int hclge_get_wol_cfg(struct hclge_dev *hdev, u32 *mode);
++struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf);
++void hclge_reset_task_schedule(struct hclge_dev *hdev);
++void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+index 305f11c854bf..4c270073c607 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+@@ -802,7 +802,7 @@ static void hclge_handle_ncsi_error(struct hclge_dev *hdev)
+ 
+ 	ae_dev->ops->set_default_reset_request(ae_dev, HNAE3_GLOBAL_RESET);
+ 	dev_warn(&hdev->pdev->dev, "requesting reset due to NCSI error\n");
+-	ae_dev->ops->reset_event(hdev->pdev, NULL);
++	hclge_reset_event(hdev->pdev, &hdev->vport[0].nic);
+ }
+ 
+ static void hclge_handle_vf_tbl(struct hclge_vport *vport,
+-- 
+2.34.1
+
diff --git a/patches/0553-net-hns3-add-support-clear-mac-statistics.patch b/patches/0553-net-hns3-add-support-clear-mac-statistics.patch
new file mode 100644
index 0000000..68643e9
--- /dev/null
+++ b/patches/0553-net-hns3-add-support-clear-mac-statistics.patch
@@ -0,0 +1,170 @@
+From ad541929e9a08a43d89cdc4b824b8c11d6dc53da Mon Sep 17 00:00:00 2001
+From: shaojijie <shaojijie@huawei.com>
+Date: Thu, 16 Mar 2023 10:32:30 +0800
+Subject: [PATCH 192/283] net: hns3: add support clear mac statistics
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+Some scenes use the standard tools ethtool and ifconfig to query traffic
+statistics in a specified period.To facilitate calculation, the driver
+needs to clear the original statistics first. The patch provides an
+customized interface for clearing MAC statistics.
+
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+---
+ .../net/ethernet/hisilicon/hns3/hnae3_ext.h   | 31 ++++++++++++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    | 40 +++++++++++++++++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |  1 +
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 17 ++++++++
+ 4 files changed, 89 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+index 0b1fa53dfb41..1cb43732bf3c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+@@ -28,5 +28,36 @@ enum hnae3_event_type_custom {
+ enum hnae3_ext_opcode {
+ 	HNAE3_EXT_OPC_RESET,
+ 	HNAE3_EXT_OPC_EVENT_CALLBACK,
++	HNAE3_EXT_OPC_GET_PFC_STORM_PARA,
++	HNAE3_EXT_OPC_SET_PFC_STORM_PARA,
++	HNAE3_EXT_OPC_SET_NOTIFY_PARAM,
++	HNAE3_EXT_OPC_SET_NOTIFY_START,
++	HNAE3_EXT_OPC_SET_TORUS_PARAM,
++	HNAE3_EXT_OPC_GET_TORUS_PARAM,
++	HNAE3_EXT_OPC_CLEAN_STATS64,
++};
++
++struct hnae3_pfc_storm_para {
++	u32 dir;
++	u32 enable;
++	u32 period_ms;
++	u32 times;
++	u32 recovery_period_ms;
++};
++
++struct hnae3_notify_pkt_param {
++	/* inter-packet gap of sending, the unit is one cycle of clock */
++	u32 ipg;
++	u16 num;     /* packet number of sending */
++	u8 enable;   /* send enable, 0=Disable, 1=Enable */
++	/* initialization flag, product does not need to set value */
++	u8 init;
++	u8 data[64]; /* note packet data */
++};
++
++struct hnae3_torus_param {
++	u32 enable;       /* 1d torus mode enable */
++	u32 mac_id;       /* export mac id of port */
++	u8 is_node0;      /* if current node is node0 */
+ };
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 34aadd10feb8..19ecd73e740c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -74,3 +74,43 @@ void nic_chip_recover_handler(struct net_device *ndev,
+ 			   &event_t, sizeof(event_t));
+ }
+ EXPORT_SYMBOL(nic_chip_recover_handler);
++
++int nic_clean_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats)
++{
++	struct hnae3_knic_private_info *kinfo;
++	struct hns3_enet_ring *ring;
++	struct hns3_nic_priv *priv;
++	struct hnae3_handle *h;
++	int i, ret;
++
++	priv = netdev_priv(ndev);
++	h = hns3_get_handle(ndev);
++	kinfo = &h->kinfo;
++
++	rtnl_lock();
++	if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
++	    test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) {
++		ret = -EBUSY;
++		goto end_unlock;
++	}
++
++	ret = nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_CLEAN_STATS64,
++				 NULL, 0);
++	if (ret)
++		goto end_unlock;
++
++	for (i = 0; i < kinfo->num_tqps; i++) {
++		ring = &priv->ring[i];
++		memset(&ring->stats, 0, sizeof(struct ring_stats));
++		ring = &priv->ring[i + kinfo->num_tqps];
++		memset(&ring->stats, 0, sizeof(struct ring_stats));
++	}
++
++	memset(&ndev->stats, 0, sizeof(struct net_device_stats));
++	netdev_info(ndev, "clean stats succ\n");
++
++end_unlock:
++	rtnl_unlock();
++	return ret;
++}
++EXPORT_SYMBOL(nic_clean_stats64);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index ce92a666db17..18c3d514ebf1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -10,4 +10,5 @@
+ int nic_netdev_match_check(struct net_device *netdev);
+ void nic_chip_recover_handler(struct net_device *ndev,
+ 			      enum hnae3_event_type_custom event_t);
++int nic_clean_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index 52c7f5085cfb..a79451ef44d0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -17,6 +17,22 @@ static nic_event_fn_t nic_event_call;
+  */
+ static DEFINE_MUTEX(hclge_nic_event_lock);
+ 
++static int hclge_clean_stats64(struct hclge_dev *hdev, void *data,
++			       size_t length)
++{
++	struct hnae3_knic_private_info *kinfo;
++	struct hclge_tqp *tqp;
++	int i;
++
++	kinfo = &hdev->vport[0].nic.kinfo;
++	for (i = 0; i < kinfo->num_tqps; i++) {
++		tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
++		memset(&tqp->tqp_stats, 0, sizeof(struct hlcge_tqp_stats));
++	}
++	memset(&hdev->mac_stats, 0, sizeof(struct hclge_mac_stats));
++	return 0;
++}
++
+ static int hclge_set_reset_task(struct hclge_dev *hdev, void *data,
+ 				size_t length)
+ {
+@@ -153,6 +169,7 @@ void hclge_ext_reset_end(struct hclge_dev *hdev, bool done)
+ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_RESET] = hclge_set_reset_task,
+ 	[HNAE3_EXT_OPC_EVENT_CALLBACK] = hclge_nic_call_event,
++	[HNAE3_EXT_OPC_CLEAN_STATS64] = hclge_clean_stats64,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+-- 
+2.34.1
+
diff --git a/patches/0554-net-hns3-add-support-configuring-function-level-inte.patch b/patches/0554-net-hns3-add-support-configuring-function-level-inte.patch
new file mode 100644
index 0000000..18795fc
--- /dev/null
+++ b/patches/0554-net-hns3-add-support-configuring-function-level-inte.patch
@@ -0,0 +1,100 @@
+From 0da9cdd2a66040323f993b7d0907ed08efc64188 Mon Sep 17 00:00:00 2001
+From: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Date: Thu, 16 Mar 2023 14:44:35 +0800
+Subject: [PATCH 193/283] net: hns3: add support configuring function-level
+ interrupt affinity
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+The patch provides a customized interface for configuring the interrupt
+affinity of the hns3 network port.
+
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    | 56 +++++++++++++++++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |  1 +
+ 2 files changed, 57 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 19ecd73e740c..4af709b1dc40 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -114,3 +114,59 @@ int nic_clean_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats)
+ 	return ret;
+ }
+ EXPORT_SYMBOL(nic_clean_stats64);
++
++int nic_set_cpu_affinity(struct net_device *ndev, cpumask_t *affinity_mask)
++{
++	struct hns3_enet_tqp_vector *tqp_vector;
++	struct hns3_nic_priv *priv;
++	int ret = 0;
++	u16 i;
++
++	if (!ndev || !affinity_mask) {
++		netdev_err(ndev,
++			   "Invalid input param when set ethernet cpu affinity\n");
++		return -EINVAL;
++	}
++
++	if (nic_netdev_match_check(ndev))
++		return -ENODEV;
++
++	priv = netdev_priv(ndev);
++	rtnl_lock();
++	if (!test_bit(HNS3_NIC_STATE_INITED, &priv->state) ||
++	    test_bit(HNS3_NIC_STATE_RESETTING, &priv->state)) {
++		ret = -EBUSY;
++		goto err_unlock;
++	}
++
++	for (i = 0; i < priv->vector_num; i++) {
++		tqp_vector = &priv->tqp_vector[i];
++		if (tqp_vector->irq_init_flag != HNS3_VECTOR_INITED)
++			continue;
++
++		tqp_vector->affinity_mask = *affinity_mask;
++
++		ret = irq_set_affinity_hint(tqp_vector->vector_irq, NULL);
++		if (ret) {
++			netdev_err(ndev,
++				   "failed to reset affinity hint, ret = %d\n", ret);
++			goto err_unlock;
++		}
++
++		ret = irq_set_affinity_hint(tqp_vector->vector_irq,
++					    &tqp_vector->affinity_mask);
++		if (ret) {
++			netdev_err(ndev,
++				   "failed to set affinity hint, ret = %d\n", ret);
++			goto err_unlock;
++		}
++	}
++
++	netdev_info(ndev, "set nic cpu affinity %*pb succeed\n",
++		    cpumask_pr_args(affinity_mask));
++
++err_unlock:
++	rtnl_unlock();
++	return ret;
++}
++EXPORT_SYMBOL(nic_set_cpu_affinity);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index 18c3d514ebf1..c0d943050922 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -11,4 +11,5 @@ int nic_netdev_match_check(struct net_device *netdev);
+ void nic_chip_recover_handler(struct net_device *ndev,
+ 			      enum hnae3_event_type_custom event_t);
+ int nic_clean_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats);
++int nic_set_cpu_affinity(struct net_device *ndev, cpumask_t *affinity_mask);
+ #endif
+-- 
+2.34.1
+
diff --git a/patches/0555-net-hns3-add-supports-fast-reporting-of-faulty-nodes.patch b/patches/0555-net-hns3-add-supports-fast-reporting-of-faulty-nodes.patch
new file mode 100644
index 0000000..6895f87
--- /dev/null
+++ b/patches/0555-net-hns3-add-supports-fast-reporting-of-faulty-nodes.patch
@@ -0,0 +1,304 @@
+From bdb17a497df12e7315c56647305899cf194db751 Mon Sep 17 00:00:00 2001
+From: shaojijie <shaojijie@huawei.com>
+Date: Thu, 16 Mar 2023 16:00:17 +0800
+Subject: [PATCH 194/283] net: hns3: add supports fast reporting of faulty
+ nodes
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+Services are switched only when no response is received within 10 seconds.
+As a result, services cannot be switched quickly. Therefore, if the chip
+is not suspended, the NIC sends a specific message to notify other nodes
+of the event. In this way, the service switchover is performed quickly.
+
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Tian Jiang <jiangtian6@h-partners.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  5 +
+ .../hns3/hns3_common/hclge_comm_cmd.c         |  1 +
+ .../hns3/hns3_common/hclge_comm_cmd.h         |  1 +
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    | 16 +++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |  3 +
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 98 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ext.h         | 29 ++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  1 +
+ 8 files changed, 154 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 970ef08ce9cc..838bb4956ee4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -103,6 +103,8 @@ enum HNAE3_DEV_CAP_BITS {
+ 	HNAE3_DEV_SUPPORT_CQ_B,
+ 	HNAE3_DEV_SUPPORT_LANE_NUM_B,
+ 	HNAE3_DEV_SUPPORT_WOL_B,
++	HNAE3_DEV_SUPPORT_VF_FAULT_B,
++	HNAE3_DEV_SUPPORT_NOTIFY_PKT_B,
+ };
+ 
+ #define hnae3_ae_dev_fd_supported(ae_dev) \
+@@ -174,6 +176,9 @@ enum HNAE3_DEV_CAP_BITS {
+ #define hnae3_ae_dev_wol_supported(ae_dev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_WOL_B, (ae_dev)->caps)
+ 
++#define hnae3_ae_dev_notify_pkt_supported(ae_dev) \
++	test_bit(HNAE3_DEV_SUPPORT_NOTIFY_PKT_B, (ae_dev)->caps)
++
+ enum HNAE3_PF_CAP_BITS {
+ 	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
+ };
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index a899b4c535dd..2cb06661bef9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -154,6 +154,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = {
+ 	{HCLGE_COMM_CAP_FD_B, HNAE3_DEV_SUPPORT_FD_B},
+ 	{HCLGE_COMM_CAP_LANE_NUM_B, HNAE3_DEV_SUPPORT_LANE_NUM_B},
+ 	{HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},
++	{HCLGE_COMM_CAP_NOTIFY_PKT_B, HNAE3_DEV_SUPPORT_NOTIFY_PKT_B},
+ };
+ 
+ static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 13562209f74d..05b8252c2522 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -97,6 +97,7 @@ enum HCLGE_COMM_CAP_BITS {
+ 	HCLGE_COMM_CAP_FD_B = 21,
+ 	HCLGE_COMM_CAP_LANE_NUM_B = 27,
+ 	HCLGE_COMM_CAP_WOL_B = 28,
++	HCLGE_COMM_CAP_NOTIFY_PKT_B = 29,
+ };
+ 
+ enum HCLGE_COMM_API_CAP_BITS {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 4af709b1dc40..08ef05d76b57 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -170,3 +170,19 @@ int nic_set_cpu_affinity(struct net_device *ndev, cpumask_t *affinity_mask)
+ 	return ret;
+ }
+ EXPORT_SYMBOL(nic_set_cpu_affinity);
++
++int nic_set_notify_pkt_param(struct net_device *ndev,
++			     struct hnae3_notify_pkt_param *param)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_SET_NOTIFY_PARAM,
++				  param, sizeof(*param));
++}
++EXPORT_SYMBOL(nic_set_notify_pkt_param);
++
++int nic_set_notify_pkt_start(struct net_device *ndev)
++{
++	return nic_invoke_pri_ops(ndev,
++				  HNAE3_EXT_OPC_SET_NOTIFY_START,
++				  NULL, 0);
++}
++EXPORT_SYMBOL(nic_set_notify_pkt_start);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index c0d943050922..ec661b400f20 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -12,4 +12,7 @@ void nic_chip_recover_handler(struct net_device *ndev,
+ 			      enum hnae3_event_type_custom event_t);
+ int nic_clean_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats);
+ int nic_set_cpu_affinity(struct net_device *ndev, cpumask_t *affinity_mask);
++int nic_set_notify_pkt_param(struct net_device *ndev,
++			     struct hnae3_notify_pkt_param *param);
++int nic_set_notify_pkt_start(struct net_device *ndev);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index a79451ef44d0..ba612b21a8ee 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -33,6 +33,101 @@ static int hclge_clean_stats64(struct hclge_dev *hdev, void *data,
+ 	return 0;
+ }
+ 
++static int hclge_notify_packet_para_cmd_send(struct hclge_dev *hdev,
++					     struct hclge_notify_pkt_param_cmd *param_cmd)
++{
++#define HCLGE_NOTIFY_PKT_DESC_NUM 4
++
++	struct hclge_desc desc[HCLGE_NOTIFY_PKT_DESC_NUM];
++	u32 i, desc_data_len;
++
++	desc_data_len = ARRAY_SIZE(desc[0].data);
++	for (i = 0; i < HCLGE_NOTIFY_PKT_DESC_NUM; i++) {
++		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_SET_NOTIFY_PKT,
++					   false);
++		if (i != HCLGE_NOTIFY_PKT_DESC_NUM - 1)
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
++	}
++
++	for (i = 0; i < HCLGE_NOTIFY_PKT_DESC_NUM * desc_data_len; i++)
++		desc[i / desc_data_len].data[i % desc_data_len] =
++						     *((__le32 *)param_cmd + i);
++
++	return hclge_cmd_send(&hdev->hw, desc, HCLGE_NOTIFY_PKT_DESC_NUM);
++}
++
++static int hclge_set_notify_packet_para(struct hclge_dev *hdev,
++					void *data, size_t length)
++{
++	struct hnae3_notify_pkt_param *param = (struct hnae3_notify_pkt_param *)data;
++	struct hclge_notify_pkt_param_cmd param_cmd;
++	u32 i, pkt_cfg = 0;
++	int ret;
++
++	if (length != sizeof(struct hnae3_notify_pkt_param))
++		return -EINVAL;
++
++	if (!hnae3_ae_dev_notify_pkt_supported(hdev->ae_dev))
++		return -EOPNOTSUPP;
++
++	if (param->enable)
++		pkt_cfg = HCLGE_NOTIFY_PARA_CFG_PKT_EN;
++	hnae3_set_field(pkt_cfg, HCLGE_NOTIFY_PARA_CFG_PKT_NUM_M,
++			HCLGE_NOTIFY_PARA_CFG_PKT_NUM_S, param->num);
++
++	param_cmd.cfg = cpu_to_le32(pkt_cfg);
++	param_cmd.ipg = cpu_to_le32(param->ipg);
++	for (i = 0; i < ARRAY_SIZE(param_cmd.data); i++)
++		param_cmd.data[i] = cpu_to_le32(*((u32 *)param->data + i));
++
++	hnae3_set_bit(param_cmd.vld_cfg, 0, 1);
++	hnae3_set_bit(param_cmd.vld_ipg, 0, 1);
++	hnae3_set_bit(param_cmd.vld_data, 0, 1);
++
++	ret = hclge_notify_packet_para_cmd_send(hdev, &param_cmd);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to set notify packet content, ret = %d\n", ret);
++		return ret;
++	}
++
++	param->init = 1;
++	memcpy(&hdev->notify_param, param, sizeof(*param));
++	return 0;
++}
++
++static int hclge_set_notify_packet_start(struct hclge_dev *hdev,
++					 void *data, size_t length)
++{
++	u32 pkt_cfg = HCLGE_NOTIFY_PARA_CFG_START_EN;
++	struct hclge_notify_pkt_param_cmd param_cmd;
++	int ret;
++
++	if (!hnae3_ae_dev_notify_pkt_supported(hdev->ae_dev))
++		return -EOPNOTSUPP;
++
++	memset(&param_cmd, 0, sizeof(param_cmd));
++	param_cmd.cfg = cpu_to_le32(pkt_cfg);
++	hnae3_set_bit(param_cmd.vld_cfg, 0, 1);
++
++	ret = hclge_notify_packet_para_cmd_send(hdev, &param_cmd);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to send notify packet, ret = %d\n", ret);
++	return ret;
++}
++
++static void hclge_ext_resotre_config(struct hclge_dev *hdev)
++{
++	if (hdev->reset_type != HNAE3_IMP_RESET &&
++	    hdev->reset_type != HNAE3_GLOBAL_RESET)
++		return;
++
++	if (hdev->notify_param.init)
++		hclge_set_notify_packet_para(hdev, &hdev->notify_param,
++					     sizeof(hdev->notify_param));
++}
++
+ static int hclge_set_reset_task(struct hclge_dev *hdev, void *data,
+ 				size_t length)
+ {
+@@ -162,6 +257,7 @@ void hclge_ext_reset_end(struct hclge_dev *hdev, bool done)
+ 		return;
+ 	}
+ 
++	hclge_ext_resotre_config(hdev);
+ 	hclge_ext_call_event(hdev, HNAE3_RESET_DONE_CUSTOM);
+ 	dev_info(&hdev->pdev->dev, "report reset done!\n");
+ }
+@@ -170,6 +266,8 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_RESET] = hclge_set_reset_task,
+ 	[HNAE3_EXT_OPC_EVENT_CALLBACK] = hclge_nic_call_event,
+ 	[HNAE3_EXT_OPC_CLEAN_STATS64] = hclge_clean_stats64,
++	[HNAE3_EXT_OPC_SET_NOTIFY_PARAM] = hclge_set_notify_packet_para,
++	[HNAE3_EXT_OPC_SET_NOTIFY_START] = hclge_set_notify_packet_start,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+index 1c1b04765e7e..ce8fc17741fc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -5,6 +5,35 @@
+ #define __HCLGE_EXT_H
+ #include <linux/types.h>
+ 
++#define HCLGE_NOTIFY_PARA_CFG_PKT_EN		BIT(0)
++#define HCLGE_NOTIFY_PARA_CFG_START_EN		BIT(1)
++#define HCLGE_NOTIFY_PARA_CFG_PKT_NUM_M		GENMASK(5, 2)
++#define HCLGE_NOTIFY_PARA_CFG_PKT_NUM_S		2
++
++struct hclge_pfc_storm_para_cmd {
++	__le32 dir;
++	__le32 enable;
++	__le32 period_ms;
++	__le32 times;
++	__le32 recovery_period_ms;
++	__le32 rsv;
++};
++
++struct hclge_notify_pkt_param_cmd {
++	__le32 cfg;
++	__le32 ipg;
++	__le32 data[16];
++	u8 vld_cfg;
++	u8 vld_ipg;
++	u8 vld_data;
++	u8 rsv[21];
++};
++
++enum hclge_ext_opcode_type {
++	HCLGE_OPC_SET_NOTIFY_PKT = 0x180A,
++	HCLGE_OPC_CFG_PAUSE_STORM_PARA = 0x7019,
++};
++
+ struct hclge_reset_fail_type_map {
+ 	enum hnae3_reset_type reset_type;
+ 	enum hnae3_event_type_custom custom_type;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index f32c8b52f022..647b0ca14e1c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -943,6 +943,7 @@ struct hclge_dev {
+ 	cpumask_t affinity_mask;
+ 	struct irq_affinity_notify affinity_notify;
+ 	struct hclge_ptp *ptp;
++	struct hnae3_notify_pkt_param notify_param;
+ };
+ 
+ /* VPort level vlan tag configuration for TX direction */
+-- 
+2.34.1
+
diff --git a/patches/0556-net-hns3-add-support-to-get-set-1d-torus-param.patch b/patches/0556-net-hns3-add-support-to-get-set-1d-torus-param.patch
new file mode 100644
index 0000000..ef865e7
--- /dev/null
+++ b/patches/0556-net-hns3-add-support-to-get-set-1d-torus-param.patch
@@ -0,0 +1,373 @@
+From 34f08dce1aaa08005809cc4243e8ada45bc32f99 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao418@huawei.com>
+Date: Thu, 16 Mar 2023 17:14:05 +0800
+Subject: [PATCH 195/283] net: hns3: add support to get/set 1d torus param
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+Two network ports on a single chip can be physically connected to form
+a 1d torus topology. TCP/UDP and RDMA communication between chip nodes
+can be implemented without switches.The patch provide interfaces for
+getting/setting 1d torus param.
+
+Signed-off-by: Hao Chen <chenhao418@huawei.com>
+Signed-off-by: Tian Jiang <jiangtian6@h-partners.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+---
+ .../hns3/hns3_common/hclge_comm_cmd.h         |   1 +
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    |  19 ++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |   4 +
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 194 ++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ext.h         |  29 +++
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   1 +
+ 6 files changed, 248 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 05b8252c2522..8f07dc44b30a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -204,4 +204,5 @@ void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring);
+ void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
+ 				     enum hclge_opcode_type opcode,
+ 				     bool is_read);
++void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 08ef05d76b57..1e1b1fb81f17 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -186,3 +186,22 @@ int nic_set_notify_pkt_start(struct net_device *ndev)
+ 				  NULL, 0);
+ }
+ EXPORT_SYMBOL(nic_set_notify_pkt_start);
++
++int nic_set_torus_param(struct net_device *ndev,
++			struct hnae3_torus_param *param)
++{
++	if (!param || (param->enable != 0 && param->enable != 1))
++		return -EINVAL;
++
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_SET_TORUS_PARAM,
++				  param, sizeof(*param));
++}
++EXPORT_SYMBOL(nic_set_torus_param);
++
++int nic_get_torus_param(struct net_device *ndev,
++			struct hnae3_torus_param *param)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_GET_TORUS_PARAM,
++				  param, sizeof(*param));
++}
++EXPORT_SYMBOL(nic_get_torus_param);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index ec661b400f20..1a8573efa642 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -15,4 +15,8 @@ int nic_set_cpu_affinity(struct net_device *ndev, cpumask_t *affinity_mask);
+ int nic_set_notify_pkt_param(struct net_device *ndev,
+ 			     struct hnae3_notify_pkt_param *param);
+ int nic_set_notify_pkt_start(struct net_device *ndev);
++int nic_set_torus_param(struct net_device *ndev,
++			struct hnae3_torus_param *param);
++int nic_get_torus_param(struct net_device *ndev,
++			struct hnae3_torus_param *param);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index ba612b21a8ee..8097f7079760 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -17,6 +17,16 @@ static nic_event_fn_t nic_event_call;
+  */
+ static DEFINE_MUTEX(hclge_nic_event_lock);
+ 
++void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
++{
++	desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR |
++				 HCLGE_COMM_CMD_FLAG_IN);
++	if (is_read)
++		desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR);
++	else
++		desc->flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_WR);
++}
++
+ static int hclge_clean_stats64(struct hclge_dev *hdev, void *data,
+ 			       size_t length)
+ {
+@@ -117,6 +127,185 @@ static int hclge_set_notify_packet_start(struct hclge_dev *hdev,
+ 	return ret;
+ }
+ 
++static int hclge_torus_cfg_switch(struct hclge_dev *hdev, bool is_rocee,
++				  bool enabled)
++{
++	struct hclge_mac_vlan_switch_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SWITCH_PARAM, true);
++	req = (struct hclge_mac_vlan_switch_cmd *)desc.data;
++	req->roce_sel = is_rocee ? 1 : 0;
++	/* set 0 to let firmware choose current function */
++	req->func_id = 0;
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get switch param, ret = %d\n", ret);
++		return ret;
++	}
++
++	hnae3_set_bit(req->switch_param, HCLGE_SWITCH_ALW_LPBK_B, 1);
++	hnae3_set_bit(req->switch_param, HCLGE_SWITCH_ALW_LCL_LPBK_B, 0);
++	hnae3_set_bit(req->switch_param, HCLGE_SWITCH_ANTI_SPOOF_B, enabled);
++	if (!is_rocee)
++		hnae3_set_bit(req->switch_param, HCLGE_SWITCH_ALW_DST_OVRD_B,
++			      enabled);
++
++	hclge_comm_cmd_reuse_desc(&desc, false);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to set switch param, ret = %d\n", ret);
++
++	return ret;
++}
++
++static int hclge_torus_cfg_vlan_filter(struct hclge_dev *hdev,
++				       bool enabled)
++{
++	struct hclge_vlan_filter_ctrl_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_VLAN_FILTER, true);
++	req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
++	req->vlan_type = HCLGE_FILTER_TYPE_PORT;
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get torus vlan filter, ret = %d\n", ret);
++		return ret;
++	}
++
++	hnae3_set_bit(req->vlan_fe, HCLGE_VLAN_FE_NIC_INGRESS, !enabled);
++	hnae3_set_bit(req->vlan_fe, HCLGE_VLAN_FE_ROCEE_INGRESS, !enabled);
++	req->vlan_type = HCLGE_FILTER_TYPE_PORT;
++
++	hclge_comm_cmd_reuse_desc(&desc, false);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to set torus vlan filter, ret = %d\n", ret);
++
++	return ret;
++}
++
++static int hclge_torus_cfg(struct hclge_dev *hdev,
++			   struct hnae3_torus_param *param)
++{
++	struct hclge_torus_cfg_cmd *req;
++	struct hclge_desc desc;
++	u32 lan_fwd_tc_cfg = 0;
++	u32 lan_port_pair = 0;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_1D_TORUS, true);
++	req = (struct hclge_torus_cfg_cmd *)desc.data;
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get torus config, ret = %d\n", ret);
++		return ret;
++	}
++
++	req->lan_port_pair = cpu_to_le32(param->mac_id &
++					 HCLGE_TORUS_MAC_ID_MASK);
++	hnae3_set_bit(lan_port_pair, HCLGE_UC_LAN_PAIR_EN, 1);
++	hnae3_set_bit(lan_port_pair, HCLGE_MC_BC_LAN_PAIR_EN, 1);
++	hnae3_set_bit(lan_port_pair, HCLGE_LLDP_LAN_PAIR_EN, 1);
++	hnae3_set_bit(lan_port_pair, HCLGE_TC2VLANPRI_MAPPING_EN, 1);
++	hnae3_set_bit(lan_port_pair, HCLGE_TORUS_LPBK_DROP_EN, 1);
++	if (param->enable)
++		req->lan_port_pair |= cpu_to_le32(lan_port_pair);
++
++	if (!param->is_node0) {
++		req->lan_fwd_tc_cfg &= cpu_to_le32(~HCLGE_TORUS_TC1_DROP_EN);
++		lan_fwd_tc_cfg &= ~HCLGE_TOURS_TCX_MAP_TCY_MASK;
++		lan_fwd_tc_cfg |= HCLGE_TOURS_TCX_MAP_TCY_INIT &
++				  HCLGE_TOURS_TCX_MAP_TCY_MASK;
++		req->lan_fwd_tc_cfg |= cpu_to_le32(lan_fwd_tc_cfg);
++	} else {
++		req->lan_fwd_tc_cfg |= cpu_to_le32(HCLGE_TORUS_TC1_DROP_EN);
++		lan_fwd_tc_cfg &= ~HCLGE_TOURS_TCX_MAP_TCY_MASK;
++		lan_fwd_tc_cfg |= HCLGE_TOURS_TCX_MAP_TCY_NODE0_INIT &
++				  HCLGE_TOURS_TCX_MAP_TCY_MASK;
++		req->lan_fwd_tc_cfg |= cpu_to_le32(lan_fwd_tc_cfg);
++	}
++
++	req->torus_en = cpu_to_le32(param->enable);
++	hclge_comm_cmd_reuse_desc(&desc, false);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev, "failed to set torus, ret = %d\n",
++			ret);
++
++	return ret;
++}
++
++static int hclge_set_torus_param(struct hclge_dev *hdev, void *data,
++				 size_t length)
++{
++	struct hnae3_torus_param *param = (struct hnae3_torus_param *)data;
++	int ret;
++
++	if (length != sizeof(struct hnae3_torus_param))
++		return -EINVAL;
++
++	ret = hclge_torus_cfg_switch(hdev, false, !!param->enable);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to config nic switch param, ret = %d\n", ret);
++		return ret;
++	}
++
++	ret = hclge_torus_cfg_switch(hdev, true, !!param->enable);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to config roce switch param, ret = %d\n", ret);
++		return ret;
++	}
++
++	ret = hclge_torus_cfg_vlan_filter(hdev, !!param->enable);
++	if (ret)
++		return ret;
++
++	ret = hclge_torus_cfg(hdev, param);
++	if (ret)
++		return ret;
++
++	hdev->torus_param = *param;
++	return 0;
++}
++
++static int hclge_get_torus_param(struct hclge_dev *hdev, void *data,
++				 size_t length)
++{
++	struct hnae3_torus_param *param = (struct hnae3_torus_param *)data;
++	struct hclge_torus_cfg_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(struct hnae3_torus_param))
++		return -EINVAL;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_1D_TORUS, true);
++	req = (struct hclge_torus_cfg_cmd *)desc.data;
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get torus param, ret = %d\n", ret);
++		return ret;
++	}
++
++	param->mac_id =
++		le32_to_cpu(req->lan_port_pair) & HCLGE_TORUS_MAC_ID_MASK;
++	param->enable = le32_to_cpu(req->torus_en);
++
++	return 0;
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+@@ -126,6 +315,9 @@ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ 	if (hdev->notify_param.init)
+ 		hclge_set_notify_packet_para(hdev, &hdev->notify_param,
+ 					     sizeof(hdev->notify_param));
++
++	hclge_set_torus_param(hdev, &hdev->torus_param,
++			      sizeof(hdev->torus_param));
+ }
+ 
+ static int hclge_set_reset_task(struct hclge_dev *hdev, void *data,
+@@ -268,6 +460,8 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_CLEAN_STATS64] = hclge_clean_stats64,
+ 	[HNAE3_EXT_OPC_SET_NOTIFY_PARAM] = hclge_set_notify_packet_para,
+ 	[HNAE3_EXT_OPC_SET_NOTIFY_START] = hclge_set_notify_packet_start,
++	[HNAE3_EXT_OPC_SET_TORUS_PARAM] = hclge_set_torus_param,
++	[HNAE3_EXT_OPC_GET_TORUS_PARAM] = hclge_get_torus_param,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+index ce8fc17741fc..abdb00e78fc3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -10,6 +10,23 @@
+ #define HCLGE_NOTIFY_PARA_CFG_PKT_NUM_M		GENMASK(5, 2)
+ #define HCLGE_NOTIFY_PARA_CFG_PKT_NUM_S		2
+ 
++#define HCLGE_TORUS_MAC_ID_MASK 0x3
++#define HCLGE_TOURS_TCX_MAP_TCY_INIT 0x1c6144
++#define HCLGE_TOURS_TCX_MAP_TCY_NODE0_INIT 0x1c6141
++
++#define HCLGE_VLAN_FE_NIC_INGRESS 0
++#define HCLGE_VLAN_FE_ROCEE_INGRESS 2
++
++#define HCLGE_TORUS_LPBK_DROP_EN 20
++#define HCLGE_TC2VLANPRI_MAPPING_EN 19
++#define HCLGE_LLDP_LAN_PAIR_EN 18
++#define HCLGE_MC_BC_LAN_PAIR_EN 17
++#define HCLGE_UC_LAN_PAIR_EN 16
++
++#define HCLGE_TORUS_TC1_DROP_EN BIT(26)
++
++#define HCLGE_TOURS_TCX_MAP_TCY_MASK 0x1c71c7
++
+ struct hclge_pfc_storm_para_cmd {
+ 	__le32 dir;
+ 	__le32 enable;
+@@ -29,8 +46,20 @@ struct hclge_notify_pkt_param_cmd {
+ 	u8 rsv[21];
+ };
+ 
++struct hclge_torus_cfg_cmd {
++	u8 rsv[4];
++	__le32 lan_port_pair;
++	__le32 lan_fwd_tc_cfg;
++	__le32 pause_time_out;
++	__le32 pause_time_out_en;
++	__le32 torus_en;
++};
++
+ enum hclge_ext_opcode_type {
++	HCLGE_OPC_CONFIG_SWITCH_PARAM = 0x1033,
++	HCLGE_OPC_CONFIG_VLAN_FILTER = 0x1100,
+ 	HCLGE_OPC_SET_NOTIFY_PKT = 0x180A,
++	HCLGE_OPC_CONFIG_1D_TORUS = 0x2300,
+ 	HCLGE_OPC_CFG_PAUSE_STORM_PARA = 0x7019,
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 647b0ca14e1c..7a505d1195ef 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -944,6 +944,7 @@ struct hclge_dev {
+ 	struct irq_affinity_notify affinity_notify;
+ 	struct hclge_ptp *ptp;
+ 	struct hnae3_notify_pkt_param notify_param;
++	struct hnae3_torus_param torus_param;
+ };
+ 
+ /* VPort level vlan tag configuration for TX direction */
+-- 
+2.34.1
+
diff --git a/patches/0557-net-hns3-add-support-query-port-ext-information.patch b/patches/0557-net-hns3-add-support-query-port-ext-information.patch
new file mode 100644
index 0000000..1b8faa9
--- /dev/null
+++ b/patches/0557-net-hns3-add-support-query-port-ext-information.patch
@@ -0,0 +1,351 @@
+From bac4441b4906c8d32fbdf1b2fde111a0f6a3b7bf Mon Sep 17 00:00:00 2001
+From: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Date: Fri, 17 Mar 2023 11:49:22 +0800
+Subject: [PATCH 196/283] net: hns3: add support query port ext information
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+The patch supports the query of port ext information.
+
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+---
+ .../net/ethernet/hisilicon/hns3/hnae3_ext.h   |  14 +++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    | 111 ++++++++++++++++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |  13 ++
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         |  91 ++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ext.h         |  21 ++++
+ 5 files changed, 250 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+index 1cb43732bf3c..baf9dfba872d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+@@ -35,6 +35,9 @@ enum hnae3_ext_opcode {
+ 	HNAE3_EXT_OPC_SET_TORUS_PARAM,
+ 	HNAE3_EXT_OPC_GET_TORUS_PARAM,
+ 	HNAE3_EXT_OPC_CLEAN_STATS64,
++	HNAE3_EXT_OPC_GET_PORT_EXT_ID_INFO,
++	HNAE3_EXT_OPC_GET_PORT_EXT_NUM_INFO,
++	HNAE3_EXT_OPC_GET_PORT_NUM,
+ };
+ 
+ struct hnae3_pfc_storm_para {
+@@ -60,4 +63,15 @@ struct hnae3_torus_param {
+ 	u32 mac_id;       /* export mac id of port */
+ 	u8 is_node0;      /* if current node is node0 */
+ };
++
++struct hane3_port_ext_id_info {
++	u32 chip_id;
++	u32 mac_id;
++	u32 io_die_id;
++};
++
++struct hane3_port_ext_num_info {
++	u32 chip_num;
++	u32 io_die_num;
++};
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 1e1b1fb81f17..889bef7bdb82 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -205,3 +205,114 @@ int nic_get_torus_param(struct net_device *ndev,
+ 				  param, sizeof(*param));
+ }
+ EXPORT_SYMBOL(nic_get_torus_param);
++static int nic_get_ext_id_info(struct net_device *ndev,
++			       struct hane3_port_ext_id_info *id_info)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_GET_PORT_EXT_ID_INFO,
++				  id_info, sizeof(*id_info));
++}
++
++int nic_get_chipid(struct net_device *ndev, u32 *chip_id)
++{
++	struct hane3_port_ext_id_info info;
++	int ret;
++
++	if (!chip_id)
++		return -EINVAL;
++
++	ret = nic_get_ext_id_info(ndev, &info);
++	if (ret)
++		return ret;
++
++	*chip_id = info.chip_id;
++	return 0;
++}
++EXPORT_SYMBOL(nic_get_chipid);
++
++int nic_get_mac_id(struct net_device *ndev, u32 *mac_id)
++{
++	struct hane3_port_ext_id_info info;
++	int ret;
++
++	if (!mac_id)
++		return -EINVAL;
++
++	ret = nic_get_ext_id_info(ndev, &info);
++	if (ret)
++		return ret;
++
++	*mac_id = info.mac_id;
++	return 0;
++}
++EXPORT_SYMBOL(nic_get_mac_id);
++
++int nic_get_io_die_id(struct net_device *ndev, u32 *io_die_id)
++{
++	struct hane3_port_ext_id_info info;
++	int ret;
++
++	if (!io_die_id)
++		return -EINVAL;
++
++	ret = nic_get_ext_id_info(ndev, &info);
++	if (ret)
++		return ret;
++
++	*io_die_id = info.io_die_id;
++	return 0;
++}
++EXPORT_SYMBOL(nic_get_io_die_id);
++
++static int nic_get_ext_num_info(struct net_device *ndev,
++				struct hane3_port_ext_num_info *num_info)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_GET_PORT_EXT_NUM_INFO,
++				  num_info, sizeof(*num_info));
++}
++
++int nic_get_chip_num(struct net_device *ndev, u32 *chip_num)
++{
++	struct hane3_port_ext_num_info info;
++	int ret;
++
++	if (!chip_num)
++		return -EINVAL;
++
++	ret = nic_get_ext_num_info(ndev, &info);
++	if (ret)
++		return ret;
++
++	*chip_num = info.chip_num;
++	return 0;
++}
++EXPORT_SYMBOL(nic_get_chip_num);
++
++int nic_get_io_die_num(struct net_device *ndev, u32 *io_die_num)
++{
++	struct hane3_port_ext_num_info info;
++	int ret;
++
++	if (!io_die_num)
++		return -EINVAL;
++
++	ret = nic_get_ext_num_info(ndev, &info);
++	if (ret)
++		return ret;
++
++	*io_die_num = info.io_die_num;
++	return 0;
++}
++EXPORT_SYMBOL(nic_get_io_die_num);
++
++int nic_get_port_num_of_die(struct net_device *ndev, u32 *port_num)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_GET_PORT_NUM,
++				  port_num, sizeof(*port_num));
++}
++EXPORT_SYMBOL(nic_get_port_num_of_die);
++
++int nic_get_port_num_per_chip(struct net_device *ndev, u32 *port_num)
++{
++	return nic_get_port_num_of_die(ndev, port_num);
++}
++EXPORT_SYMBOL(nic_get_port_num_per_chip);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index 1a8573efa642..239293ace01e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -19,4 +19,17 @@ int nic_set_torus_param(struct net_device *ndev,
+ 			struct hnae3_torus_param *param);
+ int nic_get_torus_param(struct net_device *ndev,
+ 			struct hnae3_torus_param *param);
++int nic_set_torus_param(struct net_device *ndev,
++			struct hnae3_torus_param *param);
++int nic_get_torus_param(struct net_device *ndev,
++			struct hnae3_torus_param *param);
++int nic_clean_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats);
++int nic_set_cpu_affinity(struct net_device *ndev, cpumask_t *affinity_mask);
++int nic_get_chipid(struct net_device *ndev, u32 *chip_id);
++int nic_get_mac_id(struct net_device *ndev, u32 *mac_id);
++int nic_get_io_die_id(struct net_device *ndev, u32 *io_die_id);
++int nic_get_chip_num(struct net_device *ndev, u32 *chip_num);
++int nic_get_io_die_num(struct net_device *ndev, u32 *io_die_num);
++int nic_get_port_num_of_die(struct net_device *ndev, u32 *port_num);
++int nic_get_port_num_per_chip(struct net_device *ndev, u32 *port_num);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index 8097f7079760..635f66dc37b1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -306,6 +306,94 @@ static int hclge_get_torus_param(struct hclge_dev *hdev, void *data,
+ 	return 0;
+ }
+ 
++static int hclge_get_info_from_cmd(struct hclge_dev *hdev,
++				   struct hclge_desc *desc, u32 num, int opcode)
++{
++	u32 i;
++
++	for (i = 0; i < num; i++) {
++		hclge_cmd_setup_basic_desc(desc + i, opcode, true);
++		if (i != num - 1)
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
++	}
++
++	return hclge_cmd_send(&hdev->hw, desc, num);
++}
++
++static int hclge_get_extend_port_id_info(struct hclge_dev *hdev,
++					 void *data, size_t length)
++{
++	struct hane3_port_ext_id_info *info;
++	struct hclge_id_info_cmd *info_cmd;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(struct hane3_port_ext_id_info))
++		return -EINVAL;
++
++	ret = hclge_get_info_from_cmd(hdev, &desc, 1, HCLGE_OPC_CHIP_ID_GET);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get extend port id info, ret = %d\n",
++			ret);
++		return ret;
++	}
++
++	info_cmd = (struct hclge_id_info_cmd *)desc.data;
++	info = (struct hane3_port_ext_id_info *)data;
++	info->chip_id = le32_to_cpu(info_cmd->chip_id);
++	info->mac_id = le32_to_cpu(info_cmd->mac_id);
++	info->io_die_id = le32_to_cpu(info_cmd->io_die_id);
++	return 0;
++}
++
++static int hclge_get_extend_port_num_info(struct hclge_dev *hdev,
++					  void *data, size_t length)
++{
++	struct hane3_port_ext_num_info *num_info;
++	struct hclge_num_info_cmd *resp;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(struct hane3_port_ext_num_info))
++		return -EINVAL;
++
++	ret = hclge_get_info_from_cmd(hdev, &desc, 1, HCLGE_OPC_GET_CHIP_NUM);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get extend port number info, ret = %d\n", ret);
++		return ret;
++	}
++
++	resp = (struct hclge_num_info_cmd *)(desc.data);
++	num_info = (struct hane3_port_ext_num_info *)data;
++	num_info->chip_num = le32_to_cpu(resp->chip_num);
++	num_info->io_die_num = le32_to_cpu(resp->io_die_num);
++	return 0;
++}
++
++static int hclge_get_port_num(struct hclge_dev *hdev, void *data,
++			      size_t length)
++{
++	struct hclge_port_num_info_cmd *resp;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(u32))
++		return -EINVAL;
++
++	ret = hclge_get_info_from_cmd(hdev, &desc, 1, HCLGE_OPC_GET_PORT_NUM);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get port number, ret = %d\n", ret);
++		return ret;
++	}
++
++	resp = (struct hclge_port_num_info_cmd *)(desc.data);
++	*(u32 *)data = le32_to_cpu(resp->port_num);
++	return 0;
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+@@ -462,6 +550,9 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_SET_NOTIFY_START] = hclge_set_notify_packet_start,
+ 	[HNAE3_EXT_OPC_SET_TORUS_PARAM] = hclge_set_torus_param,
+ 	[HNAE3_EXT_OPC_GET_TORUS_PARAM] = hclge_get_torus_param,
++	[HNAE3_EXT_OPC_GET_PORT_EXT_ID_INFO] = hclge_get_extend_port_id_info,
++	[HNAE3_EXT_OPC_GET_PORT_EXT_NUM_INFO] = hclge_get_extend_port_num_info,
++	[HNAE3_EXT_OPC_GET_PORT_NUM] = hclge_get_port_num,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+index abdb00e78fc3..f840129572c8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -27,6 +27,24 @@
+ 
+ #define HCLGE_TOURS_TCX_MAP_TCY_MASK 0x1c71c7
+ 
++struct hclge_id_info_cmd {
++	__le32 chip_id;
++	__le32 mac_id;
++	__le32 io_die_id;
++	u8 rsv[12];
++};
++
++struct hclge_num_info_cmd {
++	__le32 chip_num;
++	__le32 io_die_num;
++	u8 rsv[16];
++};
++
++struct hclge_port_num_info_cmd {
++	__le32 port_num;
++	u8 rsv[20];
++};
++
+ struct hclge_pfc_storm_para_cmd {
+ 	__le32 dir;
+ 	__le32 enable;
+@@ -60,6 +78,9 @@ enum hclge_ext_opcode_type {
+ 	HCLGE_OPC_CONFIG_VLAN_FILTER = 0x1100,
+ 	HCLGE_OPC_SET_NOTIFY_PKT = 0x180A,
+ 	HCLGE_OPC_CONFIG_1D_TORUS = 0x2300,
++	HCLGE_OPC_CHIP_ID_GET = 0x7003,
++	HCLGE_OPC_GET_CHIP_NUM = 0x7005,
++	HCLGE_OPC_GET_PORT_NUM = 0x7006,
+ 	HCLGE_OPC_CFG_PAUSE_STORM_PARA = 0x7019,
+ };
+ 
+-- 
+2.34.1
+
diff --git a/patches/0558-net-hns3-support-set-pfc-pause-trans-time.patch b/patches/0558-net-hns3-support-set-pfc-pause-trans-time.patch
new file mode 100644
index 0000000..e543b78
--- /dev/null
+++ b/patches/0558-net-hns3-support-set-pfc-pause-trans-time.patch
@@ -0,0 +1,247 @@
+From 7105e0796908cb12e13d97bd7c2953569a7c20b8 Mon Sep 17 00:00:00 2001
+From: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Date: Tue, 28 Mar 2023 21:49:32 +0800
+Subject: [PATCH 197/283] net: hns3: support set pfc pause trans time
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+The patch provides a customized interface to modify the pause trans time
+and retains the configured parameters.
+
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+---
+ .../net/ethernet/hisilicon/hns3/hnae3_ext.h   |  6 ++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    | 57 +++++++++++++++++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |  7 +++
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 37 ++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  1 +
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.c |  7 ++-
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.h |  2 +
+ 7 files changed, 114 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+index baf9dfba872d..5f1302488a1c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+@@ -38,6 +38,12 @@ enum hnae3_ext_opcode {
+ 	HNAE3_EXT_OPC_GET_PORT_EXT_ID_INFO,
+ 	HNAE3_EXT_OPC_GET_PORT_EXT_NUM_INFO,
+ 	HNAE3_EXT_OPC_GET_PORT_NUM,
++	HNAE3_EXT_OPC_GET_PRESENT,
++	HNAE3_EXT_OPC_SET_SFP_STATE,
++	HNAE3_EXT_OPC_DISABLE_LANE,
++	HNAE3_EXT_OPC_GET_LANE_STATUS,
++	HNAE3_EXT_OPC_DISABLE_CLOCK,
++	HNAE3_EXT_OPC_SET_PFC_TIME,
+ };
+ 
+ struct hnae3_pfc_storm_para {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 889bef7bdb82..9683099efb9c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -316,3 +316,60 @@ int nic_get_port_num_per_chip(struct net_device *ndev, u32 *port_num)
+ 	return nic_get_port_num_of_die(ndev, port_num);
+ }
+ EXPORT_SYMBOL(nic_get_port_num_per_chip);
++
++int nic_set_tx_timeout(struct net_device *ndev, int tx_timeout)
++{
++	if (nic_netdev_match_check(ndev))
++		return -ENODEV;
++
++	if (tx_timeout <= 0)
++		return -EINVAL;
++
++	ndev->watchdog_timeo = tx_timeout;
++
++	return 0;
++}
++EXPORT_SYMBOL(nic_set_tx_timeout);
++
++int nic_get_sfp_present(struct net_device *ndev, int *present)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_GET_PRESENT,
++				  present, sizeof(*present));
++}
++EXPORT_SYMBOL(nic_get_sfp_present);
++
++int nic_set_sfp_state(struct net_device *ndev, bool en)
++{
++	u32 state = en ? 1 : 0;
++
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_SET_SFP_STATE,
++				  &state, sizeof(state));
++}
++EXPORT_SYMBOL(nic_set_sfp_state);
++
++int nic_disable_net_lane(struct net_device *ndev)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_DISABLE_LANE, NULL, 0);
++}
++EXPORT_SYMBOL(nic_disable_net_lane);
++
++int nic_get_net_lane_status(struct net_device *ndev, u32 *status)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_GET_LANE_STATUS,
++				  status, sizeof(*status));
++}
++EXPORT_SYMBOL(nic_get_net_lane_status);
++
++int nic_disable_clock(struct net_device *ndev)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_DISABLE_CLOCK,
++				  NULL, 0);
++}
++EXPORT_SYMBOL(nic_disable_clock);
++
++int nic_set_pfc_time_cfg(struct net_device *ndev, u16 time)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_SET_PFC_TIME,
++				  &time, sizeof(time));
++}
++EXPORT_SYMBOL(nic_set_pfc_time_cfg);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index 239293ace01e..0f9d6683825e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -32,4 +32,11 @@ int nic_get_chip_num(struct net_device *ndev, u32 *chip_num);
+ int nic_get_io_die_num(struct net_device *ndev, u32 *io_die_num);
+ int nic_get_port_num_of_die(struct net_device *ndev, u32 *port_num);
+ int nic_get_port_num_per_chip(struct net_device *ndev, u32 *port_num);
++int nic_set_tx_timeout(struct net_device *ndev, int tx_timeout);
++int nic_get_sfp_present(struct net_device *ndev, int *present);
++int nic_set_sfp_state(struct net_device *ndev, bool en);
++int nic_disable_net_lane(struct net_device *ndev);
++int nic_get_net_lane_status(struct net_device *ndev, u32 *status);
++int nic_disable_clock(struct net_device *ndev);
++int nic_set_pfc_time_cfg(struct net_device *ndev, u16 time);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index 635f66dc37b1..0f4eff899e94 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -6,6 +6,7 @@
+ #include "hnae3_ext.h"
+ #include "hclge_cmd.h"
+ #include "hclge_ext.h"
++#include "hclge_tm.h"
+ 
+ #define HCLGE_RESET_MAX_FAIL_CNT 5
+ 
+@@ -394,6 +395,42 @@ static int hclge_get_port_num(struct hclge_dev *hdev, void *data,
+ 	return 0;
+ }
+ 
++static int hclge_set_pause_trans_time(struct hclge_dev *hdev, void *data,
++				      size_t length)
++{
++	struct hclge_cfg_pause_param_cmd *pause_param;
++	struct hclge_desc desc;
++	u16 pause_trans_time;
++	int ret;
++
++	if (length != sizeof(u16))
++		return -EINVAL;
++
++	pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
++	ret = hclge_get_info_from_cmd(hdev, &desc, 1, HCLGE_OPC_CFG_MAC_PARA);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get pause cfg info, ret = %d\n", ret);
++		return ret;
++	}
++
++	pause_trans_time = *(u16 *)data;
++	if (pause_trans_time == le16_to_cpu(pause_param->pause_trans_time))
++		return 0;
++
++	ret = hclge_pause_param_cfg(hdev, pause_param->mac_addr,
++				    pause_param->pause_trans_gap,
++				    pause_trans_time);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to set pause trans time, ret = %d\n", ret);
++		return ret;
++	}
++
++	hdev->tm_info.pause_time = pause_trans_time;
++	return 0;
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 7a505d1195ef..71ca13a29b51 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -421,6 +421,7 @@ struct hclge_tm_info {
+ 	enum hclge_fc_mode fc_mode;
+ 	u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
+ 	u8 pfc_en;	/* PFC enabled or not for user priority */
++	u16 pause_time;
+ };
+ 
+ /* max number of mac statistics on each version */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index 48382bfc84f6..ca93919ed817 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -185,8 +185,8 @@ static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
+ 	return hclge_cmd_send(&hdev->hw, &desc, 1);
+ }
+ 
+-static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
+-				 u8 pause_trans_gap, u16 pause_trans_time)
++int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
++			  u8 pause_trans_gap, u16 pause_trans_time)
+ {
+ 	struct hclge_cfg_pause_param_cmd *pause_param;
+ 	struct hclge_desc desc;
+@@ -1307,7 +1307,7 @@ static int hclge_pause_param_setup_hw(struct hclge_dev *hdev)
+ 
+ 	return hclge_pause_param_cfg(hdev, mac->mac_addr,
+ 				     HCLGE_DEFAULT_PAUSE_TRANS_GAP,
+-				     HCLGE_DEFAULT_PAUSE_TRANS_TIME);
++				     hdev->tm_info.pause_time);
+ }
+ 
+ static int hclge_pfc_setup_hw(struct hclge_dev *hdev)
+@@ -1494,6 +1494,7 @@ int hclge_tm_schd_init(struct hclge_dev *hdev)
+ 	/* fc_mode is HCLGE_FC_FULL on reset */
+ 	hdev->tm_info.fc_mode = HCLGE_FC_FULL;
+ 	hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
++	hdev->tm_info.pause_time = HCLGE_DEFAULT_PAUSE_TRANS_TIME;
+ 
+ 	if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE &&
+ 	    hdev->tm_info.num_pg != 1)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+index 8abb89beaae1..34eb52d3d7ee 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+@@ -192,6 +192,8 @@ void hclge_tm_pfc_info_update(struct hclge_dev *hdev);
+ int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
+ int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
+ int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
++int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
++			  u8 pause_trans_gap, u16 pause_trans_time);
+ int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
+ void hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
+ void hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
+-- 
+2.34.1
+
diff --git a/patches/0559-net-hns3-disbable-pfc-en-before-the-reset.patch b/patches/0559-net-hns3-disbable-pfc-en-before-the-reset.patch
new file mode 100644
index 0000000..e247349
--- /dev/null
+++ b/patches/0559-net-hns3-disbable-pfc-en-before-the-reset.patch
@@ -0,0 +1,108 @@
+From 6dd6e7a54d395f1a7a9ab7e4534ac54657d7496d Mon Sep 17 00:00:00 2001
+From: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Date: Fri, 31 Mar 2023 16:25:49 +0800
+Subject: [PATCH 198/283] net: hns3: disbable pfc en before the reset
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+To prevent the system from abnormally sending PFC frames after an
+abnormal reset. If the reset type is not imp reset or global reset,
+the system notifies the firmware to disable pfc before the reset.
+
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+---
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_ext.c    |  1 +
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c   | 15 +++++++++------
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c |  4 ++--
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h |  5 +++++
+ 4 files changed, 17 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index 0f4eff899e94..801737b11732 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -590,6 +590,7 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_GET_PORT_EXT_ID_INFO] = hclge_get_extend_port_id_info,
+ 	[HNAE3_EXT_OPC_GET_PORT_EXT_NUM_INFO] = hclge_get_extend_port_num_info,
+ 	[HNAE3_EXT_OPC_GET_PORT_NUM] = hclge_get_port_num,
++	[HNAE3_EXT_OPC_SET_PFC_TIME] = hclge_set_pause_trans_time,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 3779181b8f59..47c526b5271b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -7790,12 +7790,15 @@ static void hclge_ae_stop(struct hnae3_handle *handle)
+ 	/* If it is not PF reset or FLR, the firmware will disable the MAC,
+ 	 * so it only need to stop phy here.
+ 	 */
+-	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
+-	    hdev->reset_type != HNAE3_FUNC_RESET &&
+-	    hdev->reset_type != HNAE3_FLR_RESET) {
+-		hclge_mac_stop_phy(hdev);
+-		hclge_update_link_status(hdev);
+-		return;
++	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
++		hclge_pfc_pause_en_cfg(hdev, HCLGE_PFC_TX_RX_DISABLE,
++				       HCLGE_PFC_DISABLE);
++		if (hdev->reset_type != HNAE3_FUNC_RESET &&
++		    hdev->reset_type != HNAE3_FLR_RESET) {
++			hclge_mac_stop_phy(hdev);
++			hclge_update_link_status(hdev);
++			return;
++		}
+ 	}
+ 
+ 	hclge_reset_tqp(handle);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index ca93919ed817..b535f3dd842b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -171,8 +171,8 @@ int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
+ 	return hclge_cmd_send(&hdev->hw, &desc, 1);
+ }
+ 
+-static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
+-				  u8 pfc_bitmap)
++int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
++			   u8 pfc_bitmap)
+ {
+ 	struct hclge_desc desc;
+ 	struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+index 34eb52d3d7ee..98d0f871ee61 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+@@ -134,6 +134,9 @@ struct hclge_bp_to_qs_map_cmd {
+ 	u32 rsvd1;
+ };
+ 
++#define HCLGE_PFC_DISABLE	0
++#define HCLGE_PFC_TX_RX_DISABLE	0
++
+ struct hclge_pfc_en_cmd {
+ 	u8 tx_rx_en_bitmap;
+ 	u8 pri_en_bitmap;
+@@ -192,6 +195,8 @@ void hclge_tm_pfc_info_update(struct hclge_dev *hdev);
+ int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);
+ int hclge_tm_init_hw(struct hclge_dev *hdev, bool init);
+ int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx);
++int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
++			   u8 pfc_bitmap);
+ int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
+ 			  u8 pause_trans_gap, u16 pause_trans_time);
+ int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
+-- 
+2.34.1
+
diff --git a/patches/0560-net-hns3-add-support-query-the-presence-of-optical-m.patch b/patches/0560-net-hns3-add-support-query-the-presence-of-optical-m.patch
new file mode 100644
index 0000000..e18d37d
--- /dev/null
+++ b/patches/0560-net-hns3-add-support-query-the-presence-of-optical-m.patch
@@ -0,0 +1,100 @@
+From a61a2bd156aa74746068bcf8ac1cb7863f04527b Mon Sep 17 00:00:00 2001
+From: Tian Jiang <jiangtian6@h-partners.com>
+Date: Mon, 17 Apr 2023 14:31:28 +0800
+Subject: [PATCH 199/283] net: hns3: add support query the presence of optical
+ module
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+The patch provides an interface to check whether the optical module
+is inserted.
+
+Signed-off-by: Tian Jiang <jiangtian6@h-partners.com>
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 24 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ext.h         |  6 +++++
+ 2 files changed, 30 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index 801737b11732..f63f558327f1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -428,6 +428,29 @@ static int hclge_set_pause_trans_time(struct hclge_dev *hdev, void *data,
+ 	}
+ 
+ 	hdev->tm_info.pause_time = pause_trans_time;
++
++	return 0;
++}
++
++static int hclge_get_sfp_present(struct hclge_dev *hdev, void *data,
++				 size_t length)
++{
++	struct hclge_sfp_present_cmd *resp;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(u32))
++		return -EINVAL;
++
++	ret = hclge_get_info_from_cmd(hdev, &desc, 1,
++				      HCLGE_OPC_SFP_GET_PRESENT);
++	if (ret) {
++		dev_err(&hdev->pdev->dev, "failed to get sfp present, ret = %d\n", ret);
++		return ret;
++	}
++
++	resp = (struct hclge_sfp_present_cmd *)desc.data;
++	*(u32 *)data = le32_to_cpu(resp->sfp_present);
+ 	return 0;
+ }
+ 
+@@ -591,6 +614,7 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_GET_PORT_EXT_NUM_INFO] = hclge_get_extend_port_num_info,
+ 	[HNAE3_EXT_OPC_GET_PORT_NUM] = hclge_get_port_num,
+ 	[HNAE3_EXT_OPC_SET_PFC_TIME] = hclge_set_pause_trans_time,
++	[HNAE3_EXT_OPC_GET_PRESENT] = hclge_get_sfp_present,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+index f840129572c8..ae6f0afef1f1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -73,6 +73,11 @@ struct hclge_torus_cfg_cmd {
+ 	__le32 torus_en;
+ };
+ 
++struct hclge_sfp_present_cmd {
++	__le32 sfp_present;
++	__le32 rsv[5];
++};
++
+ enum hclge_ext_opcode_type {
+ 	HCLGE_OPC_CONFIG_SWITCH_PARAM = 0x1033,
+ 	HCLGE_OPC_CONFIG_VLAN_FILTER = 0x1100,
+@@ -82,6 +87,7 @@ enum hclge_ext_opcode_type {
+ 	HCLGE_OPC_GET_CHIP_NUM = 0x7005,
+ 	HCLGE_OPC_GET_PORT_NUM = 0x7006,
+ 	HCLGE_OPC_CFG_PAUSE_STORM_PARA = 0x7019,
++	HCLGE_OPC_SFP_GET_PRESENT = 0x7101,
+ };
+ 
+ struct hclge_reset_fail_type_map {
+-- 
+2.34.1
+
diff --git a/patches/0561-net-hns3-add-supports-configure-optical-module-enabl.patch b/patches/0561-net-hns3-add-supports-configure-optical-module-enabl.patch
new file mode 100644
index 0000000..3757686
--- /dev/null
+++ b/patches/0561-net-hns3-add-supports-configure-optical-module-enabl.patch
@@ -0,0 +1,100 @@
+From 8686a24eaf45132f9580a686491de7f55ce4e77a Mon Sep 17 00:00:00 2001
+From: Tian Jiang <jiangtian6@h-partners.com>
+Date: Mon, 17 Apr 2023 14:48:27 +0800
+Subject: [PATCH 200/283] net: hns3: add supports configure optical module
+ enable
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+The patch provides an interface for enabling or disabling
+the optical module.
+
+Signed-off-by: Tian Jiang <jiangtian6@h-partners.com>
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+---
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 25 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ext.h         |  6 +++++
+ 2 files changed, 31 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index f63f558327f1..dd595a783b55 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -454,6 +454,30 @@ static int hclge_get_sfp_present(struct hclge_dev *hdev, void *data,
+ 	return 0;
+ }
+ 
++static int hclge_set_sfp_state(struct hclge_dev *hdev, void *data,
++			       size_t length)
++{
++	struct hclge_sfp_enable_cmd *req;
++	struct hclge_desc desc;
++	u32 state;
++	int ret;
++
++	if (length != sizeof(u32))
++		return -EINVAL;
++
++	state = *(u32 *)data;
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SFP_SET_STATUS, false);
++	req = (struct hclge_sfp_enable_cmd *)desc.data;
++	req->sfp_enable = cpu_to_le32(state);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to set sfp state, ret = %d\n", ret);
++
++	return ret;
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+@@ -615,6 +639,7 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_GET_PORT_NUM] = hclge_get_port_num,
+ 	[HNAE3_EXT_OPC_SET_PFC_TIME] = hclge_set_pause_trans_time,
+ 	[HNAE3_EXT_OPC_GET_PRESENT] = hclge_get_sfp_present,
++	[HNAE3_EXT_OPC_SET_SFP_STATE] = hclge_set_sfp_state,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+index ae6f0afef1f1..607bd1668cdc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -78,6 +78,11 @@ struct hclge_sfp_present_cmd {
+ 	__le32 rsv[5];
+ };
+ 
++struct hclge_sfp_enable_cmd {
++	__le32 sfp_enable;
++	__le32 rsv[5];
++};
++
+ enum hclge_ext_opcode_type {
+ 	HCLGE_OPC_CONFIG_SWITCH_PARAM = 0x1033,
+ 	HCLGE_OPC_CONFIG_VLAN_FILTER = 0x1100,
+@@ -88,6 +93,7 @@ enum hclge_ext_opcode_type {
+ 	HCLGE_OPC_GET_PORT_NUM = 0x7006,
+ 	HCLGE_OPC_CFG_PAUSE_STORM_PARA = 0x7019,
+ 	HCLGE_OPC_SFP_GET_PRESENT = 0x7101,
++	HCLGE_OPC_SFP_SET_STATUS = 0x7102,
+ };
+ 
+ struct hclge_reset_fail_type_map {
+-- 
+2.34.1
+
diff --git a/patches/0562-net-hns3-add-support-config-and-query-serdes-lane-st.patch b/patches/0562-net-hns3-add-support-config-and-query-serdes-lane-st.patch
new file mode 100644
index 0000000..058264d
--- /dev/null
+++ b/patches/0562-net-hns3-add-support-config-and-query-serdes-lane-st.patch
@@ -0,0 +1,110 @@
+From 68696319a6fde3f464fab18aafad6b01ee2cc8f0 Mon Sep 17 00:00:00 2001
+From: Tian Jiang <jiangtian6@h-partners.com>
+Date: Mon, 17 Apr 2023 17:20:55 +0800
+Subject: [PATCH 201/283] net: hns3: add support config and query serdes lane
+ status
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+The patch supports the function of disabling and status query of lane
+channels on a port. The patch traverses all covered lanes on the
+port and powers off the serdes ds power.
+
+Signed-off-by: Tian Jiang <jiangtian6@h-partners.com>
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+---
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 46 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ext.h         |  1 +
+ 2 files changed, 47 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index dd595a783b55..b8bdace3245b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -478,6 +478,50 @@ static int hclge_set_sfp_state(struct hclge_dev *hdev, void *data,
+ 	return ret;
+ }
+ 
++static int hclge_set_net_lane_status(struct hclge_dev *hdev,
++				     u32 enable)
++{
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DISABLE_NET_LANE, false);
++	desc.data[0] = cpu_to_le32(enable);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to set net lane status, ret = %d\n", ret);
++
++	return ret;
++}
++
++static int hclge_disable_net_lane(struct hclge_dev *hdev, void *data,
++				  size_t length)
++{
++	return hclge_set_net_lane_status(hdev, 0);
++}
++
++static int hclge_get_net_lane_status(struct hclge_dev *hdev, void *data,
++				     size_t length)
++{
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(u32))
++		return -EINVAL;
++
++	ret = hclge_get_info_from_cmd(hdev, &desc, 1,
++				      HCLGE_OPC_DISABLE_NET_LANE);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get net lane status, ret = %d\n", ret);
++		return ret;
++	}
++
++	*(u32 *)data = le32_to_cpu(desc.data[0]);
++	return 0;
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+@@ -640,6 +684,8 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_SET_PFC_TIME] = hclge_set_pause_trans_time,
+ 	[HNAE3_EXT_OPC_GET_PRESENT] = hclge_get_sfp_present,
+ 	[HNAE3_EXT_OPC_SET_SFP_STATE] = hclge_set_sfp_state,
++	[HNAE3_EXT_OPC_DISABLE_LANE] = hclge_disable_net_lane,
++	[HNAE3_EXT_OPC_GET_LANE_STATUS] = hclge_get_net_lane_status,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+index 607bd1668cdc..06b3d9c494f4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -91,6 +91,7 @@ enum hclge_ext_opcode_type {
+ 	HCLGE_OPC_CHIP_ID_GET = 0x7003,
+ 	HCLGE_OPC_GET_CHIP_NUM = 0x7005,
+ 	HCLGE_OPC_GET_PORT_NUM = 0x7006,
++	HCLGE_OPC_DISABLE_NET_LANE = 0x7008,
+ 	HCLGE_OPC_CFG_PAUSE_STORM_PARA = 0x7019,
+ 	HCLGE_OPC_SFP_GET_PRESENT = 0x7101,
+ 	HCLGE_OPC_SFP_SET_STATUS = 0x7102,
+-- 
+2.34.1
+
diff --git a/patches/0563-net-hns3-add-support-disable-nic-clock.patch b/patches/0563-net-hns3-add-support-disable-nic-clock.patch
new file mode 100644
index 0000000..3354726
--- /dev/null
+++ b/patches/0563-net-hns3-add-support-disable-nic-clock.patch
@@ -0,0 +1,80 @@
+From 182d1b5868d8d6d91fe2552d3dec0edc31317dfa Mon Sep 17 00:00:00 2001
+From: Tian Jiang <jiangtian6@h-partners.com>
+Date: Mon, 17 Apr 2023 19:40:57 +0800
+Subject: [PATCH 202/283] net: hns3: add support disable nic clock
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+The patch disables the clocks of the PPP, PPU, IGU_EGU, ROCE, and
+TM modules by configuring the network subctrl register.
+
+Signed-off-by: Tian Jiang <jiangtian6@h-partners.com>
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+---
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_ext.c | 18 ++++++++++++++++++
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_ext.h |  1 +
+ 2 files changed, 19 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index b8bdace3245b..2a405fecd5ad 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -522,6 +522,23 @@ static int hclge_get_net_lane_status(struct hclge_dev *hdev, void *data,
+ 	return 0;
+ }
+ 
++static int hclge_disable_nic_clock(struct hclge_dev *hdev, void *data,
++				   size_t length)
++{
++	struct hclge_desc desc;
++	u32 nic_clock_en = 0;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_NIC_CLOCK, false);
++	desc.data[0] = cpu_to_le32(nic_clock_en);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to disable nic clock, ret = %d\n", ret);
++	return ret;
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+@@ -686,6 +703,7 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_SET_SFP_STATE] = hclge_set_sfp_state,
+ 	[HNAE3_EXT_OPC_DISABLE_LANE] = hclge_disable_net_lane,
+ 	[HNAE3_EXT_OPC_GET_LANE_STATUS] = hclge_get_net_lane_status,
++	[HNAE3_EXT_OPC_DISABLE_CLOCK] = hclge_disable_nic_clock,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+index 06b3d9c494f4..04f9ab5261e8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -84,6 +84,7 @@ struct hclge_sfp_enable_cmd {
+ };
+ 
+ enum hclge_ext_opcode_type {
++	HCLGE_OPC_CONFIG_NIC_CLOCK = 0x0060,
+ 	HCLGE_OPC_CONFIG_SWITCH_PARAM = 0x1033,
+ 	HCLGE_OPC_CONFIG_VLAN_FILTER = 0x1100,
+ 	HCLGE_OPC_SET_NOTIFY_PKT = 0x180A,
+-- 
+2.34.1
+
diff --git a/patches/0564-net-hns3-add-support-PF-provides-customized-interfac.patch b/patches/0564-net-hns3-add-support-PF-provides-customized-interfac.patch
new file mode 100644
index 0000000..66ed2fe
--- /dev/null
+++ b/patches/0564-net-hns3-add-support-PF-provides-customized-interfac.patch
@@ -0,0 +1,237 @@
+From c76711a0880d0c7b90ae4fe9a8c6ce5402ad8ae8 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Fri, 21 Apr 2023 15:55:24 +0800
+Subject: [PATCH 203/283] net: hns3: add support PF provides customized
+ interfaces to detect port faults.
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+When the link status of the PF network port changes from up to down,
+the IMP can quickly report the link down fault cause based on the
+link status. If the hardware is faulty from the beginning and the
+link is not up, the IMP does not report the link down event
+because the status is not changed.
+
+Therefore, an interface is provided to detect port faults.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+---
+ .../net/ethernet/hisilicon/hns3/hnae3_ext.h   | 15 +++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    | 23 ++++++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    | 14 +++++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  6 ++
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 55 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ext.h         |  2 +
+ 6 files changed, 115 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+index 5f1302488a1c..51913618bcba 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+@@ -44,6 +44,8 @@ enum hnae3_ext_opcode {
+ 	HNAE3_EXT_OPC_GET_LANE_STATUS,
+ 	HNAE3_EXT_OPC_DISABLE_CLOCK,
+ 	HNAE3_EXT_OPC_SET_PFC_TIME,
++	HNAE3_EXT_OPC_GET_HILINK_REF_LOS,
++	HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS,
+ };
+ 
+ struct hnae3_pfc_storm_para {
+@@ -54,6 +56,19 @@ struct hnae3_pfc_storm_para {
+ 	u32 recovery_period_ms;
+ };
+ 
++enum hnae3_port_fault_type {
++	HNAE3_FAULT_TYPE_CDR_FLASH,
++	HNAE3_FAULT_TYPE_9545_ERR,
++	HNAE3_FAULT_TYPE_CDR_CORE,
++	HNAE3_FAULT_TYPE_HILINK_REF_LOS,
++	HNAE3_FAULT_TYPE_INVALID
++};
++
++struct hnae3_port_fault {
++	u32 fault_type;
++	u32 fault_status;
++};
++
+ struct hnae3_notify_pkt_param {
+ 	/* inter-packet gap of sending, the unit is one cycle of clock */
+ 	u32 ipg;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 9683099efb9c..d4a171938d21 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -373,3 +373,26 @@ int nic_set_pfc_time_cfg(struct net_device *ndev, u16 time)
+ 				  &time, sizeof(time));
+ }
+ EXPORT_SYMBOL(nic_set_pfc_time_cfg);
++
++int nic_get_port_fault_status(struct net_device *ndev,
++			      u32 fault_type, u32 *status)
++{
++	int opcode = HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS;
++	struct hnae3_port_fault fault_para;
++	int ret;
++
++	if (!status)
++		return -EINVAL;
++
++	if (fault_type == HNAE3_FAULT_TYPE_HILINK_REF_LOS)
++		opcode = HNAE3_EXT_OPC_GET_HILINK_REF_LOS;
++
++	fault_para.fault_type = fault_type;
++	ret = nic_invoke_pri_ops(ndev, opcode, &fault_para, sizeof(fault_para));
++	if (ret)
++		return ret;
++
++	*status = fault_para.fault_status;
++	return 0;
++}
++EXPORT_SYMBOL(nic_get_port_fault_status);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index 0f9d6683825e..555c8d0dcef1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -7,6 +7,18 @@
+ #include "hns3_enet.h"
+ #include "hnae3_ext.h"
+ 
++#define HNS3_PFC_STORM_PARA_DIR_RX 0
++#define HNS3_PFC_STORM_PARA_DIR_TX 1
++#define HNS3_PFC_STORM_PARA_DISABLE 0
++#define HNS3_PFC_STORM_PARA_ENABLE 1
++#define HNS3_PFC_STORM_PARA_PERIOD_MIN 5
++#define HNS3_PFC_STORM_PARA_PERIOD_MAX 2000
++
++#define nic_get_cdr_flash_status(ndev, status)	\
++	nic_get_port_fault_status(ndev, HNAE3_FAULT_TYPE_CDR_FLASH, status)
++#define nic_get_hilink_ref_los(ndev, status)	\
++	nic_get_port_fault_status(ndev, HNAE3_FAULT_TYPE_HILINK_REF_LOS, status)
++
+ int nic_netdev_match_check(struct net_device *netdev);
+ void nic_chip_recover_handler(struct net_device *ndev,
+ 			      enum hnae3_event_type_custom event_t);
+@@ -39,4 +51,6 @@ int nic_disable_net_lane(struct net_device *ndev);
+ int nic_get_net_lane_status(struct net_device *ndev, u32 *status);
+ int nic_disable_clock(struct net_device *ndev);
+ int nic_set_pfc_time_cfg(struct net_device *ndev, u16 time);
++int nic_get_port_fault_status(struct net_device *ndev,
++			      u32 fault_type, u32 *status);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 1785eb6b0f33..07e20ed0106c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -702,6 +702,12 @@ struct hclge_sfp_info_cmd {
+ 	u8 rsv[7];
+ };
+ 
++struct hclge_port_fault_cmd {
++	__le32 fault_status;
++	__le32 port_type;
++	u8 rsv[16];
++};
++
+ #define HCLGE_MAC_CFG_FEC_AUTO_EN_B	0
+ #define HCLGE_MAC_CFG_FEC_MODE_S	1
+ #define HCLGE_MAC_CFG_FEC_MODE_M	GENMASK(3, 1)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index 2a405fecd5ad..d89c31cc5491 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -539,6 +539,59 @@ static int hclge_disable_nic_clock(struct hclge_dev *hdev, void *data,
+ 	return ret;
+ }
+ 
++static int hclge_get_hilink_ref_los(struct hclge_dev *hdev, void *data,
++				    size_t length)
++{
++	struct hclge_port_fault_cmd *fault_cmd;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(struct hnae3_port_fault))
++		return -EINVAL;
++
++	fault_cmd = (struct hclge_port_fault_cmd *)desc.data;
++	ret = hclge_get_info_from_cmd(hdev, &desc,
++				      1, HCLGE_OPC_CFG_GET_HILINK_REF_LOS);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get hilink ref los, ret = %d\n", ret);
++		return ret;
++	}
++
++	*(u32 *)data = le32_to_cpu(fault_cmd->fault_status);
++	return 0;
++}
++
++static int hclge_get_port_fault_status(struct hclge_dev *hdev, void *data,
++				       size_t length)
++{
++	struct hclge_port_fault_cmd *fault_cmd;
++	struct hnae3_port_fault *para;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(struct hnae3_port_fault))
++		return -EINVAL;
++
++	para = (struct hnae3_port_fault *)data;
++	fault_cmd = (struct hclge_port_fault_cmd *)desc.data;
++	hclge_cmd_setup_basic_desc(&desc,
++				   HCLGE_OPC_GET_PORT_FAULT_STATUS,
++				   true);
++	fault_cmd->port_type = cpu_to_le32(para->fault_type);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get port fault status, type = %u, ret = %d\n",
++			para->fault_type, ret);
++		return ret;
++	}
++
++	para->fault_status = le32_to_cpu(fault_cmd->fault_status);
++
++	return 0;
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+@@ -704,6 +757,8 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_DISABLE_LANE] = hclge_disable_net_lane,
+ 	[HNAE3_EXT_OPC_GET_LANE_STATUS] = hclge_get_net_lane_status,
+ 	[HNAE3_EXT_OPC_DISABLE_CLOCK] = hclge_disable_nic_clock,
++	[HNAE3_EXT_OPC_GET_HILINK_REF_LOS] = hclge_get_hilink_ref_los,
++	[HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS] = hclge_get_port_fault_status,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+index 04f9ab5261e8..c06b5164accd 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -94,6 +94,8 @@ enum hclge_ext_opcode_type {
+ 	HCLGE_OPC_GET_PORT_NUM = 0x7006,
+ 	HCLGE_OPC_DISABLE_NET_LANE = 0x7008,
+ 	HCLGE_OPC_CFG_PAUSE_STORM_PARA = 0x7019,
++	HCLGE_OPC_CFG_GET_HILINK_REF_LOS = 0x701B,
++	HCLGE_OPC_GET_PORT_FAULT_STATUS = 0x7023,
+ 	HCLGE_OPC_SFP_GET_PRESENT = 0x7101,
+ 	HCLGE_OPC_SFP_SET_STATUS = 0x7102,
+ };
+-- 
+2.34.1
+
diff --git a/patches/0565-net-hns3-add-support-detect-port-wire-type.patch b/patches/0565-net-hns3-add-support-detect-port-wire-type.patch
new file mode 100644
index 0000000..e2f3138
--- /dev/null
+++ b/patches/0565-net-hns3-add-support-detect-port-wire-type.patch
@@ -0,0 +1,127 @@
+From 912055a95f493c47e3425cab6c4a1cb1cecd0374 Mon Sep 17 00:00:00 2001
+From: shaojijie <shaojijie@huawei.com>
+Date: Fri, 21 Apr 2023 16:29:12 +0800
+Subject: [PATCH 204/283] net: hns3: add support detect port wire type
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+This patch add support to get port wire type.
+
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h    |  1 +
+ drivers/net/ethernet/hisilicon/hns3/hns3_ext.c     |  7 +++++++
+ drivers/net/ethernet/hisilicon/hns3/hns3_ext.h     |  1 +
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c | 14 ++++++++++++++
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c    |  4 ++--
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h    |  2 ++
+ 6 files changed, 27 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+index 51913618bcba..e326267d9d2e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+@@ -46,6 +46,7 @@ enum hnae3_ext_opcode {
+ 	HNAE3_EXT_OPC_SET_PFC_TIME,
+ 	HNAE3_EXT_OPC_GET_HILINK_REF_LOS,
+ 	HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS,
++	HNAE3_EXT_OPC_GET_PORT_TYPE,
+ };
+ 
+ struct hnae3_pfc_storm_para {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index d4a171938d21..7e0048a7a37a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -396,3 +396,10 @@ int nic_get_port_fault_status(struct net_device *ndev,
+ 	return 0;
+ }
+ EXPORT_SYMBOL(nic_get_port_fault_status);
++
++int nic_get_port_wire_type(struct net_device *ndev, u32 *wire_type)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_GET_PORT_TYPE,
++				  wire_type, sizeof(*wire_type));
++}
++EXPORT_SYMBOL(nic_get_port_wire_type);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index 555c8d0dcef1..baa3cda8b671 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -53,4 +53,5 @@ int nic_disable_clock(struct net_device *ndev);
+ int nic_set_pfc_time_cfg(struct net_device *ndev, u16 time);
+ int nic_get_port_fault_status(struct net_device *ndev,
+ 			      u32 fault_type, u32 *status);
++int nic_get_port_wire_type(struct net_device *ndev, u32 *wire_type);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index d89c31cc5491..eac784e243f5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -592,6 +592,19 @@ static int hclge_get_port_fault_status(struct hclge_dev *hdev, void *data,
+ 	return 0;
+ }
+ 
++static int hclge_get_port_wire_type(struct hclge_dev *hdev, void *data,
++				    size_t length)
++{
++	u8 module_type;
++
++	if (length != sizeof(u32))
++		return -EINVAL;
++
++	hclge_get_media_type(&hdev->vport[0].nic, NULL, &module_type);
++	*(u32 *)data = module_type;
++	return 0;
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+@@ -759,6 +772,7 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_DISABLE_CLOCK] = hclge_disable_nic_clock,
+ 	[HNAE3_EXT_OPC_GET_HILINK_REF_LOS] = hclge_get_hilink_ref_los,
+ 	[HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS] = hclge_get_port_fault_status,
++	[HNAE3_EXT_OPC_GET_PORT_TYPE] = hclge_get_port_wire_type,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 47c526b5271b..4e7f16f2c0b1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -10660,8 +10660,8 @@ static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
+ 		*auto_neg = hdev->hw.mac.autoneg;
+ }
+ 
+-static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
+-				 u8 *module_type)
++void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
++			  u8 *module_type)
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 71ca13a29b51..e22702108846 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -1174,4 +1174,6 @@ int hclge_get_wol_cfg(struct hclge_dev *hdev, u32 *mode);
+ struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf);
+ void hclge_reset_task_schedule(struct hclge_dev *hdev);
+ void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle);
++void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
++			  u8 *module_type);
+ #endif
+-- 
+2.34.1
+
diff --git a/patches/0566-net-hns3-add-support-set-mac-state.patch b/patches/0566-net-hns3-add-support-set-mac-state.patch
new file mode 100644
index 0000000..2f30785
--- /dev/null
+++ b/patches/0566-net-hns3-add-support-set-mac-state.patch
@@ -0,0 +1,176 @@
+From 61839f9ee3c7cff5f4f31b75edb5dbf46c2774f5 Mon Sep 17 00:00:00 2001
+From: wangpeiyang <wangpeiyang1@huawei.com>
+Date: Fri, 21 Apr 2023 17:01:57 +0800
+Subject: [PATCH 205/283] net: hns3: add support set mac state
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+The patch provides a customized interface to modify the MAC mode.
+
+Signed-off-by: wangpeiyang <wangpeiyang1@huawei.com>
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hnae3_ext.h   |  1 +
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    |  7 ++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |  1 +
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 34 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  8 +++--
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  1 +
+ include/linux/phy.h                           |  9 +++++
+ 7 files changed, 58 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+index e326267d9d2e..36eff4b0a228 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+@@ -47,6 +47,7 @@ enum hnae3_ext_opcode {
+ 	HNAE3_EXT_OPC_GET_HILINK_REF_LOS,
+ 	HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS,
+ 	HNAE3_EXT_OPC_GET_PORT_TYPE,
++	HNAE3_EXT_OPC_SET_MAC_STATE,
+ };
+ 
+ struct hnae3_pfc_storm_para {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 7e0048a7a37a..da1473cbf42b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -403,3 +403,10 @@ int nic_get_port_wire_type(struct net_device *ndev, u32 *wire_type)
+ 				  wire_type, sizeof(*wire_type));
+ }
+ EXPORT_SYMBOL(nic_get_port_wire_type);
++
++int nic_set_mac_state(struct net_device *ndev, int enable)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_SET_MAC_STATE,
++				  &enable, sizeof(enable));
++}
++EXPORT_SYMBOL(nic_set_mac_state);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index baa3cda8b671..4c57ddb011c3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -54,4 +54,5 @@ int nic_set_pfc_time_cfg(struct net_device *ndev, u16 time);
+ int nic_get_port_fault_status(struct net_device *ndev,
+ 			      u32 fault_type, u32 *status);
+ int nic_get_port_wire_type(struct net_device *ndev, u32 *wire_type);
++int nic_set_mac_state(struct net_device *ndev, int enable);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index eac784e243f5..bf59a796a2c6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -605,6 +605,39 @@ static int hclge_get_port_wire_type(struct hclge_dev *hdev, void *data,
+ 	return 0;
+ }
+ 
++static void hclge_set_phy_state(struct hclge_dev *hdev, bool enable)
++{
++	struct phy_device *phydev = hdev->hw.mac.phydev;
++
++	if (!phydev)
++		return;
++
++	if (enable && (phydev->state == PHY_READY ||
++		       phydev->state == PHY_HALTED))
++		phy_start(phydev);
++	else if (!enable && (phy_is_started(phydev) ||
++			     phydev->state == PHY_DOWN))
++		phy_stop(phydev);
++}
++
++static int hclge_set_mac_state(struct hclge_dev *hdev, void *data,
++			       size_t length)
++{
++	bool enable;
++	int ret;
++
++	if (length != sizeof(int))
++		return -EINVAL;
++
++	enable = !!*(int *)data;
++	ret = hclge_cfg_mac_mode(hdev, enable);
++
++	if (!ret && !hclge_comm_dev_phy_imp_supported(hdev->ae_dev))
++		hclge_set_phy_state(hdev, enable);
++
++	return ret;
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+@@ -773,6 +806,7 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_GET_HILINK_REF_LOS] = hclge_get_hilink_ref_los,
+ 	[HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS] = hclge_get_port_fault_status,
+ 	[HNAE3_EXT_OPC_GET_PORT_TYPE] = hclge_get_port_wire_type,
++	[HNAE3_EXT_OPC_SET_MAC_STATE] = hclge_set_mac_state,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 4e7f16f2c0b1..68158219e8c6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -7290,7 +7290,7 @@ static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
+ 	}
+ }
+ 
+-static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
++int hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
+ {
+ 	struct hclge_desc desc;
+ 	struct hclge_config_mac_mode_cmd *req =
+@@ -7317,8 +7317,10 @@ static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret)
+-		dev_err(&hdev->pdev->dev,
+-			"mac enable fail, ret =%d.\n", ret);
++		dev_err(&hdev->pdev->dev, "failed to %s mac, ret = %d.\n",
++			enable ? "enable" : "disable", ret);
++
++	return ret;
+ }
+ 
+ static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index e22702108846..c2fcbf658bfa 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -1176,4 +1176,5 @@ void hclge_reset_task_schedule(struct hclge_dev *hdev);
+ void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle);
+ void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
+ 			  u8 *module_type);
++int hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable);
+ #endif
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index d428623582e5..03eb46c632da 100644
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -694,6 +694,15 @@ size_t phy_speeds(unsigned int *speeds, size_t size,
+ 
+ void phy_resolve_aneg_linkmode(struct phy_device *phydev);
+ 
++/**
++ * phy_is_started - Convenience function to check whether PHY is started
++ * @phydev: The phy_device struct
++ */
++static inline bool phy_is_started(struct phy_device *phydev)
++{
++	return phydev->state >= PHY_UP;
++}
++
+ /**
+  * phy_read_mmd - Convenience function for reading a register
+  * from an MMD on a given PHY.
+-- 
+2.34.1
+
diff --git a/patches/0567-net-hns3-add-support-set-led.patch b/patches/0567-net-hns3-add-support-set-led.patch
new file mode 100644
index 0000000..d537af8
--- /dev/null
+++ b/patches/0567-net-hns3-add-support-set-led.patch
@@ -0,0 +1,191 @@
+From 94fd25546026be2603ecfe063433182d13b145bf Mon Sep 17 00:00:00 2001
+From: shaojijie <shaojijie@huawei.com>
+Date: Sun, 23 Apr 2023 10:19:24 +0800
+Subject: [PATCH 206/283] net: hns3: add support set led
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+The patch supports the configuration of the position indicator and
+error indicator modes.
+
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hnae3_ext.h   | 13 +++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    | 20 +++++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |  3 ++
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 52 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ext.h         | 10 ++++
+ 5 files changed, 98 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+index 36eff4b0a228..6b1b5c630260 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+@@ -48,6 +48,19 @@ enum hnae3_ext_opcode {
+ 	HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS,
+ 	HNAE3_EXT_OPC_GET_PORT_TYPE,
+ 	HNAE3_EXT_OPC_SET_MAC_STATE,
++	HNAE3_EXT_OPC_SET_LED,
++	HNAE3_EXT_OPC_GET_LED_SIGNAL,
++};
++
++struct hnae3_led_state_para {
++	u32 type;
++	u32 status;
++};
++
++struct hnae3_lamp_signal {
++	u8 error;
++	u8 locate;
++	u8 activity;
+ };
+ 
+ struct hnae3_pfc_storm_para {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index da1473cbf42b..64ad9be4ec4f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -410,3 +410,23 @@ int nic_set_mac_state(struct net_device *ndev, int enable)
+ 				  &enable, sizeof(enable));
+ }
+ EXPORT_SYMBOL(nic_set_mac_state);
++
++int nic_set_led(struct net_device *ndev, int type, int status)
++{
++	struct hnae3_led_state_para para;
++
++	para.status = status;
++	para.type = type;
++
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_SET_LED,
++				  &para, sizeof(para));
++}
++EXPORT_SYMBOL(nic_set_led);
++
++int nic_get_led_signal(struct net_device *ndev,
++		       struct hnae3_lamp_signal *signal)
++{
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_GET_LED_SIGNAL,
++				  signal, sizeof(*signal));
++}
++EXPORT_SYMBOL(nic_get_led_signal);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index 4c57ddb011c3..f47c05c2c660 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -55,4 +55,7 @@ int nic_get_port_fault_status(struct net_device *ndev,
+ 			      u32 fault_type, u32 *status);
+ int nic_get_port_wire_type(struct net_device *ndev, u32 *wire_type);
+ int nic_set_mac_state(struct net_device *ndev, int enable);
++int nic_set_led(struct net_device *ndev, int type, int status);
++int nic_get_led_signal(struct net_device *ndev,
++		       struct hnae3_lamp_signal *signal);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index bf59a796a2c6..4ef891d9613a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -638,6 +638,56 @@ static int hclge_set_mac_state(struct hclge_dev *hdev, void *data,
+ 	return ret;
+ }
+ 
++static int hclge_set_led(struct hclge_dev *hdev, void *data,
++			 size_t length)
++{
++	struct hclge_lamp_signal_cmd *para_cmd;
++	struct hnae3_led_state_para *para;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(struct hnae3_led_state_para))
++		return -EINVAL;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_LED, false);
++	para = (struct hnae3_led_state_para *)data;
++	para_cmd = (struct hclge_lamp_signal_cmd *)desc.data;
++	para_cmd->type = cpu_to_le32(para->type);
++	para_cmd->status = cpu_to_le32(para->status);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev, "failed to set led, ret = %d\n", ret);
++
++	return ret;
++}
++
++static int hclge_get_led_signal(struct hclge_dev *hdev, void *data,
++				size_t length)
++{
++	struct hclge_lamp_signal_cmd *signal_cmd;
++	struct hnae3_lamp_signal *signal;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(struct hnae3_lamp_signal))
++		return -EINVAL;
++
++	ret = hclge_get_info_from_cmd(hdev, &desc, 1, HCLGE_OPC_SET_LED);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get led signal, ret = %d\n", ret);
++		return ret;
++	}
++
++	signal = (struct hnae3_lamp_signal *)data;
++	signal_cmd = (struct hclge_lamp_signal_cmd *)desc.data;
++	signal->error = signal_cmd->error;
++	signal->locate = signal_cmd->locate;
++	signal->activity = signal_cmd->activity;
++	return 0;
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+@@ -807,6 +857,8 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS] = hclge_get_port_fault_status,
+ 	[HNAE3_EXT_OPC_GET_PORT_TYPE] = hclge_get_port_wire_type,
+ 	[HNAE3_EXT_OPC_SET_MAC_STATE] = hclge_set_mac_state,
++	[HNAE3_EXT_OPC_SET_LED] = hclge_set_led,
++	[HNAE3_EXT_OPC_GET_LED_SIGNAL] = hclge_get_led_signal,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+index c06b5164accd..dab62a588e53 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -83,6 +83,15 @@ struct hclge_sfp_enable_cmd {
+ 	__le32 rsv[5];
+ };
+ 
++struct hclge_lamp_signal_cmd {
++	__le32 type;
++	__le32 status;
++	u8 error;
++	u8 locate;
++	u8 activity;
++	u8 rsv[13];
++};
++
+ enum hclge_ext_opcode_type {
+ 	HCLGE_OPC_CONFIG_NIC_CLOCK = 0x0060,
+ 	HCLGE_OPC_CONFIG_SWITCH_PARAM = 0x1033,
+@@ -92,6 +101,7 @@ enum hclge_ext_opcode_type {
+ 	HCLGE_OPC_CHIP_ID_GET = 0x7003,
+ 	HCLGE_OPC_GET_CHIP_NUM = 0x7005,
+ 	HCLGE_OPC_GET_PORT_NUM = 0x7006,
++	HCLGE_OPC_SET_LED = 0x7007,
+ 	HCLGE_OPC_DISABLE_NET_LANE = 0x7008,
+ 	HCLGE_OPC_CFG_PAUSE_STORM_PARA = 0x7019,
+ 	HCLGE_OPC_CFG_GET_HILINK_REF_LOS = 0x701B,
+-- 
+2.34.1
+
diff --git a/patches/0568-net-hns3-add-extend-interface-support-for-read-and-w.patch b/patches/0568-net-hns3-add-extend-interface-support-for-read-and-w.patch
new file mode 100644
index 0000000..96d4c01
--- /dev/null
+++ b/patches/0568-net-hns3-add-extend-interface-support-for-read-and-w.patch
@@ -0,0 +1,776 @@
+From 4a236e9c4f8e24770ebec17387366b5bf40f4902 Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Sun, 23 Apr 2023 16:44:38 +0800
+Subject: [PATCH 207/283] net: hns3: add extend interface support for read and
+ write phy register
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN3D
+CVE: NA
+
+----------------------------------------------------------------------
+
+Add extend interface support for read and write
+phy register with page. Sofar it supports only
+Phy RTL8211 and YT8521.
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+---
+ .../net/ethernet/hisilicon/hns3/hnae3_ext.h   |   9 +
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    |  36 ++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |  11 +
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |   8 +-
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 559 ++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_ext.h         |  32 +
+ 6 files changed, 654 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+index 6b1b5c630260..a9503e89263d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+@@ -50,6 +50,8 @@ enum hnae3_ext_opcode {
+ 	HNAE3_EXT_OPC_SET_MAC_STATE,
+ 	HNAE3_EXT_OPC_SET_LED,
+ 	HNAE3_EXT_OPC_GET_LED_SIGNAL,
++	HNAE3_EXT_OPC_GET_PHY_REG,
++	HNAE3_EXT_OPC_SET_PHY_REG,
+ };
+ 
+ struct hnae3_led_state_para {
+@@ -57,6 +59,13 @@ struct hnae3_led_state_para {
+ 	u32 status;
+ };
+ 
++struct hnae3_phy_para {
++	u32 page_select_addr;
++	u32 reg_addr;
++	u16 page;
++	u16 data;
++};
++
+ struct hnae3_lamp_signal {
+ 	u8 error;
+ 	u8 locate;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 64ad9be4ec4f..39bd51e93ddb 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -430,3 +430,39 @@ int nic_get_led_signal(struct net_device *ndev,
+ 				  signal, sizeof(*signal));
+ }
+ EXPORT_SYMBOL(nic_get_led_signal);
++
++int nic_get_phy_reg(struct net_device *ndev, u32 page_select_addr,
++		    u16 page, u32 reg_addr, u16 *data)
++{
++	struct hnae3_phy_para para;
++	int ret;
++
++	if (!data)
++		return -EINVAL;
++
++	para.page_select_addr = page_select_addr;
++	para.page = page;
++	para.reg_addr = reg_addr;
++	ret = nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_GET_PHY_REG,
++				 &para, sizeof(para));
++	if (ret)
++		return ret;
++
++	*data = para.data;
++	return 0;
++}
++EXPORT_SYMBOL(nic_get_phy_reg);
++
++int nic_set_phy_reg(struct net_device *ndev, u32 page_select_addr,
++		    u16 page, u32 reg_addr, u16 data)
++{
++	struct hnae3_phy_para para;
++
++	para.page_select_addr = page_select_addr;
++	para.page = page;
++	para.reg_addr = reg_addr;
++	para.data = data;
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_SET_PHY_REG,
++				  &para, sizeof(para));
++}
++EXPORT_SYMBOL(nic_set_phy_reg);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index f47c05c2c660..d9c107f5e231 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -14,6 +14,13 @@
+ #define HNS3_PFC_STORM_PARA_PERIOD_MIN 5
+ #define HNS3_PFC_STORM_PARA_PERIOD_MAX 2000
+ 
++#define nic_set_8211_phy_reg nic_set_phy_reg
++#define nic_get_8211_phy_reg nic_get_phy_reg
++#define nic_set_8521_phy_reg(ndev, page_region, page, reg_addr, data) \
++	nic_set_phy_reg(ndev, 0, page_region, page, reg_addr, data)
++#define nic_get_8521_phy_reg(ndev, page_region, page, reg_addr, data) \
++	nic_get_phy_reg(ndev, 0, page_region, page, reg_addr, data)
++
+ #define nic_get_cdr_flash_status(ndev, status)	\
+ 	nic_get_port_fault_status(ndev, HNAE3_FAULT_TYPE_CDR_FLASH, status)
+ #define nic_get_hilink_ref_los(ndev, status)	\
+@@ -58,4 +65,8 @@ int nic_set_mac_state(struct net_device *ndev, int enable);
+ int nic_set_led(struct net_device *ndev, int type, int status);
+ int nic_get_led_signal(struct net_device *ndev,
+ 		       struct hnae3_lamp_signal *signal);
++int nic_get_phy_reg(struct net_device *ndev, u32 page_select_addr,
++		    u16 page, u32 reg_addr, u16 *data);
++int nic_set_phy_reg(struct net_device *ndev, u32 page_select_addr,
++		    u16 page, u32 reg_addr, u16 data);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 07e20ed0106c..a4599f717da5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -1250,11 +1250,17 @@ struct hclge_phy_link_ksetting_1_cmd {
+ 	u8 rsv[22];
+ };
+ 
++#define HCLGE_PHY_RW_DIRECTLY	0
++#define HCLGE_PHY_RW_WITH_PAGE	1
+ struct hclge_phy_reg_cmd {
+ 	__le16 reg_addr;
+ 	u8 rsv0[2];
+ 	__le16 reg_val;
+-	u8 rsv1[18];
++	u8 rsv1[2];
++	u8 type;
++	u8 dev_addr;
++	__le16 page;
++	u8 rsv2[12];
+ };
+ 
+ /* capabilities bits map between imp firmware and local driver */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index 4ef891d9613a..c1013b338650 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -688,6 +688,563 @@ static int hclge_get_led_signal(struct hclge_dev *hdev, void *data,
+ 	return 0;
+ }
+ 
++static int hclge_def_phy_opt(struct mii_bus *mdio_bus, u32 phy_addr,
++			     u16 reg_addr, u16 *data,
++			     enum hclge_phy_op_code opt_type)
++{
++	int ret;
++
++	if (opt_type == PHY_OP_READ) {
++		ret = mdio_bus->read(mdio_bus, phy_addr, reg_addr);
++		if (ret >= 0) {
++			*data = (u16)ret;
++			ret = 0;
++		}
++	} else {
++		ret = mdio_bus->write(mdio_bus, phy_addr, reg_addr, *data);
++	}
++	return ret;
++}
++
++static int hclge_phy_reg_opt(struct hclge_dev *hdev,
++			     struct hnae3_phy_para *para,
++			     enum hclge_phy_op_code opt_type)
++{
++	struct mii_bus *mdio_bus = hdev->hw.mac.mdio_bus;
++	u32 phy_addr = hdev->hw.mac.phy_addr;
++	bool need_page_select = false;
++	u16 cur_page;
++	int ret;
++
++	/* operate flow:
++	 * 1 record current page addr
++	 * 2 jump to operated page
++	 * 3 operate register(read or write)
++	 * 4 come back to the page recorded in the first step.
++	 */
++	mutex_lock(&mdio_bus->mdio_lock);
++
++	/* check if page select is needed and record current page addr.
++	 * no need to change page when read page 0
++	 */
++	if (opt_type != PHY_OP_READ || para->page != 0) {
++		ret = mdio_bus->read(mdio_bus, phy_addr,
++				     para->page_select_addr);
++		if (ret < 0) {
++			dev_err(&hdev->pdev->dev,
++				"failed to read current phy %u reg page\n",
++				phy_addr);
++			mutex_unlock(&mdio_bus->mdio_lock);
++			return ret;
++		}
++		cur_page = (u16)ret;
++		need_page_select = cur_page != para->page;
++	}
++
++	/* jump to operated page */
++	if (need_page_select) {
++		ret = mdio_bus->write(mdio_bus, phy_addr,
++				      para->page_select_addr, para->page);
++		if (ret < 0) {
++			mutex_unlock(&mdio_bus->mdio_lock);
++			dev_err(&hdev->pdev->dev,
++				"failed to change phy %u page %u to page %u\n",
++				phy_addr, cur_page, para->page);
++			return ret;
++		}
++	}
++
++	/* operate register(read or write) */
++	ret = hclge_def_phy_opt(mdio_bus, phy_addr, para->reg_addr, &para->data,
++				opt_type);
++	if (ret < 0)
++		dev_err(&hdev->pdev->dev,
++			"failed to %s phy %u page %u reg %u\n, ret = %d",
++			opt_type == PHY_OP_READ ? "read" : "write",
++			phy_addr, para->page, para->reg_addr, ret);
++
++	/* come back to the page recorded in the first step. */
++	if (need_page_select) {
++		ret = mdio_bus->write(mdio_bus, phy_addr,
++				      para->page_select_addr, cur_page);
++		if (ret < 0)
++			dev_err(&hdev->pdev->dev,
++				"failed to restore phy %u reg page %u\n",
++				phy_addr, cur_page);
++	}
++
++	mutex_unlock(&mdio_bus->mdio_lock);
++
++	return ret;
++}
++
++static int hclge_8521_phy_ext_opt(struct mii_bus *mdio_bus, u32 phy_addr,
++				  u16 reg_addr, u16 *data,
++				  enum hclge_phy_op_code opt_type)
++{
++#define EXT_REG_ADDR 0x1e
++#define EXT_DATA_ADDR 0x1f
++	int ret;
++
++	ret = mdio_bus->write(mdio_bus, phy_addr, EXT_REG_ADDR, reg_addr);
++	if (ret < 0)
++		return ret;
++
++	return hclge_def_phy_opt(mdio_bus, phy_addr, EXT_DATA_ADDR, data,
++				 opt_type);
++}
++
++static int hclge_8521_phy_mmd_opt(struct mii_bus *mdio_bus, u32 phy_addr,
++				  u32 reg_addr, u16 *data,
++				  enum hclge_phy_op_code opt_type)
++{
++#define MMD_REG_ADDR 0xd
++#define MMD_DATA_ADDR 0xe
++	u16 mmd_index;
++	u16 mmd_reg;
++	int ret;
++
++	mmd_index = reg_addr >> 16U;
++	mmd_reg = reg_addr & 0xFFFF;
++
++	ret = mdio_bus->write(mdio_bus, phy_addr, MMD_REG_ADDR, mmd_index);
++	if (ret < 0)
++		return ret;
++	ret = mdio_bus->write(mdio_bus, phy_addr, MMD_DATA_ADDR, mmd_reg);
++	if (ret < 0)
++		return ret;
++	ret = mdio_bus->write(mdio_bus, phy_addr, MMD_REG_ADDR,
++			      mmd_index | 0x4000);
++	if (ret < 0)
++		return ret;
++
++	return hclge_def_phy_opt(mdio_bus, phy_addr, MMD_DATA_ADDR, data,
++				 opt_type);
++}
++
++static void hclge_8521_phy_restores_to_utp_mii(struct hclge_dev *hdev,
++					       struct mii_bus *mdio_bus,
++					       u32 phy_addr)
++{
++	u16 phy_mii_region_val = 0x6;
++	u16 utp_region_val = 0x0;
++	int ret;
++
++	ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++				     HCLGE_8521_PHY_SMI_SDS_ADDR,
++				     &utp_region_val, PHY_OP_WRITE);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to choose phy space, ret = %d\n", ret);
++
++	ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++				     HCLGE_8521_PHY_LDS_MII_ADDR,
++				     &phy_mii_region_val, PHY_OP_WRITE);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to choose phy MII, ret = %d\n", ret);
++}
++
++static int hclge_8521_phy_utp_mii_opt(struct hnae3_phy_para *para,
++				      struct mii_bus *mdio_bus, u32 phy_addr,
++				      enum hclge_phy_op_code opt_type)
++{
++	u16 phy_mii_region_val = 0x6;
++	u16 utp_region_val = 0x0;
++	int ret;
++
++	ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++				     HCLGE_8521_PHY_SMI_SDS_ADDR,
++				     &utp_region_val, PHY_OP_WRITE);
++	if (ret)
++		return ret;
++
++	ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++				     HCLGE_8521_PHY_LDS_MII_ADDR,
++				     &phy_mii_region_val, PHY_OP_WRITE);
++	if (ret)
++		return ret;
++
++	return hclge_def_phy_opt(mdio_bus, phy_addr, (u16)para->reg_addr,
++				 &para->data, opt_type);
++}
++
++static int hclge_8521_phy_utp_mmd_opt(struct hnae3_phy_para *para,
++				      struct mii_bus *mdio_bus, u32 phy_addr,
++				      enum hclge_phy_op_code opt_type)
++{
++	u16 utp_region_val = 0x0;
++	int ret;
++
++	ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++				     HCLGE_8521_PHY_SMI_SDS_ADDR,
++				     &utp_region_val, PHY_OP_WRITE);
++	if (ret)
++		return ret;
++
++	return hclge_8521_phy_mmd_opt(mdio_bus, phy_addr, para->reg_addr,
++				      &para->data, opt_type);
++}
++
++static int hclge_8521_phy_utp_lds_opt(struct hnae3_phy_para *para,
++				      struct mii_bus *mdio_bus, u32 phy_addr,
++				      enum hclge_phy_op_code opt_type)
++{
++	u16 lds_mii_region_val = 0x4;
++	u16 utp_region_val = 0x0;
++	int ret;
++
++	ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++				     HCLGE_8521_PHY_SMI_SDS_ADDR,
++				     &utp_region_val, PHY_OP_WRITE);
++	if (ret)
++		return ret;
++
++	ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++				     HCLGE_8521_PHY_LDS_MII_ADDR,
++				     &lds_mii_region_val, PHY_OP_WRITE);
++	if (ret)
++		return ret;
++
++	return hclge_def_phy_opt(mdio_bus, phy_addr, (u16)para->reg_addr,
++				 &para->data, opt_type);
++}
++
++static int hclge_8521_phy_utp_ext_opt(struct hnae3_phy_para *para,
++				      struct mii_bus *mdio_bus, u32 phy_addr,
++				      enum hclge_phy_op_code opt_type)
++{
++	u16 utp_region_val = 0x0;
++	int ret;
++
++	ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++				     HCLGE_8521_PHY_SMI_SDS_ADDR,
++				     &utp_region_val, PHY_OP_WRITE);
++	if (ret)
++		return ret;
++
++	return hclge_8521_phy_ext_opt(mdio_bus, phy_addr, (u16)para->reg_addr,
++				      &para->data, opt_type);
++}
++
++static int hclge_8521_phy_sds_mii_opt(struct hnae3_phy_para *para,
++				      struct mii_bus *mdio_bus, u32 phy_addr,
++				      enum hclge_phy_op_code opt_type)
++{
++	u16 sds_region_val = 0x2;
++	int ret;
++
++	ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++				     HCLGE_8521_PHY_SMI_SDS_ADDR,
++				     &sds_region_val, PHY_OP_WRITE);
++	if (ret)
++		return ret;
++
++	return hclge_def_phy_opt(mdio_bus, phy_addr, (u16)para->reg_addr,
++				 &para->data, opt_type);
++}
++
++static int hclge_8521_phy_sds_ext_opt(struct hnae3_phy_para *para,
++				      struct mii_bus *mdio_bus, u32 phy_addr,
++				      enum hclge_phy_op_code opt_type)
++{
++	u16 sds_region_val = 0x2;
++	int ret;
++
++	ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++				     HCLGE_8521_PHY_SMI_SDS_ADDR,
++				     &sds_region_val, PHY_OP_WRITE);
++	if (ret)
++		return ret;
++
++	return hclge_8521_phy_ext_opt(mdio_bus, phy_addr, (u16)para->reg_addr,
++				      &para->data, opt_type);
++}
++
++static int hclge_8521_phy_opt(struct hclge_dev *hdev,
++			      struct hnae3_phy_para *para,
++			      enum hclge_phy_op_code opt_type)
++{
++	struct mii_bus *mdio_bus = hdev->hw.mac.mdio_bus;
++	u32 phy_addr = hdev->hw.mac.phy_addr;
++	int ret;
++
++	mutex_lock(&mdio_bus->mdio_lock);
++	switch (para->page) {
++	case HCLGE_PHY_REGION_UTP_MII:
++		ret = hclge_8521_phy_utp_mii_opt(para, mdio_bus,
++						 phy_addr, opt_type);
++		break;
++	case HCLGE_PHY_REGION_UTP_MMD:
++		ret = hclge_8521_phy_utp_mmd_opt(para, mdio_bus,
++						 phy_addr, opt_type);
++		break;
++	case HCLGE_PHY_REGION_UTP_LDS:
++		ret = hclge_8521_phy_utp_lds_opt(para, mdio_bus,
++						 phy_addr, opt_type);
++		break;
++	case HCLGE_PHY_REGION_UTP_EXT:
++		ret = hclge_8521_phy_utp_ext_opt(para, mdio_bus,
++						 phy_addr, opt_type);
++		break;
++	case HCLGE_PHY_REGION_SDS_MII:
++		ret = hclge_8521_phy_sds_mii_opt(para, mdio_bus,
++						 phy_addr, opt_type);
++		break;
++	case HCLGE_PHY_REGION_SDS_EXT:
++		ret = hclge_8521_phy_sds_ext_opt(para, mdio_bus,
++						 phy_addr, opt_type);
++		break;
++	case HCLGE_PHY_REGION_COM_REG:
++		ret = hclge_8521_phy_ext_opt(mdio_bus, phy_addr,
++					     (u16)para->reg_addr,
++					     &para->data, opt_type);
++		break;
++	default:
++		dev_err(&hdev->pdev->dev, "invalid reg region: %d\n",
++			para->page);
++		mutex_unlock(&mdio_bus->mdio_lock);
++		return -EINVAL;
++	}
++
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"phy operation failed %d, reg_region: %d, data: 0x%x\n",
++			ret, para->page, para->data);
++
++	/* Set the region to UTP MII after operating the 8521 phy register */
++	hclge_8521_phy_restores_to_utp_mii(hdev, mdio_bus, phy_addr);
++	mutex_unlock(&mdio_bus->mdio_lock);
++	return ret;
++}
++
++static int hclge_check_phy_opt_param(struct hclge_dev *hdev, void *data,
++				     size_t length)
++{
++	struct hnae3_phy_para *para = (struct hnae3_phy_para *)data;
++	struct hclge_mac *mac = &hdev->hw.mac;
++
++	if (length != sizeof(*para))
++		return -EINVAL;
++
++	if (mac->media_type != HNAE3_MEDIA_TYPE_COPPER) {
++		dev_err(&hdev->pdev->dev, "this is not a copper port");
++		return -EOPNOTSUPP;
++	}
++
++	if (hnae3_dev_phy_imp_supported(hdev))
++		return 0;
++
++	if (!mac->phydev) {
++		dev_err(&hdev->pdev->dev, "this net device has no phy");
++		return -EINVAL;
++	}
++
++	if (!mac->mdio_bus) {
++		dev_err(&hdev->pdev->dev, "this net device has no mdio bus");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int hclge_8211_phy_indirect_opt(struct hclge_dev *hdev,
++				       struct hnae3_phy_para *para,
++				       struct mii_bus *mdio_bus, u32 phy_addr,
++				       enum hclge_phy_op_code opt_type)
++{
++	u32 indirect_reg_data;
++	int ret;
++
++	/* select indirect page 0xa43 */
++	ret = mdio_bus->write(mdio_bus, phy_addr, para->page_select_addr,
++			      HCLGE_8211_PHY_INDIRECT_PAGE);
++	if (ret < 0) {
++		dev_err(&hdev->pdev->dev,
++			"failed to change phy %u indirect page 0xa43\n",
++			phy_addr);
++		return ret;
++	}
++	/* indirect access addr = page_no*16 + 2*(reg_no%16) */
++	indirect_reg_data = (para->page << 4) + ((para->reg_addr % 16) << 1);
++	ret = mdio_bus->write(mdio_bus, phy_addr, HCLGE_8211_PHY_INDIRECT_REG,
++			      indirect_reg_data);
++	if (ret < 0) {
++		dev_err(&hdev->pdev->dev,
++			"failed to write phy %u indirect reg\n", phy_addr);
++		return ret;
++	}
++
++	ret = hclge_def_phy_opt(mdio_bus, phy_addr,
++				HCLGE_8211_PHY_INDIRECT_DATA, &para->data,
++				opt_type);
++	if (ret < 0)
++		dev_err(&hdev->pdev->dev,
++			"failed to %s phy %u indirect data\n, ret = %d",
++			opt_type == PHY_OP_READ ? "read" : "write",
++			phy_addr, ret);
++
++	return ret;
++}
++
++static int hclge_8211_phy_need_indirect_access(u16 page)
++{
++	if (page >= HCLGE_8211_PHY_INDIRECT_RANGE1_S &&
++	    page <= HCLGE_8211_PHY_INDIRECT_RANGE1_E)
++		return true;
++	else if (page >= HCLGE_8211_PHY_INDIRECT_RANGE2_S &&
++		 page <= HCLGE_8211_PHY_INDIRECT_RANGE2_E)
++		return true;
++
++	return false;
++}
++
++static int hclge_8211_phy_reg_opt(struct hclge_dev *hdev,
++				  struct hnae3_phy_para *para,
++				  enum hclge_phy_op_code opt_type)
++{
++	struct mii_bus *mdio_bus = hdev->hw.mac.mdio_bus;
++	u32 phy_addr = hdev->hw.mac.phy_addr;
++	u16 save_page;
++	int ret;
++
++	mutex_lock(&mdio_bus->mdio_lock);
++	ret = mdio_bus->read(mdio_bus, phy_addr, para->page_select_addr);
++	if (ret < 0) {
++		dev_err(&hdev->pdev->dev,
++			"failed to record phy %u reg page\n", phy_addr);
++		mutex_unlock(&mdio_bus->mdio_lock);
++		return ret;
++	}
++	save_page = ret;
++	ret = hclge_8211_phy_indirect_opt(hdev, para, mdio_bus, phy_addr,
++					  opt_type);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to indirect access 8211 phy %u\n", phy_addr);
++	ret = mdio_bus->write(mdio_bus, phy_addr, para->page_select_addr,
++			      save_page);
++	if (ret < 0)
++		dev_err(&hdev->pdev->dev,
++			"failed to restore phy %u reg page %u\n",
++			phy_addr, save_page);
++	mutex_unlock(&mdio_bus->mdio_lock);
++
++	return ret;
++}
++
++static int hclge_rw_8211_phy_reg(struct hclge_dev *hdev,
++				 struct hnae3_phy_para *para,
++				 enum hclge_phy_op_code opt_type)
++{
++	if (hclge_8211_phy_need_indirect_access(para->page))
++		return hclge_8211_phy_reg_opt(hdev, para, opt_type);
++
++	return hclge_phy_reg_opt(hdev, para, opt_type);
++}
++
++/* used when imp support phy drvier */
++static int hclge_read_phy_reg_with_page(struct hclge_dev *hdev, u16 page,
++					u16 reg_addr, u16 *val)
++{
++	struct hclge_phy_reg_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PHY_REG, true);
++
++	req = (struct hclge_phy_reg_cmd *)desc.data;
++	req->reg_addr = cpu_to_le16(reg_addr);
++	req->type = HCLGE_PHY_RW_WITH_PAGE;
++	req->page = cpu_to_le16(page);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to read phy page %u reg %u, ret = %d\n",
++			page, reg_addr, ret);
++		return ret;
++	}
++
++	*val = le16_to_cpu(req->reg_val);
++	return 0;
++}
++
++/* used when imp support phy drvier */
++static int hclge_write_phy_reg_with_page(struct hclge_dev *hdev, u16 page,
++					 u16 reg_addr, u16 val)
++{
++	struct hclge_phy_reg_cmd *req;
++	struct hclge_desc desc;
++	int ret;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PHY_REG, false);
++
++	req = (struct hclge_phy_reg_cmd *)desc.data;
++	req->reg_addr = cpu_to_le16(reg_addr);
++	req->type = HCLGE_PHY_RW_WITH_PAGE;
++	req->page = cpu_to_le16(page);
++	req->reg_val = cpu_to_le16(val);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to write phy page %u reg %u, ret = %d\n",
++			page, reg_addr, ret);
++
++	return ret;
++}
++
++static int hclge_rw_phy_reg_with_page(struct hclge_dev *hdev,
++				      struct hnae3_phy_para *para,
++				      enum hclge_phy_op_code opt_type)
++{
++	if (opt_type == PHY_OP_READ)
++		return hclge_read_phy_reg_with_page(hdev, para->page,
++						    para->reg_addr,
++						    &para->data);
++
++	return hclge_write_phy_reg_with_page(hdev, para->page, para->reg_addr,
++					     para->data);
++}
++
++static int hclge_rw_phy_reg(struct hclge_dev *hdev, void *data,
++			    size_t length, enum hclge_phy_op_code opt_type)
++{
++	struct hnae3_phy_para *para = (struct hnae3_phy_para *)data;
++	struct hclge_mac *mac = &hdev->hw.mac;
++	u32 phy_id;
++	int ret;
++
++	ret = hclge_check_phy_opt_param(hdev, data, length);
++	if (ret < 0)
++		return ret;
++
++	if (hnae3_dev_phy_imp_supported(hdev))
++		return hclge_rw_phy_reg_with_page(hdev, para, opt_type);
++
++	phy_id = mac->phydev->phy_id & HCLGE_PHY_ID_MASK;
++	switch (phy_id) {
++	case HCLGE_PHY_ID_FOR_RTL8211:
++		return hclge_rw_8211_phy_reg(hdev, para, opt_type);
++	case HCLGE_PHY_ID_FOR_YT8521:
++		return hclge_8521_phy_opt(hdev, para, opt_type);
++	case HCLGE_PHY_ID_FOR_MVL1512:
++	default:
++		return hclge_phy_reg_opt(hdev, para, opt_type);
++	}
++}
++
++static int hclge_get_phy_reg(struct hclge_dev *hdev, void *data, size_t length)
++{
++	return hclge_rw_phy_reg(hdev, data, length, PHY_OP_READ);
++}
++
++static int hclge_set_phy_reg(struct hclge_dev *hdev, void *data, size_t length)
++{
++	return hclge_rw_phy_reg(hdev, data, length, PHY_OP_WRITE);
++}
++
+ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ {
+ 	if (hdev->reset_type != HNAE3_IMP_RESET &&
+@@ -859,6 +1416,8 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_SET_MAC_STATE] = hclge_set_mac_state,
+ 	[HNAE3_EXT_OPC_SET_LED] = hclge_set_led,
+ 	[HNAE3_EXT_OPC_GET_LED_SIGNAL] = hclge_get_led_signal,
++	[HNAE3_EXT_OPC_GET_PHY_REG] = hclge_get_phy_reg,
++	[HNAE3_EXT_OPC_SET_PHY_REG] = hclge_set_phy_reg,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+index dab62a588e53..090152a87c60 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+@@ -5,6 +5,38 @@
+ #define __HCLGE_EXT_H
+ #include <linux/types.h>
+ 
++#define HCLGE_PHY_ID_FOR_RTL8211 0x001cc910
++#define HCLGE_PHY_ID_FOR_MVL1512 0x01410dd0
++#define HCLGE_PHY_ID_FOR_YT8521  0x00000110
++#define HCLGE_PHY_ID_MASK	0xFFFFFFF0U
++
++enum hclge_phy_page_region {
++	HCLGE_PHY_REGION_UTP_MII,
++	HCLGE_PHY_REGION_UTP_MMD,
++	HCLGE_PHY_REGION_UTP_LDS,
++	HCLGE_PHY_REGION_UTP_EXT,
++	HCLGE_PHY_REGION_SDS_MII,
++	HCLGE_PHY_REGION_SDS_EXT,
++	HCLGE_PHY_REGION_COM_REG,
++	HCLGE_PHY_REGION_MAX
++};
++
++enum hclge_phy_op_code {
++	PHY_OP_READ,
++	PHY_OP_WRITE
++};
++
++#define HCLGE_8211_PHY_INDIRECT_PAGE	0xa43
++#define HCLGE_8211_PHY_INDIRECT_REG	0x1b
++#define HCLGE_8211_PHY_INDIRECT_DATA	0x1c
++#define HCLGE_8211_PHY_INDIRECT_RANGE1_S	0xDC0
++#define HCLGE_8211_PHY_INDIRECT_RANGE1_E	0xDCF
++#define HCLGE_8211_PHY_INDIRECT_RANGE2_S	0xDE0
++#define HCLGE_8211_PHY_INDIRECT_RANGE2_E	0xDF0
++
++#define HCLGE_8521_PHY_SMI_SDS_ADDR 0xA000
++#define HCLGE_8521_PHY_LDS_MII_ADDR 0x100
++
+ #define HCLGE_NOTIFY_PARA_CFG_PKT_EN		BIT(0)
+ #define HCLGE_NOTIFY_PARA_CFG_START_EN		BIT(1)
+ #define HCLGE_NOTIFY_PARA_CFG_PKT_NUM_M		GENMASK(5, 2)
+-- 
+2.34.1
+
diff --git a/patches/0569-net-ethtool-add-VxLAN-to-the-NFC-API.patch b/patches/0569-net-ethtool-add-VxLAN-to-the-NFC-API.patch
new file mode 100644
index 0000000..675cb5e
--- /dev/null
+++ b/patches/0569-net-ethtool-add-VxLAN-to-the-NFC-API.patch
@@ -0,0 +1,107 @@
+From c5a527e74f6e8d3be11488a2336ab1103535b0cb Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Wed, 18 May 2022 14:36:08 +0800
+Subject: [PATCH 208/283] net: ethtool: add VxLAN to the NFC API
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+----------------------------------------------------------------------
+
+To support for steering VxLAN flows using the ethtool NFC interface, this
+patch adds flow specifications for vxlan4(VxLAN with inner IPv4) and vxlan6
+(VxLAN with inner IPv6).
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ include/uapi/linux/ethtool.h | 50 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 50 insertions(+)
+
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index e57b68fad155..da4258a5f8c2 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -850,6 +850,28 @@ struct ethtool_usrip4_spec {
+ 	__u8    proto;
+ };
+ 
++/**
++ * struct ethtool_vxlan4_spec - general flow specification for VxLAN IPv4
++ * @vni: VxLAN network identifier
++ * @dst: Inner destination eth addr
++ * @src: Inner source eth addr
++ * @eth_type: Inner ethernet type
++ * @tos: Inner type-of-service
++ * @l4_proto: Inner transport protocol number
++ * @ip4src: Inner source host
++ * @ip4dst: Inner destination host
++ */
++struct ethtool_vxlan4_spec {
++	__be32	vni;
++	__u8	dst[ETH_ALEN];
++	__u8	src[ETH_ALEN];
++	__be16	eth_type;
++	__u8	tos;
++	__u8	l4_proto;
++	__be32	ip4src;
++	__be32	ip4dst;
++};
++
+ /**
+  * struct ethtool_tcpip6_spec - flow specification for TCP/IPv6 etc.
+  * @ip6src: Source host
+@@ -900,6 +922,28 @@ struct ethtool_usrip6_spec {
+ 	__u8    l4_proto;
+ };
+ 
++/**
++ * struct ethtool_vxlan6_spec - general flow specification for VxLAN IPv6
++ * @vni: VxLAN network identifier
++ * @dst: Inner destination eth addr
++ * @src: Inner source eth addr
++ * @eth_type: Inner ethernet type
++ * @tclass: Inner traffic Class
++ * @l4_proto: Inner transport protocol number
++ * @ip6src: Inner source host
++ * @ip6dst: Inner destination host
++ */
++struct ethtool_vxlan6_spec {
++	__be32	vni;
++	__u8	dst[ETH_ALEN];
++	__u8	src[ETH_ALEN];
++	__be16	eth_type;
++	__u8	tclass;
++	__u8	l4_proto;
++	__be32	ip6src[4];
++	__be32	ip6dst[4];
++};
++
+ union ethtool_flow_union {
+ 	struct ethtool_tcpip4_spec		tcp_ip4_spec;
+ 	struct ethtool_tcpip4_spec		udp_ip4_spec;
+@@ -915,6 +959,10 @@ union ethtool_flow_union {
+ 	struct ethtool_usrip6_spec		usr_ip6_spec;
+ 	struct ethhdr				ether_spec;
+ 	__u8					hdata[52];
++#ifndef __GENKSYMS__
++	struct ethtool_vxlan4_spec  vxlan_ip4_spec;
++	struct ethtool_vxlan6_spec  vxlan_ip6_spec;
++#endif
+ };
+ 
+ /**
+@@ -1774,6 +1822,8 @@ static inline int ethtool_validate_duplex(__u8 duplex)
+ #define	IPV4_FLOW	0x10	/* hash only */
+ #define	IPV6_FLOW	0x11	/* hash only */
+ #define	ETHER_FLOW	0x12	/* spec only (ether_spec) */
++#define	VXLAN_V4_FLOW	0x43	/* spec only (vxlan_ip4_spec) */
++#define	VXLAN_V6_FLOW	0x44	/* spec only (vxlan_ip6_spec) */
+ /* Flag to enable additional fields in struct ethtool_rx_flow_spec */
+ #define	FLOW_EXT	0x80000000
+ #define	FLOW_MAC_EXT	0x40000000
+-- 
+2.34.1
+
diff --git a/patches/0570-net-hns3-PF-supports-to-set-and-query-lane_num-by-sy.patch b/patches/0570-net-hns3-PF-supports-to-set-and-query-lane_num-by-sy.patch
new file mode 100644
index 0000000..2d5a6ce
--- /dev/null
+++ b/patches/0570-net-hns3-PF-supports-to-set-and-query-lane_num-by-sy.patch
@@ -0,0 +1,305 @@
+From 032dc6157f90eabc76f47b5a655ba7c356955c37 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao418@huawei.com>
+Date: Wed, 30 Nov 2022 18:23:35 +0800
+Subject: [PATCH 209/283] net: hns3: PF supports to set and query lane_num by
+ sysfs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+driver inclusion
+category:feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+----------------------------------------------------------------------
+
+When serdes lane support setting 25Gb/s、50Gb/s speed and user wants to
+set port speed as 50Gb/s, it can be setted as one 50Gb/s serdes lane or
+two 25Gb/s serdes lanes.
+
+So, this patch adds support to query and set lane number by sysfs
+to satisfy this scenario.
+
+Signed-off-by: Hao Chen <chenhao418@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/Makefile
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+---
+ drivers/net/ethernet/hisilicon/hns3/Makefile  |  1 +
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  7 +-
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 24 +++--
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  4 +-
+ .../hisilicon/hns3/hns3pf/hclge_sysfs.c       | 91 +++++++++++++++++++
+ 5 files changed, 118 insertions(+), 9 deletions(-)
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile
+index d0f56781b558..8a9c53f86dce 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/Makefile
+@@ -36,6 +36,7 @@ HCLGE_OBJ = 	hns3pf/hclge_main.o \
+ 			hns3pf/hclge_mdio.o \
+ 			hns3pf/hclge_debugfs.o \
+ 			hns3pf/hclge_tm.o \
++			hns3pf/hclge_sysfs.o \
+ 			hns3pf/hclge_mbx.o \
+ 			hns3pf/hclge_err.o \
+ 			hns3pf/hclge_ptp.o
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index a4599f717da5..38b82f87ec76 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -671,7 +671,9 @@ struct hclge_config_mac_speed_dup_cmd {
+ 
+ #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B	0
+ 	u8 mac_change_fec_en;
+-	u8 rsv[22];
++	u8 rsv[4];
++	u8 lane_num;
++	u8 rsv1[17];
+ };
+ 
+ #define HCLGE_RING_ID_MASK		GENMASK(9, 0)
+@@ -699,7 +701,8 @@ struct hclge_sfp_info_cmd {
+ 	__le32 speed_ability; /* speed ability for current media */
+ 	__le32 module_type;
+ 	u8 fec_ability;
+-	u8 rsv[7];
++	u8 lane_num;
++	u8 rsv[6];
+ };
+ 
+ struct hclge_port_fault_cmd {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 68158219e8c6..898c724a53b8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -2631,7 +2631,7 @@ static u8 hclge_check_speed_dup(u8 duplex, int speed)
+ }
+ 
+ int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
+-				      u8 duplex)
++			       u8 duplex, u8 lane_num)
+ {
+ 	struct hclge_config_mac_speed_dup_cmd *req;
+ 	struct hclge_desc desc;
+@@ -2688,6 +2688,7 @@ int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
+ 
+ 	hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
+ 		      1);
++	req->lane_num = lane_num;
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret) {
+@@ -2709,7 +2710,7 @@ int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
+ 	    mac->duplex == duplex)
+ 		return 0;
+ 
+-	ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
++	ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, 0);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -2874,7 +2875,8 @@ static int hclge_mac_init(struct hclge_dev *hdev)
+ 	hdev->support_sfp_query = true;
+ 	hdev->hw.mac.duplex = HCLGE_MAC_FULL;
+ 	ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
+-					 hdev->hw.mac.duplex);
++					 hdev->hw.mac.duplex,
++					 hdev->hw.mac.lane_num);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -3202,6 +3204,7 @@ static int hclge_get_sfp_info(struct hclge_dev *hdev, struct hclge_mac *mac)
+ 		mac->autoneg = resp->autoneg;
+ 		mac->support_autoneg = resp->autoneg_ability;
+ 		mac->speed_type = QUERY_ACTIVE_SPEED;
++		mac->lane_num = resp->lane_num;
+ 		if (!resp->active_fec)
+ 			mac->fec_mode = 0;
+ 		else
+@@ -7592,7 +7595,7 @@ static int hclge_set_phy_loopback(struct hclge_dev *hdev, bool en)
+ 	}
+ 
+ 	duplex = en ? DUPLEX_FULL : hdev->hw.mac.duplex;
+-	ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, duplex);
++	ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed, duplex, hdev->hw.mac.lane_num);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -11470,13 +11473,19 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 		goto err_mdiobus_unreg;
+ 	}
+ 
++	ret = hclge_register_sysfs(hdev);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to register sysfs, ret = %d\n", ret);
++		goto err_mdiobus_unreg;
++	}
++
+ 	ret = hclge_ptp_init(hdev);
+ 	if (ret)
+-		goto err_mdiobus_unreg;
++		goto err_sysfs_unregister;
+ 
+ 	ret = hclge_update_port_info(hdev);
+ 	if (ret)
+-		goto err_mdiobus_unreg;
++		goto err_sysfs_unregister;
+ 
+ 	INIT_KFIFO(hdev->mac_tnl_log);
+ 
+@@ -11529,6 +11538,8 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 
+ 	return 0;
+ 
++err_sysfs_unregister:
++	hclge_unregister_sysfs(hdev);
+ err_mdiobus_unreg:
+ 	if (hdev->hw.mac.phydev)
+ 		mdiobus_unregister(hdev->hw.mac.mdio_bus);
+@@ -11912,6 +11923,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	struct hclge_dev *hdev = ae_dev->priv;
+ 	struct hclge_mac *mac = &hdev->hw.mac;
+ 
++	hclge_unregister_sysfs(hdev);
+ 	hclge_reset_vf_rate(hdev);
+ 	hclge_clear_vf_vlan(hdev);
+ 	hclge_misc_affinity_teardown(hdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index c2fcbf658bfa..df2b56b83084 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -296,6 +296,7 @@ struct hclge_mac {
+ 	u8 duplex_last;
+ 	u8 support_autoneg;
+ 	u8 speed_type;	/* 0: sfp speed, 1: active speed */
++	u8 lane_num;
+ 	u32 speed;
+ 	u32 max_speed;
+ 	u32 speed_ability; /* speed ability supported by current media */
+@@ -1168,7 +1169,6 @@ int hclge_enable_vport_vlan_filter(struct hclge_vport *vport, bool request_en);
+ int hclge_mac_update_stats(struct hclge_dev *hdev);
+ int hclge_register_sysfs(struct hclge_dev *hdev);
+ void hclge_unregister_sysfs(struct hclge_dev *hdev);
+-int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, u8 duplex);
+ int hclge_get_wol_supported_mode(struct hclge_dev *hdev, u32 *wol_supported);
+ int hclge_get_wol_cfg(struct hclge_dev *hdev, u32 *mode);
+ struct hclge_vport *hclge_get_vf_vport(struct hclge_dev *hdev, int vf);
+@@ -1177,4 +1177,6 @@ void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle);
+ void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
+ 			  u8 *module_type);
+ int hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable);
++int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed, u8 duplex,
++			       u8 lane_num);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c
+new file mode 100644
+index 000000000000..b7cc89c3f6d8
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c
+@@ -0,0 +1,91 @@
++// SPDX-License-Identifier: GPL-2.0+
++// Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved.
++
++#include "hnae3.h"
++#include "hclge_main.h"
++
++static ssize_t lane_num_show(struct device *dev,
++			     struct device_attribute *attr, char *buf)
++{
++	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
++	struct hclge_dev *hdev = ae_dev->priv;
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n", hdev->hw.mac.lane_num);
++}
++
++static ssize_t lane_num_store(struct device *dev,
++			      struct device_attribute *attr,
++			      const char *buf, size_t count)
++{
++#define HCLGE_CONVERSION_NUM	10  /* Convert string to decimal number */
++
++	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
++	struct hclge_dev *hdev = ae_dev->priv;
++	u8 lane_num, duplex;
++	u32 speed;
++	int ret;
++
++	ret = kstrtou8(buf, HCLGE_CONVERSION_NUM, &lane_num);
++	if (ret) {
++		dev_err(dev, "input params of lane number format unmatch.\n");
++		return -EINVAL;
++	}
++
++	if (!lane_num || lane_num > 8 || !is_power_of_2(lane_num)) {
++		dev_err(dev, "lane number only supports setting 1, 2, 4, 8.\n");
++		return -EINVAL;
++	}
++
++	rtnl_lock();
++
++	if (hdev->hw.mac.support_autoneg && hdev->hw.mac.autoneg) {
++		ret = count;
++		goto out;
++	}
++
++	if (lane_num == hdev->hw.mac.lane_num) {
++		dev_info(dev, "setting lane number not changed.\n");
++		ret = count;
++		goto out;
++	}
++
++	speed = hdev->hw.mac.speed;
++	duplex = hdev->hw.mac.duplex;
++
++	ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num);
++	if (!ret)
++		ret = count;
++
++out:
++	rtnl_unlock();
++	return ret;
++}
++
++static DEVICE_ATTR_RW(lane_num);
++
++static const struct device_attribute *hclge_hw_attrs_list[] = {
++	&dev_attr_lane_num,
++};
++
++int hclge_register_sysfs(struct hclge_dev *hdev)
++{
++	int ret;
++
++	if (!hnae3_ae_dev_lane_num_supported(hdev->ae_dev))
++		return 0;
++
++	ret = device_create_file(&hdev->pdev->dev, hclge_hw_attrs_list[0]);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to create node %s, ret = %d.\n",
++			hclge_hw_attrs_list[0]->attr.name, ret);
++
++	return ret;
++}
++
++void hclge_unregister_sysfs(struct hclge_dev *hdev)
++{
++	device_remove_file(&hdev->pdev->dev, hclge_hw_attrs_list[0]);
++}
+-- 
+2.34.1
+
diff --git a/patches/0571-net-hns3-refactor-for-function-hclge_fd_convert_tupl.patch b/patches/0571-net-hns3-refactor-for-function-hclge_fd_convert_tupl.patch
new file mode 100644
index 0000000..939c7f3
--- /dev/null
+++ b/patches/0571-net-hns3-refactor-for-function-hclge_fd_convert_tupl.patch
@@ -0,0 +1,299 @@
+From e5d2eb0b4fa3fa99e86d73433506be2abf4b07ee Mon Sep 17 00:00:00 2001
+From: Jian Shen <shenjian15@huawei.com>
+Date: Sat, 24 Jul 2021 15:43:54 +0800
+Subject: [PATCH 210/283] net: hns3: refactor for function
+ hclge_fd_convert_tuple
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit fb72699dfef8706abe203ec8c8fc69a023c161ce
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fb72699dfef8706abe203ec8c8fc69a023c161ce
+
+----------------------------------------------------------------------
+
+Currently, there are too many branches for hclge_fd_convert_tuple().
+And it may be more when add new tuples. Refactor it by sorting the
+tuples according to their length. So it only needs several KEY_OPT
+now, and being flexible to add new tuples.
+
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 189 ++++++++----------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  12 ++
+ 2 files changed, 97 insertions(+), 104 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 898c724a53b8..de98538855c4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -421,36 +421,56 @@ static const struct key_info meta_data_key_info[] = {
+ };
+ 
+ static const struct key_info tuple_key_info[] = {
+-	{ OUTER_DST_MAC, 48},
+-	{ OUTER_SRC_MAC, 48},
+-	{ OUTER_VLAN_TAG_FST, 16},
+-	{ OUTER_VLAN_TAG_SEC, 16},
+-	{ OUTER_ETH_TYPE, 16},
+-	{ OUTER_L2_RSV, 16},
+-	{ OUTER_IP_TOS, 8},
+-	{ OUTER_IP_PROTO, 8},
+-	{ OUTER_SRC_IP, 32},
+-	{ OUTER_DST_IP, 32},
+-	{ OUTER_L3_RSV, 16},
+-	{ OUTER_SRC_PORT, 16},
+-	{ OUTER_DST_PORT, 16},
+-	{ OUTER_L4_RSV, 32},
+-	{ OUTER_TUN_VNI, 24},
+-	{ OUTER_TUN_FLOW_ID, 8},
+-	{ INNER_DST_MAC, 48},
+-	{ INNER_SRC_MAC, 48},
+-	{ INNER_VLAN_TAG_FST, 16},
+-	{ INNER_VLAN_TAG_SEC, 16},
+-	{ INNER_ETH_TYPE, 16},
+-	{ INNER_L2_RSV, 16},
+-	{ INNER_IP_TOS, 8},
+-	{ INNER_IP_PROTO, 8},
+-	{ INNER_SRC_IP, 32},
+-	{ INNER_DST_IP, 32},
+-	{ INNER_L3_RSV, 16},
+-	{ INNER_SRC_PORT, 16},
+-	{ INNER_DST_PORT, 16},
+-	{ INNER_L4_RSV, 32},
++	{ OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 },
++	{ OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 },
++	{ OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 },
++	{ OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
++	{ OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 },
++	{ OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 },
++	{ OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 },
++	{ OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 },
++	{ OUTER_SRC_IP, 32, KEY_OPT_IP, -1, -1 },
++	{ OUTER_DST_IP, 32, KEY_OPT_IP, -1, -1 },
++	{ OUTER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 },
++	{ OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 },
++	{ OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 },
++	{ OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 },
++	{ OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 },
++	{ OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 },
++	{ INNER_DST_MAC, 48, KEY_OPT_MAC,
++	  offsetof(struct hclge_fd_rule, tuples.dst_mac),
++	  offsetof(struct hclge_fd_rule, tuples_mask.dst_mac) },
++	{ INNER_SRC_MAC, 48, KEY_OPT_MAC,
++	  offsetof(struct hclge_fd_rule, tuples.src_mac),
++	  offsetof(struct hclge_fd_rule, tuples_mask.src_mac) },
++	{ INNER_VLAN_TAG_FST, 16, KEY_OPT_LE16,
++	  offsetof(struct hclge_fd_rule, tuples.vlan_tag1),
++	  offsetof(struct hclge_fd_rule, tuples_mask.vlan_tag1) },
++	{ INNER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
++	{ INNER_ETH_TYPE, 16, KEY_OPT_LE16,
++	  offsetof(struct hclge_fd_rule, tuples.ether_proto),
++	  offsetof(struct hclge_fd_rule, tuples_mask.ether_proto) },
++	{ INNER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 },
++	{ INNER_IP_TOS, 8, KEY_OPT_U8,
++	  offsetof(struct hclge_fd_rule, tuples.ip_tos),
++	  offsetof(struct hclge_fd_rule, tuples_mask.ip_tos) },
++	{ INNER_IP_PROTO, 8, KEY_OPT_U8,
++	  offsetof(struct hclge_fd_rule, tuples.ip_proto),
++	  offsetof(struct hclge_fd_rule, tuples_mask.ip_proto) },
++	{ INNER_SRC_IP, 32, KEY_OPT_IP,
++	  offsetof(struct hclge_fd_rule, tuples.src_ip),
++	  offsetof(struct hclge_fd_rule, tuples_mask.src_ip) },
++	{ INNER_DST_IP, 32, KEY_OPT_IP,
++	  offsetof(struct hclge_fd_rule, tuples.dst_ip),
++	  offsetof(struct hclge_fd_rule, tuples_mask.dst_ip) },
++	{ INNER_L3_RSV, 16, KEY_OPT_LE16, -1, -1 },
++	{ INNER_SRC_PORT, 16, KEY_OPT_LE16,
++	  offsetof(struct hclge_fd_rule, tuples.src_port),
++	  offsetof(struct hclge_fd_rule, tuples_mask.src_port) },
++	{ INNER_DST_PORT, 16, KEY_OPT_LE16,
++	  offsetof(struct hclge_fd_rule, tuples.dst_port),
++	  offsetof(struct hclge_fd_rule, tuples_mask.dst_port) },
++	{ INNER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 },
+ };
+ 
+ static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
+@@ -5850,96 +5870,57 @@ static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
+ static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
+ 				   struct hclge_fd_rule *rule)
+ {
++	int offset, moffset, ip_offset;
++	enum HCLGE_FD_KEY_OPT key_opt;
+ 	u16 tmp_x_s, tmp_y_s;
+ 	u32 tmp_x_l, tmp_y_l;
++	u8 *p = (u8 *)rule;
+ 	int i;
+ 
+-	if (rule->unused_tuple & tuple_bit)
++	if (rule->unused_tuple & BIT(tuple_bit))
+ 		return true;
+ 
+-	switch (tuple_bit) {
+-	case BIT(INNER_DST_MAC):
+-		for (i = 0; i < ETH_ALEN; i++) {
+-			calc_x(key_x[ETH_ALEN - 1 - i], rule->tuples.dst_mac[i],
+-			       rule->tuples_mask.dst_mac[i]);
+-			calc_y(key_y[ETH_ALEN - 1 - i], rule->tuples.dst_mac[i],
+-			       rule->tuples_mask.dst_mac[i]);
+-		}
++	key_opt = tuple_key_info[tuple_bit].key_opt;
++	offset = tuple_key_info[tuple_bit].offset;
++	moffset = tuple_key_info[tuple_bit].moffset;
+ 
+-		return true;
+-	case BIT(INNER_SRC_MAC):
+-		for (i = 0; i < ETH_ALEN; i++) {
+-			calc_x(key_x[ETH_ALEN - 1 - i], rule->tuples.src_mac[i],
+-			       rule->tuples_mask.src_mac[i]);
+-			calc_y(key_y[ETH_ALEN - 1 - i], rule->tuples.src_mac[i],
+-			       rule->tuples_mask.src_mac[i]);
+-		}
++	switch (key_opt) {
++	case KEY_OPT_U8:
++		calc_x(*key_x, p[offset], p[moffset]);
++		calc_y(*key_y, p[offset], p[moffset]);
+ 
+ 		return true;
+-	case BIT(INNER_VLAN_TAG_FST):
+-		calc_x(tmp_x_s, rule->tuples.vlan_tag1,
+-		       rule->tuples_mask.vlan_tag1);
+-		calc_y(tmp_y_s, rule->tuples.vlan_tag1,
+-		       rule->tuples_mask.vlan_tag1);
++	case KEY_OPT_LE16:
++		calc_x(tmp_x_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
++		calc_y(tmp_y_s, *(u16 *)(&p[offset]), *(u16 *)(&p[moffset]));
+ 		*(__le16 *)key_x = cpu_to_le16(tmp_x_s);
+ 		*(__le16 *)key_y = cpu_to_le16(tmp_y_s);
+ 
+ 		return true;
+-	case BIT(INNER_ETH_TYPE):
+-		calc_x(tmp_x_s, rule->tuples.ether_proto,
+-		       rule->tuples_mask.ether_proto);
+-		calc_y(tmp_y_s, rule->tuples.ether_proto,
+-		       rule->tuples_mask.ether_proto);
+-		*(__le16 *)key_x = cpu_to_le16(tmp_x_s);
+-		*(__le16 *)key_y = cpu_to_le16(tmp_y_s);
+-
+-		return true;
+-	case BIT(INNER_IP_TOS):
+-		calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
+-		calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
+-
+-		return true;
+-	case BIT(INNER_IP_PROTO):
+-		calc_x(*key_x, rule->tuples.ip_proto,
+-		       rule->tuples_mask.ip_proto);
+-		calc_y(*key_y, rule->tuples.ip_proto,
+-		       rule->tuples_mask.ip_proto);
+-
+-		return true;
+-	case BIT(INNER_SRC_IP):
+-		calc_x(tmp_x_l, rule->tuples.src_ip[IPV4_INDEX],
+-		       rule->tuples_mask.src_ip[IPV4_INDEX]);
+-		calc_y(tmp_y_l, rule->tuples.src_ip[IPV4_INDEX],
+-		       rule->tuples_mask.src_ip[IPV4_INDEX]);
++	case KEY_OPT_LE32:
++		calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
++		calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
+ 		*(__le32 *)key_x = cpu_to_le32(tmp_x_l);
+ 		*(__le32 *)key_y = cpu_to_le32(tmp_y_l);
+ 
+ 		return true;
+-	case BIT(INNER_DST_IP):
+-		calc_x(tmp_x_l, rule->tuples.dst_ip[IPV4_INDEX],
+-		       rule->tuples_mask.dst_ip[IPV4_INDEX]);
+-		calc_y(tmp_y_l, rule->tuples.dst_ip[IPV4_INDEX],
+-		       rule->tuples_mask.dst_ip[IPV4_INDEX]);
+-		*(__le32 *)key_x = cpu_to_le32(tmp_x_l);
+-		*(__le32 *)key_y = cpu_to_le32(tmp_y_l);
+-
+-		return true;
+-	case BIT(INNER_SRC_PORT):
+-		calc_x(tmp_x_s, rule->tuples.src_port,
+-		       rule->tuples_mask.src_port);
+-		calc_y(tmp_y_s, rule->tuples.src_port,
+-		       rule->tuples_mask.src_port);
+-		*(__le16 *)key_x = cpu_to_le16(tmp_x_s);
+-		*(__le16 *)key_y = cpu_to_le16(tmp_y_s);
++	case KEY_OPT_MAC:
++		for (i = 0; i < ETH_ALEN; i++) {
++			calc_x(key_x[ETH_ALEN - 1 - i], p[offset + i],
++			       p[moffset + i]);
++			calc_y(key_y[ETH_ALEN - 1 - i], p[offset + i],
++			       p[moffset + i]);
++		}
+ 
+ 		return true;
+-	case BIT(INNER_DST_PORT):
+-		calc_x(tmp_x_s, rule->tuples.dst_port,
+-		       rule->tuples_mask.dst_port);
+-		calc_y(tmp_y_s, rule->tuples.dst_port,
+-		       rule->tuples_mask.dst_port);
+-		*(__le16 *)key_x = cpu_to_le16(tmp_x_s);
+-		*(__le16 *)key_y = cpu_to_le16(tmp_y_s);
++	case KEY_OPT_IP:
++		ip_offset = IPV4_INDEX * sizeof(u32);
++		calc_x(tmp_x_l, *(u32 *)(&p[offset + ip_offset]),
++		       *(u32 *)(&p[moffset + ip_offset]));
++		calc_y(tmp_y_l, *(u32 *)(&p[offset + ip_offset]),
++		       *(u32 *)(&p[moffset + ip_offset]));
++		*(__le32 *)key_x = cpu_to_le32(tmp_x_l);
++		*(__le32 *)key_y = cpu_to_le32(tmp_y_l);
+ 
+ 		return true;
+ 	default:
+@@ -6027,12 +6008,12 @@ static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
+ 
+ 	for (i = 0; i < MAX_TUPLE; i++) {
+ 		bool tuple_valid;
+-		u32 check_tuple;
+ 
+ 		tuple_size = tuple_key_info[i].key_length / 8;
+-		check_tuple = key_cfg->tuple_active & BIT(i);
++		if (!(key_cfg->tuple_active & BIT(i)))
++			continue;
+ 
+-		tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
++		tuple_valid = hclge_fd_convert_tuple(i, cur_key_x,
+ 						     cur_key_y, rule);
+ 		if (tuple_valid) {
+ 			cur_key_x += tuple_size;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index df2b56b83084..7c0e15b5b0e0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -629,9 +629,21 @@ enum HCLGE_FD_META_DATA {
+ 	MAX_META_DATA,
+ };
+ 
++enum HCLGE_FD_KEY_OPT {
++	KEY_OPT_U8,
++	KEY_OPT_LE16,
++	KEY_OPT_LE32,
++	KEY_OPT_MAC,
++	KEY_OPT_IP,
++	KEY_OPT_VNI,
++};
++
+ struct key_info {
+ 	u8 key_type;
+ 	u8 key_length; /* use bit as unit */
++	enum HCLGE_FD_KEY_OPT key_opt;
++	int offset;
++	int moffset;
+ };
+ 
+ #define MAX_KEY_LENGTH	400
+-- 
+2.34.1
+
diff --git a/patches/0572-net-hns3-support-set-get-VxLAN-rule-of-rx-flow-direc.patch b/patches/0572-net-hns3-support-set-get-VxLAN-rule-of-rx-flow-direc.patch
new file mode 100644
index 0000000..99b646c
--- /dev/null
+++ b/patches/0572-net-hns3-support-set-get-VxLAN-rule-of-rx-flow-direc.patch
@@ -0,0 +1,467 @@
+From cd36b15b8b9b4bacc08d6a329fc9802f0efa2930 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Wed, 25 May 2022 20:15:56 +0800
+Subject: [PATCH 211/283] net: hns3: support set/get VxLAN rule of rx flow
+ director by ethtool
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+----------------------------------------------------------------------
+
+This patch adds support rule type of vxlan4 and vxlan6 for rx flow
+director by command ethtool -u/-U.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+---
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 279 +++++++++++++++++-
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   3 +
+ 2 files changed, 274 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index de98538855c4..de5c85415865 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -16,6 +16,7 @@
+ #include <net/ipv6.h>
+ #include <net/rtnetlink.h>
+ #include "kcompat.h"
++#include <net/vxlan.h>
+ #include "hclge_cmd.h"
+ #include "hclge_dcb.h"
+ #include "hclge_ext.h"
+@@ -435,7 +436,9 @@ static const struct key_info tuple_key_info[] = {
+ 	{ OUTER_SRC_PORT, 16, KEY_OPT_LE16, -1, -1 },
+ 	{ OUTER_DST_PORT, 16, KEY_OPT_LE16, -1, -1 },
+ 	{ OUTER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 },
+-	{ OUTER_TUN_VNI, 24, KEY_OPT_VNI, -1, -1 },
++	{ OUTER_TUN_VNI, 24, KEY_OPT_VNI,
++	  offsetof(struct hclge_fd_rule, tuples.outer_tun_vni),
++	  offsetof(struct hclge_fd_rule, tuples_mask.outer_tun_vni) },
+ 	{ OUTER_TUN_FLOW_ID, 8, KEY_OPT_U8, -1, -1 },
+ 	{ INNER_DST_MAC, 48, KEY_OPT_MAC,
+ 	  offsetof(struct hclge_fd_rule, tuples.dst_mac),
+@@ -5762,8 +5765,9 @@ static int hclge_init_fd_config(struct hclge_dev *hdev)
+ 
+ 	/* If use max 400bit key, we can support tuples for ether type */
+ 	if (hdev->fd_cfg.fd_mode == HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1)
+-		key_cfg->tuple_active |=
+-				BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
++		key_cfg->tuple_active |= BIT(INNER_DST_MAC) |
++					 BIT(INNER_SRC_MAC) |
++					 BIT(OUTER_TUN_VNI);
+ 
+ 	/* roce_type is used to filter roce frames
+ 	 * dst_vport is used to specify the rule
+@@ -5870,6 +5874,8 @@ static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
+ static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
+ 				   struct hclge_fd_rule *rule)
+ {
++#define HCLGE_VNI_LENGTH	3
++
+ 	int offset, moffset, ip_offset;
+ 	enum HCLGE_FD_KEY_OPT key_opt;
+ 	u16 tmp_x_s, tmp_y_s;
+@@ -5922,6 +5928,16 @@ static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
+ 		*(__le32 *)key_x = cpu_to_le32(tmp_x_l);
+ 		*(__le32 *)key_y = cpu_to_le32(tmp_y_l);
+ 
++		return true;
++	case KEY_OPT_VNI:
++		calc_x(tmp_x_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
++		calc_y(tmp_y_l, *(u32 *)(&p[offset]), *(u32 *)(&p[moffset]));
++		for (i = 0; i < HCLGE_VNI_LENGTH; i++) {
++			key_x[i] = (cpu_to_le32(tmp_x_l) >>
++				   (i * BITS_PER_BYTE)) & 0xFF;
++			key_y[i] = (cpu_to_le32(tmp_y_l) >>
++				   (i * BITS_PER_BYTE)) & 0xFF;
++		}
+ 		return true;
+ 	default:
+ 		return false;
+@@ -6138,6 +6154,45 @@ static int hclge_fd_check_ip4_tuple(struct ethtool_usrip4_spec *spec,
+ 	return 0;
+ }
+ 
++static int hclge_fd_check_vxlan4_tuple(struct ethtool_rx_flow_spec *fs,
++				       u32 *unused_tuple)
++{
++	struct ethtool_vxlan4_spec *spec = &fs->h_u.vxlan_ip4_spec;
++	struct ethtool_vxlan4_spec *mask = &fs->m_u.vxlan_ip4_spec;
++
++	/* Vni is only 24 bits and must be greater than 0, and it can not be
++	 * masked.
++	 */
++	if (!spec->vni || be32_to_cpu(spec->vni) >= VXLAN_N_VID ||
++	    mask->vni != HCLGE_FD_VXLAN_VNI_UNMASK || !unused_tuple)
++		return -EINVAL;
++
++	*unused_tuple |= BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
++
++	if (is_zero_ether_addr(spec->src))
++		*unused_tuple |= BIT(INNER_SRC_MAC);
++
++	if (is_zero_ether_addr(spec->dst))
++		*unused_tuple |= BIT(INNER_DST_MAC);
++
++	if (!spec->eth_type)
++		*unused_tuple |= BIT(INNER_ETH_TYPE);
++
++	if (!spec->ip4src)
++		*unused_tuple |= BIT(INNER_SRC_IP);
++
++	if (!spec->ip4dst)
++		*unused_tuple |= BIT(INNER_DST_IP);
++
++	if (!spec->tos)
++		*unused_tuple |= BIT(INNER_IP_TOS);
++
++	if (!spec->l4_proto)
++		*unused_tuple |= BIT(INNER_IP_PROTO);
++
++	return 0;
++}
++
+ static int hclge_fd_check_tcpip6_tuple(struct ethtool_tcpip6_spec *spec,
+ 				       u32 *unused_tuple)
+ {
+@@ -6194,6 +6249,45 @@ static int hclge_fd_check_ip6_tuple(struct ethtool_usrip6_spec *spec,
+ 	return 0;
+ }
+ 
++static int hclge_fd_check_vxlan6_tuple(struct ethtool_rx_flow_spec *fs,
++				       u32 *unused_tuple)
++{
++	struct ethtool_vxlan6_spec *spec = &fs->h_u.vxlan_ip6_spec;
++	struct ethtool_vxlan6_spec *mask = &fs->m_u.vxlan_ip6_spec;
++
++	/* Vni is only 24 bits and must be greater than 0, and it can not be
++	 * masked.
++	 */
++	if (!spec->vni || be32_to_cpu(spec->vni) >= VXLAN_N_VID ||
++	    mask->vni != HCLGE_FD_VXLAN_VNI_UNMASK || !unused_tuple)
++		return -EINVAL;
++
++	*unused_tuple |= BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
++
++	if (is_zero_ether_addr(spec->src))
++		*unused_tuple |= BIT(INNER_SRC_MAC);
++
++	if (is_zero_ether_addr(spec->dst))
++		*unused_tuple |= BIT(INNER_DST_MAC);
++
++	if (!spec->eth_type)
++		*unused_tuple |= BIT(INNER_ETH_TYPE);
++
++	if (ipv6_addr_any((struct in6_addr *)spec->ip6src))
++		*unused_tuple |= BIT(INNER_SRC_IP);
++
++	if (ipv6_addr_any((struct in6_addr *)spec->ip6dst))
++		*unused_tuple |= BIT(INNER_DST_IP);
++
++	if (!spec->tclass)
++		*unused_tuple |= BIT(INNER_IP_TOS);
++
++	if (!spec->l4_proto)
++		*unused_tuple |= BIT(INNER_IP_PROTO);
++
++	return 0;
++}
++
+ static int hclge_fd_check_ether_tuple(struct ethhdr *spec, u32 *unused_tuple)
+ {
+ 	if (!spec || !unused_tuple)
+@@ -6287,6 +6381,9 @@ static int hclge_fd_check_spec(struct hclge_dev *hdev,
+ 		ret = hclge_fd_check_ip4_tuple(&fs->h_u.usr_ip4_spec,
+ 					       unused_tuple);
+ 		break;
++	case VXLAN_V4_FLOW:
++		ret = hclge_fd_check_vxlan4_tuple(fs, unused_tuple);
++		break;
+ 	case SCTP_V6_FLOW:
+ 	case TCP_V6_FLOW:
+ 	case UDP_V6_FLOW:
+@@ -6297,6 +6394,9 @@ static int hclge_fd_check_spec(struct hclge_dev *hdev,
+ 		ret = hclge_fd_check_ip6_tuple(&fs->h_u.usr_ip6_spec,
+ 					       unused_tuple);
+ 		break;
++	case VXLAN_V6_FLOW:
++		ret = hclge_fd_check_vxlan6_tuple(fs, unused_tuple);
++		break;
+ 	case ETHER_FLOW:
+ 		if (hdev->fd_cfg.fd_mode !=
+ 			HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1) {
+@@ -6391,6 +6491,68 @@ static int hclge_fd_update_rule_list(struct hclge_dev *hdev,
+ 	return 0;
+ }
+ 
++static void hclge_fd_get_vxlan4_tuple(struct ethtool_rx_flow_spec *fs,
++				      struct hclge_fd_rule *rule)
++{
++	struct ethtool_vxlan4_spec *h = &fs->h_u.vxlan_ip4_spec;
++	struct ethtool_vxlan4_spec *m = &fs->m_u.vxlan_ip4_spec;
++
++	rule->tuples.outer_tun_vni = be32_to_cpu(h->vni);
++	rule->tuples_mask.outer_tun_vni = be32_to_cpu(m->vni);
++
++	ether_addr_copy(rule->tuples.src_mac, h->src);
++	ether_addr_copy(rule->tuples_mask.src_mac, m->src);
++
++	ether_addr_copy(rule->tuples.dst_mac, h->dst);
++	ether_addr_copy(rule->tuples_mask.dst_mac, m->dst);
++
++	rule->tuples.ether_proto = be16_to_cpu(h->eth_type);
++	rule->tuples_mask.ether_proto = be16_to_cpu(m->eth_type);
++
++	rule->tuples.ip_tos = h->tos;
++	rule->tuples_mask.ip_tos = m->tos;
++
++	rule->tuples.ip_proto = h->l4_proto;
++	rule->tuples_mask.ip_proto = m->l4_proto;
++
++	rule->tuples.src_ip[IPV4_INDEX] = be32_to_cpu(h->ip4src);
++	rule->tuples_mask.src_ip[IPV4_INDEX] = be32_to_cpu(m->ip4src);
++
++	rule->tuples.dst_ip[IPV4_INDEX] = be32_to_cpu(h->ip4dst);
++	rule->tuples_mask.dst_ip[IPV4_INDEX] = be32_to_cpu(m->ip4dst);
++}
++
++static void hclge_fd_get_vxlan6_tuple(struct ethtool_rx_flow_spec *fs,
++				      struct hclge_fd_rule *rule)
++{
++	struct ethtool_vxlan6_spec *h = &fs->h_u.vxlan_ip6_spec;
++	struct ethtool_vxlan6_spec *m = &fs->m_u.vxlan_ip6_spec;
++
++	rule->tuples.outer_tun_vni = be32_to_cpu(h->vni);
++	rule->tuples_mask.outer_tun_vni = be32_to_cpu(m->vni);
++
++	ether_addr_copy(rule->tuples.src_mac, h->src);
++	ether_addr_copy(rule->tuples_mask.src_mac, m->src);
++
++	ether_addr_copy(rule->tuples.dst_mac, h->dst);
++	ether_addr_copy(rule->tuples_mask.dst_mac, m->dst);
++
++	rule->tuples.ether_proto = be16_to_cpu(h->eth_type);
++	rule->tuples_mask.ether_proto = be16_to_cpu(m->eth_type);
++
++	rule->tuples.ip_tos = h->tclass;
++	rule->tuples_mask.ip_tos = m->tclass;
++
++	rule->tuples.ip_proto = h->l4_proto;
++	rule->tuples_mask.ip_proto = m->l4_proto;
++
++	be32_to_cpu_array(rule->tuples.src_ip, h->ip6src, IPV6_SIZE);
++	be32_to_cpu_array(rule->tuples_mask.src_ip, m->ip6src, IPV6_SIZE);
++
++	be32_to_cpu_array(rule->tuples.dst_ip, h->ip6dst, IPV6_SIZE);
++	be32_to_cpu_array(rule->tuples_mask.dst_ip, m->ip6dst, IPV6_SIZE);
++}
++
+ static int hclge_fd_get_tuple(struct hclge_dev *hdev,
+ 			      struct ethtool_rx_flow_spec *fs,
+ 			      struct hclge_fd_rule *rule)
+@@ -6424,7 +6586,6 @@ static int hclge_fd_get_tuple(struct hclge_dev *hdev,
+ 
+ 		rule->tuples.ether_proto = ETH_P_IP;
+ 		rule->tuples_mask.ether_proto = 0xFFFF;
+-
+ 		break;
+ 	case IP_USER_FLOW:
+ 		rule->tuples.src_ip[IPV4_INDEX] =
+@@ -6445,7 +6606,9 @@ static int hclge_fd_get_tuple(struct hclge_dev *hdev,
+ 
+ 		rule->tuples.ether_proto = ETH_P_IP;
+ 		rule->tuples_mask.ether_proto = 0xFFFF;
+-
++		break;
++	case VXLAN_V4_FLOW:
++		hclge_fd_get_vxlan4_tuple(fs, rule);
+ 		break;
+ 	case SCTP_V6_FLOW:
+ 	case TCP_V6_FLOW:
+@@ -6470,7 +6633,6 @@ static int hclge_fd_get_tuple(struct hclge_dev *hdev,
+ 
+ 		rule->tuples.ether_proto = ETH_P_IPV6;
+ 		rule->tuples_mask.ether_proto = 0xFFFF;
+-
+ 		break;
+ 	case IPV6_USER_FLOW:
+ 		be32_to_cpu_array(rule->tuples.src_ip,
+@@ -6488,7 +6650,9 @@ static int hclge_fd_get_tuple(struct hclge_dev *hdev,
+ 
+ 		rule->tuples.ether_proto = ETH_P_IPV6;
+ 		rule->tuples_mask.ether_proto = 0xFFFF;
+-
++		break;
++	case VXLAN_V6_FLOW:
++		hclge_fd_get_vxlan6_tuple(fs, rule);
+ 		break;
+ 	case ETHER_FLOW:
+ 		ether_addr_copy(rule->tuples.src_mac,
+@@ -6505,7 +6669,6 @@ static int hclge_fd_get_tuple(struct hclge_dev *hdev,
+ 				be16_to_cpu(fs->h_u.ether_spec.h_proto);
+ 		rule->tuples_mask.ether_proto =
+ 				be16_to_cpu(fs->m_u.ether_spec.h_proto);
+-
+ 		break;
+ 	default:
+ 		return -EOPNOTSUPP;
+@@ -6836,6 +6999,48 @@ static void hclge_fd_get_ip4_info(struct hclge_fd_rule *rule,
+ 	spec->ip_ver = ETH_RX_NFC_IP4;
+ }
+ 
++static void hclge_fd_get_vxlan4_info(struct hclge_fd_rule *rule,
++				     struct ethtool_vxlan4_spec *spec,
++				     struct ethtool_vxlan4_spec *spec_mask)
++{
++	spec->vni = cpu_to_be32(rule->tuples.outer_tun_vni);
++	spec_mask->vni = rule->unused_tuple & BIT(OUTER_TUN_VNI) ? 0 :
++			 cpu_to_be32(rule->tuples_mask.outer_tun_vni);
++
++	ether_addr_copy(spec->src, rule->tuples.src_mac);
++	ether_addr_copy(spec->dst, rule->tuples.dst_mac);
++
++	if (rule->unused_tuple & BIT(INNER_SRC_MAC))
++		eth_zero_addr(spec_mask->src);
++	else
++		ether_addr_copy(spec_mask->src, rule->tuples_mask.src_mac);
++
++	if (rule->unused_tuple & BIT(INNER_DST_MAC))
++		eth_zero_addr(spec_mask->dst);
++	else
++		ether_addr_copy(spec_mask->dst, rule->tuples_mask.dst_mac);
++
++	spec->eth_type = cpu_to_be16(rule->tuples.ether_proto);
++	spec_mask->eth_type = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 0 :
++			     cpu_to_be16(rule->tuples_mask.ether_proto);
++
++	spec->tos = rule->tuples.ip_tos;
++	spec_mask->tos = rule->unused_tuple & BIT(INNER_IP_TOS) ? 0 :
++			 rule->tuples_mask.ip_tos;
++
++	spec->l4_proto = rule->tuples.ip_proto;
++	spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 0 :
++			     rule->tuples_mask.ip_proto;
++
++	spec->ip4src = cpu_to_be32(rule->tuples.src_ip[IPV4_INDEX]);
++	spec_mask->ip4src = rule->unused_tuple & BIT(INNER_SRC_IP) ? 0 :
++			    cpu_to_be32(rule->tuples_mask.src_ip[IPV4_INDEX]);
++
++	spec->ip4dst = cpu_to_be32(rule->tuples.dst_ip[IPV4_INDEX]);
++	spec_mask->ip4dst = rule->unused_tuple & BIT(INNER_DST_IP) ? 0 :
++			    cpu_to_be32(rule->tuples_mask.dst_ip[IPV4_INDEX]);
++}
++
+ static void hclge_fd_get_tcpip6_info(struct hclge_fd_rule *rule,
+ 				     struct ethtool_tcpip6_spec *spec,
+ 				     struct ethtool_tcpip6_spec *spec_mask)
+@@ -6888,6 +7093,56 @@ static void hclge_fd_get_ip6_info(struct hclge_fd_rule *rule,
+ 			0 : rule->tuples_mask.ip_proto;
+ }
+ 
++static void hclge_fd_get_vxlan6_info(struct hclge_fd_rule *rule,
++				     struct ethtool_vxlan6_spec *spec,
++				     struct ethtool_vxlan6_spec *spec_mask)
++{
++	spec->vni = cpu_to_be32(rule->tuples.outer_tun_vni);
++	spec_mask->vni = rule->unused_tuple & BIT(OUTER_TUN_VNI) ? 0 :
++			 cpu_to_be32(rule->tuples_mask.outer_tun_vni);
++
++	ether_addr_copy(spec->src, rule->tuples.src_mac);
++	ether_addr_copy(spec->dst, rule->tuples.dst_mac);
++
++	if (rule->unused_tuple & BIT(INNER_SRC_MAC))
++		eth_zero_addr(spec_mask->src);
++	else
++		ether_addr_copy(spec_mask->src, rule->tuples_mask.src_mac);
++
++	if (rule->unused_tuple & BIT(INNER_DST_MAC))
++		eth_zero_addr(spec_mask->dst);
++	else
++		ether_addr_copy(spec_mask->dst, rule->tuples_mask.dst_mac);
++
++	spec->eth_type = cpu_to_be16(rule->tuples.ether_proto);
++	spec_mask->eth_type = rule->unused_tuple & BIT(INNER_ETH_TYPE) ? 0 :
++			     cpu_to_be16(rule->tuples_mask.ether_proto);
++
++	spec->tclass = rule->tuples.ip_tos;
++	spec_mask->tclass = rule->unused_tuple & BIT(INNER_IP_TOS) ? 0 :
++			    rule->tuples_mask.ip_tos;
++
++	spec->l4_proto = rule->tuples.ip_proto;
++	spec_mask->l4_proto = rule->unused_tuple & BIT(INNER_IP_PROTO) ? 0 :
++			     rule->tuples_mask.ip_proto;
++
++	cpu_to_be32_array(spec->ip6src,
++			  rule->tuples.src_ip, IPV6_SIZE);
++	cpu_to_be32_array(spec->ip6dst,
++			  rule->tuples.dst_ip, IPV6_SIZE);
++	if (rule->unused_tuple & BIT(INNER_SRC_IP))
++		memset(spec_mask->ip6src, 0, sizeof(spec_mask->ip6src));
++	else
++		cpu_to_be32_array(spec_mask->ip6src, rule->tuples_mask.src_ip,
++				  IPV6_SIZE);
++
++	if (rule->unused_tuple & BIT(INNER_DST_IP))
++		memset(spec_mask->ip6dst, 0, sizeof(spec_mask->ip6dst));
++	else
++		cpu_to_be32_array(spec_mask->ip6dst, rule->tuples_mask.dst_ip,
++				  IPV6_SIZE);
++}
++
+ static void hclge_fd_get_ether_info(struct hclge_fd_rule *rule,
+ 				    struct ethhdr *spec,
+ 				    struct ethhdr *spec_mask)
+@@ -6969,6 +7224,10 @@ static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
+ 		hclge_fd_get_ip4_info(rule, &fs->h_u.usr_ip4_spec,
+ 				      &fs->m_u.usr_ip4_spec);
+ 		break;
++	case VXLAN_V4_FLOW:
++		hclge_fd_get_vxlan4_info(rule, &fs->h_u.vxlan_ip4_spec,
++					 &fs->m_u.vxlan_ip4_spec);
++		break;
+ 	case SCTP_V6_FLOW:
+ 	case TCP_V6_FLOW:
+ 	case UDP_V6_FLOW:
+@@ -6979,6 +7238,10 @@ static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
+ 		hclge_fd_get_ip6_info(rule, &fs->h_u.usr_ip6_spec,
+ 				      &fs->m_u.usr_ip6_spec);
+ 		break;
++	case VXLAN_V6_FLOW:
++		hclge_fd_get_vxlan6_info(rule, &fs->h_u.vxlan_ip6_spec,
++					 &fs->m_u.vxlan_ip6_spec);
++		break;
+ 	/* The flow type of fd rule has been checked before adding in to rule
+ 	 * list. As other flow types have been handled, it must be ETHER_FLOW
+ 	 * for the default case
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 7c0e15b5b0e0..f100e9ad5842 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -651,6 +651,8 @@ struct key_info {
+ #define MAX_KEY_BYTES	(MAX_KEY_DWORDS * 4)
+ #define MAX_META_DATA_LENGTH	32
+ 
++#define HCLGE_FD_VXLAN_VNI_UNMASK	GENMASK(31, 0)
++
+ /* assigned by firmware, the real filter number for each pf may be less */
+ #define MAX_FD_FILTER_NUM	4096
+ #define HCLGE_ARFS_EXPIRE_INTERVAL	5UL
+@@ -707,6 +709,7 @@ struct hclge_fd_rule_tuples {
+ 	u16 ether_proto;
+ 	u8 ip_tos;
+ 	u8 ip_proto;
++	u32 outer_tun_vni;
+ };
+ 
+ struct hclge_fd_rule {
+-- 
+2.34.1
+
diff --git a/patches/0573-net-hns3-Use-the-correct-style-for-SPDX-License-Iden.patch b/patches/0573-net-hns3-Use-the-correct-style-for-SPDX-License-Iden.patch
new file mode 100644
index 0000000..a2f1a8a
--- /dev/null
+++ b/patches/0573-net-hns3-Use-the-correct-style-for-SPDX-License-Iden.patch
@@ -0,0 +1,109 @@
+From 9b461b129e4f7d8dad83c0b2526426c28689cec7 Mon Sep 17 00:00:00 2001
+From: Nishad Kamdar <nishadkamdar@gmail.com>
+Date: Sat, 2 Nov 2019 17:14:42 +0530
+Subject: [PATCH 212/283] net: hns3: Use the correct style for SPDX License
+ Identifier
+
+mainline inclusion
+from mainline-v5.4-rc7
+commit 2ef17216d732f40dcd96423384064d542e3ff658
+category cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2ef17216d732f40dcd96423384064d542e3ff658
+--------------------------------
+
+This patch corrects the SPDX License Identifier style in
+header files related to Hisilicon network devices. For C header files
+Documentation/process/license-rules.rst mandates C-like comments
+(opposed to C source files where C++ style should be used)
+
+Changes made by using a script provided by Joe Perches here:
+https://lkml.org/lkml/2019/2/7/46.
+
+Suggested-by: Joe Perches <joe@perches.com>
+Signed-off-by: Nishad Kamdar <nishadkamdar@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h             | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h         | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h  | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h  | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h   | 2 +-
+ 7 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 838bb4956ee4..437130f8077b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -1,4 +1,4 @@
+-// SPDX-License-Identifier: GPL-2.0+
++/* SPDX-License-Identifier: GPL-2.0+ */
+ // Copyright (c) 2016-2017 Hisilicon Limited.
+ 
+ #ifndef __HNAE3_H
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index b71d06ab6dba..74a48d3a61b3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -1,4 +1,4 @@
+-// SPDX-License-Identifier: GPL-2.0+
++/* SPDX-License-Identifier: GPL-2.0+ */
+ // Copyright (c) 2016-2017 Hisilicon Limited.
+ 
+ #ifndef __HNS3_ENET_H
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 38b82f87ec76..296facdda4c9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -1,4 +1,4 @@
+-// SPDX-License-Identifier: GPL-2.0+
++/* SPDX-License-Identifier: GPL-2.0+ */
+ // Copyright (c) 2016-2017 Hisilicon Limited.
+ 
+ #ifndef __HCLGE_CMD_H
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h
+index 278f21e02736..b04702e65689 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.h
+@@ -1,4 +1,4 @@
+-// SPDX-License-Identifier: GPL-2.0+
++/* SPDX-License-Identifier: GPL-2.0+ */
+ // Copyright (c) 2016-2017 Hisilicon Limited.
+ 
+ #ifndef __HCLGE_DCB_H__
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index f100e9ad5842..155a1719e195 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -1,4 +1,4 @@
+-// SPDX-License-Identifier: GPL-2.0+
++/* SPDX-License-Identifier: GPL-2.0+ */
+ // Copyright (c) 2016-2017 Hisilicon Limited.
+ 
+ #ifndef __HCLGE_MAIN_H
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h
+index 7e019be3816a..fd0e20190b90 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.h
+@@ -1,4 +1,4 @@
+-// SPDX-License-Identifier: GPL-2.0+
++/* SPDX-License-Identifier: GPL-2.0+ */
+ // Copyright (c) 2016-2017 Hisilicon Limited.
+ 
+ #ifndef __HCLGE_MDIO_H
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+index 98d0f871ee61..b36f19a629b2 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+@@ -1,4 +1,4 @@
+-// SPDX-License-Identifier: GPL-2.0+
++/* SPDX-License-Identifier: GPL-2.0+ */
+ // Copyright (c) 2016-2017 Hisilicon Limited.
+ 
+ #ifndef __HCLGE_TM_H
+-- 
+2.34.1
+
diff --git a/patches/0574-net-hns3-add-support-for-getting-GE-port-lanes.patch b/patches/0574-net-hns3-add-support-for-getting-GE-port-lanes.patch
new file mode 100644
index 0000000..9eb5396
--- /dev/null
+++ b/patches/0574-net-hns3-add-support-for-getting-GE-port-lanes.patch
@@ -0,0 +1,47 @@
+From 980de814b7cf31f0f22fb71acc755b186d9aad72 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao418@huawei.com>
+Date: Thu, 15 Dec 2022 11:54:02 +0800
+Subject: [PATCH 213/283] net: hns3: add support for getting GE port lanes
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+The number of lanes on the electrical port is 0, which does not
+meet the expectation. The patch add support for getting GE port
+lanes.
+
+Signed-off-by: Hao Chen <chenhao418@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c
+index b7cc89c3f6d8..6840d7bda82e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c
+@@ -7,11 +7,16 @@
+ static ssize_t lane_num_show(struct device *dev,
+ 			     struct device_attribute *attr, char *buf)
+ {
++#define HCLGE_GE_PORT_ONE_LANE	1
+ 	struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
+ 	struct hclge_dev *hdev = ae_dev->priv;
+ 
+-	return scnprintf(buf, PAGE_SIZE, "%u\n", hdev->hw.mac.lane_num);
++	if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER)
++		return scnprintf(buf, PAGE_SIZE, "%u\n",
++				 HCLGE_GE_PORT_ONE_LANE);
++	else
++		return scnprintf(buf, PAGE_SIZE, "%u\n", hdev->hw.mac.lane_num);
+ }
+ 
+ static ssize_t lane_num_store(struct device *dev,
+-- 
+2.34.1
+
diff --git a/patches/0575-net-hns3-modify-reset-delay-time-to-avoid-configurat.patch b/patches/0575-net-hns3-modify-reset-delay-time-to-avoid-configurat.patch
new file mode 100644
index 0000000..03b9e24
--- /dev/null
+++ b/patches/0575-net-hns3-modify-reset-delay-time-to-avoid-configurat.patch
@@ -0,0 +1,46 @@
+From d7e339e2321282eb7778cf000ac82dd9a760b87e Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Mon, 3 Apr 2023 14:11:07 +0800
+Subject: [PATCH 214/283] net: hns3: modify reset delay time to avoid
+ configuration timeout
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+Currently the vf function reset needs to delay 5000ms for stack recovery.
+This is too long for product configurations and cause configuration
+failures. According to the tests, 500ms delay is enough for reset process
+except PF FLR. So this patch adapts this delay in these scenarios.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 8bd2d8019425..ee76384bdf3f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -1904,7 +1904,10 @@ static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
+ 	 * might happen in case reset assertion was made by PF. Yes, this also
+ 	 * means we might end up waiting bit more even for VF reset.
+ 	 */
+-	msleep(500);
++	if (hdev->reset_type == HNAE3_VF_FULL_RESET)
++		msleep(5000);
++	else
++		msleep(500);
+ 
+ 	return 0;
+ }
+-- 
+2.34.1
+
diff --git a/patches/0576-net-hns3-fix-reset-timeout-when-enable-full-VF.patch b/patches/0576-net-hns3-fix-reset-timeout-when-enable-full-VF.patch
new file mode 100644
index 0000000..1eac74c
--- /dev/null
+++ b/patches/0576-net-hns3-fix-reset-timeout-when-enable-full-VF.patch
@@ -0,0 +1,260 @@
+From 8e0dbcfa3542090d75c09d6aa2b95486e38c29f2 Mon Sep 17 00:00:00 2001
+From: Jijie Shao <shaojijie@huawei.com>
+Date: Fri, 12 May 2023 18:00:14 +0800
+Subject: [PATCH 215/283] net: hns3: fix reset timeout when enable full VF
+
+mainline inclusion
+from mainline-v6.4-rc3
+commit 6b45d5ff8c2c61baddd67d7510075ae121c5e704
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6b45d5ff8c2c61baddd67d7510075ae121c5e704
+
+--------------------------------
+
+The timeout of the cmdq reset command has been increased to
+resolve the reset timeout issue in the full VF scenario.
+The timeout of other cmdq commands remains unchanged.
+
+Fixes: 8d307f8e8cf1 ("net: hns3: create new set of unified hclge_comm_cmd_send APIs")
+Signed-off-by: Jijie Shao <shaojijie@huawei.com>
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+---
+ .../hns3/hns3_common/hclge_comm_cmd.c         | 167 +++++++++++++++++-
+ .../hns3/hns3_common/hclge_comm_cmd.h         |   8 +-
+ 2 files changed, 171 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index 2cb06661bef9..a27736cde913 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -330,9 +330,25 @@ static int hclge_comm_cmd_csq_done(struct hclge_comm_hw *hw)
+ 	return head == hw->cmq.csq.next_to_use;
+ }
+ 
+-static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw,
++static u32 hclge_get_cmdq_tx_timeout(u16 opcode, u32 tx_timeout)
++{
++	static const struct hclge_cmdq_tx_timeout_map cmdq_tx_timeout_map[] = {
++		{HCLGE_OPC_CFG_RST_TRIGGER, HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS},
++	};
++	u32 i;
++
++	for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout_map); i++)
++		if (cmdq_tx_timeout_map[i].opcode == opcode)
++			return cmdq_tx_timeout_map[i].tx_timeout;
++
++	return tx_timeout;
++}
++
++static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw, u16 opcode,
+ 				     bool *is_completed)
+ {
++	u32 cmdq_tx_timeout = hclge_get_cmdq_tx_timeout(opcode,
++							hw->cmq.tx_timeout);
+ 	u32 timeout = 0;
+ 
+ 	do {
+@@ -342,7 +358,7 @@ static void hclge_comm_wait_for_resp(struct hclge_comm_hw *hw,
+ 		}
+ 		udelay(1);
+ 		timeout++;
+-	} while (timeout < hw->cmq.tx_timeout);
++	} while (timeout < cmdq_tx_timeout);
+ }
+ 
+ static int hclge_comm_cmd_convert_err_code(u16 desc_ret)
+@@ -406,7 +422,8 @@ static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw,
+ 	 * if multi descriptors to be sent, use the first one to check
+ 	 */
+ 	if (HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag)))
+-		hclge_comm_wait_for_resp(hw, &is_completed);
++		hclge_comm_wait_for_resp(hw, le16_to_cpu(desc->opcode),
++					 &is_completed);
+ 
+ 	if (!is_completed)
+ 		ret = -EBADE;
+@@ -475,3 +492,147 @@ int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
+ 
+ 	return ret;
+ }
++
++static void hclge_comm_cmd_uninit_regs(struct hclge_comm_hw *hw)
++{
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG, 0);
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG, 0);
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, 0);
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_HEAD_REG, 0);
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_TAIL_REG, 0);
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG, 0);
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG, 0);
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_DEPTH_REG, 0);
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_HEAD_REG, 0);
++	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG, 0);
++}
++
++void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev,
++			   struct hclge_comm_hw *hw)
++{
++	struct hclge_comm_cmq *cmdq = &hw->cmq;
++
++	hclge_comm_firmware_compat_config(ae_dev, hw, false);
++	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state);
++
++	/* wait to ensure that the firmware completes the possible left
++	 * over commands.
++	 */
++	msleep(HCLGE_COMM_CMDQ_CLEAR_WAIT_TIME);
++	spin_lock_bh(&cmdq->csq.lock);
++	spin_lock(&cmdq->crq.lock);
++	hclge_comm_cmd_uninit_regs(hw);
++	spin_unlock(&cmdq->crq.lock);
++	spin_unlock_bh(&cmdq->csq.lock);
++
++	hclge_comm_free_cmd_desc(&cmdq->csq);
++	hclge_comm_free_cmd_desc(&cmdq->crq);
++}
++
++int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw)
++{
++	struct hclge_comm_cmq *cmdq = &hw->cmq;
++	int ret;
++
++	/* Setup the lock for command queue */
++	spin_lock_init(&cmdq->csq.lock);
++	spin_lock_init(&cmdq->crq.lock);
++
++	cmdq->csq.pdev = pdev;
++	cmdq->crq.pdev = pdev;
++
++	/* Setup the queue entries for use cmd queue */
++	cmdq->csq.desc_num = HCLGE_COMM_NIC_CMQ_DESC_NUM;
++	cmdq->crq.desc_num = HCLGE_COMM_NIC_CMQ_DESC_NUM;
++
++	/* Setup Tx write back timeout */
++	cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT;
++
++	/* Setup queue rings */
++	ret = hclge_comm_alloc_cmd_queue(hw, HCLGE_COMM_TYPE_CSQ);
++	if (ret) {
++		dev_err(&pdev->dev, "CSQ ring setup error %d\n", ret);
++		return ret;
++	}
++
++	ret = hclge_comm_alloc_cmd_queue(hw, HCLGE_COMM_TYPE_CRQ);
++	if (ret) {
++		dev_err(&pdev->dev, "CRQ ring setup error %d\n", ret);
++		goto err_csq;
++	}
++
++	return 0;
++err_csq:
++	hclge_comm_free_cmd_desc(&hw->cmq.csq);
++	return ret;
++}
++
++int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,
++			u32 *fw_version, bool is_pf,
++			unsigned long reset_pending)
++{
++	struct hclge_comm_cmq *cmdq = &hw->cmq;
++	int ret;
++
++	spin_lock_bh(&cmdq->csq.lock);
++	spin_lock(&cmdq->crq.lock);
++
++	cmdq->csq.next_to_clean = 0;
++	cmdq->csq.next_to_use = 0;
++	cmdq->crq.next_to_clean = 0;
++	cmdq->crq.next_to_use = 0;
++
++	hclge_comm_cmd_init_regs(hw);
++
++	spin_unlock(&cmdq->crq.lock);
++	spin_unlock_bh(&cmdq->csq.lock);
++
++	clear_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state);
++
++	/* Check if there is new reset pending, because the higher level
++	 * reset may happen when lower level reset is being processed.
++	 */
++	if (reset_pending) {
++		ret = -EBUSY;
++		goto err_cmd_init;
++	}
++
++	/* get version and device capabilities */
++	ret = hclge_comm_cmd_query_version_and_capability(ae_dev, hw,
++							  fw_version, is_pf);
++	if (ret) {
++		dev_err(&ae_dev->pdev->dev,
++			"failed to query version and capabilities, ret = %d\n",
++			ret);
++		goto err_cmd_init;
++	}
++
++	dev_info(&ae_dev->pdev->dev,
++		 "The firmware version is %lu.%lu.%lu.%lu\n",
++		 hnae3_get_field(*fw_version, HNAE3_FW_VERSION_BYTE3_MASK,
++				 HNAE3_FW_VERSION_BYTE3_SHIFT),
++		 hnae3_get_field(*fw_version, HNAE3_FW_VERSION_BYTE2_MASK,
++				 HNAE3_FW_VERSION_BYTE2_SHIFT),
++		 hnae3_get_field(*fw_version, HNAE3_FW_VERSION_BYTE1_MASK,
++				 HNAE3_FW_VERSION_BYTE1_SHIFT),
++		 hnae3_get_field(*fw_version, HNAE3_FW_VERSION_BYTE0_MASK,
++				 HNAE3_FW_VERSION_BYTE0_SHIFT));
++
++	if (!is_pf && ae_dev->dev_version < HNAE3_DEVICE_VERSION_V3)
++		return 0;
++
++	/* ask the firmware to enable some features, driver can work without
++	 * it.
++	 */
++	ret = hclge_comm_firmware_compat_config(ae_dev, hw, true);
++	if (ret)
++		dev_warn(&ae_dev->pdev->dev,
++			 "Firmware compatible features not enabled(%d).\n",
++			 ret);
++	return 0;
++
++err_cmd_init:
++	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hw->comm_state);
++
++	return ret;
++}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 8f07dc44b30a..81904010b96b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -55,7 +55,8 @@
+ #define HCLGE_COMM_NIC_SW_RST_RDY		BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)
+ #define HCLGE_COMM_NIC_CMQ_DESC_NUM_S		3
+ #define HCLGE_COMM_NIC_CMQ_DESC_NUM		1024
+-#define HCLGE_COMM_CMDQ_TX_TIMEOUT		30000
++#define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT	30000
++#define HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS	500000
+ 
+ enum hclge_opcode_type;
+ 
+@@ -115,6 +116,11 @@ struct hclge_comm_caps_bit_map {
+ 	u16 local_bit;
+ };
+ 
++struct hclge_cmdq_tx_timeout_map {
++	u32 opcode;
++	u32 tx_timeout;
++};
++
+ struct hclge_comm_firmware_compat_cmd {
+ 	__le32 compat;
+ 	u8 rsv[20];
+-- 
+2.34.1
+
diff --git a/patches/0577-net-hns3-fix-output-information-incomplete-for-dumpi.patch b/patches/0577-net-hns3-fix-output-information-incomplete-for-dumpi.patch
new file mode 100644
index 0000000..91bdfe4
--- /dev/null
+++ b/patches/0577-net-hns3-fix-output-information-incomplete-for-dumpi.patch
@@ -0,0 +1,61 @@
+From bf1a185842e2e8c60439577a3ff6e13de63728c6 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Fri, 12 May 2023 18:00:11 +0800
+Subject: [PATCH 216/283] net: hns3: fix output information incomplete for
+ dumping tx queue info with debugfs
+
+mainline inclusion
+from mainline-v6.4-rc3
+commit 89f6bfb071182f05d7188c255b0e7251c3806f16
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=89f6bfb071182f05d7188c255b0e7251c3806f16
+
+--------------------------------
+
+In function hns3_dump_tx_queue_info, The print buffer is not enough when
+the tx BD number is configured to 32760. As a result several BD
+information wouldn't be displayed.
+
+So fix it by increasing the tx queue print buffer length.
+
+Fixes: 630a6738da82 ("net: hns3: adjust string spaces of some parameters of tx bd info in debugfs")
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index f2a11eaa7161..9e92e8f92b95 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -109,7 +109,7 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
+ 		.name = "tx_bd_queue",
+ 		.cmd = HNAE3_DBG_CMD_TX_BD,
+ 		.dentry = HNS3_DBG_DENTRY_TX_BD,
+-		.buf_len = HNS3_DBG_READ_LEN_4MB,
++		.buf_len = HNS3_DBG_READ_LEN_5MB,
+ 		.init = hns3_dbg_bd_file_init,
+ 	},
+ 	{
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h
+index 97578eabb7d8..4a5ef8a90a10 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.h
+@@ -10,6 +10,7 @@
+ #define HNS3_DBG_READ_LEN_128KB	0x20000
+ #define HNS3_DBG_READ_LEN_1MB	0x100000
+ #define HNS3_DBG_READ_LEN_4MB	0x400000
++#define HNS3_DBG_READ_LEN_5MB	0x500000
+ #define HNS3_DBG_WRITE_LEN	1024
+ 
+ #define HNS3_DBG_DATA_STR_LEN	32
+-- 
+2.34.1
+
diff --git a/patches/0578-net-hns3-add-support-for-registering-devlink-for-PF.patch b/patches/0578-net-hns3-add-support-for-registering-devlink-for-PF.patch
new file mode 100644
index 0000000..00125ab
--- /dev/null
+++ b/patches/0578-net-hns3-add-support-for-registering-devlink-for-PF.patch
@@ -0,0 +1,212 @@
+From 2c77f992d68b8f40bae799dda0f1bd78740265bf Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Mon, 26 Jul 2021 10:47:02 +0800
+Subject: [PATCH 217/283] net: hns3: add support for registering devlink for PF
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit b741269b275953786832805df329851299ab4de7
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b741269b275953786832805df329851299ab4de7
+
+--------------------------------
+
+Add devlink register support for HNS3 ethernet PF driver.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/Kconfig
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+---
+ drivers/net/ethernet/hisilicon/hns3/Makefile  |  3 +-
+ .../ethernet/hisilicon/hns3/hns3pf/Makefile   |  2 +-
+ .../hisilicon/hns3/hns3pf/hclge_devlink.c     | 54 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_devlink.h     | 15 ++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 10 +++-
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  2 +
+ 6 files changed, 83 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile
+index 8a9c53f86dce..1ac32d60dfe5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/Makefile
+@@ -39,7 +39,8 @@ HCLGE_OBJ = 	hns3pf/hclge_main.o \
+ 			hns3pf/hclge_sysfs.o \
+ 			hns3pf/hclge_mbx.o \
+ 			hns3pf/hclge_err.o \
+-			hns3pf/hclge_ptp.o
++			hns3pf/hclge_ptp.o \
++			hns3pf/hclge_devlink.o
+ 
+ 
+ HCLGE_OBJ_IT_MAIN	=	hns3_extension/hns3pf/hclge_main_it.o \
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile b/drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile
+index 14541e98407f..9a2f6e5da89b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/Makefile
+@@ -7,6 +7,6 @@ ccflags-y := -I $(srctree)/drivers/net/ethernet/hisilicon/hns3
+ ccflags-y += -I $(srctree)/$(src)
+ 
+ obj-$(CONFIG_HNS3_HCLGE) += hclge.o
+-hclge-objs = hclge_main.o hclge_cmd.o hclge_mdio.o hclge_tm.o hclge_mbx.o hclge_debugfs.o hclge_err.o
++hclge-objs = hclge_main.o hclge_cmd.o hclge_mdio.o hclge_tm.o hclge_mbx.o hclge_err.o hclge_debugfs.o hclge_ptp.o hclge_devlink.o
+ 
+ hclge-$(CONFIG_HNS3_DCB) += hclge_dcb.o
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c
+new file mode 100644
+index 000000000000..03b822b0a8e7
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c
+@@ -0,0 +1,54 @@
++// SPDX-License-Identifier: GPL-2.0+
++/* Copyright (c) 2021 Hisilicon Limited. */
++
++#include <net/devlink.h>
++
++#include "hclge_devlink.h"
++
++static const struct devlink_ops hclge_devlink_ops = {
++};
++
++int hclge_devlink_init(struct hclge_dev *hdev)
++{
++	struct pci_dev *pdev = hdev->pdev;
++	struct hclge_devlink_priv *priv;
++	struct devlink *devlink;
++	int ret;
++
++	devlink = devlink_alloc(&hclge_devlink_ops,
++				sizeof(struct hclge_devlink_priv));
++	if (!devlink)
++		return -ENOMEM;
++
++	priv = devlink_priv(devlink);
++	priv->hdev = hdev;
++
++	ret = devlink_register(devlink, &pdev->dev);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to register devlink, ret = %d\n",
++			ret);
++		goto out_reg_fail;
++	}
++
++	hdev->devlink = devlink;
++
++	return 0;
++
++out_reg_fail:
++	devlink_free(devlink);
++	return ret;
++}
++
++void hclge_devlink_uninit(struct hclge_dev *hdev)
++{
++	struct devlink *devlink = hdev->devlink;
++
++	if (!devlink)
++		return;
++
++	devlink_unregister(devlink);
++
++	devlink_free(devlink);
++
++	hdev->devlink = NULL;
++}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h
+new file mode 100644
+index 000000000000..918be04507a5
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/* Copyright (c) 2021 Hisilicon Limited. */
++
++#ifndef __HCLGE_DEVLINK_H
++#define __HCLGE_DEVLINK_H
++
++#include "hclge_main.h"
++
++struct hclge_devlink_priv {
++	struct hclge_dev *hdev;
++};
++
++int hclge_devlink_init(struct hclge_dev *hdev);
++void hclge_devlink_uninit(struct hclge_dev *hdev);
++#endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index de5c85415865..e838d68607c9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -26,6 +26,7 @@
+ #include "hclge_tm.h"
+ #include "hclge_err.h"
+ #include "hnae3.h"
++#include "hclge_devlink.h"
+ 
+ #define HCLGE_NAME			"hclge"
+ 
+@@ -11602,10 +11603,14 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	if (ret)
+ 		goto out;
+ 
++	ret = hclge_devlink_init(hdev);
++	if (ret)
++		goto err_pci_uninit;
++
+ 	/* Firmware command queue initialize */
+ 	ret = hclge_cmd_queue_init(hdev);
+ 	if (ret)
+-		goto err_pci_uninit;
++		goto err_devlink_uninit;
+ 
+ 	/* Firmware command initialize */
+ 	ret = hclge_cmd_init(hdev);
+@@ -11793,6 +11798,8 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	pci_free_irq_vectors(pdev);
+ err_cmd_uninit:
+ 	hclge_cmd_uninit(hdev);
++err_devlink_uninit:
++	hclge_devlink_uninit(hdev);
+ err_pci_uninit:
+ 	pcim_iounmap(pdev, hdev->hw.io_base);
+ 	pci_clear_master(pdev);
+@@ -12189,6 +12196,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 
+ 	hclge_cmd_uninit(hdev);
+ 	hclge_misc_irq_uninit(hdev);
++	hclge_devlink_uninit(hdev);
+ 	hclge_pci_uninit(hdev);
+ 	hclge_uninit_vport_vlan_table(hdev);
+ 	mutex_destroy(&hdev->vport_lock);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 155a1719e195..ad9c1f2fb7ce 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -8,6 +8,7 @@
+ #include <linux/phy.h>
+ #include <linux/if_vlan.h>
+ #include <linux/kfifo.h>
++#include <net/devlink.h>
+ 
+ #include "hclge_cmd.h"
+ #include "hclge_ptp.h"
+@@ -962,6 +963,7 @@ struct hclge_dev {
+ 	struct hclge_ptp *ptp;
+ 	struct hnae3_notify_pkt_param notify_param;
+ 	struct hnae3_torus_param torus_param;
++	struct devlink *devlink;
+ };
+ 
+ /* VPort level vlan tag configuration for TX direction */
+-- 
+2.34.1
+
diff --git a/patches/0579-net-hns3-add-support-for-registering-devlink-for-VF.patch b/patches/0579-net-hns3-add-support-for-registering-devlink-for-VF.patch
new file mode 100644
index 0000000..05f8e06
--- /dev/null
+++ b/patches/0579-net-hns3-add-support-for-registering-devlink-for-VF.patch
@@ -0,0 +1,197 @@
+From 4dc3ef8b862fc9fe71c08b96e61f8d94753dff46 Mon Sep 17 00:00:00 2001
+From: Yufeng Mo <moyufeng@huawei.com>
+Date: Mon, 26 Jul 2021 10:47:03 +0800
+Subject: [PATCH 218/283] net: hns3: add support for registering devlink for VF
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit cd6242991d2e3990c828a7c2215d2d3321f1da39
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cd6242991d2e3990c828a7c2215d2d3321f1da39
+
+--------------------------------
+
+Add devlink register support for HNS3 ethernet VF driver.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/Makefile
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+---
+ drivers/net/ethernet/hisilicon/hns3/Makefile  |  2 +-
+ .../ethernet/hisilicon/hns3/hns3vf/Makefile   |  2 +-
+ .../hisilicon/hns3/hns3vf/hclgevf_devlink.c   | 54 +++++++++++++++++++
+ .../hisilicon/hns3/hns3vf/hclgevf_devlink.h   | 15 ++++++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |  8 +++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.h      |  1 +
+ 6 files changed, 80 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c
+ create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile
+index 1ac32d60dfe5..45ff4d501760 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/Makefile
+@@ -52,7 +52,7 @@ hclge-objs += hns3pf/hclge_ext.o
+ hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o
+ #### compile hclgevf.ko
+ obj-$(CONFIG_HNS3_HCLGEVF) += hclgevf.o
+-hclgevf-objs := hns3vf/hclgevf_main.o hns3vf/hclgevf_cmd.o hns3vf/hclgevf_mbx.o
++hclgevf-objs := hns3vf/hclgevf_main.o hns3vf/hclgevf_cmd.o hns3vf/hclgevf_mbx.o hns3vf/hclgevf_devlink.o
+ 
+ #### compile hns3_cae.ko
+ #add rally code
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/Makefile b/drivers/net/ethernet/hisilicon/hns3/hns3vf/Makefile
+index aa06b79e85a3..51ff7d86ee90 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/Makefile
+@@ -7,4 +7,4 @@ ccflags-y := -I $(srctree)/drivers/net/ethernet/hisilicon/hns3
+ ccflags-y += -I $(srctree)/$(src)
+ 
+ obj-$(CONFIG_HNS3_HCLGEVF) += hclgevf.o
+-hclgevf-objs = hclgevf_main.o hclgevf_cmd.o hclgevf_mbx.o
+\ No newline at end of file
++hclgevf-objs = hclgevf_main.o hclgevf_cmd.o hclgevf_mbx.o  hclgevf_devlink.o
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c
+new file mode 100644
+index 000000000000..55337a975981
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c
+@@ -0,0 +1,54 @@
++// SPDX-License-Identifier: GPL-2.0+
++/* Copyright (c) 2021 Hisilicon Limited. */
++
++#include <net/devlink.h>
++
++#include "hclgevf_devlink.h"
++
++static const struct devlink_ops hclgevf_devlink_ops = {
++};
++
++int hclgevf_devlink_init(struct hclgevf_dev *hdev)
++{
++	struct pci_dev *pdev = hdev->pdev;
++	struct hclgevf_devlink_priv *priv;
++	struct devlink *devlink;
++	int ret;
++
++	devlink = devlink_alloc(&hclgevf_devlink_ops,
++				sizeof(struct hclgevf_devlink_priv));
++	if (!devlink)
++		return -ENOMEM;
++
++	priv = devlink_priv(devlink);
++	priv->hdev = hdev;
++
++	ret = devlink_register(devlink, &pdev->dev);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to register devlink, ret = %d\n",
++			ret);
++		goto out_reg_fail;
++	}
++
++	hdev->devlink = devlink;
++
++	return 0;
++
++out_reg_fail:
++	devlink_free(devlink);
++	return ret;
++}
++
++void hclgevf_devlink_uninit(struct hclgevf_dev *hdev)
++{
++	struct devlink *devlink = hdev->devlink;
++
++	if (!devlink)
++		return;
++
++	devlink_unregister(devlink);
++
++	devlink_free(devlink);
++
++	hdev->devlink = NULL;
++}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h
+new file mode 100644
+index 000000000000..e09ea3d8a963
+--- /dev/null
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/* Copyright (c) 2021 Hisilicon Limited. */
++
++#ifndef __HCLGEVF_DEVLINK_H
++#define __HCLGEVF_DEVLINK_H
++
++#include "hclgevf_main.h"
++
++struct hclgevf_devlink_priv {
++	struct hclgevf_dev *hdev;
++};
++
++int hclgevf_devlink_init(struct hclgevf_dev *hdev);
++void hclgevf_devlink_uninit(struct hclgevf_dev *hdev);
++#endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index ee76384bdf3f..623c53e22249 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -9,6 +9,7 @@
+ #include "hclge_mbx.h"
+ #include "hnae3.h"
+ #include "kcompat.h"
++#include "hclgevf_devlink.h"
+ 
+ #define HCLGEVF_NAME	"hclgevf"
+ 
+@@ -3321,6 +3322,10 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
+ 	if (ret)
+ 		return ret;
+ 
++	ret = hclgevf_devlink_init(hdev);
++	if (ret)
++		goto err_devlink_init;
++
+ 	ret = hclgevf_cmd_queue_init(hdev);
+ 	if (ret)
+ 		goto err_cmd_queue_init;
+@@ -3421,6 +3426,8 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
+ err_cmd_init:
+ 	hclgevf_cmd_uninit(hdev);
+ err_cmd_queue_init:
++	hclgevf_devlink_uninit(hdev);
++err_devlink_init:
+ 	hclgevf_pci_uninit(hdev);
+ 	clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
+ 	return ret;
+@@ -3441,6 +3448,7 @@ static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
+ 	}
+ 
+ 	hclgevf_cmd_uninit(hdev);
++	hclgevf_devlink_uninit(hdev);
+ 	hclgevf_pci_uninit(hdev);
+ 	hclgevf_uninit_mac_list(hdev);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index a8366fbf394a..3a8feb225b37 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -6,6 +6,7 @@
+ #include <linux/fs.h>
+ #include <linux/if_vlan.h>
+ #include <linux/types.h>
++#include <net/devlink.h>
+ #include "hclge_mbx.h"
+ #include "hclgevf_cmd.h"
+ #include "hnae3.h"
+-- 
+2.34.1
+
diff --git a/patches/0580-net-hns3-remove-always-exist-devlink-pointer-check.patch b/patches/0580-net-hns3-remove-always-exist-devlink-pointer-check.patch
new file mode 100644
index 0000000..0954b9a
--- /dev/null
+++ b/patches/0580-net-hns3-remove-always-exist-devlink-pointer-check.patch
@@ -0,0 +1,188 @@
+From f4f0868a16ec55852cbe66e42f6d32ce13b649d2 Mon Sep 17 00:00:00 2001
+From: Leon Romanovsky <leonro@nvidia.com>
+Date: Sat, 21 Aug 2021 17:00:42 +0800
+Subject: [PATCH 219/283] net: hns3: remove always exist devlink pointer check
+
+mainline inclusion
+from mainline-v5.15-rc1
+commit a1fcb106ae97cc34cc8101efafb89eaa837be009
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a1fcb106ae97cc34cc8101efafb89eaa837be009
+
+----------------------------------------------------------------------
+
+The devlink pointer always exists after hclge_devlink_init() succeed.
+Remove that check together with NULL setting after release and ensure
+that devlink_register is last command prior to call to devlink_reload_enable().
+
+Fixes: b741269b2759 ("net: hns3: add support for registering devlink for PF")
+Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+(fix conflicts: interface devlink_register adapt)
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c
+---
+ .../hisilicon/hns3/hns3pf/hclge_devlink.c     |  8 ++---
+ .../hisilicon/hns3/hns3vf/hclgevf_devlink.c   |  8 ++---
+ include/net/devlink.h                         |  5 +++
+ net/core/devlink.c                            | 36 +++++++++++++++++++
+ 4 files changed, 47 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c
+index 03b822b0a8e7..3a0be591112e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_devlink.c
+@@ -22,6 +22,7 @@ int hclge_devlink_init(struct hclge_dev *hdev)
+ 
+ 	priv = devlink_priv(devlink);
+ 	priv->hdev = hdev;
++	hdev->devlink = devlink;
+ 
+ 	ret = devlink_register(devlink, &pdev->dev);
+ 	if (ret) {
+@@ -30,7 +31,7 @@ int hclge_devlink_init(struct hclge_dev *hdev)
+ 		goto out_reg_fail;
+ 	}
+ 
+-	hdev->devlink = devlink;
++	devlink_reload_enable(devlink);
+ 
+ 	return 0;
+ 
+@@ -43,12 +44,9 @@ void hclge_devlink_uninit(struct hclge_dev *hdev)
+ {
+ 	struct devlink *devlink = hdev->devlink;
+ 
+-	if (!devlink)
+-		return;
++	devlink_reload_disable(devlink);
+ 
+ 	devlink_unregister(devlink);
+ 
+ 	devlink_free(devlink);
+-
+-	hdev->devlink = NULL;
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c
+index 55337a975981..a2495ebbea02 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_devlink.c
+@@ -22,6 +22,7 @@ int hclgevf_devlink_init(struct hclgevf_dev *hdev)
+ 
+ 	priv = devlink_priv(devlink);
+ 	priv->hdev = hdev;
++	hdev->devlink = devlink;
+ 
+ 	ret = devlink_register(devlink, &pdev->dev);
+ 	if (ret) {
+@@ -30,7 +31,7 @@ int hclgevf_devlink_init(struct hclgevf_dev *hdev)
+ 		goto out_reg_fail;
+ 	}
+ 
+-	hdev->devlink = devlink;
++	devlink_reload_enable(devlink);
+ 
+ 	return 0;
+ 
+@@ -43,12 +44,9 @@ void hclgevf_devlink_uninit(struct hclgevf_dev *hdev)
+ {
+ 	struct devlink *devlink = hdev->devlink;
+ 
+-	if (!devlink)
+-		return;
++	devlink_reload_disable(devlink);
+ 
+ 	devlink_unregister(devlink);
+ 
+ 	devlink_free(devlink);
+-
+-	hdev->devlink = NULL;
+ }
+diff --git a/include/net/devlink.h b/include/net/devlink.h
+index 99efc156a309..669c3cb59fcf 100644
+--- a/include/net/devlink.h
++++ b/include/net/devlink.h
+@@ -35,6 +35,9 @@ struct devlink {
+ 	struct device *dev;
+ 	possible_net_t _net;
+ 	struct mutex lock;
++	u8 reload_failed:1,
++	   reload_enabled:1,
++	   registered:1;
+ 	char priv[0] __aligned(NETDEV_ALIGN);
+ };
+ 
+@@ -477,6 +480,8 @@ struct ib_device;
+ struct devlink *devlink_alloc(const struct devlink_ops *ops, size_t priv_size);
+ int devlink_register(struct devlink *devlink, struct device *dev);
+ void devlink_unregister(struct devlink *devlink);
++void devlink_reload_enable(struct devlink *devlink);
++void devlink_reload_disable(struct devlink *devlink);
+ void devlink_free(struct devlink *devlink);
+ int devlink_port_register(struct devlink *devlink,
+ 			  struct devlink_port *devlink_port,
+diff --git a/net/core/devlink.c b/net/core/devlink.c
+index 6ad095264896..c9b36811529d 100644
+--- a/net/core/devlink.c
++++ b/net/core/devlink.c
+@@ -3900,12 +3900,48 @@ EXPORT_SYMBOL_GPL(devlink_register);
+ void devlink_unregister(struct devlink *devlink)
+ {
+ 	mutex_lock(&devlink_mutex);
++	WARN_ON(devlink->reload_enabled);
+ 	devlink_notify(devlink, DEVLINK_CMD_DEL);
+ 	list_del(&devlink->list);
+ 	mutex_unlock(&devlink_mutex);
+ }
+ EXPORT_SYMBOL_GPL(devlink_unregister);
+ 
++/**
++ *	devlink_reload_enable - Enable reload of devlink instance
++ *
++ *	@devlink: devlink
++ *
++ *	Should be called at end of device initialization
++ *	process when reload operation is supported.
++ */
++void devlink_reload_enable(struct devlink *devlink)
++{
++	mutex_lock(&devlink_mutex);
++	devlink->reload_enabled = true;
++	mutex_unlock(&devlink_mutex);
++}
++EXPORT_SYMBOL_GPL(devlink_reload_enable);
++
++/**
++ *	devlink_reload_disable - Disable reload of devlink instance
++ *
++ *	@devlink: devlink
++ *
++ *	Should be called at the beginning of device cleanup
++ *	process when reload operation is supported.
++ */
++void devlink_reload_disable(struct devlink *devlink)
++{
++	mutex_lock(&devlink_mutex);
++	/* Mutex is taken which ensures that no reload operation is in
++	 * progress while setting up forbidded flag.
++	 */
++	devlink->reload_enabled = false;
++	mutex_unlock(&devlink_mutex);
++}
++EXPORT_SYMBOL_GPL(devlink_reload_disable);
++
+ /**
+  *	devlink_free - Free devlink instance resources
+  *
+-- 
+2.34.1
+
diff --git a/patches/0581-net-hns3-Fix-for-the-compilation-problem-of-hclge_co.patch b/patches/0581-net-hns3-Fix-for-the-compilation-problem-of-hclge_co.patch
new file mode 100644
index 0000000..3d6325b
--- /dev/null
+++ b/patches/0581-net-hns3-Fix-for-the-compilation-problem-of-hclge_co.patch
@@ -0,0 +1,232 @@
+From 1d09e7b284cffc9a14c25e4cae565bbf872d6bb9 Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Tue, 11 Jul 2023 19:29:52 +0800
+Subject: [PATCH 220/283] net: hns3: Fix for the compilation problem of
+ hclge_comm_cmd
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+--------------------------------
+
+Fix because of hclge_ Cmd. c and hclge_ Transfer of cmd. h
+partial structure and functions to hclge_ Comm_ Cmd. c
+and hclge_ Comm_ Compilation alarm issues caused by cmd. h.
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/Makefile  |  1 +
+ .../hns3/hns3_common/hclge_comm_cmd.c         | 64 ++++++++++---------
+ .../hns3/hns3_common/hclge_comm_cmd.h         | 11 +++-
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 10 ---
+ 4 files changed, 43 insertions(+), 43 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile
+index 45ff4d501760..7ff21cdf43b9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/Makefile
+@@ -48,6 +48,7 @@ HCLGE_OBJ_IT_MAIN	=	hns3_extension/hns3pf/hclge_main_it.o \
+ obj-$(CONFIG_HNS3_HCLGE) += hclge.o
+ hclge-objs := $(HCLGE_OBJ) $(HCLGE_OBJ_IT_MAIN)
+ hclge-objs += hns3pf/hclge_ext.o
++hclge-objs += hns3_common/hclge_comm_cmd.o
+ 
+ hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o
+ #### compile hclgevf.ko
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index a27736cde913..d2000301b942 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -2,9 +2,11 @@
+ // Copyright (c) 2021-2021 Hisilicon Limited.
+ 
+ #include "hnae3.h"
++#include "hclge_cmd.h"
+ #include "hclge_comm_cmd.h"
+ 
+-static bool hclge_is_elem_in_array(const u16 *spec_opcode, u32 size, u16 opcode)
++static void hclge_comm_cmd_config_regs(struct hclge_comm_hw *hw,
++				       struct hclge_comm_cmq_ring *ring)
+ {
+ 	dma_addr_t dma = ring->desc_dma_addr;
+ 	u32 reg_val;
+@@ -226,40 +228,40 @@ int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
+ 					 HNAE3_PCI_REVISION_BIT_SIZE;
+ 	ae_dev->dev_version |= ae_dev->pdev->revision;
+ 
+-	for (i = 0; i < size; i++) {
+-		if (spec_opcode[i] == opcode)
+-			return true;
++	if (ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
++		hclge_comm_set_default_capability(ae_dev, is_pf);
++		return 0;
+ 	}
+ 
++	hclge_comm_parse_capability(ae_dev, is_pf, resp);
++
+ 	return false;
+ }
+ 
+-static const u16 pf_spec_opcode[] = { HCLGE_COMM_OPC_STATS_64_BIT,
+-				      HCLGE_COMM_OPC_STATS_32_BIT,
+-				      HCLGE_COMM_OPC_STATS_MAC,
+-				      HCLGE_COMM_OPC_STATS_MAC_ALL,
+-				      HCLGE_COMM_OPC_QUERY_32_BIT_REG,
+-				      HCLGE_COMM_OPC_QUERY_64_BIT_REG,
+-				      HCLGE_COMM_QUERY_CLEAR_MPF_RAS_INT,
+-				      HCLGE_COMM_QUERY_CLEAR_PF_RAS_INT,
+-				      HCLGE_COMM_QUERY_CLEAR_ALL_MPF_MSIX_INT,
+-				      HCLGE_COMM_QUERY_CLEAR_ALL_PF_MSIX_INT,
+-				      HCLGE_COMM_QUERY_ALL_ERR_INFO };
+-
+-static const u16 vf_spec_opcode[] = { HCLGE_COMM_OPC_STATS_64_BIT,
+-				      HCLGE_COMM_OPC_STATS_32_BIT,
+-				      HCLGE_COMM_OPC_STATS_MAC };
+-
+-static bool hclge_comm_is_special_opcode(u16 opcode, bool is_pf)
++static const u16 spec_opcode[] = { HCLGE_OPC_STATS_64_BIT,
++				   HCLGE_OPC_STATS_32_BIT,
++				   HCLGE_OPC_STATS_MAC,
++				   HCLGE_OPC_STATS_MAC_ALL,
++				   HCLGE_OPC_QUERY_32_BIT_REG,
++				   HCLGE_OPC_QUERY_64_BIT_REG,
++				   HCLGE_QUERY_CLEAR_MPF_RAS_INT,
++				   HCLGE_QUERY_CLEAR_PF_RAS_INT,
++				   HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
++				   HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT,
++				   HCLGE_QUERY_ALL_ERR_INFO };
++
++static bool hclge_comm_is_special_opcode(u16 opcode)
+ {
+ 	/* these commands have several descriptors,
+ 	 * and use the first one to save opcode and return value
+ 	 */
+-	const u16 *spec_opcode = is_pf ? pf_spec_opcode : vf_spec_opcode;
+-	u32 size = is_pf ? ARRAY_SIZE(pf_spec_opcode) :
+-				ARRAY_SIZE(vf_spec_opcode);
++	u32 i;
+ 
+-	return hclge_is_elem_in_array(spec_opcode, size, opcode);
++	for (i = 0; i < ARRAY_SIZE(spec_opcode); i++)
++		if (spec_opcode[i] == opcode)
++			return true;
++
++	return false;
+ }
+ 
+ static int hclge_comm_ring_space(struct hclge_comm_cmq_ring *ring)
+@@ -389,7 +391,7 @@ static int hclge_comm_cmd_convert_err_code(u16 desc_ret)
+ 
+ static int hclge_comm_cmd_check_retval(struct hclge_comm_hw *hw,
+ 				       struct hclge_desc *desc, int num,
+-				       int ntc, bool is_pf)
++				       int ntc)
+ {
+ 	u16 opcode, desc_ret;
+ 	int handle;
+@@ -401,7 +403,7 @@ static int hclge_comm_cmd_check_retval(struct hclge_comm_hw *hw,
+ 		if (ntc >= hw->cmq.csq.desc_num)
+ 			ntc = 0;
+ 	}
+-	if (likely(!hclge_comm_is_special_opcode(opcode, is_pf)))
++	if (likely(!hclge_comm_is_special_opcode(opcode)))
+ 		desc_ret = le16_to_cpu(desc[num - 1].retval);
+ 	else
+ 		desc_ret = le16_to_cpu(desc[0].retval);
+@@ -413,7 +415,7 @@ static int hclge_comm_cmd_check_retval(struct hclge_comm_hw *hw,
+ 
+ static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw,
+ 				       struct hclge_desc *desc,
+-				       int num, int ntc, bool is_pf)
++				       int num, int ntc)
+ {
+ 	bool is_completed = false;
+ 	int handle, ret;
+@@ -428,7 +430,7 @@ static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw,
+ 	if (!is_completed)
+ 		ret = -EBADE;
+ 	else
+-		ret = hclge_comm_cmd_check_retval(hw, desc, num, ntc, is_pf);
++		ret = hclge_comm_cmd_check_retval(hw, desc, num, ntc);
+ 
+ 	/* Clean the command send queue */
+ 	handle = hclge_comm_cmd_csq_clean(hw);
+@@ -451,7 +453,7 @@ static int hclge_comm_cmd_check_result(struct hclge_comm_hw *hw,
+  * sends the queue, cleans the queue, etc
+  **/
+ int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
+-			int num, bool is_pf)
++			int num)
+ {
+ 	struct hclge_comm_cmq_ring *csq = &hw->cmq.csq;
+ 	int ret;
+@@ -486,7 +488,7 @@ int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
+ 	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CSQ_TAIL_REG,
+ 			     hw->cmq.csq.next_to_use);
+ 
+-	ret = hclge_comm_cmd_check_result(hw, desc, num, ntc, is_pf);
++	ret = hclge_comm_cmd_check_result(hw, desc, num, ntc);
+ 
+ 	spin_unlock_bh(&hw->cmq.csq.lock);
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 81904010b96b..de9da88134e5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -5,7 +5,6 @@
+ #define __HCLGE_COMM_CMD_H
+ #include <linux/types.h>
+ 
+-#include "hclge_cmd.h"
+ #include "hnae3.h"
+ 
+ #define HCLGE_COMM_CMD_FLAG_IN			BIT(0)
+@@ -135,6 +134,14 @@ struct hclge_comm_errcode {
+ 	int common_errno;
+ };
+ 
++#define HCLGE_COMM_QUERY_CAP_LENGTH		3
++struct hclge_comm_query_version_cmd {
++	__le32 firmware;
++	__le32 hardware;
++	__le32 api_caps;
++	__le32 caps[HCLGE_COMM_QUERY_CAP_LENGTH]; /* capabilities of device */
++};
++
+ #define HCLGE_DESC_DATA_LEN		6
+ struct hclge_desc {
+ 	__le16 opcode;
+@@ -203,7 +210,7 @@ int hclge_comm_cmd_query_version_and_capability(struct hnae3_ae_dev *ae_dev,
+ 						u32 *fw_version, bool is_pf);
+ int hclge_comm_alloc_cmd_queue(struct hclge_comm_hw *hw, int ring_type);
+ int hclge_comm_cmd_send(struct hclge_comm_hw *hw, struct hclge_desc *desc,
+-			int num, bool is_pf);
++			int num);
+ int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,
+ 				      struct hclge_comm_hw *hw, bool en);
+ void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index c1013b338650..4f93ad1ac62e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -18,16 +18,6 @@ static nic_event_fn_t nic_event_call;
+  */
+ static DEFINE_MUTEX(hclge_nic_event_lock);
+ 
+-void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
+-{
+-	desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR |
+-				 HCLGE_COMM_CMD_FLAG_IN);
+-	if (is_read)
+-		desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR);
+-	else
+-		desc->flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_WR);
+-}
+-
+ static int hclge_clean_stats64(struct hclge_dev *hdev, void *data,
+ 			       size_t length)
+ {
+-- 
+2.34.1
+
diff --git a/patches/0582-The-kabi-issue-is-resolved-when-the-rx_buf_len-exten.patch b/patches/0582-The-kabi-issue-is-resolved-when-the-rx_buf_len-exten.patch
new file mode 100644
index 0000000..c6d888c
--- /dev/null
+++ b/patches/0582-The-kabi-issue-is-resolved-when-the-rx_buf_len-exten.patch
@@ -0,0 +1,39 @@
+From db69f51a48e932632092cd6098c8e07db2d3234c Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Wed, 12 Jul 2023 20:01:04 +0800
+Subject: [PATCH 221/283] The kabi issue is resolved when the rx_buf_len
+ extension ring is used to set parameters or obtain APIs
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+--------------------------------
+
+Fix it because ethtool_ Get in ops structure_ Ringparam, set_ Kabi problem caused by
+changes in ringparam member parameters.
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ include/linux/ethtool.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 812026982640..c51da6a2c1de 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -417,9 +417,9 @@ struct ethtool_ops {
+ 			      struct ethtool_eeprom *, u8 *);
+ 	int	(*get_coalesce)(struct net_device *, struct ethtool_coalesce *);
+ 	int	(*set_coalesce)(struct net_device *, struct ethtool_coalesce *);
+-	void	(*get_ringparam)(struct net_device *,
++	void    (*get_ringparam)(struct net_device *,
+ 				 struct ethtool_ringparam *);
+-	int	(*set_ringparam)(struct net_device *,
++	int     (*set_ringparam)(struct net_device *,
+ 				 struct ethtool_ringparam *);
+ 	void	(*get_pauseparam)(struct net_device *,
+ 				  struct ethtool_pauseparam*);
+-- 
+2.34.1
+
diff --git a/patches/0583-net-hns3-Resolved-the-kabi-change-issue-caused-by-ne.patch b/patches/0583-net-hns3-Resolved-the-kabi-change-issue-caused-by-ne.patch
new file mode 100644
index 0000000..d69a641
--- /dev/null
+++ b/patches/0583-net-hns3-Resolved-the-kabi-change-issue-caused-by-ne.patch
@@ -0,0 +1,39 @@
+From e4e46ba6ae2995d6d05a50735b94ebe3590c02d3 Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Thu, 13 Jul 2023 11:35:28 +0800
+Subject: [PATCH 222/283] net: hns3: Resolved the kabi change issue caused by
+ new members in the devlink structure
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+--------------------------------
+
+Fix the addition of reload in the devlink structure_ Failed, reload_ Kabi
+issues caused by enabled and registered members.
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ include/net/devlink.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/include/net/devlink.h b/include/net/devlink.h
+index 669c3cb59fcf..a943659a705e 100644
+--- a/include/net/devlink.h
++++ b/include/net/devlink.h
+@@ -35,9 +35,11 @@ struct devlink {
+ 	struct device *dev;
+ 	possible_net_t _net;
+ 	struct mutex lock;
++#ifndef __GENKSYMS__
+ 	u8 reload_failed:1,
+ 	   reload_enabled:1,
+ 	   registered:1;
++#endif
+ 	char priv[0] __aligned(NETDEV_ALIGN);
+ };
+ 
+-- 
+2.34.1
+
diff --git a/patches/0584-ethtool-Extend-link-modes-settings-uAPI-with-lanes.patch b/patches/0584-ethtool-Extend-link-modes-settings-uAPI-with-lanes.patch
new file mode 100644
index 0000000..207bc32
--- /dev/null
+++ b/patches/0584-ethtool-Extend-link-modes-settings-uAPI-with-lanes.patch
@@ -0,0 +1,787 @@
+From 2de748113445fa1321d5c04ea5a7cd8daf506b3a Mon Sep 17 00:00:00 2001
+From: Danielle Ratson <danieller@nvidia.com>
+Date: Tue, 2 Feb 2021 20:06:06 +0200
+Subject: [PATCH 223/283] ethtool: Extend link modes settings uAPI with lanes
+
+mainline inclusion
+from mainline-v5.12-rc1-dontuse
+commit 012ce4dd3102a0f4d80167de343e9d44b257c1b8
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=012ce4dd3102a0f4d80167de343e9d44b257c1b8
+
+--------------------------------
+
+Currently, when auto negotiation is on, the user can advertise all the
+linkmodes which correspond to a specific speed, but does not have a
+similar selector for the number of lanes. This is significant when a
+specific speed can be achieved using different number of lanes.  For
+example, 2x50 or 4x25.
+
+Add 'ETHTOOL_A_LINKMODES_LANES' attribute and expand 'struct
+ethtool_link_settings' with lanes field in order to implement a new
+lanes-selector that will enable the user to advertise a specific number
+of lanes as well.
+
+When auto negotiation is off, lanes parameter can be forced only if the
+driver supports it. Add a capability bit in 'struct ethtool_ops' that
+allows ethtool know if the driver can handle the lanes parameter when
+auto negotiation is off, so if it does not, an error message will be
+returned when trying to set lanes.
+
+Example:
+
+$ ethtool -s swp1 lanes 4
+$ ethtool swp1
+  Settings for swp1:
+	Supported ports: [ FIBRE ]
+        Supported link modes:   1000baseKX/Full
+                                10000baseKR/Full
+                                40000baseCR4/Full
+				40000baseSR4/Full
+				40000baseLR4/Full
+                                25000baseCR/Full
+                                25000baseSR/Full
+				50000baseCR2/Full
+                                100000baseSR4/Full
+				100000baseCR4/Full
+        Supported pause frame use: Symmetric Receive-only
+        Supports auto-negotiation: Yes
+        Supported FEC modes: Not reported
+        Advertised link modes:  40000baseCR4/Full
+				40000baseSR4/Full
+				40000baseLR4/Full
+                                100000baseSR4/Full
+				100000baseCR4/Full
+        Advertised pause frame use: No
+        Advertised auto-negotiation: Yes
+        Advertised FEC modes: Not reported
+        Speed: Unknown!
+        Duplex: Unknown! (255)
+        Auto-negotiation: on
+        Port: Direct Attach Copper
+        PHYAD: 0
+        Transceiver: internal
+        Link detected: no
+
+Signed-off-by: Danielle Ratson <danieller@nvidia.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	Documentation/networking/ethtool-netlink.rst
+	include/linux/ethtool.h
+	include/uapi/linux/ethtool_netlink.h
+	net/ethtool/linkmodes.c
+	net/ethtool/netlink.h
+---
+ Documentation/networking/ethtool-netlink.rst |  26 +
+ include/linux/ethtool.h                      |   7 +-
+ include/net/netlink.h                        |   6 +
+ include/uapi/linux/ethtool.h                 |  17 +
+ include/uapi/linux/ethtool_netlink.h         |   3 +
+ net/ethtool/Makefile                         |   2 +-
+ net/ethtool/linkmodes.c                      | 512 +++++++++++++++++++
+ net/ethtool/netlink.h                        |   2 +
+ 8 files changed, 573 insertions(+), 2 deletions(-)
+ create mode 100644 net/ethtool/linkmodes.c
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+index 1cf07b28382d..18109dfc26e7 100644
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -218,6 +218,32 @@ an ``ACT_REPLY`` message. Performing an action also triggers a notification
+ 
+ Later sections describe the format and semantics of these messages.
+ 
++LINKMODES_SET
++=============
++
++Request contents:
++
++  ==========================================  ======  ==========================
++  ``ETHTOOL_A_LINKMODES_HEADER``              nested  request header
++  ``ETHTOOL_A_LINKMODES_AUTONEG``             u8      autonegotiation status
++  ``ETHTOOL_A_LINKMODES_OURS``                bitset  advertised link modes
++  ``ETHTOOL_A_LINKMODES_PEER``                bitset  partner link modes
++  ``ETHTOOL_A_LINKMODES_SPEED``               u32     link speed (Mb/s)
++  ``ETHTOOL_A_LINKMODES_DUPLEX``              u8      duplex mode
++  ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG``    u8      Master/slave port mode
++  ``ETHTOOL_A_LINKMODES_LANES``               u32     lanes
++  ==========================================  ======  ==========================
++
++``ETHTOOL_A_LINKMODES_OURS`` bit set allows setting advertised link modes. If
++autonegotiation is on (either set now or kept from before), advertised modes
++are not changed (no ``ETHTOOL_A_LINKMODES_OURS`` attribute) and at least one
++of speed, duplex and lanes is specified, kernel adjusts advertised modes to all
++supported modes matching speed, duplex, lanes or all (whatever is specified).
++This autoselection is done on ethtool side with ioctl interface, netlink
++interface is supposed to allow requesting changes without knowing what exactly
++kernel supports.
++
++
+ RINGS_GET
+ =========
+ 
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index c51da6a2c1de..1b0afcdaf34e 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -130,9 +130,10 @@ static inline u32 ethtool_rxfh_indir_default(u32 index, u32 n_rx_rings)
+ 	return index % n_rx_rings;
+ }
+ 
+-/* number of link mode bits/ulongs handled internally by kernel */
++#ifdef __GENKSYMS__
+ #define __ETHTOOL_LINK_MODE_MASK_NBITS			\
+ 	(__ETHTOOL_LINK_MODE_LAST + 1)
++#endif
+ 
+ /* declare a link mode bitmap */
+ #define __ETHTOOL_DECLARE_LINK_MODE_MASK(name)		\
+@@ -148,6 +149,7 @@ struct ethtool_link_ksettings {
+ 		__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
+ 		__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising);
+ 	} link_modes;
++	u32	lanes;
+ };
+ 
+ /**
+@@ -249,6 +251,8 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+ 	(ETHTOOL_COALESCE_USE_ADAPTIVE_RX | ETHTOOL_COALESCE_USE_ADAPTIVE_TX)
+ /**
+  * struct ethtool_ops - optional netdev operations
++ * @cap_link_lanes_supported: indicates if the driver supports lanes
++ *	parameter.
+  * @supported_coalesce_params: supported types of interrupt coalescing.
+  * @supported_ring_params: supported ring params.
+  * @get_drvinfo: Report driver/device information.  Should only set the
+@@ -392,6 +396,7 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+  */
+ struct ethtool_ops {
+ #ifndef __GENKSYMS__
++	u32     cap_link_lanes_supported:1;
+ 	u32     supported_coalesce_params;
+ 	u32     supported_ring_params;
+ #endif
+diff --git a/include/net/netlink.h b/include/net/netlink.h
+index f30598d66eec..849a0ef9f695 100644
+--- a/include/net/netlink.h
++++ b/include/net/netlink.h
+@@ -272,6 +272,12 @@ struct nla_policy {
+ 		      tp == NLA_MSECS ||		\
+ 		      tp == NLA_BINARY) + tp)
+ 
++#define NLA_POLICY_RANGE(tp, _min, _max) {		 \
++	.type = NLA_ENSURE_INT_OR_BINARY_TYPE(tp),		\
++	.validation_type = NLA_VALIDATE_RANGE,		\
++	.min = _min,				\
++	.max = _max					\
++}
+ 
+ #define NLA_POLICY_MIN(tp, _min) {			\
+ 	.type = NLA_ENSURE_INT_OR_BINARY_TYPE(tp),	\
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index da4258a5f8c2..4f19dca5fcfa 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -1629,9 +1629,12 @@ enum ethtool_link_mode_bit_indices {
+ 	 * macro for bits > 31. The only way to use indices > 31 is to
+ 	 * use the new ETHTOOL_GLINKSETTINGS/ETHTOOL_SLINKSETTINGS API.
+ 	 */
++#ifndef __GENKSYMS__
+ 	__ETHTOOL_LINK_MODE_MASK_NBITS,
++#else
+ 	__ETHTOOL_LINK_MODE_LAST
+ 	  = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
++#endif
+ };
+ 
+ #define __ETHTOOL_LINK_MODE_LEGACY_MASK(base_name)	\
+@@ -1739,6 +1742,8 @@ enum ethtool_link_mode_bit_indices {
+ #define SPEED_50000		50000
+ #define SPEED_56000		56000
+ #define SPEED_100000		100000
++#define SPEED_200000		200000
++#define SPEED_400000		400000
+ 
+ #define SPEED_UNKNOWN		-1
+ 
+@@ -1764,6 +1769,18 @@ static inline int ethtool_validate_duplex(__u8 duplex)
+ 	return 0;
+ }
+ 
++#define MASTER_SLAVE_CFG_UNSUPPORTED			0
++#define MASTER_SLAVE_CFG_UNKNOWN 				1
++#define MASTER_SLAVE_CFG_MASTER_PREFERRED		2
++#define MASTER_SLAVE_CFG_SLAVE_PREFERRED		3
++#define MASTER_SLAVE_CFG_MASTER_FORCE			4
++#define MASTER_SLAVE_CFG_SLAVE_FORCE			5
++#define MASTER_SLAVE_STATE_UNSUPPORTED			0
++#define MASTER_SLAVE_STATE_UNKNOWN				1
++#define MASTER_SLAVE_STATE_MASTER				2
++#define MASTER_SLAVE_STATE_SLAVE				3
++#define MASTER_SLAVE_STATE_ERR					4
++
+ /* Which connector port. */
+ #define PORT_TP			0x00
+ #define PORT_AUI		0x01
+diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
+index 4eed3507a005..0c03f091574f 100644
+--- a/include/uapi/linux/ethtool_netlink.h
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -197,6 +197,9 @@ enum {
+ 	ETHTOOL_A_LINKMODES_PEER,		/* bitset */
+ 	ETHTOOL_A_LINKMODES_SPEED,		/* u32 */
+ 	ETHTOOL_A_LINKMODES_DUPLEX,		/* u8 */
++	ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG,	/* u8 */
++	ETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE,	/* u8 */
++	ETHTOOL_A_LINKMODES_LANES,		/* u32 */
+ 
+ 	/* add new constants above here */
+ 	__ETHTOOL_A_LINKMODES_CNT,
+diff --git a/net/ethtool/Makefile b/net/ethtool/Makefile
+index 6f1cdf8a57b3..685d55945c99 100644
+--- a/net/ethtool/Makefile
++++ b/net/ethtool/Makefile
+@@ -4,4 +4,4 @@ obj-y				+= ioctl.o common.o
+ 
+ obj-$(CONFIG_ETHTOOL_NETLINK)	+= ethtool_nl.o
+ 
+-ethtool_nl-y	:= netlink.o rings.o
++ethtool_nl-y	:= netlink.o rings.o linkmodes.o
+diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
+new file mode 100644
+index 000000000000..b632e14d6c27
+--- /dev/null
++++ b/net/ethtool/linkmodes.c
+@@ -0,0 +1,512 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include "netlink.h"
++#include "common.h"
++#include "bitset.h"
++
++struct linkmodes_req_info {
++	struct ethnl_req_info		base;
++};
++
++struct linkmodes_reply_data {
++	struct ethnl_reply_data		base;
++	struct ethtool_link_ksettings	ksettings;
++	struct ethtool_link_settings	*lsettings;
++	bool				peer_empty;
++};
++
++#define LINKMODES_REPDATA(__reply_base) \
++	container_of(__reply_base, struct linkmodes_reply_data, base)
++
++const struct nla_policy ethnl_linkmodes_get_policy[] = {
++	[ETHTOOL_A_LINKMODES_HEADER]		=
++		NLA_POLICY_NESTED(ethnl_header_policy),
++};
++
++static int linkmodes_prepare_data(const struct ethnl_req_info *req_base,
++				  struct ethnl_reply_data *reply_base,
++				  struct genl_info *info)
++{
++	struct linkmodes_reply_data *data = LINKMODES_REPDATA(reply_base);
++	struct net_device *dev = reply_base->dev;
++	int ret;
++
++	data->lsettings = &data->ksettings.base;
++
++	ret = ethnl_ops_begin(dev);
++	if (ret < 0)
++		return ret;
++
++	ret = __ethtool_get_link_ksettings(dev, &data->ksettings);
++	if (ret < 0 && info) {
++		GENL_SET_ERR_MSG(info, "failed to retrieve link settings");
++		goto out;
++	}
++
++	data->peer_empty =
++		bitmap_empty(data->ksettings.link_modes.lp_advertising,
++			     __ETHTOOL_LINK_MODE_MASK_NBITS);
++
++out:
++	ethnl_ops_complete(dev);
++	return ret;
++}
++
++static int linkmodes_reply_size(const struct ethnl_req_info *req_base,
++				const struct ethnl_reply_data *reply_base)
++{
++	const struct linkmodes_reply_data *data = LINKMODES_REPDATA(reply_base);
++	const struct ethtool_link_ksettings *ksettings = &data->ksettings;
++	const struct ethtool_link_settings *lsettings = &ksettings->base;
++	bool compact = req_base->flags & ETHTOOL_FLAG_COMPACT_BITSETS;
++	int len, ret;
++
++	len = nla_total_size(sizeof(u8)) /* LINKMODES_AUTONEG */
++		+ nla_total_size(sizeof(u32)) /* LINKMODES_SPEED */
++		+ nla_total_size(sizeof(u8)) /* LINKMODES_DUPLEX */
++		+ 0;
++	ret = ethnl_bitset_size(ksettings->link_modes.advertising,
++				ksettings->link_modes.supported,
++				__ETHTOOL_LINK_MODE_MASK_NBITS,
++				link_mode_names, compact);
++	if (ret < 0)
++		return ret;
++	len += ret;
++	if (!data->peer_empty) {
++		ret = ethnl_bitset_size(ksettings->link_modes.lp_advertising,
++					NULL, __ETHTOOL_LINK_MODE_MASK_NBITS,
++					link_mode_names, compact);
++		if (ret < 0)
++			return ret;
++		len += ret;
++	}
++
++	if (lsettings->master_slave_cfg != MASTER_SLAVE_CFG_UNSUPPORTED)
++		len += nla_total_size(sizeof(u8));
++
++	if (lsettings->master_slave_state != MASTER_SLAVE_STATE_UNSUPPORTED)
++		len += nla_total_size(sizeof(u8));
++
++	return len;
++}
++
++static int linkmodes_fill_reply(struct sk_buff *skb,
++				const struct ethnl_req_info *req_base,
++				const struct ethnl_reply_data *reply_base)
++{
++	const struct linkmodes_reply_data *data = LINKMODES_REPDATA(reply_base);
++	const struct ethtool_link_ksettings *ksettings = &data->ksettings;
++	const struct ethtool_link_settings *lsettings = &ksettings->base;
++	bool compact = req_base->flags & ETHTOOL_FLAG_COMPACT_BITSETS;
++	int ret;
++
++	if (nla_put_u8(skb, ETHTOOL_A_LINKMODES_AUTONEG, lsettings->autoneg))
++		return -EMSGSIZE;
++
++	ret = ethnl_put_bitset(skb, ETHTOOL_A_LINKMODES_OURS,
++			       ksettings->link_modes.advertising,
++			       ksettings->link_modes.supported,
++			       __ETHTOOL_LINK_MODE_MASK_NBITS, link_mode_names,
++			       compact);
++	if (ret < 0)
++		return -EMSGSIZE;
++	if (!data->peer_empty) {
++		ret = ethnl_put_bitset(skb, ETHTOOL_A_LINKMODES_PEER,
++				       ksettings->link_modes.lp_advertising,
++				       NULL, __ETHTOOL_LINK_MODE_MASK_NBITS,
++				       link_mode_names, compact);
++		if (ret < 0)
++			return -EMSGSIZE;
++	}
++
++	if (nla_put_u32(skb, ETHTOOL_A_LINKMODES_SPEED, lsettings->speed) ||
++	    nla_put_u8(skb, ETHTOOL_A_LINKMODES_DUPLEX, lsettings->duplex))
++		return -EMSGSIZE;
++
++	if (lsettings->master_slave_cfg != MASTER_SLAVE_CFG_UNSUPPORTED &&
++	    nla_put_u8(skb, ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG,
++		       lsettings->master_slave_cfg))
++		return -EMSGSIZE;
++
++	if (lsettings->master_slave_state != MASTER_SLAVE_STATE_UNSUPPORTED &&
++	    nla_put_u8(skb, ETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE,
++		       lsettings->master_slave_state))
++		return -EMSGSIZE;
++
++	return 0;
++}
++
++const struct ethnl_request_ops ethnl_linkmodes_request_ops = {
++	.request_cmd		= ETHTOOL_MSG_LINKMODES_GET,
++	.reply_cmd		= ETHTOOL_MSG_LINKMODES_GET_REPLY,
++	.hdr_attr		= ETHTOOL_A_LINKMODES_HEADER,
++	.req_info_size		= sizeof(struct linkmodes_req_info),
++	.reply_data_size	= sizeof(struct linkmodes_reply_data),
++
++	.prepare_data		= linkmodes_prepare_data,
++	.reply_size		= linkmodes_reply_size,
++	.fill_reply		= linkmodes_fill_reply,
++};
++
++/* LINKMODES_SET */
++
++struct link_mode_info {
++	int				speed;
++	u8				lanes;
++	u8				duplex;
++};
++
++#define __LINK_MODE_LANES_CR		1
++#define __LINK_MODE_LANES_CR2		2
++#define __LINK_MODE_LANES_CR4		4
++#define __LINK_MODE_LANES_CR8		8
++#define __LINK_MODE_LANES_DR		1
++#define __LINK_MODE_LANES_DR2		2
++#define __LINK_MODE_LANES_DR4		4
++#define __LINK_MODE_LANES_DR8		8
++#define __LINK_MODE_LANES_KR		1
++#define __LINK_MODE_LANES_KR2		2
++#define __LINK_MODE_LANES_KR4		4
++#define __LINK_MODE_LANES_KR8		8
++#define __LINK_MODE_LANES_SR		1
++#define __LINK_MODE_LANES_SR2		2
++#define __LINK_MODE_LANES_SR4		4
++#define __LINK_MODE_LANES_SR8		8
++#define __LINK_MODE_LANES_ER		1
++#define __LINK_MODE_LANES_KX		1
++#define __LINK_MODE_LANES_KX4		4
++#define __LINK_MODE_LANES_LR		1
++#define __LINK_MODE_LANES_LR4		4
++#define __LINK_MODE_LANES_LR4_ER4	4
++#define __LINK_MODE_LANES_LR_ER_FR	1
++#define __LINK_MODE_LANES_LR2_ER2_FR2	2
++#define __LINK_MODE_LANES_LR4_ER4_FR4	4
++#define __LINK_MODE_LANES_LR8_ER8_FR8	8
++#define __LINK_MODE_LANES_LRM		1
++#define __LINK_MODE_LANES_MLD2		2
++#define __LINK_MODE_LANES_T		1
++#define __LINK_MODE_LANES_T1		1
++#define __LINK_MODE_LANES_X		1
++#define __LINK_MODE_LANES_FX		1
++
++#define __DEFINE_LINK_MODE_PARAMS(_speed, _type, _duplex)	\
++	[ETHTOOL_LINK_MODE(_speed, _type, _duplex)] = {		\
++		.speed  = SPEED_ ## _speed, \
++		.lanes  = __LINK_MODE_LANES_ ## _type, \
++		.duplex	= __DUPLEX_ ## _duplex \
++	}
++#define __DUPLEX_Half DUPLEX_HALF
++#define __DUPLEX_Full DUPLEX_FULL
++#define __DEFINE_SPECIAL_MODE_PARAMS(_mode) \
++	[ETHTOOL_LINK_MODE_ ## _mode ## _BIT] = { \
++		.speed	= SPEED_UNKNOWN, \
++		.lanes	= 0, \
++		.duplex	= DUPLEX_UNKNOWN, \
++	}
++
++static const struct link_mode_info link_mode_params[] = {
++	__DEFINE_LINK_MODE_PARAMS(10, T, Half),
++	__DEFINE_LINK_MODE_PARAMS(10, T, Full),
++	__DEFINE_LINK_MODE_PARAMS(100, T, Half),
++	__DEFINE_LINK_MODE_PARAMS(100, T, Full),
++	__DEFINE_LINK_MODE_PARAMS(1000, T, Half),
++	__DEFINE_LINK_MODE_PARAMS(1000, T, Full),
++	__DEFINE_SPECIAL_MODE_PARAMS(Autoneg),
++	__DEFINE_SPECIAL_MODE_PARAMS(TP),
++	__DEFINE_SPECIAL_MODE_PARAMS(AUI),
++	__DEFINE_SPECIAL_MODE_PARAMS(MII),
++	__DEFINE_SPECIAL_MODE_PARAMS(FIBRE),
++	__DEFINE_SPECIAL_MODE_PARAMS(BNC),
++	__DEFINE_LINK_MODE_PARAMS(10000, T, Full),
++	__DEFINE_SPECIAL_MODE_PARAMS(Pause),
++	__DEFINE_SPECIAL_MODE_PARAMS(Asym_Pause),
++	__DEFINE_LINK_MODE_PARAMS(2500, X, Full),
++	__DEFINE_SPECIAL_MODE_PARAMS(Backplane),
++	__DEFINE_LINK_MODE_PARAMS(1000, KX, Full),
++	__DEFINE_LINK_MODE_PARAMS(10000, KX4, Full),
++	__DEFINE_LINK_MODE_PARAMS(10000, KR, Full),
++	[ETHTOOL_LINK_MODE_10000baseR_FEC_BIT] = {
++		.speed	= SPEED_10000,
++		.duplex = DUPLEX_FULL,
++	},
++	__DEFINE_LINK_MODE_PARAMS(20000, MLD2, Full),
++	__DEFINE_LINK_MODE_PARAMS(20000, KR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(40000, KR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(40000, CR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(40000, SR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(40000, LR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(56000, KR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(56000, CR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(56000, SR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(56000, LR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(25000, CR, Full),
++	__DEFINE_LINK_MODE_PARAMS(25000, KR, Full),
++	__DEFINE_LINK_MODE_PARAMS(25000, SR, Full),
++	__DEFINE_LINK_MODE_PARAMS(50000, CR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(50000, KR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, KR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, SR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, CR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, LR4_ER4, Full),
++	__DEFINE_LINK_MODE_PARAMS(50000, SR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(1000, X, Full),
++	__DEFINE_LINK_MODE_PARAMS(10000, CR, Full),
++	__DEFINE_LINK_MODE_PARAMS(10000, SR, Full),
++	__DEFINE_LINK_MODE_PARAMS(10000, LR, Full),
++	__DEFINE_LINK_MODE_PARAMS(10000, LRM, Full),
++	__DEFINE_LINK_MODE_PARAMS(10000, ER, Full),
++	__DEFINE_LINK_MODE_PARAMS(2500, T, Full),
++	__DEFINE_LINK_MODE_PARAMS(5000, T, Full),
++	__DEFINE_SPECIAL_MODE_PARAMS(FEC_NONE),
++	__DEFINE_SPECIAL_MODE_PARAMS(FEC_RS),
++	__DEFINE_SPECIAL_MODE_PARAMS(FEC_BASER),
++	__DEFINE_LINK_MODE_PARAMS(50000, KR, Full),
++	__DEFINE_LINK_MODE_PARAMS(50000, SR, Full),
++	__DEFINE_LINK_MODE_PARAMS(50000, CR, Full),
++	__DEFINE_LINK_MODE_PARAMS(50000, LR_ER_FR, Full),
++	__DEFINE_LINK_MODE_PARAMS(50000, DR, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, KR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, SR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, CR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, LR2_ER2_FR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, DR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(200000, KR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(200000, SR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(200000, LR4_ER4_FR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(200000, DR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(200000, CR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(100, T1, Full),
++	__DEFINE_LINK_MODE_PARAMS(1000, T1, Full),
++	__DEFINE_LINK_MODE_PARAMS(400000, KR8, Full),
++	__DEFINE_LINK_MODE_PARAMS(400000, SR8, Full),
++	__DEFINE_LINK_MODE_PARAMS(400000, LR8_ER8_FR8, Full),
++	__DEFINE_LINK_MODE_PARAMS(400000, DR8, Full),
++	__DEFINE_LINK_MODE_PARAMS(400000, CR8, Full),
++	__DEFINE_SPECIAL_MODE_PARAMS(FEC_LLRS),
++	__DEFINE_LINK_MODE_PARAMS(100000, KR, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, SR, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, LR_ER_FR, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, DR, Full),
++	__DEFINE_LINK_MODE_PARAMS(100000, CR, Full),
++	__DEFINE_LINK_MODE_PARAMS(200000, KR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(200000, SR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(200000, LR2_ER2_FR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(200000, DR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(200000, CR2, Full),
++	__DEFINE_LINK_MODE_PARAMS(400000, KR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(400000, SR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(400000, LR4_ER4_FR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(400000, DR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(400000, CR4, Full),
++	__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
++	__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
++};
++
++const struct nla_policy ethnl_linkmodes_set_policy[] = {
++	[ETHTOOL_A_LINKMODES_HEADER]		=
++		NLA_POLICY_NESTED(ethnl_header_policy),
++	[ETHTOOL_A_LINKMODES_AUTONEG]		= { .type = NLA_U8 },
++	[ETHTOOL_A_LINKMODES_OURS]		= { .type = NLA_NESTED },
++	[ETHTOOL_A_LINKMODES_SPEED]		= { .type = NLA_U32 },
++	[ETHTOOL_A_LINKMODES_DUPLEX]		= { .type = NLA_U8 },
++	[ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG]	= { .type = NLA_U8 },
++	[ETHTOOL_A_LINKMODES_LANES]		=
++		NLA_POLICY_RANGE(NLA_U32, 1, 8),
++};
++
++/* Set advertised link modes to all supported modes matching requested speed,
++ * lanes and duplex values. Called when autonegotiation is on, speed, lanes or
++ * duplex is requested but no link mode change. This is done in userspace with
++ * ioctl() interface, move it into kernel for netlink.
++ * Returns true if advertised modes bitmap was modified.
++ */
++static bool ethnl_auto_linkmodes(struct ethtool_link_ksettings *ksettings,
++				 bool req_speed, bool req_lanes,
++				 bool req_duplex)
++{
++	unsigned long *advertising = ksettings->link_modes.advertising;
++	unsigned long *supported = ksettings->link_modes.supported;
++	DECLARE_BITMAP(old_adv, __ETHTOOL_LINK_MODE_MASK_NBITS);
++	unsigned int i;
++
++	BUILD_BUG_ON(ARRAY_SIZE(link_mode_params) !=
++		     __ETHTOOL_LINK_MODE_MASK_NBITS);
++
++	bitmap_copy(old_adv, advertising, __ETHTOOL_LINK_MODE_MASK_NBITS);
++
++	for (i = 0; i < __ETHTOOL_LINK_MODE_MASK_NBITS; i++) {
++		const struct link_mode_info *info = &link_mode_params[i];
++
++		if (info->speed == SPEED_UNKNOWN)
++			continue;
++		if (test_bit(i, supported) &&
++		    (!req_speed || info->speed == ksettings->base.speed) &&
++		    (!req_lanes || info->lanes == ksettings->lanes) &&
++		    (!req_duplex || info->duplex == ksettings->base.duplex))
++			set_bit(i, advertising);
++		else
++			clear_bit(i, advertising);
++	}
++
++	return !bitmap_equal(old_adv, advertising,
++			     __ETHTOOL_LINK_MODE_MASK_NBITS);
++}
++
++static bool ethnl_validate_master_slave_cfg(u8 cfg)
++{
++	switch (cfg) {
++	case MASTER_SLAVE_CFG_MASTER_PREFERRED:
++	case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
++	case MASTER_SLAVE_CFG_MASTER_FORCE:
++	case MASTER_SLAVE_CFG_SLAVE_FORCE:
++		return true;
++	}
++
++	return false;
++}
++
++static int ethnl_check_linkmodes(struct genl_info *info, struct nlattr **tb)
++{
++	const struct nlattr *master_slave_cfg, *lanes_cfg;
++
++	master_slave_cfg = tb[ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG];
++	if (master_slave_cfg &&
++	    !ethnl_validate_master_slave_cfg(nla_get_u8(master_slave_cfg))) {
++		NL_SET_ERR_MSG_ATTR(info->extack, master_slave_cfg,
++				    "master/slave value is invalid");
++		return -EOPNOTSUPP;
++	}
++
++	lanes_cfg = tb[ETHTOOL_A_LINKMODES_LANES];
++	if (lanes_cfg && !is_power_of_2(nla_get_u32(lanes_cfg))) {
++		NL_SET_ERR_MSG_ATTR(info->extack, lanes_cfg,
++				    "lanes value is invalid");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int ethnl_update_linkmodes(struct genl_info *info, struct nlattr **tb,
++				  struct ethtool_link_ksettings *ksettings,
++				  bool *mod, const struct net_device *dev)
++{
++	struct ethtool_link_settings *lsettings = &ksettings->base;
++	bool req_speed, req_lanes, req_duplex;
++	const struct nlattr *master_slave_cfg, *lanes_cfg;
++	int ret;
++
++	master_slave_cfg = tb[ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG];
++	if (master_slave_cfg) {
++		if (lsettings->master_slave_cfg == MASTER_SLAVE_CFG_UNSUPPORTED) {
++			NL_SET_ERR_MSG_ATTR(info->extack, master_slave_cfg,
++					    "master/slave configuration not supported by device");
++			return -EOPNOTSUPP;
++		}
++	}
++
++	*mod = false;
++	req_speed = tb[ETHTOOL_A_LINKMODES_SPEED];
++	req_lanes = tb[ETHTOOL_A_LINKMODES_LANES];
++	req_duplex = tb[ETHTOOL_A_LINKMODES_DUPLEX];
++
++	ethnl_update_u8(&lsettings->autoneg, tb[ETHTOOL_A_LINKMODES_AUTONEG],
++			mod);
++
++	lanes_cfg = tb[ETHTOOL_A_LINKMODES_LANES];
++	if (lanes_cfg) {
++		/* If autoneg is off and lanes parameter is
++		 * not supported by the driver,
++		 * return an error.
++		 */
++		if (!lsettings->autoneg &&
++		    !dev->ethtool_ops->cap_link_lanes_supported) {
++			NL_SET_ERR_MSG_ATTR(info->extack, lanes_cfg,
++					    "lanes configuration not supported by device");
++			return -EOPNOTSUPP;
++		}
++	} else if (!lsettings->autoneg) {
++		/* If autoneg is off and lanes parameter is
++		 * not passed from user,
++		 * set the lanes parameter to 0.
++		 */
++		ksettings->lanes = 0;
++	}
++
++	ret = ethnl_update_bitset(ksettings->link_modes.advertising,
++				  __ETHTOOL_LINK_MODE_MASK_NBITS,
++				  tb[ETHTOOL_A_LINKMODES_OURS], link_mode_names,
++				  info->extack, mod);
++	if (ret < 0)
++		return ret;
++	ethnl_update_u32(&lsettings->speed, tb[ETHTOOL_A_LINKMODES_SPEED],
++			 mod);
++	ethnl_update_u32(&ksettings->lanes, lanes_cfg, mod);
++	ethnl_update_u8(&lsettings->duplex, tb[ETHTOOL_A_LINKMODES_DUPLEX],
++			mod);
++	ethnl_update_u8(&lsettings->master_slave_cfg, master_slave_cfg, mod);
++
++	if (!tb[ETHTOOL_A_LINKMODES_OURS] && lsettings->autoneg &&
++	    (req_speed || req_lanes || req_duplex) &&
++	    ethnl_auto_linkmodes(ksettings, req_speed, req_lanes, req_duplex))
++		*mod = true;
++
++	return 0;
++}
++
++int ethnl_set_linkmodes(struct sk_buff *skb, struct genl_info *info)
++{
++	struct ethtool_link_ksettings ksettings = {};
++	struct ethnl_req_info req_info = {};
++	struct nlattr **tb = info->attrs;
++	struct net_device *dev;
++	bool mod = false;
++	int ret;
++
++	ret = ethnl_check_linkmodes(info, tb);
++	if (ret < 0)
++		return ret;
++
++	ret = ethnl_parse_header_dev_get(&req_info,
++					 tb[ETHTOOL_A_LINKMODES_HEADER],
++					 genl_info_net(info), info->extack,
++					 true);
++	if (ret < 0)
++		return ret;
++	dev = req_info.dev;
++	ret = -EOPNOTSUPP;
++	if (!dev->ethtool_ops->get_link_ksettings ||
++	    !dev->ethtool_ops->set_link_ksettings)
++		goto out_dev;
++
++	rtnl_lock();
++	ret = ethnl_ops_begin(dev);
++	if (ret < 0)
++		goto out_rtnl;
++
++	ret = __ethtool_get_link_ksettings(dev, &ksettings);
++	if (ret < 0) {
++		GENL_SET_ERR_MSG(info, "failed to retrieve link settings");
++		goto out_ops;
++	}
++
++	ret = ethnl_update_linkmodes(info, tb, &ksettings, &mod, dev);
++	if (ret < 0)
++		goto out_ops;
++
++	if (mod) {
++		ret = dev->ethtool_ops->set_link_ksettings(dev, &ksettings);
++		if (ret < 0)
++			GENL_SET_ERR_MSG(info, "link settings update failed");
++		else
++			ethtool_notify(dev, ETHTOOL_MSG_LINKMODES_NTF, NULL);
++	}
++
++out_ops:
++	ethnl_ops_complete(dev);
++out_rtnl:
++	rtnl_unlock();
++out_dev:
++	dev_put(dev);
++	return ret;
++}
+diff --git a/net/ethtool/netlink.h b/net/ethtool/netlink.h
+index bc2b83877e01..bf71eaf2ace8 100644
+--- a/net/ethtool/netlink.h
++++ b/net/ethtool/netlink.h
+@@ -338,6 +338,8 @@ extern const struct nla_policy ethnl_strset_get_policy[ETHTOOL_A_STRSET_COUNTS_O
+ extern const struct nla_policy ethnl_linkinfo_get_policy[ETHTOOL_A_LINKINFO_HEADER + 1];
+ extern const struct nla_policy ethnl_linkinfo_set_policy[ETHTOOL_A_LINKINFO_TP_MDIX_CTRL + 1];
+ extern const struct nla_policy ethnl_linkmodes_get_policy[ETHTOOL_A_LINKMODES_HEADER + 1];
++extern const struct nla_policy
++		ethnl_linkmodes_set_policy[ETHTOOL_A_LINKMODES_LANES + 1];
+ extern const struct nla_policy ethnl_linkstate_get_policy[ETHTOOL_A_LINKSTATE_HEADER + 1];
+ extern const struct nla_policy ethnl_debug_get_policy[ETHTOOL_A_DEBUG_HEADER + 1];
+ extern const struct nla_policy ethnl_debug_set_policy[ETHTOOL_A_DEBUG_MSGMASK + 1];
+-- 
+2.34.1
+
diff --git a/patches/0585-net-hns3-add-support-to-query-and-set-lane-number-by.patch b/patches/0585-net-hns3-add-support-to-query-and-set-lane-number-by.patch
new file mode 100644
index 0000000..b74d482
--- /dev/null
+++ b/patches/0585-net-hns3-add-support-to-query-and-set-lane-number-by.patch
@@ -0,0 +1,358 @@
+From a8ed6dd2923eaa49dc933a6bc98afe746f5e92cb Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao418@huawei.com>
+Date: Tue, 6 Sep 2022 17:12:23 +0800
+Subject: [PATCH 224/283] net: hns3: add support to query and set lane number
+ by ethtool
+
+mainline inclusion
+from mainline-v5.1-rc1
+commit 0f032f93c4ee9ff667b493db7b21c94cff31edc6
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0f032f93c4ee9ff667b493db7b21c94cff31edc6
+
+--------------------------------
+
+When serdes lane support setting 25Gb/s or 50Gb/s speed and user wants to
+set port speed as 50Gb/s, it can be setted as one 50Gb/s serdes lane or
+two 25Gb/s serdes lanes.
+
+So, this patch adds support to query and set lane number by ethtool
+to satisfy this scenario.
+
+Signed-off-by: Hao Chen <chenhao418@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  9 +++++--
+ .../hns3/hns3_common/hclge_comm_cmd.c         |  1 +
+ .../hns3/hns3_common/hclge_comm_cmd.h         |  1 +
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    |  6 +++++
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  8 ++----
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 27 ++++++++++++-------
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 23 ++++++++++------
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  3 ++-
+ .../hisilicon/hns3/hns3pf/hclge_mdio.c        |  2 +-
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |  2 +-
+ 10 files changed, 53 insertions(+), 29 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 437130f8077b..31a593966a42 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -101,6 +101,7 @@ enum HNAE3_DEV_CAP_BITS {
+ 	HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
+ 	HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,
+ 	HNAE3_DEV_SUPPORT_CQ_B,
++	HNAE3_DEV_SUPPORT_FEC_STATS_B,
+ 	HNAE3_DEV_SUPPORT_LANE_NUM_B,
+ 	HNAE3_DEV_SUPPORT_WOL_B,
+ 	HNAE3_DEV_SUPPORT_VF_FAULT_B,
+@@ -179,6 +180,9 @@ enum HNAE3_DEV_CAP_BITS {
+ #define hnae3_ae_dev_notify_pkt_supported(ae_dev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_NOTIFY_PKT_B, (ae_dev)->caps)
+ 
++#define hnae3_ae_dev_lane_num_supported(ae_dev) \
++	test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)
++
+ enum HNAE3_PF_CAP_BITS {
+ 	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
+ };
+@@ -606,10 +610,11 @@ struct hnae3_ae_ops {
+ 	void (*client_stop)(struct hnae3_handle *handle);
+ 	int (*get_status)(struct hnae3_handle *handle);
+ 	void (*get_ksettings_an_result)(struct hnae3_handle *handle,
+-					u8 *auto_neg, u32 *speed, u8 *duplex);
++					u8 *auto_neg, u32 *speed, u8 *duplex,
++					u32 *lane_num);
+ 
+ 	int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
+-				   u8 duplex);
++				   u8 duplex, u8 lane_num);
+ 
+ 	void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
+ 			       u8 *module_type);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index d2000301b942..c4d647519977 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -154,6 +154,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = {
+ 	{HCLGE_COMM_CAP_CQ_B, HNAE3_DEV_SUPPORT_CQ_B},
+ 	{HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},
+ 	{HCLGE_COMM_CAP_FD_B, HNAE3_DEV_SUPPORT_FD_B},
++	{HCLGE_COMM_CAP_FEC_STATS_B, HNAE3_DEV_SUPPORT_FEC_STATS_B},
+ 	{HCLGE_COMM_CAP_LANE_NUM_B, HNAE3_DEV_SUPPORT_LANE_NUM_B},
+ 	{HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},
+ 	{HCLGE_COMM_CAP_NOTIFY_PKT_B, HNAE3_DEV_SUPPORT_NOTIFY_PKT_B},
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index de9da88134e5..2b8df9b03412 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -95,6 +95,7 @@ enum HCLGE_COMM_CAP_BITS {
+ 	HCLGE_COMM_CAP_CQ_B = 18,
+ 	HCLGE_COMM_CAP_GRO_B = 20,
+ 	HCLGE_COMM_CAP_FD_B = 21,
++	HCLGE_COMM_CAP_FEC_STATS_B = 25,
+ 	HCLGE_COMM_CAP_LANE_NUM_B = 27,
+ 	HCLGE_COMM_CAP_WOL_B = 28,
+ 	HCLGE_COMM_CAP_NOTIFY_PKT_B = 29,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 9e92e8f92b95..afe3f673364c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -367,6 +367,12 @@ static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
+ 	}, {
+ 		.name = "support modify vlan filter state",
+ 		.cap_bit = HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B,
++	}, {
++		.name = "support FEC statistics",
++		.cap_bit = HNAE3_DEV_SUPPORT_FEC_STATS_B,
++	}, {
++		.name = "support lane num",
++		.cap_bit = HNAE3_DEV_SUPPORT_LANE_NUM_B,
+ 	}
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 72cc7f16aa7e..3066d7e960de 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -2053,8 +2053,7 @@ netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
+ 	struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
+ 	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
+ 	struct netdev_queue *dev_queue;
+-	int pre_ntu, next_to_use_head;
+-	int ret;
++	int pre_ntu, ret;
+ 
+ 	/* Hardware can only handle short frames above 32 bytes */
+ 	if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
+@@ -2094,7 +2093,7 @@ netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
+ 	 */
+ 	ret = hns3_handle_desc_filling(ring, skb);
+ 	if (unlikely(ret <= 0))
+-		goto fill_err;
++		goto out_err_tx_ok;
+ 
+ 	pre_ntu = ring->next_to_use ? (ring->next_to_use - 1) :
+ 					(ring->desc_num - 1);
+@@ -2119,9 +2118,6 @@ netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
+ 
+ 	return NETDEV_TX_OK;
+ 
+-fill_err:
+-	hns3_clear_desc(ring, next_to_use_head);
+-
+ out_err_tx_ok:
+ 	dev_kfree_skb_any(skb);
+ 	hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 52d448686a06..ece3e95e80d6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -766,7 +766,8 @@ static void hns3_get_ksettings(struct hnae3_handle *h,
+ 		ops->get_ksettings_an_result(h,
+ 					     &cmd->base.autoneg,
+ 					     &cmd->base.speed,
+-					     &cmd->base.duplex);
++					     &cmd->base.duplex,
++					     &cmd->lanes);
+ 
+ 	/* 2.get link mode */
+ 	if (ops->get_link_mode)
+@@ -848,6 +849,7 @@ static int hns3_check_ksettings_param(const struct net_device *netdev,
+ 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
+ 	u8 module_type = HNAE3_MODULE_TYPE_UNKNOWN;
+ 	u8 media_type = HNAE3_MEDIA_TYPE_UNKNOWN;
++	u32 lane_num;
+ 	u8 autoneg;
+ 	u32 speed;
+ 	u8 duplex;
+@@ -860,9 +862,10 @@ static int hns3_check_ksettings_param(const struct net_device *netdev,
+ 		return 0;
+ 
+ 	if (ops->get_ksettings_an_result) {
+-		ops->get_ksettings_an_result(handle, &autoneg, &speed, &duplex);
++		ops->get_ksettings_an_result(handle, &autoneg, &speed,
++						&duplex, &lane_num);
+ 		if (cmd->base.autoneg == autoneg && cmd->base.speed == speed &&
+-		    cmd->base.duplex == duplex)
++		    cmd->base.duplex == duplex && cmd->lanes == lane_num)
+ 			return 0;
+ 	}
+ 
+@@ -899,12 +902,14 @@ static int hns3_set_link_ksettings(struct net_device *netdev,
+ 	if (cmd->base.speed == SPEED_1000 && cmd->base.duplex == DUPLEX_HALF)
+ 		return -EINVAL;
+ 
+-	if (netif_msg_ifdown(handle))
+-		netdev_info(netdev,
+-			    "set link(%s): autoneg=%u, speed=%u, duplex=%u\n",
+-			    netdev->phydev ? "phy" : "mac",
+-			    cmd->base.autoneg, cmd->base.speed,
+-			    cmd->base.duplex);
++	if (cmd->lanes && !hnae3_ae_dev_lane_num_supported(ae_dev))
++		return -EOPNOTSUPP;
++
++	netif_dbg(handle, drv, netdev,
++		  "set link(%s): autoneg=%u, speed=%u, duplex=%u, lanes=%u\n",
++		  netdev->phydev ? "phy" : "mac",
++		  cmd->base.autoneg, cmd->base.speed, cmd->base.duplex,
++		  cmd->lanes);
+ 
+ 	/* Only support ksettings_set for netdev with phy attached for now */
+ 	if (netdev->phydev) {
+@@ -942,7 +947,8 @@ static int hns3_set_link_ksettings(struct net_device *netdev,
+ 
+ 	if (ops->cfg_mac_speed_dup_h)
+ 		ret = ops->cfg_mac_speed_dup_h(handle, cmd->base.speed,
+-					       cmd->base.duplex);
++					       cmd->base.duplex,
++						   (u8)(cmd->lanes));
+ 
+ 	return ret;
+ }
+@@ -2028,6 +2034,7 @@ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ static const struct ethtool_ops hns3_ethtool_ops = {
+ 	.supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
+ 	.supported_ring_params = HNS3_ETHTOOL_RING,
++	.cap_link_lanes_supported = true,
+ 	.self_test = hns3_self_test,
+ 	.get_drvinfo = hns3_get_drvinfo,
+ 	.get_link = hns3_get_link,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index e838d68607c9..5cb599ca53ea 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -2724,33 +2724,37 @@ int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
+ 	return 0;
+ }
+ 
+-int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
++int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed,
++			    u8 duplex, u8 lane_num)
+ {
+ 	struct hclge_mac *mac = &hdev->hw.mac;
+ 	int ret;
+ 
+ 	duplex = hclge_check_speed_dup(duplex, speed);
+ 	if (!mac->support_autoneg && mac->speed == speed &&
+-	    mac->duplex == duplex)
++	    mac->duplex == duplex &&
++		(mac->lane_num == lane_num || lane_num == 0))
+ 		return 0;
+ 
+-	ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, 0);
++	ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num);
+ 	if (ret)
+ 		return ret;
+ 
+ 	hdev->hw.mac.speed = speed;
+ 	hdev->hw.mac.duplex = duplex;
++	if (!lane_num)
++		hdev->hw.mac.lane_num = lane_num;
+ 
+ 	return 0;
+ }
+ 
+ static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
+-				     u8 duplex)
++				     u8 duplex, u8 lane_num)
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+ 
+-	return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
++	return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num);
+ }
+ 
+ static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
+@@ -3409,13 +3413,13 @@ static int hclge_update_port_info(struct hclge_dev *hdev)
+ 			return 0;
+ 		}
+ 		return hclge_cfg_mac_speed_dup(hdev, mac->speed,
+-					       HCLGE_MAC_FULL);
++					       HCLGE_MAC_FULL, mac->lane_num);
+ 	} else {
+ 		if (speed == HCLGE_MAC_SPEED_UNKNOWN)
+ 			return 0; /* do nothing if no SFP */
+ 
+ 		/* must config full duplex for SFP */
+-		return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL);
++		return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0);
+ 	}
+ }
+ 
+@@ -10897,7 +10901,8 @@ static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
+ }
+ 
+ static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
+-					  u8 *auto_neg, u32 *speed, u8 *duplex)
++					  u8 *auto_neg, u32 *speed,
++					  u8 *duplex, u32 *lane_num)
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+@@ -10908,6 +10913,8 @@ static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
+ 		*duplex = hdev->hw.mac.duplex;
+ 	if (auto_neg)
+ 		*auto_neg = hdev->hw.mac.autoneg;
++	if (lane_num)
++		*lane_num = hdev->hw.mac.lane_num;
+ }
+ 
+ void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index ad9c1f2fb7ce..00b4d476efe8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -1134,7 +1134,8 @@ static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
+ }
+ 
+ int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
+-int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
++int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed,
++			    u8 duplex, u8 lane_num);
+ int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
+ 			  u16 vlan_id, bool is_kill);
+ int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+index b9c81e2e60b2..3f2c898b0bf9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+@@ -187,7 +187,7 @@ static void hclge_mac_adjust_link(struct net_device *netdev)
+ 	speed = netdev->phydev->speed;
+ 	duplex = netdev->phydev->duplex;
+ 
+-	ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
++	ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, 0);
+ 	if (ret)
+ 		netdev_err(netdev, "failed to adjust link.\n");
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 623c53e22249..b38c903659a6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -3606,7 +3606,7 @@ static int hclgevf_get_status(struct hnae3_handle *handle)
+ 
+ static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
+ 					    u8 *auto_neg, u32 *speed,
+-					    u8 *duplex)
++					    u8 *duplex, u32 *lane_num)
+ {
+ 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
+ 
+-- 
+2.34.1
+
diff --git a/patches/0586-net-hns3-avoid-mult-div-op-in-critical-data-path.patch b/patches/0586-net-hns3-avoid-mult-div-op-in-critical-data-path.patch
new file mode 100644
index 0000000..25eed96
--- /dev/null
+++ b/patches/0586-net-hns3-avoid-mult-div-op-in-critical-data-path.patch
@@ -0,0 +1,77 @@
+From e76635fec8f1ec43ceddda52fac7ff36ee4052f3 Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Sat, 23 Feb 2019 17:22:09 +0800
+Subject: [PATCH 225/283] net: hns3: avoid mult + div op in critical data path
+
+mainline inclusion
+from mainline-v5.1-rc1
+commit 3fe13ed95dd3c4aede3313a2dd2d589c207b51d0
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3fe13ed95dd3c4aede3313a2dd2d589c207b51d0
+
+--------------------------------
+
+This patch uses shift offset to avoid doing mult and div operation.
+
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 5 +++--
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 3 +++
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 3066d7e960de..303b7b76bc8d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -913,6 +913,7 @@ static int hns3_set_tso(struct sk_buff *skb, u32 *paylen_fdop_ol4cs,
+ 
+ 	/* normal or tunnel packet */
+ 	l4_offset = l4.hdr - skb->data;
++	hdr_len = (l4.tcp->doff << 2) + l4_offset;
+ 
+ 	/* remove payload length from inner pseudo checksum when tso */
+ 	l4_paylen = skb->len - l4_offset;
+@@ -1466,8 +1467,8 @@ static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
+ 		return HNS3_LIKELY_BD_NUM;
+ 	}
+ 
+-	frag_buf_num = hns3_tx_bd_count(size);
+-	sizeoflast = size % HNS3_MAX_BD_SIZE;
++	frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) >> HNS3_MAX_BD_SIZE_OFFSET;
++	sizeoflast = size & HNS3_TX_LAST_SIZE_M;
+ 	sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
+ 
+ 	/* When frag size is bigger than hardware limit, split this frag */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 74a48d3a61b3..163f7cdadd54 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -185,6 +185,8 @@ enum hns3_nic_state {
+ #define HNS3_TXD_MSS_M				(0x3fff << HNS3_TXD_MSS_S)
+ #define HNS3_TXD_HW_CS_B			14
+ 
++#define HNS3_TX_LAST_SIZE_M                    0xffff
++
+ #define HNS3_VECTOR_TX_IRQ			BIT_ULL(0)
+ #define HNS3_VECTOR_RX_IRQ			BIT_ULL(1)
+ 
+@@ -196,6 +198,7 @@ enum hns3_nic_state {
+ #define HNS3_MAX_TSO_BD_NUM			63U
+ #define HNS3_MAX_TSO_SIZE			1048576U
+ #define HNS3_MAX_NON_TSO_SIZE			9728U
++#define HNS3_MAX_BD_SIZE_OFFSET			16
+ 
+ #define HNS3_VECTOR_GL0_OFFSET			0x100
+ #define HNS3_VECTOR_GL1_OFFSET			0x200
+-- 
+2.34.1
+
diff --git a/patches/0587-ethtool-netlink-bitset-handling.patch b/patches/0587-ethtool-netlink-bitset-handling.patch
new file mode 100644
index 0000000..4333b9e
--- /dev/null
+++ b/patches/0587-ethtool-netlink-bitset-handling.patch
@@ -0,0 +1,871 @@
+From 1757aa93e2a09ccf669cdbba1c4f148db90eade0 Mon Sep 17 00:00:00 2001
+From: Michal Kubecek <mkubecek@suse.cz>
+Date: Fri, 27 Dec 2019 15:55:28 +0100
+Subject: [PATCH 226/283] ethtool: netlink bitset handling
+
+mainline inclusion
+from mainline-v5.6-rc1
+commit 10b518d4e6dd5390e40f7d8de0f08753c1195a7e
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=10b518d4e6dd5390e40f7d8de0f08753c1195a7e
+
+--------------------------------
+
+The ethtool netlink code uses common framework for passing arbitrary
+length bit sets to allow future extensions. A bitset can be a list (only
+one bitmap) or can consist of value and mask pair (used e.g. when client
+want to modify only some bits). A bitset can use one of two formats:
+verbose (bit by bit) or compact.
+
+Verbose format consists of bitset size (number of bits), list flag and
+an array of bit nests, telling which bits are part of the list or which
+bits are in the mask and which of them are to be set. In requests, bits
+can be identified by index (position) or by name. In replies, kernel
+provides both index and name. Verbose format is suitable for "one shot"
+applications like standard ethtool command as it avoids the need to
+either keep bit names (e.g. link modes) in sync with kernel or having to
+add an extra roundtrip for string set request (e.g. for private flags).
+
+Compact format uses one (list) or two (value/mask) arrays of 32-bit
+words to store the bitmap(s). It is more suitable for long running
+applications (ethtool in monitor mode or network management daemons)
+which can retrieve the names once and then pass only compact bitmaps to
+save space.
+
+Userspace requests can use either format; ETHTOOL_FLAG_COMPACT_BITSETS
+flag in request header tells kernel which format to use in reply.
+Notifications always use compact format.
+
+As some code uses arrays of unsigned long for internal representation and
+some arrays of u32 (or even a single u32), two sets of parse/compose
+helpers are introduced. To avoid code duplication, helpers for unsigned
+long arrays are implemented as wrappers around helpers for u32 arrays.
+There are two reasons for this choice: (1) u32 arrays are more frequent in
+ethtool code and (2) unsigned long array can be always interpreted as an
+u32 array on little endian 64-bit and all 32-bit architectures while we
+would need special handling for odd number of u32 words in the opposite
+direction.
+
+Signed-off-by: Michal Kubecek <mkubecek@suse.cz>
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	Documentation/networking/ethtool-netlink.rst
+	include/uapi/linux/ethtool_netlink.h
+	net/ethtool/Makefile
+---
+ Documentation/networking/ethtool-netlink.rst |   2 +
+ net/ethtool/Makefile                         |   2 +-
+ net/ethtool/bitset.c                         | 736 +++++++++++++++++++
+ net/ethtool/bitset.h                         |  28 +
+ 4 files changed, 767 insertions(+), 1 deletion(-)
+ create mode 100644 net/ethtool/bitset.c
+ create mode 100644 net/ethtool/bitset.h
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+index 18109dfc26e7..83b3ecda4f16 100644
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -76,6 +76,8 @@ of the flag should be interpreted the way the client expects. A client must
+ not set flags it does not understand.
+ 
+ 
++Bit sets
++========
+ 
+ For short bitmaps of (reasonably) fixed length, standard ``NLA_BITFIELD32``
+ type is used. For arbitrary length bitmaps, ethtool netlink uses a nested
+diff --git a/net/ethtool/Makefile b/net/ethtool/Makefile
+index 685d55945c99..70e62f840e28 100644
+--- a/net/ethtool/Makefile
++++ b/net/ethtool/Makefile
+@@ -4,4 +4,4 @@ obj-y				+= ioctl.o common.o
+ 
+ obj-$(CONFIG_ETHTOOL_NETLINK)	+= ethtool_nl.o
+ 
+-ethtool_nl-y	:= netlink.o rings.o linkmodes.o
++ethtool_nl-y	:= netlink.o rings.o linkmodes.o bitset.o
+\ No newline at end of file
+diff --git a/net/ethtool/bitset.c b/net/ethtool/bitset.c
+new file mode 100644
+index 000000000000..61a9de207020
+--- /dev/null
++++ b/net/ethtool/bitset.c
+@@ -0,0 +1,736 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include <linux/ethtool_netlink.h>
++#include <linux/bitmap.h>
++#include "netlink.h"
++#include "bitset.h"
++
++/* Some bitmaps are internally represented as an array of unsigned long, some
++ * as an array of u32 (some even as single u32 for now). To avoid the need of
++ * wrappers on caller side, we provide two set of functions: those with "32"
++ * suffix in their names expect u32 based bitmaps, those without it expect
++ * unsigned long bitmaps.
++ */
++
++static u32 ethnl_lower_bits(unsigned int n)
++{
++	return ~(u32)0 >> (32 - n % 32);
++}
++
++static u32 ethnl_upper_bits(unsigned int n)
++{
++	return ~(u32)0 << (n % 32);
++}
++
++/**
++ * ethnl_bitmap32_clear() - Clear u32 based bitmap
++ * @dst:   bitmap to clear
++ * @start: beginning of the interval
++ * @end:   end of the interval
++ * @mod:   set if bitmap was modified
++ *
++ * Clear @nbits bits of a bitmap with indices @start <= i < @end
++ */
++static void ethnl_bitmap32_clear(u32 *dst, unsigned int start, unsigned int end,
++				 bool *mod)
++{
++	unsigned int start_word = start / 32;
++	unsigned int end_word = end / 32;
++	unsigned int i;
++	u32 mask;
++
++	if (end <= start)
++		return;
++
++	if (start % 32) {
++		mask = ethnl_upper_bits(start);
++		if (end_word == start_word) {
++			mask &= ethnl_lower_bits(end);
++			if (dst[start_word] & mask) {
++				dst[start_word] &= ~mask;
++				*mod = true;
++			}
++			return;
++		}
++		if (dst[start_word] & mask) {
++			dst[start_word] &= ~mask;
++			*mod = true;
++		}
++		start_word++;
++	}
++
++	for (i = start_word; i < end_word; i++) {
++		if (dst[i]) {
++			dst[i] = 0;
++			*mod = true;
++		}
++	}
++	if (end % 32) {
++		mask = ethnl_lower_bits(end);
++		if (dst[end_word] & mask) {
++			dst[end_word] &= ~mask;
++			*mod = true;
++		}
++	}
++}
++
++/**
++ * ethnl_bitmap32_not_zero() - Check if any bit is set in an interval
++ * @map:   bitmap to test
++ * @start: beginning of the interval
++ * @end:   end of the interval
++ *
++ * Return: true if there is non-zero bit with  index @start <= i < @end,
++ *         false if the whole interval is zero
++ */
++static bool ethnl_bitmap32_not_zero(const u32 *map, unsigned int start,
++				    unsigned int end)
++{
++	unsigned int start_word = start / 32;
++	unsigned int end_word = end / 32;
++	u32 mask;
++
++	if (end <= start)
++		return true;
++
++	if (start % 32) {
++		mask = ethnl_upper_bits(start);
++		if (end_word == start_word) {
++			mask &= ethnl_lower_bits(end);
++			return map[start_word] & mask;
++		}
++		if (map[start_word] & mask)
++			return true;
++		start_word++;
++	}
++
++	if (!memchr_inv(map + start_word, '\0',
++			(end_word - start_word) * sizeof(u32)))
++		return true;
++	if (end % 32 == 0)
++		return true;
++	return map[end_word] & ethnl_lower_bits(end);
++}
++
++/**
++ * ethnl_bitmap32_update() - Modify u32 based bitmap according to value/mask
++ *			     pair
++ * @dst:   bitmap to update
++ * @nbits: bit size of the bitmap
++ * @value: values to set
++ * @mask:  mask of bits to set
++ * @mod:   set to true if bitmap is modified, preserve if not
++ *
++ * Set bits in @dst bitmap which are set in @mask to values from @value, leave
++ * the rest untouched. If destination bitmap was modified, set @mod to true,
++ * leave as it is if not.
++ */
++static void ethnl_bitmap32_update(u32 *dst, unsigned int nbits,
++				  const u32 *value, const u32 *mask, bool *mod)
++{
++	while (nbits > 0) {
++		u32 real_mask = mask ? *mask : ~(u32)0;
++		u32 new_value;
++
++		if (nbits < 32)
++			real_mask &= ethnl_lower_bits(nbits);
++		new_value = (*dst & ~real_mask) | (*value & real_mask);
++		if (new_value != *dst) {
++			*dst = new_value;
++			*mod = true;
++		}
++
++		if (nbits <= 32)
++			break;
++		dst++;
++		nbits -= 32;
++		value++;
++		if (mask)
++			mask++;
++	}
++}
++
++static bool ethnl_bitmap32_test_bit(const u32 *map, unsigned int index)
++{
++	return map[index / 32] & (1U << (index % 32));
++}
++
++/**
++ * ethnl_bitset32_size() - Calculate size of bitset nested attribute
++ * @val:     value bitmap (u32 based)
++ * @mask:    mask bitmap (u32 based, optional)
++ * @nbits:   bit length of the bitset
++ * @names:   array of bit names (optional)
++ * @compact: assume compact format for output
++ *
++ * Estimate length of netlink attribute composed by a later call to
++ * ethnl_put_bitset32() call with the same arguments.
++ *
++ * Return: negative error code or attribute length estimate
++ */
++int ethnl_bitset32_size(const u32 *val, const u32 *mask, unsigned int nbits,
++			ethnl_string_array_t names, bool compact)
++{
++	unsigned int len = 0;
++
++	/* list flag */
++	if (!mask)
++		len += nla_total_size(sizeof(u32));
++	/* size */
++	len += nla_total_size(sizeof(u32));
++
++	if (compact) {
++		unsigned int nwords = DIV_ROUND_UP(nbits, 32);
++
++		/* value, mask */
++		len += (mask ? 2 : 1) * nla_total_size(nwords * sizeof(u32));
++	} else {
++		unsigned int bits_len = 0;
++		unsigned int bit_len, i;
++
++		for (i = 0; i < nbits; i++) {
++			const char *name = names ? names[i] : NULL;
++
++			if (!ethnl_bitmap32_test_bit(mask ?: val, i))
++				continue;
++			/* index */
++			bit_len = nla_total_size(sizeof(u32));
++			/* name */
++			if (name)
++				bit_len += ethnl_strz_size(name);
++			/* value */
++			if (mask && ethnl_bitmap32_test_bit(val, i))
++				bit_len += nla_total_size(0);
++
++			/* bit nest */
++			bits_len += nla_total_size(bit_len);
++		}
++		/* bits nest */
++		len += nla_total_size(bits_len);
++	}
++
++	/* outermost nest */
++	return nla_total_size(len);
++}
++
++/**
++ * ethnl_put_bitset32() - Put a bitset nest into a message
++ * @skb:      skb with the message
++ * @attrtype: attribute type for the bitset nest
++ * @val:      value bitmap (u32 based)
++ * @mask:     mask bitmap (u32 based, optional)
++ * @nbits:    bit length of the bitset
++ * @names:    array of bit names (optional)
++ * @compact:  use compact format for the output
++ *
++ * Compose a nested attribute representing a bitset. If @mask is null, simple
++ * bitmap (bit list) is created, if @mask is provided, represent a value/mask
++ * pair. Bit names are only used in verbose mode and when provided by calller.
++ *
++ * Return: 0 on success, negative error value on error
++ */
++int ethnl_put_bitset32(struct sk_buff *skb, int attrtype, const u32 *val,
++		       const u32 *mask, unsigned int nbits,
++		       ethnl_string_array_t names, bool compact)
++{
++	struct nlattr *nest;
++	struct nlattr *attr;
++
++	nest = nla_nest_start(skb, attrtype);
++	if (!nest)
++		return -EMSGSIZE;
++
++	if (!mask && nla_put_flag(skb, ETHTOOL_A_BITSET_NOMASK))
++		goto nla_put_failure;
++	if (nla_put_u32(skb, ETHTOOL_A_BITSET_SIZE, nbits))
++		goto nla_put_failure;
++	if (compact) {
++		unsigned int nwords = DIV_ROUND_UP(nbits, 32);
++		unsigned int nbytes = nwords * sizeof(u32);
++		u32 *dst;
++
++		attr = nla_reserve(skb, ETHTOOL_A_BITSET_VALUE, nbytes);
++		if (!attr)
++			goto nla_put_failure;
++		dst = nla_data(attr);
++		memcpy(dst, val, nbytes);
++		if (nbits % 32)
++			dst[nwords - 1] &= ethnl_lower_bits(nbits);
++
++		if (mask) {
++			attr = nla_reserve(skb, ETHTOOL_A_BITSET_MASK, nbytes);
++			if (!attr)
++				goto nla_put_failure;
++			dst = nla_data(attr);
++			memcpy(dst, mask, nbytes);
++			if (nbits % 32)
++				dst[nwords - 1] &= ethnl_lower_bits(nbits);
++		}
++	} else {
++		struct nlattr *bits;
++		unsigned int i;
++
++		bits = nla_nest_start(skb, ETHTOOL_A_BITSET_BITS);
++		if (!bits)
++			goto nla_put_failure;
++		for (i = 0; i < nbits; i++) {
++			const char *name = names ? names[i] : NULL;
++
++			if (!ethnl_bitmap32_test_bit(mask ?: val, i))
++				continue;
++			attr = nla_nest_start(skb, ETHTOOL_A_BITSET_BITS_BIT);
++			if (!attr)
++				goto nla_put_failure;
++			if (nla_put_u32(skb, ETHTOOL_A_BITSET_BIT_INDEX, i))
++				goto nla_put_failure;
++			if (name &&
++			    ethnl_put_strz(skb, ETHTOOL_A_BITSET_BIT_NAME,
++					   name))
++				goto nla_put_failure;
++			if (mask && ethnl_bitmap32_test_bit(val, i) &&
++			    nla_put_flag(skb, ETHTOOL_A_BITSET_BIT_VALUE))
++				goto nla_put_failure;
++			nla_nest_end(skb, attr);
++		}
++		nla_nest_end(skb, bits);
++	}
++
++	nla_nest_end(skb, nest);
++	return 0;
++
++nla_put_failure:
++	nla_nest_cancel(skb, nest);
++	return -EMSGSIZE;
++}
++
++static const struct nla_policy bitset_policy[ETHTOOL_A_BITSET_MAX + 1] = {
++	[ETHTOOL_A_BITSET_UNSPEC]	= { .type = NLA_REJECT },
++	[ETHTOOL_A_BITSET_NOMASK]	= { .type = NLA_FLAG },
++	[ETHTOOL_A_BITSET_SIZE]		= { .type = NLA_U32 },
++	[ETHTOOL_A_BITSET_BITS]		= { .type = NLA_NESTED },
++	[ETHTOOL_A_BITSET_VALUE]	= { .type = NLA_BINARY },
++	[ETHTOOL_A_BITSET_MASK]		= { .type = NLA_BINARY },
++};
++
++static const struct nla_policy bit_policy[ETHTOOL_A_BITSET_BIT_MAX + 1] = {
++	[ETHTOOL_A_BITSET_BIT_UNSPEC]	= { .type = NLA_REJECT },
++	[ETHTOOL_A_BITSET_BIT_INDEX]	= { .type = NLA_U32 },
++	[ETHTOOL_A_BITSET_BIT_NAME]	= { .type = NLA_NUL_STRING },
++	[ETHTOOL_A_BITSET_BIT_VALUE]	= { .type = NLA_FLAG },
++};
++
++/**
++ * ethnl_bitset_is_compact() - check if bitset attribute represents a compact
++ *			       bitset
++ * @bitset:  nested attribute representing a bitset
++ * @compact: pointer for return value
++ *
++ * Return: 0 on success, negative error code on failure
++ */
++int ethnl_bitset_is_compact(const struct nlattr *bitset, bool *compact)
++{
++	struct nlattr *tb[ETHTOOL_A_BITSET_MAX + 1];
++	int ret;
++
++	ret = nla_parse_nested(tb, ETHTOOL_A_BITSET_MAX, bitset,
++			       bitset_policy, NULL);
++	if (ret < 0)
++		return ret;
++
++	if (tb[ETHTOOL_A_BITSET_BITS]) {
++		if (tb[ETHTOOL_A_BITSET_VALUE] || tb[ETHTOOL_A_BITSET_MASK])
++			return -EINVAL;
++		*compact = false;
++		return 0;
++	}
++	if (!tb[ETHTOOL_A_BITSET_SIZE] || !tb[ETHTOOL_A_BITSET_VALUE])
++		return -EINVAL;
++
++	*compact = true;
++	return 0;
++}
++
++/**
++ * ethnl_name_to_idx() - look up string index for a name
++ * @names:   array of ETH_GSTRING_LEN sized strings
++ * @n_names: number of strings in the array
++ * @name:    name to look up
++ *
++ * Return: index of the string if found, -ENOENT if not found
++ */
++static int ethnl_name_to_idx(ethnl_string_array_t names, unsigned int n_names,
++			     const char *name)
++{
++	unsigned int i;
++
++	if (!names)
++		return -ENOENT;
++
++	for (i = 0; i < n_names; i++) {
++		/* names[i] may not be null terminated */
++		if (!strncmp(names[i], name, ETH_GSTRING_LEN) &&
++		    strlen(name) <= ETH_GSTRING_LEN)
++			return i;
++	}
++
++	return -ENOENT;
++}
++
++static int ethnl_parse_bit(unsigned int *index, bool *val, unsigned int nbits,
++			   const struct nlattr *bit_attr, bool no_mask,
++			   ethnl_string_array_t names,
++			   struct netlink_ext_ack *extack)
++{
++	struct nlattr *tb[ETHTOOL_A_BITSET_BIT_MAX + 1];
++	int ret, idx;
++
++	ret = nla_parse_nested(tb, ETHTOOL_A_BITSET_BIT_MAX, bit_attr,
++			       bit_policy, extack);
++	if (ret < 0)
++		return ret;
++
++	if (tb[ETHTOOL_A_BITSET_BIT_INDEX]) {
++		const char *name;
++
++		idx = nla_get_u32(tb[ETHTOOL_A_BITSET_BIT_INDEX]);
++		if (idx >= nbits) {
++			NL_SET_ERR_MSG_ATTR(extack,
++					    tb[ETHTOOL_A_BITSET_BIT_INDEX],
++					    "bit index too high");
++			return -EOPNOTSUPP;
++		}
++		name = names ? names[idx] : NULL;
++		if (tb[ETHTOOL_A_BITSET_BIT_NAME] && name &&
++		    strncmp(nla_data(tb[ETHTOOL_A_BITSET_BIT_NAME]), name,
++			    nla_len(tb[ETHTOOL_A_BITSET_BIT_NAME]))) {
++			NL_SET_ERR_MSG_ATTR(extack, bit_attr,
++					    "bit index and name mismatch");
++			return -EINVAL;
++		}
++	} else if (tb[ETHTOOL_A_BITSET_BIT_NAME]) {
++		idx = ethnl_name_to_idx(names, nbits,
++					nla_data(tb[ETHTOOL_A_BITSET_BIT_NAME]));
++		if (idx < 0) {
++			NL_SET_ERR_MSG_ATTR(extack,
++					    tb[ETHTOOL_A_BITSET_BIT_NAME],
++					    "bit name not found");
++			return -EOPNOTSUPP;
++		}
++	} else {
++		NL_SET_ERR_MSG_ATTR(extack, bit_attr,
++				    "neither bit index nor name specified");
++		return -EINVAL;
++	}
++
++	*index = idx;
++	*val = no_mask || tb[ETHTOOL_A_BITSET_BIT_VALUE];
++	return 0;
++}
++
++static int
++ethnl_update_bitset32_verbose(u32 *bitmap, unsigned int nbits,
++			      const struct nlattr *attr, struct nlattr **tb,
++			      ethnl_string_array_t names,
++			      struct netlink_ext_ack *extack, bool *mod)
++{
++	struct nlattr *bit_attr;
++	bool no_mask;
++	int rem;
++	int ret;
++
++	if (tb[ETHTOOL_A_BITSET_VALUE]) {
++		NL_SET_ERR_MSG_ATTR(extack, tb[ETHTOOL_A_BITSET_VALUE],
++				    "value only allowed in compact bitset");
++		return -EINVAL;
++	}
++	if (tb[ETHTOOL_A_BITSET_MASK]) {
++		NL_SET_ERR_MSG_ATTR(extack, tb[ETHTOOL_A_BITSET_MASK],
++				    "mask only allowed in compact bitset");
++		return -EINVAL;
++	}
++	no_mask = tb[ETHTOOL_A_BITSET_NOMASK];
++
++	nla_for_each_nested(bit_attr, tb[ETHTOOL_A_BITSET_BITS], rem) {
++		bool old_val, new_val;
++		unsigned int idx;
++
++		if (nla_type(bit_attr) != ETHTOOL_A_BITSET_BITS_BIT) {
++			NL_SET_ERR_MSG_ATTR(extack, bit_attr,
++					    "only ETHTOOL_A_BITSET_BITS_BIT allowed in ETHTOOL_A_BITSET_BITS");
++			return -EINVAL;
++		}
++		ret = ethnl_parse_bit(&idx, &new_val, nbits, bit_attr, no_mask,
++				      names, extack);
++		if (ret < 0)
++			return ret;
++		old_val = bitmap[idx / 32] & ((u32)1 << (idx % 32));
++		if (new_val != old_val) {
++			if (new_val)
++				bitmap[idx / 32] |= ((u32)1 << (idx % 32));
++			else
++				bitmap[idx / 32] &= ~((u32)1 << (idx % 32));
++			*mod = true;
++		}
++	}
++
++	return 0;
++}
++
++static int ethnl_compact_sanity_checks(unsigned int nbits,
++				       const struct nlattr *nest,
++				       struct nlattr **tb,
++				       struct netlink_ext_ack *extack)
++{
++	bool no_mask = tb[ETHTOOL_A_BITSET_NOMASK];
++	unsigned int attr_nbits, attr_nwords;
++	const struct nlattr *test_attr;
++
++	if (no_mask && tb[ETHTOOL_A_BITSET_MASK]) {
++		NL_SET_ERR_MSG_ATTR(extack, tb[ETHTOOL_A_BITSET_MASK],
++				    "mask not allowed in list bitset");
++		return -EINVAL;
++	}
++	if (!tb[ETHTOOL_A_BITSET_SIZE]) {
++		NL_SET_ERR_MSG_ATTR(extack, nest,
++				    "missing size in compact bitset");
++		return -EINVAL;
++	}
++	if (!tb[ETHTOOL_A_BITSET_VALUE]) {
++		NL_SET_ERR_MSG_ATTR(extack, nest,
++				    "missing value in compact bitset");
++		return -EINVAL;
++	}
++	if (!no_mask && !tb[ETHTOOL_A_BITSET_MASK]) {
++		NL_SET_ERR_MSG_ATTR(extack, nest,
++				    "missing mask in compact nonlist bitset");
++		return -EINVAL;
++	}
++
++	attr_nbits = nla_get_u32(tb[ETHTOOL_A_BITSET_SIZE]);
++	attr_nwords = DIV_ROUND_UP(attr_nbits, 32);
++	if (nla_len(tb[ETHTOOL_A_BITSET_VALUE]) != attr_nwords * sizeof(u32)) {
++		NL_SET_ERR_MSG_ATTR(extack, tb[ETHTOOL_A_BITSET_VALUE],
++				    "bitset value length does not match size");
++		return -EINVAL;
++	}
++	if (tb[ETHTOOL_A_BITSET_MASK] &&
++	    nla_len(tb[ETHTOOL_A_BITSET_MASK]) != attr_nwords * sizeof(u32)) {
++		NL_SET_ERR_MSG_ATTR(extack, tb[ETHTOOL_A_BITSET_MASK],
++				    "bitset mask length does not match size");
++		return -EINVAL;
++	}
++	if (attr_nbits <= nbits)
++		return 0;
++
++	test_attr = no_mask ? tb[ETHTOOL_A_BITSET_VALUE] :
++			      tb[ETHTOOL_A_BITSET_MASK];
++	if (ethnl_bitmap32_not_zero(nla_data(test_attr), nbits, attr_nbits)) {
++		NL_SET_ERR_MSG_ATTR(extack, test_attr,
++				    "cannot modify bits past kernel bitset size");
++		return -EINVAL;
++	}
++	return 0;
++}
++
++/**
++ * ethnl_update_bitset32() - Apply a bitset nest to a u32 based bitmap
++ * @bitmap:  bitmap to update
++ * @nbits:   size of the updated bitmap in bits
++ * @attr:    nest attribute to parse and apply
++ * @names:   array of bit names; may be null for compact format
++ * @extack:  extack for error reporting
++ * @mod:     set this to true if bitmap is modified, leave as it is if not
++ *
++ * Apply bitset netsted attribute to a bitmap. If the attribute represents
++ * a bit list, @bitmap is set to its contents; otherwise, bits in mask are
++ * set to values from value. Bitmaps in the attribute may be longer than
++ * @nbits but the message must not request modifying any bits past @nbits.
++ *
++ * Return: negative error code on failure, 0 on success
++ */
++int ethnl_update_bitset32(u32 *bitmap, unsigned int nbits,
++			  const struct nlattr *attr, ethnl_string_array_t names,
++			  struct netlink_ext_ack *extack, bool *mod)
++{
++	struct nlattr *tb[ETHTOOL_A_BITSET_MAX + 1];
++	unsigned int change_bits;
++	bool no_mask;
++	int ret;
++
++	if (!attr)
++		return 0;
++	ret = nla_parse_nested(tb, ETHTOOL_A_BITSET_MAX, attr, bitset_policy,
++			       extack);
++	if (ret < 0)
++		return ret;
++
++	if (tb[ETHTOOL_A_BITSET_BITS])
++		return ethnl_update_bitset32_verbose(bitmap, nbits, attr, tb,
++						     names, extack, mod);
++	ret = ethnl_compact_sanity_checks(nbits, attr, tb, extack);
++	if (ret < 0)
++		return ret;
++
++	no_mask = tb[ETHTOOL_A_BITSET_NOMASK];
++	change_bits = min_t(unsigned int,
++			    nla_get_u32(tb[ETHTOOL_A_BITSET_SIZE]), nbits);
++	ethnl_bitmap32_update(bitmap, change_bits,
++			      nla_data(tb[ETHTOOL_A_BITSET_VALUE]),
++			      no_mask ? NULL :
++					nla_data(tb[ETHTOOL_A_BITSET_MASK]),
++			      mod);
++	if (no_mask && change_bits < nbits)
++		ethnl_bitmap32_clear(bitmap, change_bits, nbits, mod);
++
++	return 0;
++}
++
++#if BITS_PER_LONG == 64 && defined(__BIG_ENDIAN)
++
++/* 64-bit big endian architectures are the only case when u32 based bitmaps
++ * and unsigned long based bitmaps have different memory layout so that we
++ * cannot simply cast the latter to the former and need actual wrappers
++ * converting the latter to the former.
++ *
++ * To reduce the number of slab allocations, the wrappers use fixed size local
++ * variables for bitmaps up to ETHNL_SMALL_BITMAP_BITS bits which is the
++ * majority of bitmaps used by ethtool.
++ */
++#define ETHNL_SMALL_BITMAP_BITS 128
++#define ETHNL_SMALL_BITMAP_WORDS DIV_ROUND_UP(ETHNL_SMALL_BITMAP_BITS, 32)
++
++int ethnl_bitset_size(const unsigned long *val, const unsigned long *mask,
++		      unsigned int nbits, ethnl_string_array_t names,
++		      bool compact)
++{
++	u32 small_mask32[ETHNL_SMALL_BITMAP_WORDS];
++	u32 small_val32[ETHNL_SMALL_BITMAP_WORDS];
++	u32 *mask32;
++	u32 *val32;
++	int ret;
++
++	if (nbits > ETHNL_SMALL_BITMAP_BITS) {
++		unsigned int nwords = DIV_ROUND_UP(nbits, 32);
++
++		val32 = kmalloc_array(2 * nwords, sizeof(u32), GFP_KERNEL);
++		if (!val32)
++			return -ENOMEM;
++		mask32 = val32 + nwords;
++	} else {
++		val32 = small_val32;
++		mask32 = small_mask32;
++	}
++
++	bitmap_to_arr32(val32, val, nbits);
++	if (mask)
++		bitmap_to_arr32(mask32, mask, nbits);
++	else
++		mask32 = NULL;
++	ret = ethnl_bitset32_size(val32, mask32, nbits, names, compact);
++
++	if (nbits > ETHNL_SMALL_BITMAP_BITS)
++		kfree(val32);
++
++	return ret;
++}
++
++int ethnl_put_bitset(struct sk_buff *skb, int attrtype,
++		     const unsigned long *val, const unsigned long *mask,
++		     unsigned int nbits, ethnl_string_array_t names,
++		     bool compact)
++{
++	u32 small_mask32[ETHNL_SMALL_BITMAP_WORDS];
++	u32 small_val32[ETHNL_SMALL_BITMAP_WORDS];
++	u32 *mask32;
++	u32 *val32;
++	int ret;
++
++	if (nbits > ETHNL_SMALL_BITMAP_BITS) {
++		unsigned int nwords = DIV_ROUND_UP(nbits, 32);
++
++		val32 = kmalloc_array(2 * nwords, sizeof(u32), GFP_KERNEL);
++		if (!val32)
++			return -ENOMEM;
++		mask32 = val32 + nwords;
++	} else {
++		val32 = small_val32;
++		mask32 = small_mask32;
++	}
++
++	bitmap_to_arr32(val32, val, nbits);
++	if (mask)
++		bitmap_to_arr32(mask32, mask, nbits);
++	else
++		mask32 = NULL;
++	ret = ethnl_put_bitset32(skb, attrtype, val32, mask32, nbits, names,
++				 compact);
++
++	if (nbits > ETHNL_SMALL_BITMAP_BITS)
++		kfree(val32);
++
++	return ret;
++}
++
++int ethnl_update_bitset(unsigned long *bitmap, unsigned int nbits,
++			const struct nlattr *attr, ethnl_string_array_t names,
++			struct netlink_ext_ack *extack, bool *mod)
++{
++	u32 small_bitmap32[ETHNL_SMALL_BITMAP_WORDS];
++	u32 *bitmap32 = small_bitmap32;
++	bool u32_mod = false;
++	int ret;
++
++	if (nbits > ETHNL_SMALL_BITMAP_BITS) {
++		unsigned int dst_words = DIV_ROUND_UP(nbits, 32);
++
++		bitmap32 = kmalloc_array(dst_words, sizeof(u32), GFP_KERNEL);
++		if (!bitmap32)
++			return -ENOMEM;
++	}
++
++	bitmap_to_arr32(bitmap32, bitmap, nbits);
++	ret = ethnl_update_bitset32(bitmap32, nbits, attr, names, extack,
++				    &u32_mod);
++	if (u32_mod) {
++		bitmap_from_arr32(bitmap, bitmap32, nbits);
++		*mod = true;
++	}
++
++	if (nbits > ETHNL_SMALL_BITMAP_BITS)
++		kfree(bitmap32);
++
++	return ret;
++}
++
++#else
++
++/* On little endian 64-bit and all 32-bit architectures, an unsigned long
++ * based bitmap can be interpreted as u32 based one using a simple cast.
++ */
++
++int ethnl_bitset_size(const unsigned long *val, const unsigned long *mask,
++		      unsigned int nbits, ethnl_string_array_t names,
++		      bool compact)
++{
++	return ethnl_bitset32_size((const u32 *)val, (const u32 *)mask, nbits,
++				   names, compact);
++}
++
++int ethnl_put_bitset(struct sk_buff *skb, int attrtype,
++		     const unsigned long *val, const unsigned long *mask,
++		     unsigned int nbits, ethnl_string_array_t names,
++		     bool compact)
++{
++	return ethnl_put_bitset32(skb, attrtype, (const u32 *)val,
++				  (const u32 *)mask, nbits, names, compact);
++}
++
++int ethnl_update_bitset(unsigned long *bitmap, unsigned int nbits,
++			const struct nlattr *attr, ethnl_string_array_t names,
++			struct netlink_ext_ack *extack, bool *mod)
++{
++	return ethnl_update_bitset32((u32 *)bitmap, nbits, attr, names, extack,
++				     mod);
++}
++
++#endif /* BITS_PER_LONG == 64 && defined(__BIG_ENDIAN) */
+diff --git a/net/ethtool/bitset.h b/net/ethtool/bitset.h
+new file mode 100644
+index 000000000000..b8247e34109d
+--- /dev/null
++++ b/net/ethtool/bitset.h
+@@ -0,0 +1,28 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef _NET_ETHTOOL_BITSET_H
++#define _NET_ETHTOOL_BITSET_H
++
++typedef const char (*const ethnl_string_array_t)[ETH_GSTRING_LEN];
++
++int ethnl_bitset_is_compact(const struct nlattr *bitset, bool *compact);
++int ethnl_bitset_size(const unsigned long *val, const unsigned long *mask,
++		      unsigned int nbits, ethnl_string_array_t names,
++		      bool compact);
++int ethnl_bitset32_size(const u32 *val, const u32 *mask, unsigned int nbits,
++			ethnl_string_array_t names, bool compact);
++int ethnl_put_bitset(struct sk_buff *skb, int attrtype,
++		     const unsigned long *val, const unsigned long *mask,
++		     unsigned int nbits, ethnl_string_array_t names,
++		     bool compact);
++int ethnl_put_bitset32(struct sk_buff *skb, int attrtype, const u32 *val,
++		       const u32 *mask, unsigned int nbits,
++		       ethnl_string_array_t names, bool compact);
++int ethnl_update_bitset(unsigned long *bitmap, unsigned int nbits,
++			const struct nlattr *attr, ethnl_string_array_t names,
++			struct netlink_ext_ack *extack, bool *mod);
++int ethnl_update_bitset32(u32 *bitmap, unsigned int nbits,
++			  const struct nlattr *attr, ethnl_string_array_t names,
++			  struct netlink_ext_ack *extack, bool *mod);
++
++#endif /* _NET_ETHTOOL_BITSET_H */
+-- 
+2.34.1
+
diff --git a/patches/0588-ethtool-support-FEC-settings-over-netlink.patch b/patches/0588-ethtool-support-FEC-settings-over-netlink.patch
new file mode 100644
index 0000000..a541643
--- /dev/null
+++ b/patches/0588-ethtool-support-FEC-settings-over-netlink.patch
@@ -0,0 +1,585 @@
+From e67a441d116007df864d97daeccf6966268ba84f Mon Sep 17 00:00:00 2001
+From: Jakub Kicinski <kuba@kernel.org>
+Date: Mon, 29 Mar 2021 20:59:52 -0700
+Subject: [PATCH 227/283] ethtool: support FEC settings over netlink
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit 1e5d1f69d9fb8ea0679f9e85915e8e7fdacfbe7a
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=1e5d1f69d9fb8ea0679f9e85915e8e7fdacfbe7a
+
+--------------------------------
+
+Add FEC API to netlink.
+
+This is not a 1-to-1 conversion.
+
+FEC settings already depend on link modes to tell user which
+modes are supported. Take this further an use link modes for
+manual configuration. Old struct ethtool_fecparam is still
+used to talk to the drivers, so we need to translate back
+and forth. We can revisit the internal API if number of FEC
+encodings starts to grow.
+
+Enforce only one active FEC bit (by using a bit position
+rather than another mask).
+
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	Documentation/networking/ethtool-netlink.rst
+	include/uapi/linux/ethtool_netlink.h
+	net/ethtool/Makefile
+	net/ethtool/netlink.c
+	net/ethtool/netlink.h
+---
+ Documentation/networking/ethtool-netlink.rst |  61 ++++-
+ include/linux/netdevice.h                    |   2 +
+ include/net/genetlink.h                      |   3 +-
+ include/net/netlink.h                        |  11 +
+ include/uapi/linux/ethtool_netlink.h         |  18 ++
+ net/ethtool/Makefile                         |   2 +-
+ net/ethtool/fec.c                            | 238 +++++++++++++++++++
+ net/ethtool/netlink.c                        |  19 ++
+ net/ethtool/netlink.h                        |   4 +
+ 9 files changed, 354 insertions(+), 4 deletions(-)
+ create mode 100644 net/ethtool/fec.c
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+index 83b3ecda4f16..39d038e327e9 100644
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -182,12 +182,16 @@ Userspace to kernel:
+   ===================================== ================================
+   ``ETHTOOL_MSG_RINGS_GET``             get ring sizes
+   ``ETHTOOL_MSG_RINGS_SET``             set ring sizes
++  ``ETHTOOL_MSG_FEC_GET``               get FEC settings
++  ``ETHTOOL_MSG_FEC_SET``               set FEC settings
+   ===================================== ================================
+ 
+ Kernel to userspace:
+ 
+   ===================================== =================================
+   ``ETHTOOL_MSG_RINGS_GET_REPLY``       ring sizes
++  ``ETHTOOL_MSG_FEC_GET_REPLY``         FEC settings
++  ``ETHTOOL_MSG_FEC_NTF``               FEC settings
+   ===================================== =================================
+ 
+ ``GET`` requests are sent by userspace applications to retrieve device
+@@ -293,6 +297,59 @@ Kernel checks that requested ring sizes do not exceed limits reported by
+ driver. Driver may impose additional constraints and may not suspport all
+ attributes.
+ 
++FEC_GET
++=======
++
++Gets FEC configuration and state like ``ETHTOOL_GFECPARAM`` ioctl request.
++
++Request contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_FEC_HEADER``               nested  request header
++  =====================================  ======  ==========================
++
++Kernel response contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_FEC_HEADER``               nested  request header
++  ``ETHTOOL_A_FEC_MODES``                bitset  configured modes
++  ``ETHTOOL_A_FEC_AUTO``                 bool    FEC mode auto selection
++  ``ETHTOOL_A_FEC_ACTIVE``               u32     index of active FEC mode
++  =====================================  ======  ==========================
++
++``ETHTOOL_A_FEC_ACTIVE`` is the bit index of the FEC link mode currently
++active on the interface. This attribute may not be present if device does
++not support FEC.
++
++``ETHTOOL_A_FEC_MODES`` and ``ETHTOOL_A_FEC_AUTO`` are only meaningful when
++autonegotiation is disabled. If ``ETHTOOL_A_FEC_AUTO`` is non-zero driver will
++select the FEC mode automatically based on the parameters of the SFP module.
++This is equivalent to the ``ETHTOOL_FEC_AUTO`` bit of the ioctl interface.
++``ETHTOOL_A_FEC_MODES`` carry the current FEC configuration using link mode
++bits (rather than old ``ETHTOOL_FEC_*`` bits).
++
++FEC_SET
++=======
++
++Sets FEC parameters like ``ETHTOOL_SFECPARAM`` ioctl request.
++
++Request contents:
++
++  =====================================  ======  ==========================
++  ``ETHTOOL_A_FEC_HEADER``               nested  request header
++  ``ETHTOOL_A_FEC_MODES``                bitset  configured modes
++  ``ETHTOOL_A_FEC_AUTO``                 bool    FEC mode auto selection
++  =====================================  ======  ==========================
++
++``FEC_SET`` is only meaningful when autonegotiation is disabled. Otherwise
++FEC mode is selected as part of autonegotiation.
++
++``ETHTOOL_A_FEC_MODES`` selects which FEC mode should be used. It's recommended
++to set only one bit, if multiple bits are set driver may choose between them
++in an implementation specific way.
++
++``ETHTOOL_A_FEC_AUTO`` requests the driver to choose FEC mode based on SFP
++module parameters. This does not mean autonegotiation.
+ 
+ Request translation
+ ===================
+@@ -382,6 +439,6 @@ have their netlink replacement yet.
+   ``ETHTOOL_SLINKSETTINGS``           n/a
+   ``ETHTOOL_PHY_GTUNABLE``            n/a
+   ``ETHTOOL_PHY_STUNABLE``            n/a
+-  ``ETHTOOL_GFECPARAM``               n/a
+-  ``ETHTOOL_SFECPARAM``               n/a
++  ``ETHTOOL_GFECPARAM``               ``ETHTOOL_MSG_FEC_GET``
++  ``ETHTOOL_SFECPARAM``               ``ETHTOOL_MSG_FEC_SET``
+   =================================== =====================================
+diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
+index 5f110d6a0faa..98935a2a887c 100644
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -4401,6 +4401,8 @@ int skb_crc32c_csum_help(struct sk_buff *skb);
+ int skb_csum_hwoffload_help(struct sk_buff *skb,
+ 			    const netdev_features_t features);
+ 
++void ethtool_notify(struct net_device *dev, unsigned int cmd, const void *data);
++
+ struct sk_buff *__skb_gso_segment(struct sk_buff *skb,
+ 				  netdev_features_t features, bool tx_path);
+ struct sk_buff *skb_mac_gso_segment(struct sk_buff *skb,
+diff --git a/include/net/genetlink.h b/include/net/genetlink.h
+index 5aa6238b0de2..a057409a44a5 100644
+--- a/include/net/genetlink.h
++++ b/include/net/genetlink.h
+@@ -141,13 +141,14 @@ static inline int genl_err_attr(struct genl_info *info, int err,
+  * @done: completion callback for dumps
+  */
+ struct genl_ops {
+-	const struct nla_policy	*policy;
+ 	int		       (*doit)(struct sk_buff *skb,
+ 				       struct genl_info *info);
+ 	int		       (*start)(struct netlink_callback *cb);
+ 	int		       (*dumpit)(struct sk_buff *skb,
+ 					 struct netlink_callback *cb);
+ 	int		       (*done)(struct netlink_callback *cb);
++	const struct nla_policy *policy;
++	unsigned int		maxattr;
+ 	u8			cmd;
+ 	u8			internal_flags;
+ 	u8			flags;
+diff --git a/include/net/netlink.h b/include/net/netlink.h
+index 849a0ef9f695..7b7c14128558 100644
+--- a/include/net/netlink.h
++++ b/include/net/netlink.h
+@@ -259,6 +259,11 @@ struct nla_policy {
+ #endif
+ };
+ 
++#define _NLA_POLICY_NESTED(maxattr, policy) \
++	{ .type = NLA_NESTED, .nested_policy = policy, .len = maxattr }
++#define NLA_POLICY_NESTED(policy) \
++	_NLA_POLICY_NESTED(ARRAY_SIZE(policy) - 1, policy)
++
+ #define __NLA_IS_UINT_TYPE(tp)						\
+ 	(tp == NLA_U8 || tp == NLA_U16 || tp == NLA_U32 || tp == NLA_U64)
+ #define __NLA_IS_SINT_TYPE(tp)						\
+@@ -285,6 +290,12 @@ struct nla_policy {
+ 	.min = _min,					\
+ }
+ 
++#define NLA_POLICY_MAX(tp, _max) {			\
++	.type = NLA_ENSURE_INT_OR_BINARY_TYPE(tp),	\
++	.validation_type = NLA_VALIDATE_MAX,		\
++	.max = _max,					\
++}
++
+ /**
+  * struct nl_info - netlink source information
+  * @nlh: Netlink message header of original request
+diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
+index 0c03f091574f..8dffdf192102 100644
+--- a/include/uapi/linux/ethtool_netlink.h
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -30,6 +30,8 @@ enum {
+ 	ETHTOOL_MSG_PRIVFLAGS_SET,
+ 	ETHTOOL_MSG_RINGS_GET,
+ 	ETHTOOL_MSG_RINGS_SET,
++	ETHTOOL_MSG_FEC_GET,
++	ETHTOOL_MSG_FEC_SET,
+ 
+ 	/* add new constants above here */
+ 	__ETHTOOL_MSG_USER_CNT,
+@@ -56,6 +58,9 @@ enum {
+ 	ETHTOOL_MSG_PRIVFLAGS_NTF,
+ 	ETHTOOL_MSG_RINGS_GET_REPLY,
+ 	ETHTOOL_MSG_RINGS_NTF,
++	ETHTOOL_MSG_FEC_GET_REPLY,
++	ETHTOOL_MSG_FEC_NTF,
++
+ 	/* add new constants above here */
+ 	__ETHTOOL_MSG_KERNEL_CNT,
+ 	ETHTOOL_MSG_KERNEL_MAX = __ETHTOOL_MSG_KERNEL_CNT - 1
+@@ -290,6 +295,19 @@ enum {
+ 	ETHTOOL_A_RINGS_MAX = (__ETHTOOL_A_RINGS_CNT - 1)
+ };
+ 
++/* FEC */
++
++enum {
++	ETHTOOL_A_FEC_UNSPEC,
++	ETHTOOL_A_FEC_HEADER,				/* nest - _A_HEADER_* */
++	ETHTOOL_A_FEC_MODES,				/* bitset */
++	ETHTOOL_A_FEC_AUTO,				/* u8 */
++	ETHTOOL_A_FEC_ACTIVE,				/* u32 */
++
++	__ETHTOOL_A_FEC_CNT,
++	ETHTOOL_A_FEC_MAX = (__ETHTOOL_A_FEC_CNT - 1)
++};
++
+ /* generic netlink info */
+ #define ETHTOOL_GENL_NAME "ethtool"
+ #define ETHTOOL_GENL_VERSION 1
+diff --git a/net/ethtool/Makefile b/net/ethtool/Makefile
+index 70e62f840e28..8900e8ff22f8 100644
+--- a/net/ethtool/Makefile
++++ b/net/ethtool/Makefile
+@@ -4,4 +4,4 @@ obj-y				+= ioctl.o common.o
+ 
+ obj-$(CONFIG_ETHTOOL_NETLINK)	+= ethtool_nl.o
+ 
+-ethtool_nl-y	:= netlink.o rings.o linkmodes.o bitset.o
+\ No newline at end of file
++ethtool_nl-y	:= netlink.o rings.o linkmodes.o bitset.o fec.o
+\ No newline at end of file
+diff --git a/net/ethtool/fec.c b/net/ethtool/fec.c
+new file mode 100644
+index 000000000000..31454b9188bd
+--- /dev/null
++++ b/net/ethtool/fec.c
+@@ -0,0 +1,238 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include "netlink.h"
++#include "common.h"
++#include "bitset.h"
++
++struct fec_req_info {
++	struct ethnl_req_info		base;
++};
++
++struct fec_reply_data {
++	struct ethnl_reply_data		base;
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(fec_link_modes);
++	u32 active_fec;
++	u8 fec_auto;
++};
++
++#define FEC_REPDATA(__reply_base) \
++	container_of(__reply_base, struct fec_reply_data, base)
++
++#define ETHTOOL_FEC_MASK	((ETHTOOL_FEC_LLRS << 1) - 1)
++
++const struct nla_policy ethnl_fec_get_policy[ETHTOOL_A_FEC_HEADER + 1] = {
++	[ETHTOOL_A_FEC_HEADER]	= NLA_POLICY_NESTED(ethnl_header_policy),
++};
++
++static void
++ethtool_fec_to_link_modes(u32 fec, unsigned long *link_modes, u8 *fec_auto)
++{
++	if (fec_auto)
++		*fec_auto = !!(fec & ETHTOOL_FEC_AUTO);
++
++	if (fec & ETHTOOL_FEC_OFF)
++		__set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, link_modes);
++	if (fec & ETHTOOL_FEC_RS)
++		__set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, link_modes);
++	if (fec & ETHTOOL_FEC_BASER)
++		__set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, link_modes);
++	if (fec & ETHTOOL_FEC_LLRS)
++		__set_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, link_modes);
++}
++
++static int
++ethtool_link_modes_to_fecparam(struct ethtool_fecparam *fec,
++			       unsigned long *link_modes, u8 fec_auto)
++{
++	memset(fec, 0, sizeof(*fec));
++
++	if (fec_auto)
++		fec->fec |= ETHTOOL_FEC_AUTO;
++
++	if (__test_and_clear_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, link_modes))
++		fec->fec |= ETHTOOL_FEC_OFF;
++	if (__test_and_clear_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, link_modes))
++		fec->fec |= ETHTOOL_FEC_RS;
++	if (__test_and_clear_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, link_modes))
++		fec->fec |= ETHTOOL_FEC_BASER;
++	if (__test_and_clear_bit(ETHTOOL_LINK_MODE_FEC_LLRS_BIT, link_modes))
++		fec->fec |= ETHTOOL_FEC_LLRS;
++
++	if (!bitmap_empty(link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS))
++		return -EINVAL;
++
++	return 0;
++}
++
++static int fec_prepare_data(const struct ethnl_req_info *req_base,
++			    struct ethnl_reply_data *reply_base,
++			    struct genl_info *info)
++{
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(active_fec_modes) = {};
++	struct fec_reply_data *data = FEC_REPDATA(reply_base);
++	struct net_device *dev = reply_base->dev;
++	struct ethtool_fecparam fec = {};
++	int ret;
++
++	if (!dev->ethtool_ops->get_fecparam)
++		return -EOPNOTSUPP;
++	ret = ethnl_ops_begin(dev);
++	if (ret < 0)
++		return ret;
++	ret = dev->ethtool_ops->get_fecparam(dev, &fec);
++	ethnl_ops_complete(dev);
++	if (ret)
++		return ret;
++
++	WARN_ON_ONCE(fec.reserved);
++
++	ethtool_fec_to_link_modes(fec.fec, data->fec_link_modes,
++				  &data->fec_auto);
++
++	ethtool_fec_to_link_modes(fec.active_fec, active_fec_modes, NULL);
++	data->active_fec = find_first_bit(active_fec_modes,
++					  __ETHTOOL_LINK_MODE_MASK_NBITS);
++	/* Don't report attr if no FEC mode set. Note that
++	 * ethtool_fecparam_to_link_modes() ignores NONE and AUTO.
++	 */
++	if (data->active_fec == __ETHTOOL_LINK_MODE_MASK_NBITS)
++		data->active_fec = 0;
++
++	return 0;
++}
++
++static int fec_reply_size(const struct ethnl_req_info *req_base,
++			  const struct ethnl_reply_data *reply_base)
++{
++	bool compact = req_base->flags & ETHTOOL_FLAG_COMPACT_BITSETS;
++	const struct fec_reply_data *data = FEC_REPDATA(reply_base);
++	int len = 0;
++	int ret;
++
++	ret = ethnl_bitset_size(data->fec_link_modes, NULL,
++				__ETHTOOL_LINK_MODE_MASK_NBITS,
++				link_mode_names, compact);
++	if (ret < 0)
++		return ret;
++	len += ret;
++
++	len += nla_total_size(sizeof(u8)) +	/* _FEC_AUTO */
++	       nla_total_size(sizeof(u32));	/* _FEC_ACTIVE */
++
++	return len;
++}
++
++static int fec_fill_reply(struct sk_buff *skb,
++			  const struct ethnl_req_info *req_base,
++			  const struct ethnl_reply_data *reply_base)
++{
++	bool compact = req_base->flags & ETHTOOL_FLAG_COMPACT_BITSETS;
++	const struct fec_reply_data *data = FEC_REPDATA(reply_base);
++	int ret;
++
++	ret = ethnl_put_bitset(skb, ETHTOOL_A_FEC_MODES,
++			       data->fec_link_modes, NULL,
++			       __ETHTOOL_LINK_MODE_MASK_NBITS,
++			       link_mode_names, compact);
++	if (ret < 0)
++		return ret;
++
++	if (nla_put_u8(skb, ETHTOOL_A_FEC_AUTO, data->fec_auto) ||
++	    (data->active_fec &&
++	     nla_put_u32(skb, ETHTOOL_A_FEC_ACTIVE, data->active_fec)))
++		return -EMSGSIZE;
++
++	return 0;
++}
++
++const struct ethnl_request_ops ethnl_fec_request_ops = {
++	.request_cmd		= ETHTOOL_MSG_FEC_GET,
++	.reply_cmd		= ETHTOOL_MSG_FEC_GET_REPLY,
++	.hdr_attr		= ETHTOOL_A_FEC_HEADER,
++	.req_info_size		= sizeof(struct fec_req_info),
++	.reply_data_size	= sizeof(struct fec_reply_data),
++
++	.prepare_data		= fec_prepare_data,
++	.reply_size		= fec_reply_size,
++	.fill_reply		= fec_fill_reply,
++};
++
++/* FEC_SET */
++
++const struct nla_policy ethnl_fec_set_policy[ETHTOOL_A_FEC_AUTO + 1] = {
++	[ETHTOOL_A_FEC_HEADER]	= NLA_POLICY_NESTED(ethnl_header_policy),
++	[ETHTOOL_A_FEC_MODES]	= { .type = NLA_NESTED },
++	[ETHTOOL_A_FEC_AUTO]	= NLA_POLICY_MAX(NLA_U8, 1),
++};
++
++int ethnl_set_fec(struct sk_buff *skb, struct genl_info *info)
++{
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(fec_link_modes) = {};
++	struct ethnl_req_info req_info = {};
++	struct nlattr **tb = info->attrs;
++	struct ethtool_fecparam fec = {};
++	const struct ethtool_ops *ops;
++	struct net_device *dev;
++	bool mod = false;
++	u8 fec_auto;
++	int ret;
++
++	ret = ethnl_parse_header_dev_get(&req_info, tb[ETHTOOL_A_FEC_HEADER],
++					 genl_info_net(info), info->extack,
++					 true);
++	if (ret < 0)
++		return ret;
++	dev = req_info.dev;
++	ops = dev->ethtool_ops;
++	ret = -EOPNOTSUPP;
++	if (!ops->get_fecparam || !ops->set_fecparam)
++		goto out_dev;
++
++	rtnl_lock();
++	ret = ethnl_ops_begin(dev);
++	if (ret < 0)
++		goto out_rtnl;
++	ret = ops->get_fecparam(dev, &fec);
++	if (ret < 0)
++		goto out_ops;
++
++	ethtool_fec_to_link_modes(fec.fec, fec_link_modes, &fec_auto);
++
++	ret = ethnl_update_bitset(fec_link_modes,
++				  __ETHTOOL_LINK_MODE_MASK_NBITS,
++				  tb[ETHTOOL_A_FEC_MODES],
++				  link_mode_names, info->extack, &mod);
++	if (ret < 0)
++		goto out_ops;
++	ethnl_update_u8(&fec_auto, tb[ETHTOOL_A_FEC_AUTO], &mod);
++
++	ret = 0;
++	if (!mod)
++		goto out_ops;
++
++	ret = ethtool_link_modes_to_fecparam(&fec, fec_link_modes, fec_auto);
++	if (ret) {
++		NL_SET_ERR_MSG_ATTR(info->extack, tb[ETHTOOL_A_FEC_MODES],
++				    "invalid FEC modes requested");
++		goto out_ops;
++	}
++	if (!fec.fec) {
++		ret = -EINVAL;
++		NL_SET_ERR_MSG_ATTR(info->extack, tb[ETHTOOL_A_FEC_MODES],
++				    "no FEC modes set");
++		goto out_ops;
++	}
++
++	ret = dev->ethtool_ops->set_fecparam(dev, &fec);
++	if (ret < 0)
++		goto out_ops;
++	ethtool_notify(dev, ETHTOOL_MSG_FEC_NTF, NULL);
++
++out_ops:
++	ethnl_ops_complete(dev);
++out_rtnl:
++	rtnl_unlock();
++out_dev:
++	dev_put(dev);
++	return ret;
++}
+diff --git a/net/ethtool/netlink.c b/net/ethtool/netlink.c
+index d86613309591..0b740fe1cd35 100644
+--- a/net/ethtool/netlink.c
++++ b/net/ethtool/netlink.c
+@@ -288,6 +288,7 @@ struct ethnl_dump_ctx {
+ static const struct ethnl_request_ops *
+ ethnl_default_requests[__ETHTOOL_MSG_USER_CNT] = {
+ 	[ETHTOOL_MSG_RINGS_GET]		= &ethnl_rings_request_ops,
++	[ETHTOOL_MSG_FEC_GET]		= &ethnl_fec_request_ops,
+ };
+ 
+ static struct ethnl_dump_ctx *ethnl_dump_context(struct netlink_callback *cb)
+@@ -599,6 +600,7 @@ static int ethnl_default_done(struct netlink_callback *cb)
+ static const struct ethnl_request_ops *
+ ethnl_default_notify_ops[ETHTOOL_MSG_KERNEL_MAX + 1] = {
+ 	[ETHTOOL_MSG_RINGS_NTF]		= &ethnl_rings_request_ops,
++	[ETHTOOL_MSG_FEC_NTF]		= &ethnl_fec_request_ops,
+ };
+ 
+ /* default notification handler */
+@@ -685,6 +687,7 @@ static const ethnl_notify_handler_t ethnl_notify_handlers[] = {
+ 	[ETHTOOL_MSG_WOL_NTF]		= ethnl_default_notify,
+ 	[ETHTOOL_MSG_FEATURES_NTF]	= ethnl_default_notify,
+ 	[ETHTOOL_MSG_PRIVFLAGS_NTF]	= ethnl_default_notify,
++	[ETHTOOL_MSG_FEC_NTF]		= ethnl_default_notify,
+ };
+ 
+ void ethtool_notify(struct net_device *dev, unsigned int cmd, const void *data)
+@@ -774,6 +777,22 @@ static const struct genl_ops ethtool_genl_ops[] = {
+ 		.flags	= GENL_UNS_ADMIN_PERM,
+ 		.doit	= ethnl_set_rings,
+ 	},
++	{
++		.cmd	= ETHTOOL_MSG_FEC_GET,
++		.doit	= ethnl_default_doit,
++		.start	= ethnl_default_start,
++		.dumpit	= ethnl_default_dumpit,
++		.done	= ethnl_default_done,
++		.policy = ethnl_fec_get_policy,
++		.maxattr = ARRAY_SIZE(ethnl_fec_get_policy) - 1,
++	},
++	{
++		.cmd	= ETHTOOL_MSG_FEC_SET,
++		.flags	= GENL_UNS_ADMIN_PERM,
++		.doit	= ethnl_set_fec,
++		.policy = ethnl_fec_set_policy,
++		.maxattr = ARRAY_SIZE(ethnl_fec_set_policy) - 1,
++	},
+ };
+ 
+ static const struct genl_multicast_group ethtool_nl_mcgrps[] = {
+diff --git a/net/ethtool/netlink.h b/net/ethtool/netlink.h
+index bf71eaf2ace8..17155d446f2d 100644
+--- a/net/ethtool/netlink.h
++++ b/net/ethtool/netlink.h
+@@ -331,6 +331,7 @@ extern const struct ethnl_request_ops ethnl_coalesce_request_ops;
+ extern const struct ethnl_request_ops ethnl_pause_request_ops;
+ extern const struct ethnl_request_ops ethnl_eee_request_ops;
+ extern const struct ethnl_request_ops ethnl_tsinfo_request_ops;
++extern const struct ethnl_request_ops ethnl_fec_request_ops;
+ 
+ extern const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_FLAGS + 1];
+ extern const struct nla_policy ethnl_header_policy_stats[ETHTOOL_A_HEADER_FLAGS + 1];
+@@ -351,6 +352,8 @@ extern const struct nla_policy ethnl_privflags_get_policy[ETHTOOL_A_PRIVFLAGS_HE
+ extern const struct nla_policy ethnl_privflags_set_policy[ETHTOOL_A_PRIVFLAGS_FLAGS + 1];
+ extern const struct nla_policy ethnl_rings_get_policy[ETHTOOL_A_RINGS_HEADER + 1];
+ extern const struct nla_policy ethnl_rings_set_policy[ETHTOOL_A_RINGS_RX_BUF_LEN + 1];
++extern const struct nla_policy ethnl_fec_get_policy[ETHTOOL_A_FEC_HEADER + 1];
++extern const struct nla_policy ethnl_fec_set_policy[ETHTOOL_A_FEC_AUTO + 1];
+ 
+ int ethnl_set_linkinfo(struct sk_buff *skb, struct genl_info *info);
+ int ethnl_set_linkmodes(struct sk_buff *skb, struct genl_info *info);
+@@ -359,5 +362,6 @@ int ethnl_set_wol(struct sk_buff *skb, struct genl_info *info);
+ int ethnl_set_features(struct sk_buff *skb, struct genl_info *info);
+ int ethnl_set_privflags(struct sk_buff *skb, struct genl_info *info);
+ int ethnl_set_rings(struct sk_buff *skb, struct genl_info *info);
++int ethnl_set_fec(struct sk_buff *skb, struct genl_info *info);
+ 
+ #endif /* _NET_ETHTOOL_NETLINK_H */
+-- 
+2.34.1
+
diff --git a/patches/0589-ethtool-fec_prepare_data-jump-to-error-handling.patch b/patches/0589-ethtool-fec_prepare_data-jump-to-error-handling.patch
new file mode 100644
index 0000000..127ea13
--- /dev/null
+++ b/patches/0589-ethtool-fec_prepare_data-jump-to-error-handling.patch
@@ -0,0 +1,60 @@
+From 0b24f8a8b5e8f3fb22b9dd58467eefb0fb641428 Mon Sep 17 00:00:00 2001
+From: Jakub Kicinski <kuba@kernel.org>
+Date: Thu, 15 Apr 2021 15:53:14 -0700
+Subject: [PATCH 228/283] ethtool: fec_prepare_data() - jump to error handling
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit 3d7cc109ecf76afc74f40eb71d5c9baa03c167a3
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=3d7cc109ecf76afc74f40eb71d5c9baa03c167a3
+
+--------------------------------
+
+Refactor fec_prepare_data() a little bit to skip the body
+of the function and exit on error. Currently the code
+depends on the fact that we only have one call which
+may fail between ethnl_ops_begin() and ethnl_ops_complete()
+and simply saves the error code. This will get hairy with
+the stats also being queried.
+
+No functional changes.
+
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ net/ethtool/fec.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/net/ethtool/fec.c b/net/ethtool/fec.c
+index 31454b9188bd..3e7d091ee7aa 100644
+--- a/net/ethtool/fec.c
++++ b/net/ethtool/fec.c
+@@ -80,9 +80,8 @@ static int fec_prepare_data(const struct ethnl_req_info *req_base,
+ 	if (ret < 0)
+ 		return ret;
+ 	ret = dev->ethtool_ops->get_fecparam(dev, &fec);
+-	ethnl_ops_complete(dev);
+ 	if (ret)
+-		return ret;
++		goto out_complete;
+ 
+ 	WARN_ON_ONCE(fec.reserved);
+ 
+@@ -98,7 +97,9 @@ static int fec_prepare_data(const struct ethnl_req_info *req_base,
+ 	if (data->active_fec == __ETHTOOL_LINK_MODE_MASK_NBITS)
+ 		data->active_fec = 0;
+ 
+-	return 0;
++out_complete:
++	ethnl_ops_complete(dev);
++	return ret;
+ }
+ 
+ static int fec_reply_size(const struct ethnl_req_info *req_base,
+-- 
+2.34.1
+
diff --git a/patches/0590-ethtool-add-FEC-statistics.patch b/patches/0590-ethtool-add-FEC-statistics.patch
new file mode 100644
index 0000000..46b12d9
--- /dev/null
+++ b/patches/0590-ethtool-add-FEC-statistics.patch
@@ -0,0 +1,599 @@
+From baec17f8f0b7359c3a9bbd6d2dfaf35f413f5e0b Mon Sep 17 00:00:00 2001
+From: Jakub Kicinski <kuba@kernel.org>
+Date: Thu, 15 Apr 2021 15:53:15 -0700
+Subject: [PATCH 229/283] ethtool: add FEC statistics
+
+mainline inclusion
+from mainline-v5.13-rc1
+commit be85dbfeb37c8c4d4344da2ee594d78034b82489
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=be85dbfeb37c8c4d4344da2ee594d78034b82489
+
+--------------------------------
+
+Similarly to pause statistics add stats for FEC.
+
+The IEEE standard mandates two sets of counters:
+ - 30.5.1.1.17 aFECCorrectedBlocks
+ - 30.5.1.1.18 aFECUncorrectableBlocks
+where block is a block of bits FEC operates on.
+Each of these counters is defined per lane (PCS instance).
+
+Multiple vendors provide number of corrected _bits_ rather
+than/as well as blocks.
+
+This set adds the 2 standard-based block counters and a extra
+one for corrected bits.
+
+Counters are exposed to user space via netlink in new attributes.
+Each attribute carries an array of u64s, first element is
+the total count, and the following ones are a per-lane break down.
+
+Much like with pause stats the operation will not fail when driver
+does not implement the get_fec_stats callback (nor can the driver
+fail the operation by returning an error). If stats can't be
+reported the relevant attributes will be empty.
+
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	Documentation/networking/statistics.rst
+	include/linux/ethtool.h
+	include/uapi/linux/ethtool_netlink.h
+---
+ Documentation/networking/ethtool-netlink.rst |  21 +++
+ Documentation/networking/statistics.rst      | 180 +++++++++++++++++++
+ include/linux/ethtool.h                      |  72 ++++++--
+ include/net/netlink.h                        |   9 +-
+ include/uapi/linux/ethtool_netlink.h         |  15 ++
+ net/ethtool/fec.c                            |  73 +++++++-
+ net/ethtool/netlink.c                        |  12 ++
+ 7 files changed, 367 insertions(+), 15 deletions(-)
+ create mode 100644 Documentation/networking/statistics.rst
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+index 39d038e327e9..01da978de86d 100644
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -315,6 +315,7 @@ Kernel response contents:
+   ``ETHTOOL_A_FEC_MODES``                bitset  configured modes
+   ``ETHTOOL_A_FEC_AUTO``                 bool    FEC mode auto selection
+   ``ETHTOOL_A_FEC_ACTIVE``               u32     index of active FEC mode
++  ``ETHTOOL_A_FEC_STATS``                nested  FEC statistics
+   =====================================  ======  ==========================
+ 
+ ``ETHTOOL_A_FEC_ACTIVE`` is the bit index of the FEC link mode currently
+@@ -328,6 +329,26 @@ This is equivalent to the ``ETHTOOL_FEC_AUTO`` bit of the ioctl interface.
+ ``ETHTOOL_A_FEC_MODES`` carry the current FEC configuration using link mode
+ bits (rather than old ``ETHTOOL_FEC_*`` bits).
+ 
++``ETHTOOL_A_FEC_STATS`` are reported if ``ETHTOOL_FLAG_STATS`` was set in
++``ETHTOOL_A_HEADER_FLAGS``.
++Each attribute carries an array of 64bit statistics. First entry in the array
++contains the total number of events on the port, while the following entries
++are counters corresponding to lanes/PCS instances. The number of entries in
++the array will be:
++
+++--------------+---------------------------------------------+
++| `0`          | device does not support FEC statistics      |
+++--------------+---------------------------------------------+
++| `1`          | device does not support per-lane break down |
+++--------------+---------------------------------------------+
++| `1 + #lanes` | device has full support for FEC stats       |
+++--------------+---------------------------------------------+
++
++Drivers fill in the statistics in the following structure:
++
++.. kernel-doc:: include/linux/ethtool.h
++    :identifiers: ethtool_fec_stats
++
+ FEC_SET
+ =======
+ 
+diff --git a/Documentation/networking/statistics.rst b/Documentation/networking/statistics.rst
+new file mode 100644
+index 000000000000..b748fe44ee02
+--- /dev/null
++++ b/Documentation/networking/statistics.rst
+@@ -0,0 +1,180 @@
++.. SPDX-License-Identifier: GPL-2.0
++
++====================
++Interface statistics
++====================
++
++Overview
++========
++
++This document is a guide to Linux network interface statistics.
++
++There are three main sources of interface statistics in Linux:
++
++ - standard interface statistics based on
++   :c:type:`struct rtnl_link_stats64 <rtnl_link_stats64>`;
++ - protocol-specific statistics; and
++ - driver-defined statistics available via ethtool.
++
++Standard interface statistics
++-----------------------------
++
++There are multiple interfaces to reach the standard statistics.
++Most commonly used is the `ip` command from `iproute2`::
++
++  $ ip -s -s link show dev ens4u1u1
++  6: ens4u1u1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc fq_codel state UP mode DEFAULT group default qlen 1000
++    link/ether 48:2a:e3:4c:b1:d1 brd ff:ff:ff:ff:ff:ff
++    RX: bytes  packets  errors  dropped overrun mcast
++    74327665117 69016965 0       0       0       0
++    RX errors: length   crc     frame   fifo    missed
++               0        0       0       0       0
++    TX: bytes  packets  errors  dropped carrier collsns
++    21405556176 44608960 0       0       0       0
++    TX errors: aborted  fifo   window heartbeat transns
++               0        0       0       0       128
++    altname enp58s0u1u1
++
++Note that `-s` has been specified twice to see all members of
++:c:type:`struct rtnl_link_stats64 <rtnl_link_stats64>`.
++If `-s` is specified once the detailed errors won't be shown.
++
++`ip` supports JSON formatting via the `-j` option.
++
++Protocol-specific statistics
++----------------------------
++
++Some of the interfaces used for configuring devices are also able
++to report related statistics. For example ethtool interface used
++to configure pause frames can report corresponding hardware counters::
++
++  $ ethtool --include-statistics -a eth0
++  Pause parameters for eth0:
++  Autonegotiate:	on
++  RX:			on
++  TX:			on
++  Statistics:
++    tx_pause_frames: 1
++    rx_pause_frames: 1
++
++Driver-defined statistics
++-------------------------
++
++Driver-defined ethtool statistics can be dumped using `ethtool -S $ifc`, e.g.::
++
++  $ ethtool -S ens4u1u1
++  NIC statistics:
++     tx_single_collisions: 0
++     tx_multi_collisions: 0
++
++uAPIs
++=====
++
++procfs
++------
++
++The historical `/proc/net/dev` text interface gives access to the list
++of interfaces as well as their statistics.
++
++Note that even though this interface is using
++:c:type:`struct rtnl_link_stats64 <rtnl_link_stats64>`
++internally it combines some of the fields.
++
++sysfs
++-----
++
++Each device directory in sysfs contains a `statistics` directory (e.g.
++`/sys/class/net/lo/statistics/`) with files corresponding to
++members of :c:type:`struct rtnl_link_stats64 <rtnl_link_stats64>`.
++
++This simple interface is convenient especially in constrained/embedded
++environments without access to tools. However, it's inefficient when
++reading multiple stats as it internally performs a full dump of
++:c:type:`struct rtnl_link_stats64 <rtnl_link_stats64>`
++and reports only the stat corresponding to the accessed file.
++
++Sysfs files are documented in
++`Documentation/ABI/testing/sysfs-class-net-statistics`.
++
++
++netlink
++-------
++
++`rtnetlink` (`NETLINK_ROUTE`) is the preferred method of accessing
++:c:type:`struct rtnl_link_stats64 <rtnl_link_stats64>` stats.
++
++Statistics are reported both in the responses to link information
++requests (`RTM_GETLINK`) and statistic requests (`RTM_GETSTATS`,
++when `IFLA_STATS_LINK_64` bit is set in the `.filter_mask` of the request).
++
++ethtool
++-------
++
++Ethtool IOCTL interface allows drivers to report implementation
++specific statistics. Historically it has also been used to report
++statistics for which other APIs did not exist, like per-device-queue
++statistics, or standard-based statistics (e.g. RFC 2863).
++
++Statistics and their string identifiers are retrieved separately.
++Identifiers via `ETHTOOL_GSTRINGS` with `string_set` set to `ETH_SS_STATS`,
++and values via `ETHTOOL_GSTATS`. User space should use `ETHTOOL_GDRVINFO`
++to retrieve the number of statistics (`.n_stats`).
++
++ethtool-netlink
++---------------
++
++Ethtool netlink is a replacement for the older IOCTL interface.
++
++Protocol-related statistics can be requested in get commands by setting
++the `ETHTOOL_FLAG_STATS` flag in `ETHTOOL_A_HEADER_FLAGS`. Currently
++statistics are supported in the following commands:
++
++  - `ETHTOOL_MSG_PAUSE_GET`
++  - `ETHTOOL_MSG_FEC_GET`
++
++debugfs
++-------
++
++Some drivers expose extra statistics via `debugfs`.
++
++struct rtnl_link_stats64
++========================
++
++.. kernel-doc:: include/uapi/linux/if_link.h
++    :identifiers: rtnl_link_stats64
++
++Notes for driver authors
++========================
++
++Drivers should report all statistics which have a matching member in
++:c:type:`struct rtnl_link_stats64 <rtnl_link_stats64>` exclusively
++via `.ndo_get_stats64`. Reporting such standard stats via ethtool
++or debugfs will not be accepted.
++
++Drivers must ensure best possible compliance with
++:c:type:`struct rtnl_link_stats64 <rtnl_link_stats64>`.
++Please note for example that detailed error statistics must be
++added into the general `rx_error` / `tx_error` counters.
++
++The `.ndo_get_stats64` callback can not sleep because of accesses
++via `/proc/net/dev`. If driver may sleep when retrieving the statistics
++from the device it should do so periodically asynchronously and only return
++a recent copy from `.ndo_get_stats64`. Ethtool interrupt coalescing interface
++allows setting the frequency of refreshing statistics, if needed.
++
++Retrieving ethtool statistics is a multi-syscall process, drivers are advised
++to keep the number of statistics constant to avoid race conditions with
++user space trying to read them.
++
++Statistics must persist across routine operations like bringing the interface
++down and up.
++
++Kernel-internal data structures
++-------------------------------
++
++The following structures are internal to the kernel, their members are
++translated to netlink attributes when dumped. Drivers must not overwrite
++the statistics they don't report with 0.
++
++- ethtool_pause_stats()
++- ethtool_fec_stats()
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 1b0afcdaf34e..e9b7695a4c0e 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -249,6 +249,48 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+ 	ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ)
+ #define ETHTOOL_COALESCE_USE_ADAPTIVE					\
+ 	(ETHTOOL_COALESCE_USE_ADAPTIVE_RX | ETHTOOL_COALESCE_USE_ADAPTIVE_TX)
++
++#define ETHTOOL_STAT_NOT_SET	(~0ULL)
++
++static inline void ethtool_stats_init(u64 *stats, unsigned int n)
++{
++	while (n--)
++		stats[n] = ETHTOOL_STAT_NOT_SET;
++}
++
++#define ETHTOOL_MAX_LANES	8
++
++/**
++ * struct ethtool_fec_stats - statistics for IEEE 802.3 FEC
++ * @corrected_blocks: number of received blocks corrected by FEC
++ *	Reported to user space as %ETHTOOL_A_FEC_STAT_CORRECTED.
++ *
++ *	Equivalent to `30.5.1.1.17 aFECCorrectedBlocks` from the standard.
++ *
++ * @uncorrectable_blocks: number of received blocks FEC was not able to correct
++ *	Reported to user space as %ETHTOOL_A_FEC_STAT_UNCORR.
++ *
++ *	Equivalent to `30.5.1.1.18 aFECUncorrectableBlocks` from the standard.
++ *
++ * @corrected_bits: number of bits corrected by FEC
++ *	Similar to @corrected_blocks but counts individual bit changes,
++ *	not entire FEC data blocks. This is a non-standard statistic.
++ *	Reported to user space as %ETHTOOL_A_FEC_STAT_CORR_BITS.
++ *
++ * @lane: per-lane/PCS-instance counts as defined by the standard
++ * @total: error counts for the entire port, for drivers incapable of reporting
++ *	per-lane stats
++ *
++ * Drivers should fill in either only total or per-lane statistics, core
++ * will take care of adding lane values up to produce the total.
++ */
++struct ethtool_fec_stats {
++	struct ethtool_fec_stat {
++		u64 total;
++		u64 lanes[ETHTOOL_MAX_LANES];
++	} corrected_blocks, uncorrectable_blocks, corrected_bits;
++};
++
+ /**
+  * struct ethtool_ops - optional netdev operations
+  * @cap_link_lanes_supported: indicates if the driver supports lanes
+@@ -363,19 +405,21 @@ bool ethtool_convert_link_mode_to_legacy_u32(u32 *legacy_u32,
+  *	a TX queue has this number, return -EINVAL. If only a RX queue or a TX
+  *	queue has this number, ignore the inapplicable fields.
+  *	Returns a negative error code or zero.
+- * @get_link_ksettings: When defined, takes precedence over the
+- *	%get_settings method. Get various device settings
+- *	including Ethernet link settings. The %cmd and
+- *	%link_mode_masks_nwords fields should be ignored (use
+- *	%__ETHTOOL_LINK_MODE_MASK_NBITS instead of the latter), any
+- *	change to them will be overwritten by kernel. Returns a
+- *	negative error code or zero.
+- * @set_link_ksettings: When defined, takes precedence over the
+- *	%set_settings method. Set various device settings including
+- *	Ethernet link settings. The %cmd and %link_mode_masks_nwords
+- *	fields should be ignored (use %__ETHTOOL_LINK_MODE_MASK_NBITS
+- *	instead of the latter), any change to them will be overwritten
+- *	by kernel. Returns a negative error code or zero.
++ * @get_link_ksettings: Get various device settings including Ethernet link
++ *	settings. The %cmd and %link_mode_masks_nwords fields should be
++ *	ignored (use %__ETHTOOL_LINK_MODE_MASK_NBITS instead of the latter),
++ *	any change to them will be overwritten by kernel. Returns a negative
++ *	error code or zero.
++ * @set_link_ksettings: Set various device settings including Ethernet link
++ *	settings. The %cmd and %link_mode_masks_nwords fields should be
++ *	ignored (use %__ETHTOOL_LINK_MODE_MASK_NBITS instead of the latter),
++ *	any change to them will be overwritten by kernel. Returns a negative
++ *	error code or zero.
++ * @get_fec_stats: Report FEC statistics.
++ *	Core will sum up per-lane stats to get the total.
++ *	Drivers must not zero statistics which they don't report. The stats
++ *	structure is initialized to ETHTOOL_STAT_NOT_SET indicating driver does
++ *	not report statistics.
+  * @get_fecparam: Get the network device Forward Error Correction parameters.
+  * @set_fecparam: Set the network device Forward Error Correction parameters.
+  * @get_ethtool_phy_stats: Return extended statistics about the PHY device.
+@@ -481,6 +525,8 @@ struct ethtool_ops {
+ 				      struct ethtool_link_ksettings *);
+ 	int	(*set_link_ksettings)(struct net_device *,
+ 				      const struct ethtool_link_ksettings *);
++	void	(*get_fec_stats)(struct net_device *dev,
++				 struct ethtool_fec_stats *fec_stats);
+ 	int	(*get_fecparam)(struct net_device *,
+ 				      struct ethtool_fecparam *);
+ 	int	(*set_fecparam)(struct net_device *,
+diff --git a/include/net/netlink.h b/include/net/netlink.h
+index 7b7c14128558..e91076f81d3e 100644
+--- a/include/net/netlink.h
++++ b/include/net/netlink.h
+@@ -270,7 +270,8 @@ struct nla_policy {
+ 	(tp == NLA_S8 || tp == NLA_S16 || tp == NLA_S32 || tp == NLA_S64)
+ 
+ #define __NLA_ENSURE(condition) BUILD_BUG_ON_ZERO(!(condition))
+-
++#define NLA_ENSURE_UINT_TYPE(tp)			\
++	(__NLA_ENSURE(__NLA_IS_UINT_TYPE(tp)) + tp)
+ #define NLA_ENSURE_INT_OR_BINARY_TYPE(tp)		\
+ 	(__NLA_ENSURE(__NLA_IS_UINT_TYPE(tp) ||		\
+ 		      __NLA_IS_SINT_TYPE(tp) ||		\
+@@ -296,6 +297,12 @@ struct nla_policy {
+ 	.max = _max,					\
+ }
+ 
++#define NLA_POLICY_MASK(tp, _mask) {			\
++	.type = NLA_ENSURE_UINT_TYPE(tp),		\
++	.validation_type = NLA_VALIDATE_MASK,		\
++	.mask = _mask,					\
++}
++
+ /**
+  * struct nl_info - netlink source information
+  * @nlh: Netlink message header of original request
+diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
+index 8dffdf192102..3b7ed0fe545a 100644
+--- a/include/uapi/linux/ethtool_netlink.h
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -72,6 +72,7 @@ enum {
+ #define ETHTOOL_FLAG_COMPACT_BITSETS	(1 << 0)
+ /* provide optional reply for SET or ACT requests */
+ #define ETHTOOL_FLAG_OMIT_REPLY	(1 << 1)
++#define ETHTOOL_FLAG_STATS		(1 << 2)
+ 
+ #define ETHTOOL_FLAG_ALL (ETHTOOL_FLAG_COMPACT_BITSETS | \
+ 			  ETHTOOL_FLAG_OMIT_REPLY)
+@@ -303,11 +304,25 @@ enum {
+ 	ETHTOOL_A_FEC_MODES,				/* bitset */
+ 	ETHTOOL_A_FEC_AUTO,				/* u8 */
+ 	ETHTOOL_A_FEC_ACTIVE,				/* u32 */
++	ETHTOOL_A_FEC_STATS,				/* nest - _A_FEC_STAT */
+ 
+ 	__ETHTOOL_A_FEC_CNT,
+ 	ETHTOOL_A_FEC_MAX = (__ETHTOOL_A_FEC_CNT - 1)
+ };
+ 
++enum {
++	ETHTOOL_A_FEC_STAT_UNSPEC,
++	ETHTOOL_A_FEC_STAT_PAD,
++
++	ETHTOOL_A_FEC_STAT_CORRECTED,			/* array, u64 */
++	ETHTOOL_A_FEC_STAT_UNCORR,			/* array, u64 */
++	ETHTOOL_A_FEC_STAT_CORR_BITS,			/* array, u64 */
++
++	/* add new constants above here */
++	__ETHTOOL_A_FEC_STAT_CNT,
++	ETHTOOL_A_FEC_STAT_MAX = (__ETHTOOL_A_FEC_STAT_CNT - 1)
++};
++
+ /* generic netlink info */
+ #define ETHTOOL_GENL_NAME "ethtool"
+ #define ETHTOOL_GENL_VERSION 1
+diff --git a/net/ethtool/fec.c b/net/ethtool/fec.c
+index 3e7d091ee7aa..8738dafd5417 100644
+--- a/net/ethtool/fec.c
++++ b/net/ethtool/fec.c
+@@ -13,6 +13,10 @@ struct fec_reply_data {
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(fec_link_modes);
+ 	u32 active_fec;
+ 	u8 fec_auto;
++	struct fec_stat_grp {
++		u64 stats[1 + ETHTOOL_MAX_LANES];
++		u8 cnt;
++	} corr, uncorr, corr_bits;
+ };
+ 
+ #define FEC_REPDATA(__reply_base) \
+@@ -21,7 +25,7 @@ struct fec_reply_data {
+ #define ETHTOOL_FEC_MASK	((ETHTOOL_FEC_LLRS << 1) - 1)
+ 
+ const struct nla_policy ethnl_fec_get_policy[ETHTOOL_A_FEC_HEADER + 1] = {
+-	[ETHTOOL_A_FEC_HEADER]	= NLA_POLICY_NESTED(ethnl_header_policy),
++	[ETHTOOL_A_FEC_HEADER]	= NLA_POLICY_NESTED(ethnl_header_policy_stats),
+ };
+ 
+ static void
+@@ -64,6 +68,28 @@ ethtool_link_modes_to_fecparam(struct ethtool_fecparam *fec,
+ 	return 0;
+ }
+ 
++static void
++fec_stats_recalc(struct fec_stat_grp *grp, struct ethtool_fec_stat *stats)
++{
++	int i;
++
++	if (stats->lanes[0] == ETHTOOL_STAT_NOT_SET) {
++		grp->stats[0] = stats->total;
++		grp->cnt = stats->total != ETHTOOL_STAT_NOT_SET;
++		return;
++	}
++
++	grp->cnt = 1;
++	grp->stats[0] = 0;
++	for (i = 0; i < ETHTOOL_MAX_LANES; i++) {
++		if (stats->lanes[i] == ETHTOOL_STAT_NOT_SET)
++			break;
++
++		grp->stats[0] += stats->lanes[i];
++		grp->stats[grp->cnt++] = stats->lanes[i];
++	}
++}
++
+ static int fec_prepare_data(const struct ethnl_req_info *req_base,
+ 			    struct ethnl_reply_data *reply_base,
+ 			    struct genl_info *info)
+@@ -82,6 +108,17 @@ static int fec_prepare_data(const struct ethnl_req_info *req_base,
+ 	ret = dev->ethtool_ops->get_fecparam(dev, &fec);
+ 	if (ret)
+ 		goto out_complete;
++	if (req_base->flags & ETHTOOL_FLAG_STATS &&
++	    dev->ethtool_ops->get_fec_stats) {
++		struct ethtool_fec_stats stats;
++
++		ethtool_stats_init((u64 *)&stats, sizeof(stats) / 8);
++		dev->ethtool_ops->get_fec_stats(dev, &stats);
++
++		fec_stats_recalc(&data->corr, &stats.corrected_blocks);
++		fec_stats_recalc(&data->uncorr, &stats.uncorrectable_blocks);
++		fec_stats_recalc(&data->corr_bits, &stats.corrected_bits);
++	}
+ 
+ 	WARN_ON_ONCE(fec.reserved);
+ 
+@@ -120,9 +157,40 @@ static int fec_reply_size(const struct ethnl_req_info *req_base,
+ 	len += nla_total_size(sizeof(u8)) +	/* _FEC_AUTO */
+ 	       nla_total_size(sizeof(u32));	/* _FEC_ACTIVE */
+ 
++	if (req_base->flags & ETHTOOL_FLAG_STATS)
++		len += 3 * nla_total_size_64bit(sizeof(u64) *
++						(1 + ETHTOOL_MAX_LANES));
++
+ 	return len;
+ }
+ 
++static int fec_put_stats(struct sk_buff *skb, const struct fec_reply_data *data)
++{
++	struct nlattr *nest;
++
++	nest = nla_nest_start(skb, ETHTOOL_A_FEC_STATS);
++	if (!nest)
++		return -EMSGSIZE;
++
++	if (nla_put_64bit(skb, ETHTOOL_A_FEC_STAT_CORRECTED,
++			  sizeof(u64) * data->corr.cnt,
++			  data->corr.stats, ETHTOOL_A_FEC_STAT_PAD) ||
++	    nla_put_64bit(skb, ETHTOOL_A_FEC_STAT_UNCORR,
++			  sizeof(u64) * data->uncorr.cnt,
++			  data->uncorr.stats, ETHTOOL_A_FEC_STAT_PAD) ||
++	    nla_put_64bit(skb, ETHTOOL_A_FEC_STAT_CORR_BITS,
++			  sizeof(u64) * data->corr_bits.cnt,
++			  data->corr_bits.stats, ETHTOOL_A_FEC_STAT_PAD))
++		goto err_cancel;
++
++	nla_nest_end(skb, nest);
++	return 0;
++
++err_cancel:
++	nla_nest_cancel(skb, nest);
++	return -EMSGSIZE;
++}
++
+ static int fec_fill_reply(struct sk_buff *skb,
+ 			  const struct ethnl_req_info *req_base,
+ 			  const struct ethnl_reply_data *reply_base)
+@@ -143,6 +211,9 @@ static int fec_fill_reply(struct sk_buff *skb,
+ 	     nla_put_u32(skb, ETHTOOL_A_FEC_ACTIVE, data->active_fec)))
+ 		return -EMSGSIZE;
+ 
++	if (req_base->flags & ETHTOOL_FLAG_STATS && fec_put_stats(skb, data))
++		return -EMSGSIZE;
++
+ 	return 0;
+ }
+ 
+diff --git a/net/ethtool/netlink.c b/net/ethtool/netlink.c
+index 0b740fe1cd35..1fdf23c0a6ec 100644
+--- a/net/ethtool/netlink.c
++++ b/net/ethtool/netlink.c
+@@ -9,6 +9,10 @@ static struct genl_family ethtool_genl_family;
+ static bool ethnl_ok __read_mostly;
+ static u32 ethnl_bcast_seq;
+ 
++#define ETHTOOL_FLAGS_BASIC (ETHTOOL_FLAG_COMPACT_BITSETS |	\
++			     ETHTOOL_FLAG_OMIT_REPLY)
++#define ETHTOOL_FLAGS_STATS (ETHTOOL_FLAGS_BASIC | ETHTOOL_FLAG_STATS)
++
+ const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_MAX + 1] = {
+ 	[ETHTOOL_A_HEADER_UNSPEC]	= { .type = NLA_REJECT },
+ 	[ETHTOOL_A_HEADER_DEV_INDEX]	= { .type = NLA_U32 },
+@@ -17,6 +21,14 @@ const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_MAX + 1] = {
+ 	[ETHTOOL_A_HEADER_FLAGS]	= { .type = NLA_U32 },
+ };
+ 
++const struct nla_policy ethnl_header_policy_stats[] = {
++	[ETHTOOL_A_HEADER_DEV_INDEX]	= { .type = NLA_U32 },
++	[ETHTOOL_A_HEADER_DEV_NAME]	= { .type = NLA_NUL_STRING,
++					    .len = ALTIFNAMSIZ - 1 },
++	[ETHTOOL_A_HEADER_FLAGS]	= NLA_POLICY_MASK(NLA_U32,
++							  ETHTOOL_FLAGS_STATS),
++};
++
+ /**
+  * ethnl_parse_header_dev_get() - parse request header
+  * @req_info:    structure to put results into
+-- 
+2.34.1
+
diff --git a/patches/0591-net-hns3-add-querying-fec-statistics.patch b/patches/0591-net-hns3-add-querying-fec-statistics.patch
new file mode 100644
index 0000000..27918a9
--- /dev/null
+++ b/patches/0591-net-hns3-add-querying-fec-statistics.patch
@@ -0,0 +1,370 @@
+From 3c5d13af11f1365abb755a87e71edad5ee38f9d7 Mon Sep 17 00:00:00 2001
+From: Hao Lan <lanhao@huawei.com>
+Date: Tue, 6 Sep 2022 17:12:22 +0800
+Subject: [PATCH 230/283] net: hns3: add querying fec statistics
+
+mainline inclusion
+from mainline-v6.1-rc1
+commit 2cb343b9d3e59db0836045ff1dd67dfd15066697
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2cb343b9d3e59db0836045ff1dd67dfd15066697
+
+--------------------------------
+
+FEC statistics can be used to check the transmission quality of links.
+This patch implements the get_fec_stats callback of ethtool_ops to support
+querying FEC statistics by command "ethtool -I --show-fec eth0".
+
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |   4 +
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  14 ++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  15 ++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 156 ++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  22 +++
+ 5 files changed, 211 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 31a593966a42..903a942bc851 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -182,6 +182,8 @@ enum HNAE3_DEV_CAP_BITS {
+ 
+ #define hnae3_ae_dev_lane_num_supported(ae_dev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)
++#define hnae3_ae_dev_fec_stats_supported(ae_dev) \
++	test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps)
+ 
+ enum HNAE3_PF_CAP_BITS {
+ 	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
+@@ -619,6 +621,8 @@ struct hnae3_ae_ops {
+ 	void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
+ 			       u8 *module_type);
+ 	int (*check_port_speed)(struct hnae3_handle *handle, u32 speed);
++	void (*get_fec_stats)(struct hnae3_handle *handle,
++			      struct ethtool_fec_stats *fec_stats);
+ 	void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability,
+ 			u8 *fec_mode);
+ 	int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index ece3e95e80d6..2a6de6297446 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1578,6 +1578,19 @@ static void hns3_set_msglevel(struct net_device *netdev, u32 msg_level)
+ 	h->msg_enable = msg_level;
+ }
+ 
++static void hns3_get_fec_stats(struct net_device *netdev,
++			       struct ethtool_fec_stats *fec_stats)
++{
++	struct hnae3_handle *handle = hns3_get_handle(netdev);
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
++	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
++
++	if (!hnae3_ae_dev_fec_stats_supported(ae_dev) || !ops->get_fec_stats)
++		return;
++
++	ops->get_fec_stats(handle, fec_stats);
++}
++
+ /* Translate local fec value into ethtool value. */
+ static unsigned int loc_to_eth_fec(u8 loc_fec)
+ {
+@@ -2065,6 +2078,7 @@ static const struct ethtool_ops hns3_ethtool_ops = {
+ 	.set_msglevel = hns3_set_msglevel,
+ 	.get_fecparam = hns3_get_fecparam,
+ 	.set_fecparam = hns3_set_fecparam,
++	.get_fec_stats = hns3_get_fec_stats,
+ 	.get_module_info = hns3_get_module_info,
+ 	.get_module_eeprom = hns3_get_module_eeprom,
+ 	.get_priv_flags = hns3_get_priv_flags,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 296facdda4c9..ef1b6d90bd75 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -122,6 +122,7 @@ enum hclge_opcode_type {
+ 	HCLGE_OPC_MAC_TNL_INT_EN	= 0x0311,
+ 	HCLGE_OPC_CLEAR_MAC_TNL_INT	= 0x0312,
+ 	HCLGE_OPC_COMMON_LOOPBACK       = 0x0315,
++	HCLGE_OPC_QUERY_FEC_STATS       = 0x0316,
+ 	HCLGE_OPC_CONFIG_FEC_MODE	= 0x031A,
+ 	/* check sum command */
+ 	HCLGE_OPC_CFG_CHECKSUM_EN       = 0x0601,
+@@ -727,6 +728,20 @@ struct hclge_config_fec_cmd {
+ 	u8 rsv[22];
+ };
+ 
++#define HCLGE_FEC_STATS_CMD_NUM 4
++
++struct hclge_query_fec_stats_cmd {
++	/* fec rs mode total stats */
++	__le32 rs_fec_corr_blocks;
++	__le32 rs_fec_uncorr_blocks;
++	__le32 rs_fec_error_blocks;
++	/* fec base-r mode per lanes stats */
++	u8 base_r_lane_num;
++	u8 rsv[3];
++	__le32 base_r_fec_corr_blocks;
++	__le32 base_r_fec_uncorr_blocks;
++};
++
+ #define HCLGE_MAC_UPLINK_PORT		0x100
+ 
+ struct hclge_config_max_frm_size_cmd {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 5cb599ca53ea..ecc792a57c23 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -72,6 +72,7 @@ static void hclge_sync_mac_table(struct hclge_dev *hdev);
+ static void hclge_restore_hw_table(struct hclge_dev *hdev);
+ static void hclge_sync_promisc_mode(struct hclge_dev *hdev);
+ static void hclge_reset_end(struct hnae3_handle *handle, bool done);
++static void hclge_update_fec_stats(struct hclge_dev *hdev);
+ 
+ static struct hnae3_ae_algo ae_algo;
+ 
+@@ -777,6 +778,8 @@ static void hclge_update_stats_for_all(struct hclge_dev *hdev)
+ 		}
+ 	}
+ 
++	hclge_update_fec_stats(hdev);
++
+ 	status = hclge_mac_update_stats(hdev);
+ 	if (status)
+ 		dev_err(&hdev->pdev->dev,
+@@ -2834,6 +2837,157 @@ static int hclge_halt_autoneg(struct hnae3_handle *handle, bool halt)
+ 	return 0;
+ }
+ 
++static void hclge_parse_fec_stats_lanes(struct hclge_dev *hdev,
++					struct hclge_desc *desc, u32 desc_len)
++{
++	u32 lane_size = HCLGE_FEC_STATS_MAX_LANES * 2;
++	u32 desc_index = 0;
++	u32 data_index = 0;
++	u32 i;
++
++	for (i = 0; i < lane_size; i++) {
++		if (data_index >= HCLGE_DESC_DATA_LEN) {
++			desc_index++;
++			data_index = 0;
++		}
++
++		if (desc_index >= desc_len)
++			return;
++
++		hdev->fec_stats.per_lanes[i] +=
++			le32_to_cpu(desc[desc_index].data[data_index]);
++		data_index++;
++	}
++}
++
++static void hclge_parse_fec_stats(struct hclge_dev *hdev,
++				  struct hclge_desc *desc, u32 desc_len)
++{
++	struct hclge_query_fec_stats_cmd *req;
++
++	req = (struct hclge_query_fec_stats_cmd *)desc[0].data;
++
++	hdev->fec_stats.base_r_lane_num = req->base_r_lane_num;
++	hdev->fec_stats.rs_corr_blocks +=
++		le32_to_cpu(req->rs_fec_corr_blocks);
++	hdev->fec_stats.rs_uncorr_blocks +=
++		le32_to_cpu(req->rs_fec_uncorr_blocks);
++	hdev->fec_stats.rs_error_blocks +=
++		le32_to_cpu(req->rs_fec_error_blocks);
++	hdev->fec_stats.base_r_corr_blocks +=
++		le32_to_cpu(req->base_r_fec_corr_blocks);
++	hdev->fec_stats.base_r_uncorr_blocks +=
++		le32_to_cpu(req->base_r_fec_uncorr_blocks);
++
++	hclge_parse_fec_stats_lanes(hdev, &desc[1], desc_len - 1);
++}
++
++static int hclge_update_fec_stats_hw(struct hclge_dev *hdev)
++{
++	struct hclge_desc desc[HCLGE_FEC_STATS_CMD_NUM];
++	int ret;
++	u32 i;
++
++	for (i = 0; i < HCLGE_FEC_STATS_CMD_NUM; i++) {
++		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_FEC_STATS,
++					   true);
++		if (i != (HCLGE_FEC_STATS_CMD_NUM - 1))
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
++	}
++
++	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_FEC_STATS_CMD_NUM);
++	if (ret)
++		return ret;
++
++	hclge_parse_fec_stats(hdev, desc, HCLGE_FEC_STATS_CMD_NUM);
++
++	return 0;
++}
++
++static void hclge_update_fec_stats(struct hclge_dev *hdev)
++{
++	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	int ret;
++
++	if (!hnae3_ae_dev_fec_stats_supported(ae_dev) ||
++	    test_and_set_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state))
++		return;
++
++	ret = hclge_update_fec_stats_hw(hdev);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to update fec stats, ret = %d\n", ret);
++
++	clear_bit(HCLGE_STATE_FEC_STATS_UPDATING, &hdev->state);
++}
++
++static void hclge_get_fec_stats_total(struct hclge_dev *hdev,
++				      struct ethtool_fec_stats *fec_stats)
++{
++	fec_stats->corrected_blocks.total = hdev->fec_stats.rs_corr_blocks;
++	fec_stats->uncorrectable_blocks.total =
++		hdev->fec_stats.rs_uncorr_blocks;
++}
++
++static void hclge_get_fec_stats_lanes(struct hclge_dev *hdev,
++				      struct ethtool_fec_stats *fec_stats)
++{
++	u32 i;
++
++	if (hdev->fec_stats.base_r_lane_num == 0 ||
++	    hdev->fec_stats.base_r_lane_num > HCLGE_FEC_STATS_MAX_LANES) {
++		dev_err(&hdev->pdev->dev,
++			"fec stats lane number(%llu) is invalid\n",
++			hdev->fec_stats.base_r_lane_num);
++		return;
++	}
++
++	for (i = 0; i < hdev->fec_stats.base_r_lane_num; i++) {
++		fec_stats->corrected_blocks.lanes[i] =
++			hdev->fec_stats.base_r_corr_per_lanes[i];
++		fec_stats->uncorrectable_blocks.lanes[i] =
++			hdev->fec_stats.base_r_uncorr_per_lanes[i];
++	}
++}
++
++static void hclge_comm_get_fec_stats(struct hclge_dev *hdev,
++				     struct ethtool_fec_stats *fec_stats)
++{
++	u32 fec_mode = hdev->hw.mac.fec_mode;
++
++	switch (fec_mode) {
++	case BIT(HNAE3_FEC_RS):
++	case BIT(HNAE3_FEC_LLRS):
++		hclge_get_fec_stats_total(hdev, fec_stats);
++		break;
++	case BIT(HNAE3_FEC_BASER):
++		hclge_get_fec_stats_lanes(hdev, fec_stats);
++		break;
++	default:
++		dev_err(&hdev->pdev->dev,
++			"fec stats is not supported by current fec mode(0x%x)\n",
++			fec_mode);
++		break;
++	}
++}
++
++static void hclge_get_fec_stats(struct hnae3_handle *handle,
++				struct ethtool_fec_stats *fec_stats)
++{
++	struct hclge_vport *vport = hclge_get_vport(handle);
++	struct hclge_dev *hdev = vport->back;
++	u32 fec_mode = hdev->hw.mac.fec_mode;
++
++	if (fec_mode == BIT(HNAE3_FEC_NONE) ||
++	    fec_mode == BIT(HNAE3_FEC_AUTO) ||
++	    fec_mode == BIT(HNAE3_FEC_USER_DEF))
++		return;
++
++	hclge_update_fec_stats(hdev);
++
++	hclge_comm_get_fec_stats(hdev, fec_stats);
++}
++
+ static int hclge_set_fec_hw(struct hclge_dev *hdev, u32 fec_mode)
+ {
+ 	struct hclge_config_fec_cmd *req;
+@@ -11820,6 +11974,7 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ static void hclge_stats_clear(struct hclge_dev *hdev)
+ {
+ 	memset(&hdev->mac_stats, 0, sizeof(hdev->mac_stats));
++	memset(&hdev->fec_stats, 0, sizeof(hdev->fec_stats));
+ }
+ 
+ static int hclge_set_mac_spoofchk(struct hclge_dev *hdev, int vf, bool enable)
+@@ -13051,6 +13206,7 @@ struct hnae3_ae_ops hclge_ops = {
+ 	.cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
+ 	.get_media_type = hclge_get_media_type,
+ 	.check_port_speed = hclge_check_port_speed,
++	.get_fec_stats = hclge_get_fec_stats,
+ 	.get_fec = hclge_get_fec,
+ 	.set_fec = hclge_set_fec,
+ 	.get_rss_key_size = hclge_get_rss_key_size,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 00b4d476efe8..e2a041114926 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -246,6 +246,7 @@ enum HCLGE_DEV_STATE {
+ 	HCLGE_STATE_HW_QB_ENABLE,
+ 	HCLGE_STATE_PTP_EN,
+ 	HCLGE_STATE_PTP_TX_HANDLING,
++	HCLGE_STATE_FEC_STATS_UPDATING,
+ 	HCLGE_STATE_MAX
+ };
+ 
+@@ -553,6 +554,26 @@ struct hclge_mac_stats {
+ 
+ #define HCLGE_STATS_TIMER_INTERVAL	300UL
+ 
++/* fec stats ,opcode id: 0x0316 */
++#define HCLGE_FEC_STATS_MAX_LANES	8
++struct hclge_fec_stats {
++	/* fec rs mode total stats */
++	u64 rs_corr_blocks;
++	u64 rs_uncorr_blocks;
++	u64 rs_error_blocks;
++	/* fec base-r mode per lanes stats */
++	u64 base_r_lane_num;
++	u64 base_r_corr_blocks;
++	u64 base_r_uncorr_blocks;
++	union {
++		struct {
++			u64 base_r_corr_per_lanes[HCLGE_FEC_STATS_MAX_LANES];
++			u64 base_r_uncorr_per_lanes[HCLGE_FEC_STATS_MAX_LANES];
++		};
++		u64 per_lanes[HCLGE_FEC_STATS_MAX_LANES * 2];
++	};
++};
++
+ struct hclge_vlan_type_cfg {
+ 	u16 rx_ot_fst_vlan_type;
+ 	u16 rx_ot_sec_vlan_type;
+@@ -842,6 +863,7 @@ struct hclge_dev {
+ 	struct hclge_hw hw;
+ 	struct hclge_misc_vector misc_vector;
+ 	struct hclge_mac_stats mac_stats;
++	struct hclge_fec_stats fec_stats;
+ 	unsigned long state;
+ 	unsigned long flr_state;
+ 	unsigned long last_reset_time;
+-- 
+2.34.1
+
diff --git a/patches/0592-net-hns3-The-kabi-issue-is-resolved-when-the-lane-me.patch b/patches/0592-net-hns3-The-kabi-issue-is-resolved-when-the-lane-me.patch
new file mode 100644
index 0000000..d71e0b0
--- /dev/null
+++ b/patches/0592-net-hns3-The-kabi-issue-is-resolved-when-the-lane-me.patch
@@ -0,0 +1,63 @@
+From 2d50293e720035b378749f2d37b85e0b0af81d7f Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Sat, 26 Aug 2023 10:10:33 +0800
+Subject: [PATCH 231/283] net:hns3 The kabi issue is resolved when the lane
+ members are added to the ethtool_link_ksettings structure
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+--------------------------------
+
+Fix it because hnae3_ Ae_ Get in ops structure_ Ksettings_ An_
+Result, cfg_ Mac_ Speed_ Dup_ Kabi problem caused by changes in
+h member parameters.
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h | 8 +++++++-
+ include/linux/ethtool.h                     | 2 ++
+ 2 files changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 903a942bc851..526a607a0242 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -611,12 +611,18 @@ struct hnae3_ae_ops {
+ 	int (*client_start)(struct hnae3_handle *handle);
+ 	void (*client_stop)(struct hnae3_handle *handle);
+ 	int (*get_status)(struct hnae3_handle *handle);
++#ifndef __GENKSYMS__
+ 	void (*get_ksettings_an_result)(struct hnae3_handle *handle,
+ 					u8 *auto_neg, u32 *speed, u8 *duplex,
+ 					u32 *lane_num);
+-
+ 	int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
+ 				   u8 duplex, u8 lane_num);
++#else
++	void (*get_ksettings_an_result)(struct hnae3_handle *handle,
++					u8 *auto_neg, u32 *speed, u8 *duplex);
++	int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
++				   u8 duplex);
++#endif
+ 
+ 	void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
+ 			       u8 *module_type);
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index e9b7695a4c0e..56bc3e94af94 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -149,7 +149,9 @@ struct ethtool_link_ksettings {
+ 		__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
+ 		__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising);
+ 	} link_modes;
++#ifndef __GENKSYMS__
+ 	u32	lanes;
++#endif
+ };
+ 
+ /**
+-- 
+2.34.1
+
diff --git a/patches/0593-net-ethtool-Fix-the-Kabi-problem-is-caused-by-the-ne.patch b/patches/0593-net-ethtool-Fix-the-Kabi-problem-is-caused-by-the-ne.patch
new file mode 100644
index 0000000..b6ac85c
--- /dev/null
+++ b/patches/0593-net-ethtool-Fix-the-Kabi-problem-is-caused-by-the-ne.patch
@@ -0,0 +1,61 @@
+From dcc39ce3833585ec968d19e74bb50f335114b55e Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Sat, 26 Aug 2023 10:37:04 +0800
+Subject: [PATCH 232/283] net:ethtool Fix the Kabi problem is caused by the new
+ FEC callback function in ethtool_ops
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+--------------------------------
+
+Fix it because ethtool_ Add member get in the ops structure_ Fec_ Stats, as well as
+genl_ Kabi change caused by adding member maxattr in the ops structure.
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ include/linux/ethtool.h | 2 ++
+ include/net/genetlink.h | 4 +++-
+ 2 files changed, 5 insertions(+), 1 deletion(-)
+
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 56bc3e94af94..4bc3cd4060da 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -527,8 +527,10 @@ struct ethtool_ops {
+ 				      struct ethtool_link_ksettings *);
+ 	int	(*set_link_ksettings)(struct net_device *,
+ 				      const struct ethtool_link_ksettings *);
++#ifndef __GENKSYMS__
+ 	void	(*get_fec_stats)(struct net_device *dev,
+ 				 struct ethtool_fec_stats *fec_stats);
++#endif
+ 	int	(*get_fecparam)(struct net_device *,
+ 				      struct ethtool_fecparam *);
+ 	int	(*set_fecparam)(struct net_device *,
+diff --git a/include/net/genetlink.h b/include/net/genetlink.h
+index a057409a44a5..83554e1cc08e 100644
+--- a/include/net/genetlink.h
++++ b/include/net/genetlink.h
+@@ -141,14 +141,16 @@ static inline int genl_err_attr(struct genl_info *info, int err,
+  * @done: completion callback for dumps
+  */
+ struct genl_ops {
++	const struct nla_policy *policy;
+ 	int		       (*doit)(struct sk_buff *skb,
+ 				       struct genl_info *info);
+ 	int		       (*start)(struct netlink_callback *cb);
+ 	int		       (*dumpit)(struct sk_buff *skb,
+ 					 struct netlink_callback *cb);
+ 	int		       (*done)(struct netlink_callback *cb);
+-	const struct nla_policy *policy;
++#ifndef __GENKSYMS__
+ 	unsigned int		maxattr;
++#endif
+ 	u8			cmd;
+ 	u8			internal_flags;
+ 	u8			flags;
+-- 
+2.34.1
+
diff --git a/patches/0594-net-hns3-refactor-hclge_update_desc_vfid-for-extensi.patch b/patches/0594-net-hns3-refactor-hclge_update_desc_vfid-for-extensi.patch
new file mode 100644
index 0000000..3924793
--- /dev/null
+++ b/patches/0594-net-hns3-refactor-hclge_update_desc_vfid-for-extensi.patch
@@ -0,0 +1,74 @@
+From 171fd7525febbb9861c2883f1aba6e6ef1791fbf Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Thu, 28 Jul 2022 16:49:48 +0800
+Subject: [PATCH 233/283] net: hns3: refactor hclge_update_desc_vfid for
+ extension
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+Now, hclge_update_desc_vfid is used to set vf bitmap for batch operations.
+But it used fixed description index, so it is hard to extend for more
+scenario.
+
+So this patch refactor description index in the function for reuse.
+
+Fixes: a90bb9a5ea1d ("net: hns3: Cleanup for endian issue in hns3 driver")
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+(cherry picked from commit 417e0f6b3c4624a400f8741d1ef6713817bc62f8)
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 13 +++++++------
+ 1 file changed, 7 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index ecc792a57c23..2b644db7f9d6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -8341,16 +8341,16 @@ static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
+ 		word_num = vfid / 32;
+ 		bit_num  = vfid % 32;
+ 		if (clr)
+-			desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
++			desc[0].data[word_num] &= cpu_to_le32(~(1 << bit_num));
+ 		else
+-			desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
++			desc[0].data[word_num] |= cpu_to_le32(1 << bit_num);
+ 	} else {
+ 		word_num = (vfid - HCLGE_VF_NUM_IN_FIRST_DESC) / 32;
+ 		bit_num  = vfid % 32;
+ 		if (clr)
+-			desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
++			desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
+ 		else
+-			desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
++			desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
+ 	}
+ 
+ 	return 0;
+@@ -8824,7 +8824,7 @@ int hclge_add_mc_addr_common(struct hclge_vport *vport,
+ 		memset(desc[1].data, 0, sizeof(desc[0].data));
+ 		memset(desc[2].data, 0, sizeof(desc[0].data));
+ 	}
+-	status = hclge_update_desc_vfid(desc, vport->vport_id, false);
++	status = hclge_update_desc_vfid(&desc[1], vport->vport_id, false);
+ 	if (status)
+ 		return status;
+ 	status = hclge_add_mac_vlan_tbl(vport, &req, desc);
+@@ -8869,7 +8869,8 @@ int hclge_rm_mc_addr_common(struct hclge_vport *vport,
+ 	status = hclge_lookup_mc_mac_vlan_tbl(vport, &req, desc);
+ 	if (!status) {
+ 		/* This mac addr exist, remove this handle's VFID for it */
+-		status = hclge_update_desc_vfid(desc, vport->vport_id, true);
++		status = hclge_update_desc_vfid(&desc[1], vport->vport_id,
++						true);
+ 		if (status)
+ 			return status;
+ 
+-- 
+2.34.1
+
diff --git a/patches/0595-net-hns3-add-support-config-dscp-map-to-tc.patch b/patches/0595-net-hns3-add-support-config-dscp-map-to-tc.patch
new file mode 100644
index 0000000..f24f82b
--- /dev/null
+++ b/patches/0595-net-hns3-add-support-config-dscp-map-to-tc.patch
@@ -0,0 +1,392 @@
+From fd581d89a3769e1c0e818b98ffd6c786bf879758 Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 11 Oct 2022 23:14:15 +0800
+Subject: [PATCH 234/283] net: hns3: add support config dscp map to tc
+
+mainline inclusion
+from mainline-v6.0-rc3
+commit 0ba22bcb222d2761feccb46d0ee4eb9db1f53a7d
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0ba22bcb222d
+
+----------------------------------------------------------------------
+
+This patch add support config dscp map to tc by implementing ieee_setapp
+and ieee_delapp of struct dcbnl_rtnl_ops. Driver will convert mapping
+relationship from dscp-prio to dscp-tc.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  8 ++
+ .../net/ethernet/hisilicon/hns3/hns3_dcbnl.c  | 28 ++++++
+ .../hisilicon/hns3/hns3pf/hclge_dcb.c         | 89 +++++++++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 20 +++++
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  4 +
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 50 ++++++++++-
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.h |  5 ++
+ 7 files changed, 203 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 526a607a0242..d05ee2c939b8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -343,6 +343,11 @@ enum hnae3_dbg_cmd {
+ 	HNAE3_DBG_CMD_UNKNOWN,
+ };
+ 
++enum hnae3_tc_map_mode {
++	HNAE3_TC_MAP_MODE_PRIO,
++	HNAE3_TC_MAP_MODE_DSCP,
++};
++
+ struct hnae3_vector_info {
+ 	u8 __iomem *io_addr;
+ 	int vector;
+@@ -831,6 +836,8 @@ struct hnae3_dcb_ops {
+ 	int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *);
+ 	int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *);
+ 	int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *);
++	int (*ieee_setapp)(struct hnae3_handle *h, struct dcb_app *app);
++	int (*ieee_delapp)(struct hnae3_handle *h, struct dcb_app *app);
+ 
+ 	/* DCBX configuration */
+ 	u8   (*getdcbx)(struct hnae3_handle *);
+@@ -886,6 +893,7 @@ struct hnae3_knic_private_info {
+ #endif
+ 
+ 	struct hnae3_tc_info tc_info;
++	u8 tc_map_mode;
+ 
+ 	u16 num_tqps;		  /* total number of TQPs in this handle */
+ 	struct hnae3_queue **tqp;  /* array base of all TQPs in this instance */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_dcbnl.c b/drivers/net/ethernet/hisilicon/hns3/hns3_dcbnl.c
+index d2ec4c573bf8..3b6dbf158b98 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_dcbnl.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_dcbnl.c
+@@ -56,6 +56,32 @@ static int hns3_dcbnl_ieee_setpfc(struct net_device *ndev, struct ieee_pfc *pfc)
+ 	return -EOPNOTSUPP;
+ }
+ 
++static int hns3_dcbnl_ieee_setapp(struct net_device *ndev, struct dcb_app *app)
++{
++	struct hnae3_handle *h = hns3_get_handle(ndev);
++
++	if (hns3_nic_resetting(ndev))
++		return -EBUSY;
++
++	if (h->kinfo.dcb_ops->ieee_setapp)
++		return h->kinfo.dcb_ops->ieee_setapp(h, app);
++
++	return -EOPNOTSUPP;
++}
++
++static int hns3_dcbnl_ieee_delapp(struct net_device *ndev, struct dcb_app *app)
++{
++	struct hnae3_handle *h = hns3_get_handle(ndev);
++
++	if (hns3_nic_resetting(ndev))
++		return -EBUSY;
++
++	if (h->kinfo.dcb_ops->ieee_setapp)
++		return h->kinfo.dcb_ops->ieee_delapp(h, app);
++
++	return -EOPNOTSUPP;
++}
++
+ /* DCBX configuration */
+ static u8 hns3_dcbnl_getdcbx(struct net_device *ndev)
+ {
+@@ -83,6 +109,8 @@ static const struct dcbnl_rtnl_ops hns3_dcbnl_ops = {
+ 	.ieee_setets	= hns3_dcbnl_ieee_setets,
+ 	.ieee_getpfc	= hns3_dcbnl_ieee_getpfc,
+ 	.ieee_setpfc	= hns3_dcbnl_ieee_setpfc,
++	.ieee_setapp    = hns3_dcbnl_ieee_setapp,
++	.ieee_delapp    = hns3_dcbnl_ieee_delapp,
+ 	.getdcbx	= hns3_dcbnl_getdcbx,
+ 	.setdcbx	= hns3_dcbnl_setdcbx,
+ };
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+index 428bb7d6ab94..8a5fc7bd09c6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+@@ -361,6 +361,93 @@ static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
+ 	return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
+ }
+ 
++static int hclge_ieee_setapp(struct hnae3_handle *h, struct dcb_app *app)
++{
++	struct hclge_vport *vport = hclge_get_vport(h);
++	struct net_device *netdev = h->kinfo.netdev;
++	struct hclge_dev *hdev = vport->back;
++	struct dcb_app old_app;
++	int ret;
++
++	if (app->selector != IEEE_8021QAZ_APP_SEL_DSCP ||
++	    app->protocol >= HCLGE_MAX_DSCP ||
++	    app->priority >= HNAE3_MAX_USER_PRIO)
++		return -EINVAL;
++
++	dev_info(&hdev->pdev->dev, "setapp dscp=%u priority=%u\n",
++		 app->protocol, app->priority);
++
++	if (app->priority == hdev->tm_info.dscp_prio[app->protocol])
++		return 0;
++
++	ret = dcb_ieee_setapp(netdev, app);
++	if (ret)
++		return ret;
++
++	old_app.selector = IEEE_8021QAZ_APP_SEL_DSCP;
++	old_app.protocol = app->protocol;
++	old_app.priority = hdev->tm_info.dscp_prio[app->protocol];
++
++	hdev->tm_info.dscp_prio[app->protocol] = app->priority;
++	ret = hclge_dscp_to_tc_map(hdev);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to set dscp to tc map, ret = %d\n", ret);
++		hdev->tm_info.dscp_prio[app->protocol] = old_app.priority;
++		(void)dcb_ieee_delapp(netdev, app);
++		return ret;
++	}
++
++	vport->nic.kinfo.tc_map_mode = HNAE3_TC_MAP_MODE_DSCP;
++	if (old_app.priority == HCLGE_PRIO_ID_INVALID)
++		hdev->tm_info.dscp_app_cnt++;
++	else
++		ret = dcb_ieee_delapp(netdev, &old_app);
++
++	return ret;
++}
++
++static int hclge_ieee_delapp(struct hnae3_handle *h, struct dcb_app *app)
++{
++	struct hclge_vport *vport = hclge_get_vport(h);
++	struct net_device *netdev = h->kinfo.netdev;
++	struct hclge_dev *hdev = vport->back;
++	int ret;
++
++	if (app->selector != IEEE_8021QAZ_APP_SEL_DSCP ||
++	    app->protocol >= HCLGE_MAX_DSCP ||
++	    app->priority >= HNAE3_MAX_USER_PRIO ||
++	    app->priority != hdev->tm_info.dscp_prio[app->protocol])
++		return -EINVAL;
++
++	dev_info(&hdev->pdev->dev, "delapp dscp=%u priority=%u\n",
++		 app->protocol, app->priority);
++
++	ret = dcb_ieee_delapp(netdev, app);
++	if (ret)
++		return ret;
++
++	hdev->tm_info.dscp_prio[app->protocol] = HCLGE_PRIO_ID_INVALID;
++	ret = hclge_dscp_to_tc_map(hdev);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to del dscp to tc map, ret = %d\n", ret);
++		hdev->tm_info.dscp_prio[app->protocol] = app->priority;
++		(void)dcb_ieee_setapp(netdev, app);
++		return ret;
++	}
++
++	if (hdev->tm_info.dscp_app_cnt)
++		hdev->tm_info.dscp_app_cnt--;
++
++	if (!hdev->tm_info.dscp_app_cnt) {
++		vport->nic.kinfo.tc_map_mode = HNAE3_TC_MAP_MODE_PRIO;
++		ret = hclge_up_to_tc_map(hdev);
++	}
++
++	return ret;
++}
++
+ /* DCBX configuration */
+ static u8 hclge_getdcbx(struct hnae3_handle *h)
+ {
+@@ -546,6 +633,8 @@ static const struct hnae3_dcb_ops hns3_dcb_ops = {
+ 	.ieee_setets	= hclge_ieee_setets,
+ 	.ieee_getpfc	= hclge_ieee_getpfc,
+ 	.ieee_setpfc	= hclge_ieee_setpfc,
++	.ieee_setapp    = hclge_ieee_setapp,
++	.ieee_delapp    = hclge_ieee_delapp,
+ 	.getdcbx	= hclge_getdcbx,
+ 	.setdcbx	= hclge_setdcbx,
+ 	.setup_tc	= hclge_setup_tc,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 2b644db7f9d6..87e5793cf13c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -13182,6 +13182,25 @@ static int hclge_get_link_diagnosis_info(struct hnae3_handle *handle,
+ 	return 0;
+ }
+ 
++static int hclge_get_dscp_prio(struct hnae3_handle *h, u8 dscp, u8 *tc_mode,
++			       u8 *priority)
++{
++	struct hclge_vport *vport = hclge_get_vport(h);
++	struct hclge_dev *hdev = vport->back;
++
++	if (dscp >= HCLGE_MAX_DSCP)
++		return -EINVAL;
++
++	if (tc_mode)
++		*tc_mode = vport->nic.kinfo.tc_map_mode;
++	if (priority)
++		*priority = hdev->tm_info.dscp_prio[dscp] ==
++				HCLGE_PRIO_ID_INVALID ? 0 :
++				hdev->tm_info.dscp_prio[dscp];
++
++	return 0;
++}
++
+ struct hnae3_ae_ops hclge_ops = {
+ 	.init_ae_dev = hclge_init_ae_dev,
+ 	.uninit_ae_dev = hclge_uninit_ae_dev,
+@@ -13286,6 +13305,7 @@ struct hnae3_ae_ops hclge_ops = {
+ 	.get_rx_hwts = hclge_ptp_get_rx_hwts,
+ 	.get_ts_info = hclge_ptp_get_ts_info,
+ 	.get_link_diagnosis_info = hclge_get_link_diagnosis_info,
++	.get_dscp_prio = hclge_get_dscp_prio,
+ 	.get_wol = hclge_get_wol,
+ 	.set_wol = hclge_set_wol,
+ 	.priv_ops = hclge_ext_ops_handle,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index e2a041114926..2caf07f80484 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -414,11 +414,15 @@ struct hclge_cfg {
+ 	u16 umv_space;
+ };
+ 
++#define HCLGE_MAX_DSCP			64
++#define HCLGE_PRIO_ID_INVALID		0xff
+ struct hclge_tm_info {
+ 	u8 num_tc;
+ 	u8 num_pg;      /* It must be 1 if vNET-Base schd */
++	u8 dscp_app_cnt;
+ 	u8 pg_dwrr[HCLGE_PG_NUM];
+ 	u8 prio_tc[HNAE3_MAX_USER_PRIO];
++	u8 dscp_prio[HCLGE_MAX_DSCP];
+ 	struct hclge_pg_info pg_info[HCLGE_PG_NUM];
+ 	struct hclge_tc_info tc_info[HNAE3_MAX_TC];
+ 	enum hclge_fc_mode fc_mode;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index b535f3dd842b..25f39c3fde05 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -248,7 +248,7 @@ static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id)
+ 	return 0;
+ }
+ 
+-static int hclge_up_to_tc_map(struct hclge_dev *hdev)
++int hclge_up_to_tc_map(struct hclge_dev *hdev)
+ {
+ 	struct hclge_desc desc;
+ 	u8 *pri = (u8 *)desc.data;
+@@ -266,6 +266,47 @@ static int hclge_up_to_tc_map(struct hclge_dev *hdev)
+ 	return hclge_cmd_send(&hdev->hw, &desc, 1);
+ }
+ 
++static void hclge_dscp_to_prio_map_init(struct hclge_dev *hdev)
++{
++	u8 i;
++
++	hdev->vport[0].nic.kinfo.tc_map_mode = HNAE3_TC_MAP_MODE_PRIO;
++	hdev->tm_info.dscp_app_cnt = 0;
++	for (i = 0; i < HCLGE_MAX_DSCP; i++)
++		hdev->tm_info.dscp_prio[i] = HCLGE_PRIO_ID_INVALID;
++}
++
++int hclge_dscp_to_tc_map(struct hclge_dev *hdev)
++{
++	struct hclge_desc desc[HCLGE_DSCP_MAP_TC_BD_NUM];
++	u8 *req0 = (u8 *)desc[0].data;
++	u8 *req1 = (u8 *)desc[1].data;
++	u8 pri_id, tc_id, i, j;
++
++	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QOS_MAP, false);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
++	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_QOS_MAP, false);
++
++	/* The low 32 dscp setting use bd0, high 32 dscp setting use bd1 */
++	for (i = 0; i < HCLGE_MAX_DSCP / HCLGE_DSCP_MAP_TC_BD_NUM; i++) {
++		pri_id = hdev->tm_info.dscp_prio[i];
++		pri_id = pri_id == HCLGE_PRIO_ID_INVALID ? 0 : pri_id;
++		tc_id = hdev->tm_info.prio_tc[pri_id];
++		/* Each dscp setting has 4 bits, so each byte saves two dscp
++		 * setting
++		 */
++		req0[i >> 1] |= tc_id << HCLGE_DSCP_TC_SHIFT(i);
++
++		j = i + HCLGE_MAX_DSCP / HCLGE_DSCP_MAP_TC_BD_NUM;
++		pri_id = hdev->tm_info.dscp_prio[j];
++		pri_id = pri_id == HCLGE_PRIO_ID_INVALID ? 0 : pri_id;
++		tc_id = hdev->tm_info.prio_tc[pri_id];
++		req1[i >> 1] |= tc_id << HCLGE_DSCP_TC_SHIFT(i);
++	}
++
++	return hclge_cmd_send(&hdev->hw, desc, HCLGE_DSCP_MAP_TC_BD_NUM);
++}
++
+ static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev,
+ 				      u8 pg_id, u8 pri_bit_map)
+ {
+@@ -1157,6 +1198,12 @@ static int hclge_tm_map_cfg(struct hclge_dev *hdev)
+ 	if (ret)
+ 		return ret;
+ 
++	if (hdev->vport[0].nic.kinfo.tc_map_mode == HNAE3_TC_MAP_MODE_DSCP) {
++		ret = hclge_dscp_to_tc_map(hdev);
++		if (ret)
++			return ret;
++	}
++
+ 	ret = hclge_tm_pg_to_pri_map(hdev);
+ 	if (ret)
+ 		return ret;
+@@ -1501,6 +1548,7 @@ int hclge_tm_schd_init(struct hclge_dev *hdev)
+ 		return -EINVAL;
+ 
+ 	hclge_tm_schd_info_init(hdev);
++	hclge_dscp_to_prio_map_init(hdev);
+ 
+ 	return hclge_tm_init_hw(hdev, true);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+index b36f19a629b2..6dafd954c774 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+@@ -24,6 +24,9 @@
+ #define HCLGE_TM_PF_MAX_PRI_NUM		8
+ #define HCLGE_TM_PF_MAX_QSET_NUM	8
+ 
++#define HCLGE_DSCP_MAP_TC_BD_NUM	2
++#define HCLGE_DSCP_TC_SHIFT(n)		(((n) & 1) * 4)
++
+ struct hclge_pg_to_pri_link_cmd {
+ 	u8 pg_id;
+ 	u8 rsvd1[3];
+@@ -227,4 +230,6 @@ int hclge_tm_get_pg_shaper(struct hclge_dev *hdev, u8 pg_id,
+ 			   struct hclge_tm_shaper_para *para);
+ int hclge_tm_get_port_shaper(struct hclge_dev *hdev,
+ 			     struct hclge_tm_shaper_para *para);
++int hclge_up_to_tc_map(struct hclge_dev *hdev);
++int hclge_dscp_to_tc_map(struct hclge_dev *hdev);
+ #endif
+-- 
+2.34.1
+
diff --git a/patches/0596-net-hns3-fix-strncpy-not-using-dest-buf-length-as-le.patch b/patches/0596-net-hns3-fix-strncpy-not-using-dest-buf-length-as-le.patch
new file mode 100644
index 0000000..f50e228
--- /dev/null
+++ b/patches/0596-net-hns3-fix-strncpy-not-using-dest-buf-length-as-le.patch
@@ -0,0 +1,123 @@
+From 2a6d050445917e451c37ea8c2c7286f6f4df3e1c Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao418@huawei.com>
+Date: Thu, 27 Oct 2022 15:27:35 +0800
+Subject: [PATCH 235/283] net: hns3: fix strncpy() not using dest-buf length as
+ length issue
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+Now, strncpy() in hns3_dbg_fill_content() use src-length as copy-length,
+it may result in dest-buf overflow.
+
+This patch add some values check to avoid this issue.
+
+Fixes: 721091d171a1 ("net: hns3: refactor dump bd info of debugfs")
+Signed-off-by: Hao Chen <chenhao418@huawei.com>
+(cherry picked from commit 68023e0709aa1eb47549d58867e9285cf9980535)
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    | 31 ++++++++++++++-----
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     | 29 ++++++++++++++---
+ 2 files changed, 48 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index afe3f673364c..ca2c5e6bd40d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -380,19 +380,36 @@ static void hns3_dbg_fill_content(char *content, u16 len,
+ 				  const struct hns3_dbg_item *items,
+ 				  const char **result, u16 size)
+ {
++#define HNS3_DBG_LINE_END_LEN	2
+ 	char *pos = content;
++	u16 item_len;
+ 	u16 i;
+ 
++	if (!len) {
++		return;
++	} else if (len <= HNS3_DBG_LINE_END_LEN) {
++		*pos++ = '\0';
++		return;
++	}
++
+ 	memset(content, ' ', len);
+-	for (i = 0; i < size; i++) {
+-		if (result)
+-			strncpy(pos, result[i], strlen(result[i]));
+-		else
+-			strncpy(pos, items[i].name, strlen(items[i].name));
++	len -= HNS3_DBG_LINE_END_LEN;
+ 
+-		pos += strlen(items[i].name) + items[i].interval;
++	for (i = 0; i < size; i++) {
++		item_len = strlen(items[i].name) + items[i].interval;
++		if (len < item_len)
++			break;
++
++		if (result) {
++			if (item_len < strlen(result[i]))
++				break;
++			memcpy(pos, result[i], strlen(result[i]));
++		} else {
++			memcpy(pos, items[i].name, strlen(items[i].name));
++		}
++		pos += item_len;
++		len -= item_len;
+ 	}
+-
+ 	*pos++ = '\n';
+ 	*pos++ = '\0';
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index 63cc42060a31..087079070353 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -81,16 +81,35 @@ static void hclge_dbg_fill_content(char *content, u16 len,
+ 				   const struct hclge_dbg_item *items,
+ 				   const char **result, u16 size)
+ {
++#define HCLGE_DBG_LINE_END_LEN	2
+ 	char *pos = content;
++	u16 item_len;
+ 	u16 i;
+ 
++	if (!len) {
++		return;
++	} else if (len <= HCLGE_DBG_LINE_END_LEN) {
++		*pos++ = '\0';
++		return;
++	}
++
+ 	memset(content, ' ', len);
++	len -= HCLGE_DBG_LINE_END_LEN;
++
+ 	for (i = 0; i < size; i++) {
+-		if (result)
+-			strncpy(pos, result[i], strlen(result[i]));
+-		else
+-			strncpy(pos, items[i].name, strlen(items[i].name));
+-		pos += strlen(items[i].name) + items[i].interval;
++		item_len = strlen(items[i].name) + items[i].interval;
++		if (len < item_len)
++			break;
++
++		if (result) {
++			if (item_len < strlen(result[i]))
++				break;
++			memcpy(pos, result[i], strlen(result[i]));
++		} else {
++			memcpy(pos, items[i].name, strlen(items[i].name));
++		}
++		pos += item_len;
++		len -= item_len;
+ 	}
+ 	*pos++ = '\n';
+ 	*pos++ = '\0';
+-- 
+2.34.1
+
diff --git a/patches/0597-net-hns3-fix-GRE-checksum-offload-issue.patch b/patches/0597-net-hns3-fix-GRE-checksum-offload-issue.patch
new file mode 100644
index 0000000..0c6aec1
--- /dev/null
+++ b/patches/0597-net-hns3-fix-GRE-checksum-offload-issue.patch
@@ -0,0 +1,85 @@
+From 81c45d5a7a94f4a11969a7de829aa146d75acec6 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Tue, 23 May 2023 10:35:55 +0800
+Subject: [PATCH 236/283] net: hns3: fix GRE checksum offload issue
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+The device_version V3 hardware can't offload the checksum for IP in GRE
+packets, but can do it for NvGRE. So default to disable the checksum and
+GSO offload for GRE, but keep the ability to enable it when only using
+NvGRE.
+
+Fixes: 76ad4f0ee747 ("net: hns3: Add support of HNS3 Ethernet Driver for hip08 SoC")
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+(cherry picked from commit df924f69199ae2297033cbe69ac656d7c1aadab6)
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  3 +++
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 22 ++++++++++---------
+ 2 files changed, 15 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index d05ee2c939b8..ec9aa9233506 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -111,6 +111,9 @@ enum HNAE3_DEV_CAP_BITS {
+ #define hnae3_ae_dev_fd_supported(ae_dev) \
+ 		test_bit(HNAE3_DEV_SUPPORT_FD_B, (ae_dev)->caps)
+ 
++#define hnae3_ae_dev_gro_supported(ae_dev) \
++		test_bit(HNAE3_DEV_SUPPORT_GRO_B, (ae_dev)->caps)
++
+ #define hnae3_dev_fd_supported(hdev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps)
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 303b7b76bc8d..5b7bf29f0934 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -2991,22 +2991,24 @@ static void hns3_set_default_feature(struct net_device *netdev)
+ 
+ 	netdev->priv_flags |= IFF_UNICAST_FLT;
+ 
+-	netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
+-
+ 	netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
+ 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
+ 		NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_GSO |
+-		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_GRE |
+-		NETIF_F_GSO_GRE_CSUM | NETIF_F_GSO_UDP_TUNNEL |
+-		NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_SCTP_CRC |
+-		NETIF_F_FRAGLIST;
++		NETIF_F_GRO | NETIF_F_TSO | NETIF_F_TSO6 |
++		NETIF_F_GSO_UDP_TUNNEL |
++		NETIF_F_SCTP_CRC | NETIF_F_FRAGLIST;
++
++	if (pdev->revision == HNAE3_DEVICE_VERSION_V2) {
++		netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
++		netdev->features |= NETIF_F_GSO_GRE_CSUM;
++		netdev->features |= NETIF_F_GSO_GRE;
++	}
+ 
+-	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
++	if (hnae3_ae_dev_gro_supported(ae_dev))
+ 		netdev->features |= NETIF_F_GRO_HW;
+ 
+-		if (!(h->flags & HNAE3_SUPPORT_VF))
+-			netdev->features |= NETIF_F_NTUPLE;
+-	}
++	if (hnae3_ae_dev_fd_supported(ae_dev))
++		netdev->features |= NETIF_F_NTUPLE;
+ 
+ 	if (test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps))
+ 		netdev->features |= NETIF_F_GSO_UDP_L4;
+-- 
+2.34.1
+
diff --git a/patches/0598-net-hns3-fix-the-imp-capability-bit-cannot-exceed-32.patch b/patches/0598-net-hns3-fix-the-imp-capability-bit-cannot-exceed-32.patch
new file mode 100644
index 0000000..975a498
--- /dev/null
+++ b/patches/0598-net-hns3-fix-the-imp-capability-bit-cannot-exceed-32.patch
@@ -0,0 +1,95 @@
+From 6b47ae6a2b6de16ce9d89f30012767f24b22f203 Mon Sep 17 00:00:00 2001
+From: Hao Lan <lanhao@huawei.com>
+Date: Thu, 25 May 2023 00:22:46 +0800
+Subject: [PATCH 237/283] net: hns3: fix the imp capability bit cannot exceed
+ 32 bits issue
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+Current only the first 32 bits of the capability flag bit are considered.
+When the matching capability flag bit is greater than 31 bits,
+it will get an error bit.This patch use bitmap to solve this issue.
+It can handle each capability bit whitout bit width limit.
+
+Fixes: da77aef9cc58 ("net: hns3: create common cmdq resource allocate/free/query APIs")
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+(cherry picked from commit 702c687cf9c1a8da10769f2dd4adb4b97e7b868b)
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  3 ++-
+ .../hns3/hns3_common/hclge_comm_cmd.c         | 21 ++++++++++++++++---
+ 2 files changed, 20 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index ec9aa9233506..36a7285f68cf 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -30,6 +30,7 @@
+ #include <linux/pci.h>
+ #include <linux/pkt_sched.h>
+ #include <linux/types.h>
++#include <linux/bitmap.h>
+ #include <net/pkt_cls.h>
+ 
+ #define HNAE3_MOD_VERSION "23.7.1"
+@@ -428,7 +429,7 @@ struct hnae3_ae_dev {
+ #ifndef __GENKSYMS__
+ 	struct hnae3_dev_specs dev_specs;
+ 	u32 dev_version;
+-	unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)];
++	DECLARE_BITMAP(caps, HNAE3_DEV_CAPS_MAX_NUM);
+ #endif
+ 	void *priv;
+ };
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index c4d647519977..a3ed8e531b25 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -173,6 +173,20 @@ static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
+ 	{HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},
+ };
+ 
++static void
++hclge_comm_capability_to_bitmap(unsigned long *bitmap, __le32 *caps)
++{
++	const unsigned int words = HCLGE_COMM_QUERY_CAP_LENGTH;
++	u32 val[HCLGE_COMM_QUERY_CAP_LENGTH];
++	unsigned int i;
++
++	for (i = 0; i < words; i++)
++		val[i] = __le32_to_cpu(caps[i]);
++
++	bitmap_from_arr32(bitmap, val,
++			  HCLGE_COMM_QUERY_CAP_LENGTH * BITS_PER_TYPE(u32));
++}
++
+ static void
+ hclge_comm_parse_capability(struct hnae3_ae_dev *ae_dev, bool is_pf,
+ 			    struct hclge_comm_query_version_cmd *cmd)
+@@ -181,11 +195,12 @@ hclge_comm_parse_capability(struct hnae3_ae_dev *ae_dev, bool is_pf,
+ 				is_pf ? hclge_pf_cmd_caps : hclge_vf_cmd_caps;
+ 	u32 size = is_pf ? ARRAY_SIZE(hclge_pf_cmd_caps) :
+ 				ARRAY_SIZE(hclge_vf_cmd_caps);
+-	u32 caps, i;
++	DECLARE_BITMAP(caps, HCLGE_COMM_QUERY_CAP_LENGTH * BITS_PER_TYPE(u32));
++	u32 i;
+ 
+-	caps = __le32_to_cpu(cmd->caps[0]);
++	hclge_comm_capability_to_bitmap(caps, cmd->caps);
+ 	for (i = 0; i < size; i++)
+-		if (hnae3_get_bit(caps, caps_map[i].imp_bit))
++		if (test_bit(caps_map[i].imp_bit, caps))
+ 			set_bit(caps_map[i].local_bit, ae_dev->caps);
+ }
+ 
+-- 
+2.34.1
+
diff --git a/patches/0599-net-hns3-add-tm-flush-when-setting-tm.patch b/patches/0599-net-hns3-add-tm-flush-when-setting-tm.patch
new file mode 100644
index 0000000..ca129b9
--- /dev/null
+++ b/patches/0599-net-hns3-add-tm-flush-when-setting-tm.patch
@@ -0,0 +1,246 @@
+From 6167109134780f83d165e837c738feb76231fbc4 Mon Sep 17 00:00:00 2001
+From: Hao Lan <lanhao@huawei.com>
+Date: Thu, 25 May 2023 20:20:06 +0800
+Subject: [PATCH 238/283] net: hns3: add tm flush when setting tm
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+When the tm module is configured with traffic, traffic
+may be abnormal. This patch fixes this problem.
+Before the tm module is configured, traffic processing
+should be stopped. After the tm module is configured,
+traffic processing is enabled.
+
+Fixes: 848440544b41 ("net: hns3: Add support of TX Scheduler & Shaper to HNS3 driver")
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+(cherry picked from commit b62afba40728081d30d3471e742e06c1f9d6fdfc)
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  3 ++
+ .../hns3/hns3_common/hclge_comm_cmd.c         |  1 +
+ .../hns3/hns3_common/hclge_comm_cmd.h         |  1 +
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    |  3 ++
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  1 +
+ .../hisilicon/hns3/hns3pf/hclge_dcb.c         | 34 ++++++++++++++++---
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 31 ++++++++++++++++-
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_tm.h |  4 +++
+ 8 files changed, 72 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 36a7285f68cf..e085e384501c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -107,6 +107,7 @@ enum HNAE3_DEV_CAP_BITS {
+ 	HNAE3_DEV_SUPPORT_WOL_B,
+ 	HNAE3_DEV_SUPPORT_VF_FAULT_B,
+ 	HNAE3_DEV_SUPPORT_NOTIFY_PKT_B,
++	HNAE3_DEV_SUPPORT_TM_FLUSH_B,
+ };
+ 
+ #define hnae3_ae_dev_fd_supported(ae_dev) \
+@@ -188,6 +189,8 @@ enum HNAE3_DEV_CAP_BITS {
+ 	test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)
+ #define hnae3_ae_dev_fec_stats_supported(ae_dev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps)
++#define hnae3_ae_dev_tm_flush_supported(hdev) \
++	test_bit(HNAE3_DEV_SUPPORT_TM_FLUSH_B, (hdev)->ae_dev->caps)
+ 
+ enum HNAE3_PF_CAP_BITS {
+ 	HNAE3_PF_SUPPORT_VLAN_FLTR_MDF_B = 0,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index a3ed8e531b25..cdfce19de621 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -158,6 +158,7 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = {
+ 	{HCLGE_COMM_CAP_LANE_NUM_B, HNAE3_DEV_SUPPORT_LANE_NUM_B},
+ 	{HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},
+ 	{HCLGE_COMM_CAP_NOTIFY_PKT_B, HNAE3_DEV_SUPPORT_NOTIFY_PKT_B},
++	{HCLGE_COMM_CAP_TM_FLUSH_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B},
+ };
+ 
+ static const struct hclge_comm_caps_bit_map hclge_vf_cmd_caps[] = {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 2b8df9b03412..2b9c92a00049 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -99,6 +99,7 @@ enum HCLGE_COMM_CAP_BITS {
+ 	HCLGE_COMM_CAP_LANE_NUM_B = 27,
+ 	HCLGE_COMM_CAP_WOL_B = 28,
+ 	HCLGE_COMM_CAP_NOTIFY_PKT_B = 29,
++	HCLGE_COMM_CAP_TM_FLUSH_B = 31,
+ };
+ 
+ enum HCLGE_COMM_API_CAP_BITS {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index ca2c5e6bd40d..5e4be179cf99 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -373,6 +373,9 @@ static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
+ 	}, {
+ 		.name = "support lane num",
+ 		.cap_bit = HNAE3_DEV_SUPPORT_LANE_NUM_B,
++	}, {
++		.name = "support tm flush",
++		.cap_bit = HNAE3_DEV_SUPPORT_TM_FLUSH_B,
+ 	}
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index ef1b6d90bd75..8d1914041bd1 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -172,6 +172,7 @@ enum hclge_opcode_type {
+ 	HCLGE_OPC_TM_INTERNAL_STS	= 0x0850,
+ 	HCLGE_OPC_TM_INTERNAL_CNT	= 0x0851,
+ 	HCLGE_OPC_TM_INTERNAL_STS_1	= 0x0852,
++	HCLGE_OPC_TM_FLUSH		= 0x0872,
+ 
+ 	/* Packet buffer allocate commands */
+ 	HCLGE_OPC_TX_BUFF_ALLOC		= 0x0901,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+index 8a5fc7bd09c6..977dc9648636 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
+@@ -216,6 +216,10 @@ static int hclge_notify_down_uinit(struct hclge_dev *hdev)
+ 	if (ret)
+ 		return ret;
+ 
++	ret = hclge_tm_flush_cfg(hdev, true);
++	if (ret)
++		return ret;
++
+ 	return hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
+ }
+ 
+@@ -227,6 +231,10 @@ static int hclge_notify_init_up(struct hclge_dev *hdev)
+ 	if (ret)
+ 		return ret;
+ 
++	ret = hclge_tm_flush_cfg(hdev, false);
++	if (ret)
++		return ret;
++
+ 	return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
+ }
+ 
+@@ -314,6 +322,7 @@ static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
+ 	struct net_device *netdev = h->kinfo.netdev;
+ 	struct hclge_dev *hdev = vport->back;
+ 	u8 i, j, pfc_map, *prio_tc;
++	int last_bad_ret = 0;
+ 	int ret;
+ 
+ 	if (!(hdev->dcbx_cap & DCB_CAP_DCBX_VER_IEEE))
+@@ -352,13 +361,28 @@ static int hclge_ieee_setpfc(struct hnae3_handle *h, struct ieee_pfc *pfc)
+ 	if (ret)
+ 		return ret;
+ 
+-	ret = hclge_buffer_alloc(hdev);
+-	if (ret) {
+-		hclge_notify_client(hdev, HNAE3_UP_CLIENT);
++	ret = hclge_tm_flush_cfg(hdev, true);
++	if (ret)
+ 		return ret;
+-	}
+ 
+-	return hclge_notify_client(hdev, HNAE3_UP_CLIENT);
++	/* No matter whether the following operations are performed
++	 * successfully or not, disabling the tm flush and notify
++	 * the network status to up are necessary.
++	 * Do not return immediately.
++	 */
++	ret = hclge_buffer_alloc(hdev);
++	if (ret)
++		last_bad_ret = ret;
++
++	ret = hclge_tm_flush_cfg(hdev, false);
++	if (ret)
++		last_bad_ret = ret;
++
++	ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
++	if (ret)
++		last_bad_ret = ret;
++
++	return last_bad_ret;
+ }
+ 
+ static int hclge_ieee_setapp(struct hnae3_handle *h, struct dcb_app *app)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index 25f39c3fde05..a18b2d2e4bb4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -1345,7 +1345,11 @@ int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
+ 		return ret;
+ 
+ 	/* Cfg schd mode for each level schd */
+-	return hclge_tm_schd_mode_hw(hdev);
++	ret = hclge_tm_schd_mode_hw(hdev);
++	if (ret)
++		return ret;
++
++	return hclge_tm_flush_cfg(hdev, false);
+ }
+ 
+ static int hclge_pause_param_setup_hw(struct hclge_dev *hdev)
+@@ -1916,3 +1920,28 @@ int hclge_tm_get_port_shaper(struct hclge_dev *hdev,
+ 
+ 	return 0;
+ }
++
++int hclge_tm_flush_cfg(struct hclge_dev *hdev, bool enable)
++{
++	struct hclge_desc desc;
++	int ret;
++
++	if (!hnae3_ae_dev_tm_flush_supported(hdev))
++		return 0;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_FLUSH, false);
++
++	desc.data[0] = cpu_to_le32(enable ? HCLGE_TM_FLUSH_EN_MSK : 0);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to config tm flush, ret = %d\n", ret);
++		return ret;
++	}
++
++	if (enable)
++		msleep(HCLGE_TM_FLUSH_TIME_MS);
++
++	return ret;
++}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+index 6dafd954c774..d9dae3e60b9b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+@@ -27,6 +27,9 @@
+ #define HCLGE_DSCP_MAP_TC_BD_NUM	2
+ #define HCLGE_DSCP_TC_SHIFT(n)		(((n) & 1) * 4)
+ 
++#define HCLGE_TM_FLUSH_TIME_MS	10
++#define HCLGE_TM_FLUSH_EN_MSK	BIT(0)
++
+ struct hclge_pg_to_pri_link_cmd {
+ 	u8 pg_id;
+ 	u8 rsvd1[3];
+@@ -232,4 +235,5 @@ int hclge_tm_get_port_shaper(struct hclge_dev *hdev,
+ 			     struct hclge_tm_shaper_para *para);
+ int hclge_up_to_tc_map(struct hclge_dev *hdev);
+ int hclge_dscp_to_tc_map(struct hclge_dev *hdev);
++int hclge_tm_flush_cfg(struct hclge_dev *hdev, bool enable);
+ #endif
+-- 
+2.34.1
+
diff --git a/patches/0600-net-hns3-restore-user-pause-configure-when-disable-a.patch b/patches/0600-net-hns3-restore-user-pause-configure-when-disable-a.patch
new file mode 100644
index 0000000..45551df
--- /dev/null
+++ b/patches/0600-net-hns3-restore-user-pause-configure-when-disable-a.patch
@@ -0,0 +1,72 @@
+From 8831abda8b2f895ad4ee125bbd8cb3475ec37544 Mon Sep 17 00:00:00 2001
+From: Peiyang Wang <wangpeiyang1@huawei.com>
+Date: Mon, 29 May 2023 21:09:14 +0800
+Subject: [PATCH 239/283] net: hns3: restore user pause configure when disable
+ autoneg
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+Restore the mac pause state to user configuration when autoneg is disabled
+
+Fixes: 1770a7a3aeb2 ("net: hns3: add support to update flow control settings after autoneg")
+Signed-off-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Peiyang Wang <wangpeiyang1@huawei.com>
+(cherry picked from commit ae9425ebb8bf32e4777c72eba778153c8d971c5d)
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 6 +++++-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c   | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h   | 1 +
+ 3 files changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 87e5793cf13c..0f180546a4d2 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -10942,8 +10942,12 @@ int hclge_cfg_flowctrl(struct hclge_dev *hdev)
+ 	u32 rx_pause, tx_pause;
+ 	u8 flowctl;
+ 
+-	if (!phydev->link || !phydev->autoneg)
++	if (!phydev->link)
+ 		return 0;
++
++	if (!phydev->autoneg)
++		return hclge_mac_pause_setup_hw(hdev);
++
+ #ifdef HAS_LINK_MODE_OPS
+ 	local_advertising = linkmode_adv_to_lcl_adv_t(phydev->advertising);
+ #else
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+index a18b2d2e4bb4..ffb4edc08791 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
+@@ -1406,7 +1406,7 @@ static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc)
+ 	return 0;
+ }
+ 
+-static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev)
++int hclge_mac_pause_setup_hw(struct hclge_dev *hdev)
+ {
+ 	bool tx_en, rx_en;
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+index d9dae3e60b9b..225a537b8da3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h
+@@ -206,6 +206,7 @@ int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
+ int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
+ 			  u8 pause_trans_gap, u16 pause_trans_time);
+ int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr);
++int hclge_mac_pause_setup_hw(struct hclge_dev *hdev);
+ void hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats);
+ void hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats);
+ int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate);
+-- 
+2.34.1
+
diff --git a/patches/0601-net-hns3-fix-set-cpu-affinity-when-state-down.patch b/patches/0601-net-hns3-fix-set-cpu-affinity-when-state-down.patch
new file mode 100644
index 0000000..f1bc012
--- /dev/null
+++ b/patches/0601-net-hns3-fix-set-cpu-affinity-when-state-down.patch
@@ -0,0 +1,43 @@
+From bfd50c812fdd7aa6dd8e1e06188a5e288017ff04 Mon Sep 17 00:00:00 2001
+From: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Date: Thu, 1 Jun 2023 19:40:57 +0800
+Subject: [PATCH 240/283] net: hns3: fix set cpu affinity when state down
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+The CPU affinity can be configured when the network
+port is down. The patch fixes the problem.
+
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+(cherry picked from commit b2b62276a1f2ee4854d1ae8627161c50cda895a9)
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_ext.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 39bd51e93ddb..168c9c903158 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -139,6 +139,13 @@ int nic_set_cpu_affinity(struct net_device *ndev, cpumask_t *affinity_mask)
+ 		goto err_unlock;
+ 	}
+ 
++	if (test_bit(HNS3_NIC_STATE_DOWN, &priv->state)) {
++		netdev_err(ndev,
++			   "ethernet is down, not support cpu affinity set\n");
++		ret = -ENETDOWN;
++		goto err_unlock;
++	}
++
+ 	for (i = 0; i < priv->vector_num; i++) {
+ 		tqp_vector = &priv->tqp_vector[i];
+ 		if (tqp_vector->irq_init_flag != HNS3_VECTOR_INITED)
+-- 
+2.34.1
+
diff --git a/patches/0602-net-hns3-add-wait-until-mac-link-down.patch b/patches/0602-net-hns3-add-wait-until-mac-link-down.patch
new file mode 100644
index 0000000..6f7690b
--- /dev/null
+++ b/patches/0602-net-hns3-add-wait-until-mac-link-down.patch
@@ -0,0 +1,61 @@
+From 55f3d527e8f6e9cdb8e54715cc55557589b36c1d Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Tue, 6 Jun 2023 15:12:20 +0800
+Subject: [PATCH 241/283] net: hns3: add wait until mac link down
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+In some configure flow of hns3 driver, for example, change mtu, it will
+disable MAC through firmware before configuration. But firmware disables
+MAC asynchronously. The rx traffic may be not stopped in this case.
+
+So fixes it by waiting until mac link is down.
+
+Fixes: a9775bb64aa7 ("net: hns3: fix set and get link ksettings issue")
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c  | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 0f180546a4d2..6dd6ff86a2d8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -7698,6 +7698,8 @@ static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
+ 
+ int hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
+ {
++#define HCLGE_LINK_STATUS_WAIT_CNT  3
++
+ 	struct hclge_desc desc;
+ 	struct hclge_config_mac_mode_cmd *req =
+ 		(struct hclge_config_mac_mode_cmd *)desc.data;
+@@ -7722,11 +7724,17 @@ int hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
+ 	req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+-	if (ret)
++	if (ret) {
+ 		dev_err(&hdev->pdev->dev, "failed to %s mac, ret = %d.\n",
+ 			enable ? "enable" : "disable", ret);
++		return ret;
++	}
+ 
+-	return ret;
++	if (!enable)
++		hclge_mac_link_status_wait(hdev, HCLGE_LINK_STATUS_DOWN,
++					   HCLGE_LINK_STATUS_WAIT_CNT);
++
++	return 0;
+ }
+ 
+ static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid,
+-- 
+2.34.1
+
diff --git a/patches/0603-net-hns3-refactor-hclge_mac_link_status_wait-for-int.patch b/patches/0603-net-hns3-refactor-hclge_mac_link_status_wait-for-int.patch
new file mode 100644
index 0000000..0474f3d
--- /dev/null
+++ b/patches/0603-net-hns3-refactor-hclge_mac_link_status_wait-for-int.patch
@@ -0,0 +1,81 @@
+From 665da11cee9a9ff06c1d367c0843a0d31b49ee46 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Thu, 8 Jun 2023 19:40:24 +0800
+Subject: [PATCH 242/283] net: hns3: refactor hclge_mac_link_status_wait for
+ interface reuse
+
+driver inclusion
+category: cleanup
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+Some nic configurations could only be performed after link is down. So this
+patch refactor this API for reuse.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c    | 14 +++++++++-----
+ 1 file changed, 9 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 6dd6ff86a2d8..26054593839a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -73,6 +73,8 @@ static void hclge_restore_hw_table(struct hclge_dev *hdev);
+ static void hclge_sync_promisc_mode(struct hclge_dev *hdev);
+ static void hclge_reset_end(struct hnae3_handle *handle, bool done);
+ static void hclge_update_fec_stats(struct hclge_dev *hdev);
++static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret,
++				      int wait_cnt);
+ 
+ static struct hnae3_ae_algo ae_algo;
+ 
+@@ -7797,10 +7799,9 @@ static void hclge_phy_link_status_wait(struct hclge_dev *hdev,
+ 	} while (++i < HCLGE_PHY_LINK_STATUS_NUM);
+ }
+ 
+-static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret)
++static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret,
++				      int wait_cnt)
+ {
+-#define HCLGE_MAC_LINK_STATUS_NUM  100
+-
+ 	int link_status;
+ 	int i = 0;
+ 	int ret;
+@@ -7813,13 +7814,15 @@ static int hclge_mac_link_status_wait(struct hclge_dev *hdev, int link_ret)
+ 			return 0;
+ 
+ 		msleep(HCLGE_LINK_STATUS_MS);
+-	} while (++i < HCLGE_MAC_LINK_STATUS_NUM);
++	} while (++i < wait_cnt);
+ 	return -EBUSY;
+ }
+ 
+ static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en,
+ 					  bool is_phy)
+ {
++#define HCLGE_MAC_LINK_STATUS_NUM  100
++
+ 	int link_ret;
+ 
+ 	link_ret = en ? HCLGE_LINK_STATUS_UP : HCLGE_LINK_STATUS_DOWN;
+@@ -7827,7 +7830,8 @@ static int hclge_mac_phy_link_status_wait(struct hclge_dev *hdev, bool en,
+ 	if (is_phy)
+ 		hclge_phy_link_status_wait(hdev, link_ret);
+ 
+-	return hclge_mac_link_status_wait(hdev, link_ret);
++	return hclge_mac_link_status_wait(hdev, link_ret,
++					  HCLGE_MAC_LINK_STATUS_NUM);
+ }
+ 
+ static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
+-- 
+2.34.1
+
diff --git a/patches/0604-net-hns3-fix-setting-wrong-tx_timeout-value-issue.patch b/patches/0604-net-hns3-fix-setting-wrong-tx_timeout-value-issue.patch
new file mode 100644
index 0000000..44174b3
--- /dev/null
+++ b/patches/0604-net-hns3-fix-setting-wrong-tx_timeout-value-issue.patch
@@ -0,0 +1,63 @@
+From 7e1a34028c5ab29f6c2a8fda7008a84956d1abc0 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao418@huawei.com>
+Date: Tue, 25 Jul 2023 15:48:37 +0800
+Subject: [PATCH 243/283] net: hns3: fix setting wrong tx_timeout value issue
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+When user set tx_timeout, hns3 driver should set tx_timeout * HZ to
+ndev->watchdog_timeo but tx_timeout.
+
+So, change it to be correct.
+
+Fixes: dd347d0de71ab (net: hns3: add support modified tx timeout)
+Signed-off-by: Hao Chen <chenhao418@huawei.com>
+Signed-off-by: Jijie Shao <shaojijie@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_ext.c | 6 ++++--
+ drivers/net/ethernet/hisilicon/hns3/hns3_ext.h | 1 +
+ 2 files changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 168c9c903158..45189aaea9a3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -326,13 +326,15 @@ EXPORT_SYMBOL(nic_get_port_num_per_chip);
+ 
+ int nic_set_tx_timeout(struct net_device *ndev, int tx_timeout)
+ {
++	int watchdog_timeo = tx_timeout * HZ;
++
+ 	if (nic_netdev_match_check(ndev))
+ 		return -ENODEV;
+ 
+-	if (tx_timeout <= 0)
++	if (watchdog_timeo <= 0 || watchdog_timeo > HNS3_MAX_TX_TIMEOUT)
+ 		return -EINVAL;
+ 
+-	ndev->watchdog_timeo = tx_timeout;
++	ndev->watchdog_timeo = watchdog_timeo;
+ 
+ 	return 0;
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index d9c107f5e231..f883beae8bf4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -13,6 +13,7 @@
+ #define HNS3_PFC_STORM_PARA_ENABLE 1
+ #define HNS3_PFC_STORM_PARA_PERIOD_MIN 5
+ #define HNS3_PFC_STORM_PARA_PERIOD_MAX 2000
++#define HNS3_MAX_TX_TIMEOUT (10 * 60 * HZ)
+ 
+ #define nic_set_8211_phy_reg nic_set_phy_reg
+ #define nic_get_8211_phy_reg nic_get_phy_reg
+-- 
+2.34.1
+
diff --git a/patches/0605-net-hns3-refactor-hclge_cmd_send-with-new-hclge_comm.patch b/patches/0605-net-hns3-refactor-hclge_cmd_send-with-new-hclge_comm.patch
new file mode 100644
index 0000000..631064f
--- /dev/null
+++ b/patches/0605-net-hns3-refactor-hclge_cmd_send-with-new-hclge_comm.patch
@@ -0,0 +1,1314 @@
+From 7900620e28e61fcd7d4970c6b649e292567363b8 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:50 +0800
+Subject: [PATCH 244/283] net: hns3: refactor hclge_cmd_send with new
+ hclge_comm_cmd_send API
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit eaa5607db377a73e639162a459d8b125c6a67bfb
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=eaa5607db377a73e639162a459d8b125c6a67bfb
+
+----------------------------------------------------------------------
+
+This patch firstly uses new hardware description struct hclge_comm_hw as
+child member of hclge_hw and deletes the original child memebers of
+hclge_hw. All the hclge_hw variables used in PF module is modified
+according to the new hclge_hw.
+
+Secondly hclge_cmd_send is refactored to use hclge_comm_cmd_send APIs. The
+old functions called by hclge_cmd_send are deleted and hclge_cmd_send is
+kept to avoid too many meaningless modifications.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/Makefile
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+---
+ drivers/net/ethernet/hisilicon/hns3/Makefile  |   3 +-
+ .../hisilicon/hns3/hns3_cae/hns3_cae_cmd.c    |  68 ++--
+ .../hisilicon/hns3/hns3_cae/hns3_cae_qos.c    |  16 +-
+ .../hisilicon/hns3/hns3_cae/hns3_cae_rss.c    |   6 +-
+ .../hisilicon/hns3/hns3_cae/hns3_cae_stat.c   |  20 +-
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         | 305 +++---------------
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  75 +----
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  65 ++--
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   8 +-
+ .../hisilicon/hns3/hns3pf/hclge_mbx.c         |  11 +-
+ .../hisilicon/hns3/hns3pf/hclge_mdio.c        |   4 +-
+ .../hisilicon/hns3/hns3pf/hclge_ptp.c         |   2 +-
+ 12 files changed, 160 insertions(+), 423 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile
+index 7ff21cdf43b9..95069b38ab65 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/Makefile
+@@ -42,7 +42,6 @@ HCLGE_OBJ = 	hns3pf/hclge_main.o \
+ 			hns3pf/hclge_ptp.o \
+ 			hns3pf/hclge_devlink.o
+ 
+-
+ HCLGE_OBJ_IT_MAIN	=	hns3_extension/hns3pf/hclge_main_it.o \
+ 				hns3_extension/hns3pf/hclge_sysfs.o
+ obj-$(CONFIG_HNS3_HCLGE) += hclge.o
+@@ -53,7 +52,7 @@ hclge-objs += hns3_common/hclge_comm_cmd.o
+ hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o
+ #### compile hclgevf.ko
+ obj-$(CONFIG_HNS3_HCLGEVF) += hclgevf.o
+-hclgevf-objs := hns3vf/hclgevf_main.o hns3vf/hclgevf_cmd.o hns3vf/hclgevf_mbx.o hns3vf/hclgevf_devlink.o
++hclgevf-objs := hns3vf/hclgevf_main.o hns3vf/hclgevf_cmd.o hns3vf/hclgevf_mbx.o hns3vf/hclgevf_devlink.o hns3_common/hclge_comm_cmd.o
+ 
+ #### compile hns3_cae.ko
+ #add rally code
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.c
+index 10ae1eee1ab9..203ee3135f9d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.c
+@@ -3,7 +3,7 @@
+ 
+ #include "hns3_cae_cmd.h"
+ 
+-static int hns3_cae_ring_space(struct hclge_cmq_ring *ring)
++static int hns3_cae_ring_space(struct hclge_comm_cmq_ring *ring)
+ {
+ 	int ntu = ring->next_to_use;
+ 	int ntc = ring->next_to_clean;
+@@ -12,7 +12,7 @@ static int hns3_cae_ring_space(struct hclge_cmq_ring *ring)
+ 	return ring->desc_num - used - 1;
+ }
+ 
+-static int is_valid_csq_clean_head(struct hclge_cmq_ring *ring, int head)
++static int is_valid_csq_clean_head(struct hclge_comm_cmq_ring *ring, int head)
+ {
+ 	int ntu = ring->next_to_use;
+ 	int ntc = ring->next_to_clean;
+@@ -51,29 +51,29 @@ static bool hns3_cae_is_special_opcode(u16 opcode)
+ static int hns3_cae_cmd_convert_err_code(u16 desc_ret)
+ {
+ 	switch (desc_ret) {
+-	case HCLGE_CMD_EXEC_SUCCESS:
++	case HCLGE_COMM_CMD_EXEC_SUCCESS:
+ 		return 0;
+-	case HCLGE_CMD_NO_AUTH:
++	case HCLGE_COMM_CMD_NO_AUTH:
+ 		return -EPERM;
+-	case HCLGE_CMD_NOT_SUPPORTED:
++	case HCLGE_COMM_CMD_NOT_SUPPORTED:
+ 		return -EOPNOTSUPP;
+-	case HCLGE_CMD_QUEUE_FULL:
++	case HCLGE_COMM_CMD_QUEUE_FULL:
+ 		return -EXFULL;
+-	case HCLGE_CMD_NEXT_ERR:
++	case HCLGE_COMM_CMD_NEXT_ERR:
+ 		return -ENOSR;
+-	case HCLGE_CMD_UNEXE_ERR:
++	case HCLGE_COMM_CMD_UNEXE_ERR:
+ 		return -ENOTBLK;
+-	case HCLGE_CMD_PARA_ERR:
++	case HCLGE_COMM_CMD_PARA_ERR:
+ 		return -EINVAL;
+-	case HCLGE_CMD_RESULT_ERR:
++	case HCLGE_COMM_CMD_RESULT_ERR:
+ 		return -ERANGE;
+-	case HCLGE_CMD_TIMEOUT:
++	case HCLGE_COMM_CMD_TIMEOUT:
+ 		return -ETIME;
+-	case HCLGE_CMD_HILINK_ERR:
++	case HCLGE_COMM_CMD_HILINK_ERR:
+ 		return -ENOLINK;
+-	case HCLGE_CMD_QUEUE_ILLEGAL:
++	case HCLGE_COMM_CMD_QUEUE_ILLEGAL:
+ 		return -ENXIO;
+-	case HCLGE_CMD_INVALID:
++	case HCLGE_COMM_CMD_INVALID:
+ 		return -EBADR;
+ 	default:
+ 		return -EIO;
+@@ -84,13 +84,13 @@ static int hns3_cae_cmd_csq_done(struct hclge_hw *hw)
+ {
+ 	u32 head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
+ 
+-	return head == hw->cmq.csq.next_to_use;
++	return head == hw->hw.cmq.csq.next_to_use;
+ }
+ 
+ static int hns3_cae_cmd_csq_clean(struct hclge_hw *hw)
+ {
+ 	struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
+-	struct hclge_cmq_ring *csq = &hw->cmq.csq;
++	struct hclge_comm_cmq_ring *csq = &hw->hw.cmq.csq;
+ 	int clean;
+ 	u32 head;
+ 
+@@ -120,9 +120,9 @@ static int hns3_cae_cmd_check_retval(struct hclge_hw *hw,
+ 
+ 	opcode = le16_to_cpu(desc[0].opcode);
+ 	for (handle = 0; handle < num; handle++) {
+-		desc[handle] = hw->cmq.csq.desc[ntc];
++		desc[handle] = hw->hw.cmq.csq.desc[ntc];
+ 		ntc++;
+-		if (ntc >= hw->cmq.csq.desc_num)
++		if (ntc >= hw->hw.cmq.csq.desc_num)
+ 			ntc = 0;
+ 	}
+ 	if (likely(!hns3_cae_is_special_opcode(opcode)))
+@@ -130,7 +130,7 @@ static int hns3_cae_cmd_check_retval(struct hclge_hw *hw,
+ 	else
+ 		desc_ret = le16_to_cpu(desc[0].retval);
+ 
+-	hw->cmq.last_status = desc_ret;
++	hw->hw.cmq.last_status = desc_ret;
+ 
+ 	return hns3_cae_cmd_convert_err_code(desc_ret);
+ }
+@@ -167,28 +167,28 @@ void hns3_cae_cmd_setup_basic_desc(struct hclge_desc *desc,
+ int hns3_cae_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc, int num)
+ {
+ 	struct hclge_desc *desc_to_use = NULL;
+-	struct hclge_cmq_ring *csq = NULL;
++	struct hclge_comm_cmq_ring *csq = NULL;
+ 	bool complete = false;
+ 	u32 timeout = 0;
+ 	int handle = 0;
+ 	int retval;
+ 	int ntc;
+ 
+-	csq = &hdev->hw.cmq.csq;
+-	spin_lock_bh(&hdev->hw.cmq.csq.lock);
++	csq = &hdev->hw.hw.cmq.csq;
++	spin_lock_bh(&hdev->hw.hw.cmq.csq.lock);
+ 
+ 	if (test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) {
+-		spin_unlock_bh(&hdev->hw.cmq.csq.lock);
++		spin_unlock_bh(&hdev->hw.hw.cmq.csq.lock);
+ 		return -EBUSY;
+ 	}
+ 
+-	if (num > hns3_cae_ring_space(&hdev->hw.cmq.csq)) {
++	if (num > hns3_cae_ring_space(&hdev->hw.hw.cmq.csq)) {
+ 		/* If CMDQ ring is full, SW HEAD and HW HEAD may be different,
+ 		 * need update the SW HEAD pointer csq->next_to_clean
+ 		 */
+ 		csq->next_to_clean = hclge_read_dev(&hdev->hw,
+ 						    HCLGE_NIC_CSQ_HEAD_REG);
+-		spin_unlock_bh(&hdev->hw.cmq.csq.lock);
++		spin_unlock_bh(&hdev->hw.hw.cmq.csq.lock);
+ 		return -EBUSY;
+ 	}
+ 
+@@ -196,26 +196,26 @@ int hns3_cae_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc, int num)
+ 	 * Record the location of desc in the ring for this time
+ 	 * which will be use for hardware to write back
+ 	 */
+-	ntc = hdev->hw.cmq.csq.next_to_use;
++	ntc = hdev->hw.hw.cmq.csq.next_to_use;
+ 	while (handle < num) {
+ 		desc_to_use =
+-			&hdev->hw.cmq.csq.desc[hdev->hw.cmq.csq.next_to_use];
++			&hdev->hw.hw.cmq.csq.desc[hdev->hw.hw.cmq.csq.next_to_use];
+ 		*desc_to_use = desc[handle];
+-		(hdev->hw.cmq.csq.next_to_use)++;
+-		if (hdev->hw.cmq.csq.next_to_use >= hdev->hw.cmq.csq.desc_num)
+-			hdev->hw.cmq.csq.next_to_use = 0;
++		(hdev->hw.hw.cmq.csq.next_to_use)++;
++		if (hdev->hw.hw.cmq.csq.next_to_use >= hdev->hw.hw.cmq.csq.desc_num)
++			hdev->hw.hw.cmq.csq.next_to_use = 0;
+ 		handle++;
+ 	}
+ 
+ 	/* Write to hardware */
+ 	hclge_write_dev(&hdev->hw, HCLGE_NIC_CSQ_TAIL_REG,
+-			hdev->hw.cmq.csq.next_to_use);
++			hdev->hw.hw.cmq.csq.next_to_use);
+ 
+ 	/**
+ 	 * If the command is sync, wait for the firmware to write back,
+ 	 * if multi descriptors to be sent, use the first one to check
+ 	 */
+-	if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) {
++	if (HCLGE_COMM_SEND_SYNC(le16_to_cpu(desc->flag))) {
+ 		do {
+ 			if (hns3_cae_cmd_csq_done(&hdev->hw)) {
+ 				complete = true;
+@@ -223,7 +223,7 @@ int hns3_cae_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc, int num)
+ 			}
+ 			udelay(1);
+ 			timeout++;
+-		} while (timeout < hdev->hw.cmq.tx_timeout);
++		} while (timeout < hdev->hw.hw.cmq.tx_timeout);
+ 	}
+ 
+ 	if (!complete)
+@@ -238,7 +238,7 @@ int hns3_cae_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc, int num)
+ 		dev_warn(&hdev->pdev->dev,
+ 			 "cleaned %d, need to clean %d\n", handle, num);
+ 
+-	spin_unlock_bh(&hdev->hw.cmq.csq.lock);
++	spin_unlock_bh(&hdev->hw.hw.cmq.csq.lock);
+ 
+ 	return retval;
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_qos.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_qos.c
+index fb872de05c97..4bbe8bbcfe03 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_qos.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_qos.c
+@@ -21,7 +21,7 @@ int hns3_cmd_rx_priv_wl_config(struct hclge_dev *hdev, u16 tc,
+ 			       u32 high, u32 low, u32 en)
+ {
+ 	struct hclge_rx_priv_wl_buf *req = NULL;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_desc desc[2];
+ 	int idx;
+ 	int i;
+@@ -94,7 +94,7 @@ int hns3_cmd_common_thrd_config(struct hclge_dev *hdev, u16 tc,
+ {
+ #define HNS3_CAE_THRD_ALLOC_BD_NUM	2
+ 	struct hclge_rx_com_thrd *req = NULL;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_desc desc[2];
+ 	int idx;
+ 	int i;
+@@ -166,7 +166,7 @@ int hns3_cae_common_thrd_cfg(const struct hns3_nic_priv *net_priv,
+ 
+ int hns3_cmd_common_wl_config(struct hclge_dev *hdev, u32 high, u32 low, u32 en)
+ {
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_rx_com_wl *req = NULL;
+ 	struct hclge_desc desc;
+ 
+@@ -196,7 +196,7 @@ int hns3_cae_common_wl_cfg(const struct hns3_nic_priv *net_priv,
+ 				    (struct hns3_rx_priv_buff_wl_param *)buf_in;
+ 	bool check = !buf_in ||
+ 		     in_size < sizeof(struct hns3_rx_priv_buff_wl_param);
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_rx_com_wl *req = NULL;
+ 	struct hclge_vport *vport = NULL;
+ 	struct hclge_desc desc;
+@@ -248,7 +248,7 @@ int hns3_cae_rx_buff_cfg(const struct hns3_nic_priv *net_priv,
+ 					   (struct hns3_rx_buff_param *)buf_out;
+ 	struct hns3_rx_buff_param *in_info =
+ 					    (struct hns3_rx_buff_param *)buf_in;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_vport *vport = NULL;
+ 	struct hclge_dev *hdev = NULL;
+ 	struct hclge_desc desc;
+@@ -293,7 +293,7 @@ int hns3_cae_tx_buff_cfg(const struct hns3_nic_priv *net_priv,
+ 					   (struct hns3_tx_buff_param *)buf_out;
+ 	struct hns3_tx_buff_param *in_info =
+ 					    (struct hns3_tx_buff_param *)buf_in;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_vport *vport = NULL;
+ 	struct hclge_desc desc;
+ 	struct hclge_dev *hdev = NULL;
+@@ -335,7 +335,7 @@ int hns3_cae_show_comm_thres(const struct hns3_nic_priv *net_priv,
+ 	struct hns3_total_priv_wl_param *out_info =
+ 				     (struct hns3_total_priv_wl_param *)buf_out;
+ 	struct hclge_rx_com_thrd *req = NULL;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_desc desc[2];
+ 	bool check = !buf_out ||
+ 		     out_size < sizeof(struct hns3_total_priv_wl_param);
+@@ -386,7 +386,7 @@ int hns3_cae_show_rx_priv_wl(const struct hns3_nic_priv *net_priv,
+ 	struct hns3_total_priv_wl_param *out_info =
+ 				     (struct hns3_total_priv_wl_param *)buf_out;
+ 	struct hclge_rx_priv_wl_buf *req = NULL;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_desc desc[2];
+ 	bool check = !buf_out ||
+ 		     out_size < sizeof(struct hns3_total_priv_wl_param);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_rss.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_rss.c
+index f263156bc547..e62f8585d7ec 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_rss.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_rss.c
+@@ -23,7 +23,7 @@ static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
+ 				  const u8 hfunc, const u8 *key)
+ {
+ 	struct hclge_rss_config_cmd *req = NULL;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_desc desc;
+ 	int key_offset;
+ 	int key_size;
+@@ -64,7 +64,7 @@ static int hns3_cae_set_rss_cfg(const struct hns3_nic_priv *net_priv,
+ 	struct hclge_vport *vport = hns3_cae_get_vport(net_priv->ae_handle);
+ 	struct hclge_dev *hdev = vport->back;
+ 	u8 *key = vport->rss_hash_key;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	u8 hash_config;
+ 
+ 	if (check) {
+@@ -93,7 +93,7 @@ static int hns3_cae_get_rss_cfg(const struct hns3_nic_priv *net_priv,
+ 	bool check = !buf_out || out_size < sizeof(u8);
+ 	struct hclge_rss_config_cmd *req = NULL;
+ 	struct hclge_dev *hdev = vport->back;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	u8 *out_buf = (u8 *)buf_out;
+ 	struct hclge_desc desc;
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_stat.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_stat.c
+index 684d72953c30..fe68f6908224 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_stat.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_stat.c
+@@ -30,7 +30,7 @@ static int hns3_get_stat_val(struct ring_stats *r_stats, char *val_name,
+ 
+ 	if (!r_stats || !val_name || !val || strlen(val_name) >= max_name_len) {
+ 		pr_info("%s param is null.\n", __func__);
+-		return HCLGE_ERR_CSQ_ERROR;
++		return HCLGE_COMM_ERR_CSQ_ERROR;
+ 	}
+ 
+ 	*val = NULL;
+@@ -92,10 +92,10 @@ static int hns3_get_stat_val(struct ring_stats *r_stats, char *val_name,
+ 		break;
+ 	default:
+ 		pr_info("val name [%s] is not existed.\n", val_name);
+-		return HCLGE_ERR_CSQ_ERROR;
++		return HCLGE_COMM_ERR_CSQ_ERROR;
+ 	}
+ 
+-	return HCLGE_STATUS_SUCCESS;
++	return HCLGE_COMM_STATUS_SUCCESS;
+ }
+ 
+ static int hns3_read_stat_mode_cfg(const struct hns3_nic_priv *nic_dev,
+@@ -119,7 +119,7 @@ static int hns3_read_stat_mode_cfg(const struct hns3_nic_priv *nic_dev,
+ 	stat_sw_param = (struct stat_sw_mode_param *)buf_in;
+ 	if (!buf_out || out_size < sizeof(u64)) {
+ 		dev_err(&hdev->pdev->dev, "Get stat buf out is null.\n");
+-		return HCLGE_ERR_CSQ_ERROR;
++		return HCLGE_COMM_ERR_CSQ_ERROR;
+ 	}
+ 
+ 	ring_idx = stat_sw_param->ring_idx;
+@@ -127,7 +127,7 @@ static int hns3_read_stat_mode_cfg(const struct hns3_nic_priv *nic_dev,
+ 		dev_err(&hdev->pdev->dev,
+ 			"Get stat ring_idx[%d] >= num_tqps[%d].\n", ring_idx,
+ 			kinfo->num_tqps);
+-		return HCLGE_ERR_CSQ_ERROR;
++		return HCLGE_COMM_ERR_CSQ_ERROR;
+ 	}
+ 
+ 	if (stat_sw_param->is_rx)
+@@ -139,12 +139,12 @@ static int hns3_read_stat_mode_cfg(const struct hns3_nic_priv *nic_dev,
+ 	if (ret || !val) {
+ 		pr_info("get stat val name [%s] error.\n",
+ 			stat_sw_param->val_name);
+-		return HCLGE_ERR_CSQ_ERROR;
++		return HCLGE_COMM_ERR_CSQ_ERROR;
+ 	}
+ 
+ 	*ret_data = le64_to_cpu(*val);
+ 
+-	return HCLGE_STATUS_SUCCESS;
++	return HCLGE_COMM_STATUS_SUCCESS;
+ }
+ 
+ static int hns3_set_stat_mode_cfg(const struct hns3_nic_priv *nic_dev,
+@@ -170,7 +170,7 @@ static int hns3_set_stat_mode_cfg(const struct hns3_nic_priv *nic_dev,
+ 		dev_err(&hdev->pdev->dev,
+ 			"Set stat ring_idx[%d] >= num_tqps[%d].\n", ring_idx,
+ 			kinfo->num_tqps);
+-		return HCLGE_ERR_CSQ_ERROR;
++		return HCLGE_COMM_ERR_CSQ_ERROR;
+ 	}
+ 
+ 	if (stat_sw_param->is_rx)
+@@ -182,12 +182,12 @@ static int hns3_set_stat_mode_cfg(const struct hns3_nic_priv *nic_dev,
+ 	if (ret || !val) {
+ 		pr_info("Set stat val name [%s] error.\n",
+ 			stat_sw_param->val_name);
+-		return HCLGE_ERR_CSQ_ERROR;
++		return HCLGE_COMM_ERR_CSQ_ERROR;
+ 	}
+ 
+ 	*val = cpu_to_le64(stat_sw_param->data);
+ 
+-	return HCLGE_STATUS_SUCCESS;
++	return HCLGE_COMM_STATUS_SUCCESS;
+ }
+ 
+ int hns3_stat_mode_cfg(const struct hns3_nic_priv *nic_dev,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 6d9c3945328a..dc73c90605dc 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -12,29 +12,7 @@
+ #include "hnae3.h"
+ #include "hclge_main.h"
+ 
+-#define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
+-
+-static int hclge_ring_space(struct hclge_cmq_ring *ring)
+-{
+-	int ntu = ring->next_to_use;
+-	int ntc = ring->next_to_clean;
+-	int used = (ntu - ntc + ring->desc_num) % ring->desc_num;
+-
+-	return ring->desc_num - used - 1;
+-}
+-
+-static int is_valid_csq_clean_head(struct hclge_cmq_ring *ring, int head)
+-{
+-	int ntu = ring->next_to_use;
+-	int ntc = ring->next_to_clean;
+-
+-	if (ntu > ntc)
+-		return head >= ntc && head <= ntu;
+-
+-	return head >= ntc || head <= ntu;
+-}
+-
+-static int hclge_alloc_cmd_desc(struct hclge_cmq_ring *ring)
++static int hclge_alloc_cmd_desc(struct hclge_comm_cmq_ring *ring)
+ {
+ 	int size  = ring->desc_num * sizeof(struct hclge_desc);
+ 
+@@ -47,12 +25,12 @@ static int hclge_alloc_cmd_desc(struct hclge_cmq_ring *ring)
+ 	return 0;
+ }
+ 
+-static void hclge_free_cmd_desc(struct hclge_cmq_ring *ring)
++static void hclge_free_cmd_desc(struct hclge_comm_cmq_ring *ring)
+ {
+ 	int size  = ring->desc_num * sizeof(struct hclge_desc);
+ 
+ 	if (ring->desc) {
+-		dma_free_coherent(cmq_ring_to_dev(ring), size,
++		dma_free_coherent(&ring->pdev->dev, size,
+ 				  ring->desc, ring->desc_dma_addr);
+ 		ring->desc = NULL;
+ 	}
+@@ -61,12 +39,13 @@ static void hclge_free_cmd_desc(struct hclge_cmq_ring *ring)
+ static int hclge_alloc_cmd_queue(struct hclge_dev *hdev, int ring_type)
+ {
+ 	struct hclge_hw *hw = &hdev->hw;
+-	struct hclge_cmq_ring *ring =
+-		(ring_type == HCLGE_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
++	struct hclge_comm_cmq_ring *ring =
++		(ring_type == HCLGE_TYPE_CSQ) ? &hw->hw.cmq.csq :
++						&hw->hw.cmq.crq;
+ 	int ret;
+ 
+ 	ring->ring_type = ring_type;
+-	ring->dev = hdev;
++	ring->pdev = hdev->pdev;
+ 
+ 	ret = hclge_alloc_cmd_desc(ring);
+ 	if (ret) {
+@@ -98,11 +77,10 @@ void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
+ 		desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
+ }
+ 
+-static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring)
++static void hclge_cmd_config_regs(struct hclge_hw *hw,
++				  struct hclge_comm_cmq_ring *ring)
+ {
+ 	dma_addr_t dma = ring->desc_dma_addr;
+-	struct hclge_dev *hdev = ring->dev;
+-	struct hclge_hw *hw = &hdev->hw;
+ 	u32 reg_val;
+ 
+ 	if (ring->ring_type == HCLGE_TYPE_CSQ) {
+@@ -144,174 +122,8 @@ static void hclge_cmd_clear_regs(struct hclge_hw *hw)
+ 
+ static void hclge_cmd_init_regs(struct hclge_hw *hw)
+ {
+-	hclge_cmd_config_regs(&hw->cmq.csq);
+-	hclge_cmd_config_regs(&hw->cmq.crq);
+-}
+-
+-static int hclge_cmd_csq_clean(struct hclge_hw *hw)
+-{
+-	struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
+-	struct hclge_cmq_ring *csq = &hw->cmq.csq;
+-	u32 head;
+-	int clean;
+-
+-	head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
+-	rmb(); /* Make sure head is ready before touch any data */
+-
+-	if (!is_valid_csq_clean_head(csq, head)) {
+-		dev_warn(&hdev->pdev->dev, "wrong cmd head (%u, %d-%d)\n", head,
+-			 csq->next_to_use, csq->next_to_clean);
+-		dev_warn(&hdev->pdev->dev,
+-			 "Disabling any further commands to IMP firmware\n");
+-		set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
+-		dev_warn(&hdev->pdev->dev,
+-			 "IMP firmware watchdog reset soon expected!\n");
+-		return -EIO;
+-	}
+-
+-	clean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num;
+-	csq->next_to_clean = head;
+-	return clean;
+-}
+-
+-static int hclge_cmd_csq_done(struct hclge_hw *hw)
+-{
+-	u32 head = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
+-	return head == hw->cmq.csq.next_to_use;
+-}
+-
+-static bool hclge_is_special_opcode(u16 opcode)
+-{
+-	/* these commands have several descriptors,
+-	 * and use the first one to save opcode and return value
+-	 */
+-	u16 spec_opcode[] = {HCLGE_OPC_STATS_64_BIT,
+-			     HCLGE_OPC_STATS_32_BIT,
+-			     HCLGE_OPC_STATS_MAC,
+-			     HCLGE_OPC_STATS_MAC_ALL,
+-			     HCLGE_OPC_QUERY_32_BIT_REG,
+-			     HCLGE_OPC_QUERY_64_BIT_REG,
+-			     HCLGE_QUERY_CLEAR_MPF_RAS_INT,
+-			     HCLGE_QUERY_CLEAR_PF_RAS_INT,
+-			     HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
+-			     HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT,
+-			     HCLGE_QUERY_ALL_ERR_INFO};
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
+-		if (spec_opcode[i] == opcode)
+-			return true;
+-	}
+-
+-	return false;
+-}
+-
+-struct errcode {
+-	u32 imp_errcode;
+-	int common_errno;
+-};
+-
+-static void hclge_cmd_copy_desc(struct hclge_hw *hw, struct hclge_desc *desc,
+-				int num)
+-{
+-	struct hclge_desc *desc_to_use;
+-	int handle = 0;
+-
+-	while (handle < num) {
+-		desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
+-		*desc_to_use = desc[handle];
+-		(hw->cmq.csq.next_to_use)++;
+-		if (hw->cmq.csq.next_to_use >= hw->cmq.csq.desc_num)
+-			hw->cmq.csq.next_to_use = 0;
+-		handle++;
+-	}
+-}
+-
+-static int hclge_cmd_convert_err_code(u16 desc_ret)
+-{
+-	struct errcode hclge_cmd_errcode[] = {
+-		{HCLGE_CMD_EXEC_SUCCESS, 0},
+-		{HCLGE_CMD_NO_AUTH, -EPERM},
+-		{HCLGE_CMD_NOT_SUPPORTED, -EOPNOTSUPP},
+-		{HCLGE_CMD_QUEUE_FULL, -EXFULL},
+-		{HCLGE_CMD_NEXT_ERR, -ENOSR},
+-		{HCLGE_CMD_UNEXE_ERR, -ENOTBLK},
+-		{HCLGE_CMD_PARA_ERR, -EINVAL},
+-		{HCLGE_CMD_RESULT_ERR, -ERANGE},
+-		{HCLGE_CMD_TIMEOUT, -ETIME},
+-		{HCLGE_CMD_HILINK_ERR, -ENOLINK},
+-		{HCLGE_CMD_QUEUE_ILLEGAL, -ENXIO},
+-		{HCLGE_CMD_INVALID, -EBADR},
+-	};
+-	u32 errcode_count = ARRAY_SIZE(hclge_cmd_errcode);
+-	u32 i;
+-
+-	for (i = 0; i < errcode_count; i++)
+-		if (hclge_cmd_errcode[i].imp_errcode == desc_ret)
+-			return hclge_cmd_errcode[i].common_errno;
+-
+-	return -EIO;
+-}
+-
+-static int hclge_cmd_check_retval(struct hclge_hw *hw, struct hclge_desc *desc,
+-				  int num, int ntc)
+-{
+-	u16 opcode, desc_ret;
+-	int handle;
+-
+-	opcode = le16_to_cpu(desc[0].opcode);
+-	for (handle = 0; handle < num; handle++) {
+-		desc[handle] = hw->cmq.csq.desc[ntc];
+-		ntc++;
+-		if (ntc >= hw->cmq.csq.desc_num)
+-			ntc = 0;
+-	}
+-	if (likely(!hclge_is_special_opcode(opcode)))
+-		desc_ret = le16_to_cpu(desc[num - 1].retval);
+-	else
+-		desc_ret = le16_to_cpu(desc[0].retval);
+-
+-	hw->cmq.last_status = desc_ret;
+-
+-	return hclge_cmd_convert_err_code(desc_ret);
+-}
+-
+-static int hclge_cmd_check_result(struct hclge_hw *hw, struct hclge_desc *desc,
+-				  int num, int ntc)
+-{
+-	struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
+-	bool is_completed = false;
+-	u32 timeout = 0;
+-	int handle, ret;
+-
+-	/**
+-	 * If the command is sync, wait for the firmware to write back,
+-	 * if multi descriptors to be sent, use the first one to check
+-	 */
+-	if (HCLGE_SEND_SYNC(le16_to_cpu(desc->flag))) {
+-		do {
+-			if (hclge_cmd_csq_done(hw)) {
+-				is_completed = true;
+-				break;
+-			}
+-			udelay(1);
+-			timeout++;
+-		} while (timeout < hw->cmq.tx_timeout);
+-	}
+-
+-	if (!is_completed)
+-		ret = -EBADE;
+-	else
+-		ret = hclge_cmd_check_retval(hw, desc, num, ntc);
+-
+-	/* Clean the command send queue */
+-	handle = hclge_cmd_csq_clean(hw);
+-	if (handle < 0)
+-		ret = handle;
+-	else if (handle != num)
+-		dev_warn(&hdev->pdev->dev,
+-			 "cleaned %d, need to clean %d\n", handle, num);
+-	return ret;
++	hclge_cmd_config_regs(hw, &hw->hw.cmq.csq);
++	hclge_cmd_config_regs(hw, &hw->hw.cmq.crq);
+ }
+ 
+ /**
+@@ -325,43 +137,7 @@ static int hclge_cmd_check_result(struct hclge_hw *hw, struct hclge_desc *desc,
+  **/
+ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
+ {
+-	struct hclge_dev *hdev = container_of(hw, struct hclge_dev, hw);
+-	struct hclge_cmq_ring *csq = &hw->cmq.csq;
+-	int ret;
+-	int ntc;
+-
+-	spin_lock_bh(&hw->cmq.csq.lock);
+-
+-	if (test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) {
+-		spin_unlock_bh(&hw->cmq.csq.lock);
+-		return -EBUSY;
+-	}
+-
+-	if (num > hclge_ring_space(&hw->cmq.csq)) {
+-		/* If CMDQ ring is full, SW HEAD and HW HEAD may be different,
+-		 * need update the SW HEAD pointer csq->next_to_clean
+-		 */
+-		csq->next_to_clean = hclge_read_dev(hw, HCLGE_NIC_CSQ_HEAD_REG);
+-		spin_unlock_bh(&hw->cmq.csq.lock);
+-		return -EBUSY;
+-	}
+-
+-	/**
+-	 * Record the location of desc in the ring for this time
+-	 * which will be use for hardware to write back
+-	 */
+-	ntc = hw->cmq.csq.next_to_use;
+-
+-	hclge_cmd_copy_desc(hw, desc, num);
+-
+-	/* Write to hardware */
+-	hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, hw->cmq.csq.next_to_use);
+-
+-	ret = hclge_cmd_check_result(hw, desc, num, ntc);
+-
+-	spin_unlock_bh(&hw->cmq.csq.lock);
+-
+-	return ret;
++	return hclge_comm_cmd_send(&hw->hw, desc, num);
+ }
+ 
+ static void hclge_set_default_capability(struct hclge_dev *hdev)
+@@ -403,7 +179,7 @@ static void hclge_parse_capability(struct hclge_dev *hdev,
+ 				ae_dev->caps);
+ }
+ 
+-static enum hclge_cmd_status
++static enum hclge_comm_cmd_status
+ hclge_cmd_query_version_and_capability(struct hclge_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+@@ -434,11 +210,15 @@ hclge_cmd_query_version_and_capability(struct hclge_dev *hdev)
+ 
+ int hclge_cmd_queue_init(struct hclge_dev *hdev)
+ {
++	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+ 	int ret;
+ 
+ 	/* Setup the lock for command queue */
+-	spin_lock_init(&hdev->hw.cmq.csq.lock);
+-	spin_lock_init(&hdev->hw.cmq.crq.lock);
++	spin_lock_init(&cmdq->csq.lock);
++	spin_lock_init(&cmdq->crq.lock);
++
++	cmdq->csq.pdev = hdev->pdev;
++	cmdq->crq.pdev = hdev->pdev;
+ 
+ 	/* clear up all command register,
+ 	 * in case there are some residual values
+@@ -446,11 +226,11 @@ int hclge_cmd_queue_init(struct hclge_dev *hdev)
+ 	hclge_cmd_clear_regs(&hdev->hw);
+ 
+ 	/* Setup the queue entries for use cmd queue */
+-	hdev->hw.cmq.csq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
+-	hdev->hw.cmq.crq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
++	cmdq->csq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
++	cmdq->crq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
+ 
+ 	/* Setup Tx write back timeout */
+-	hdev->hw.cmq.tx_timeout = HCLGE_CMDQ_TX_TIMEOUT;
++	cmdq->tx_timeout = HCLGE_CMDQ_TX_TIMEOUT;
+ 
+ 	/* Setup queue rings */
+ 	ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CSQ);
+@@ -469,7 +249,7 @@ int hclge_cmd_queue_init(struct hclge_dev *hdev)
+ 
+ 	return 0;
+ err_csq:
+-	hclge_free_cmd_desc(&hdev->hw.cmq.csq);
++	hclge_free_cmd_desc(&hdev->hw.hw.cmq.csq);
+ 	return ret;
+ }
+ 
+@@ -500,22 +280,23 @@ static int hclge_firmware_compat_config(struct hclge_dev *hdev, bool en)
+ 
+ int hclge_cmd_init(struct hclge_dev *hdev)
+ {
++	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+ 	int ret;
+ 
+-	spin_lock_bh(&hdev->hw.cmq.csq.lock);
+-	spin_lock(&hdev->hw.cmq.crq.lock);
++	spin_lock_bh(&cmdq->csq.lock);
++	spin_lock(&cmdq->crq.lock);
+ 
+-	hdev->hw.cmq.csq.next_to_clean = 0;
+-	hdev->hw.cmq.csq.next_to_use = 0;
+-	hdev->hw.cmq.crq.next_to_clean = 0;
+-	hdev->hw.cmq.crq.next_to_use = 0;
++	cmdq->csq.next_to_clean = 0;
++	cmdq->csq.next_to_use = 0;
++	cmdq->crq.next_to_clean = 0;
++	cmdq->crq.next_to_use = 0;
+ 
+ 	hclge_cmd_init_regs(&hdev->hw);
+ 
+-	spin_unlock(&hdev->hw.cmq.crq.lock);
+-	spin_unlock_bh(&hdev->hw.cmq.csq.lock);
++	spin_unlock(&cmdq->crq.lock);
++	spin_unlock_bh(&cmdq->csq.lock);
+ 
+-	clear_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
++	clear_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 
+ 	/* Check if there is new reset pending, because the higher level
+ 	 * reset may happen when lower level reset is being processed.
+@@ -559,26 +340,30 @@ int hclge_cmd_init(struct hclge_dev *hdev)
+ 	return 0;
+ 
+ err_cmd_init:
+-	set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
++	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 
+ 	return ret;
+ }
+ 
+ void hclge_cmd_uninit(struct hclge_dev *hdev)
+ {
++	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
++
++	cmdq->csq.pdev = hdev->pdev;
++
+ 	hclge_firmware_compat_config(hdev, false);
+ 
+-	set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
++	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 	/* wait to ensure that the firmware completes the possible left
+ 	 * over commands.
+ 	 */
+ 	msleep(HCLGE_CMDQ_CLEAR_WAIT_TIME);
+-	spin_lock_bh(&hdev->hw.cmq.csq.lock);
+-	spin_lock(&hdev->hw.cmq.crq.lock);
++	spin_lock_bh(&cmdq->csq.lock);
++	spin_lock(&cmdq->crq.lock);
+ 	hclge_cmd_clear_regs(&hdev->hw);
+-	spin_unlock(&hdev->hw.cmq.crq.lock);
+-	spin_unlock_bh(&hdev->hw.cmq.csq.lock);
++	spin_unlock(&cmdq->crq.lock);
++	spin_unlock_bh(&cmdq->csq.lock);
+ 
+-	hclge_free_cmd_desc(&hdev->hw.cmq.csq);
+-	hclge_free_cmd_desc(&hdev->hw.cmq.crq);
++	hclge_free_cmd_desc(&cmdq->csq);
++	hclge_free_cmd_desc(&cmdq->crq);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 8d1914041bd1..1a980ba5e59d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -11,63 +11,18 @@
+ 
+ #define HCLGE_CMDQ_TX_TIMEOUT		30000
+ #define HCLGE_CMDQ_CLEAR_WAIT_TIME	200
+-#define HCLGE_DESC_DATA_LEN		6
+ 
+ struct hclge_dev;
+ 
+ #define HCLGE_CMDQ_RX_INVLD_B		0
+ #define HCLGE_CMDQ_RX_OUTVLD_B		1
+ 
+-struct hclge_cmq_ring {
+-	dma_addr_t desc_dma_addr;
+-	struct hclge_desc *desc;
+-	struct hclge_dev *dev;
+-	u32 head;
+-	u32 tail;
+-
+-	u16 buf_size;
+-	u16 desc_num;
+-	int next_to_use;
+-	int next_to_clean;
+-	u8 ring_type; /* cmq ring type */
+-	spinlock_t lock; /* Command queue lock */
+-};
+-
+-enum hclge_cmd_return_status {
+-	HCLGE_CMD_EXEC_SUCCESS	= 0,
+-	HCLGE_CMD_NO_AUTH	= 1,
+-	HCLGE_CMD_NOT_SUPPORTED	= 2,
+-	HCLGE_CMD_QUEUE_FULL	= 3,
+-	HCLGE_CMD_NEXT_ERR	= 4,
+-	HCLGE_CMD_UNEXE_ERR	= 5,
+-	HCLGE_CMD_PARA_ERR	= 6,
+-	HCLGE_CMD_RESULT_ERR	= 7,
+-	HCLGE_CMD_TIMEOUT	= 8,
+-	HCLGE_CMD_HILINK_ERR	= 9,
+-	HCLGE_CMD_QUEUE_ILLEGAL	= 10,
+-	HCLGE_CMD_INVALID	= 11,
+-};
+-
+-enum hclge_cmd_status {
+-	HCLGE_STATUS_SUCCESS	= 0,
+-	HCLGE_ERR_CSQ_FULL	= -1,
+-	HCLGE_ERR_CSQ_TIMEOUT	= -2,
+-	HCLGE_ERR_CSQ_ERROR	= -3,
+-};
+-
+ struct hclge_misc_vector {
+ 	u8 __iomem *addr;
+ 	int vector_irq;
+ 	char name[HNAE3_INT_NAME_LEN];
+ };
+ 
+-struct hclge_cmq {
+-	struct hclge_cmq_ring csq;
+-	struct hclge_cmq_ring crq;
+-	u16 tx_timeout;
+-	enum hclge_cmd_status last_status;
+-};
+-
+ #define HCLGE_CMD_FLAG_IN	BIT(0)
+ #define HCLGE_CMD_FLAG_OUT	BIT(1)
+ #define HCLGE_CMD_FLAG_NEXT	BIT(2)
+@@ -329,6 +284,9 @@ enum hclge_opcode_type {
+ #define HCLGE_TQP_REG_OFFSET		0x80000
+ #define HCLGE_TQP_REG_SIZE		0x200
+ 
++#define HCLGE_TQP_MAX_SIZE_DEV_V2	1024
++#define HCLGE_TQP_EXT_REG_OFFSET	0x100
++
+ #define HCLGE_RCB_INIT_QUERY_TIMEOUT	10
+ #define HCLGE_RCB_INIT_FLAG_EN_B	0
+ #define HCLGE_RCB_INIT_FLAG_FINI_B	8
+@@ -1289,25 +1247,6 @@ struct hclge_caps_bit_map {
+ };
+ 
+ int hclge_cmd_init(struct hclge_dev *hdev);
+-static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
+-{
+-	writel(value, base + reg);
+-}
+-
+-#define hclge_write_dev(a, reg, value) \
+-	hclge_write_reg((a)->io_base, reg, value)
+-#define hclge_read_dev(a, reg) \
+-	hclge_read_reg((a)->io_base, reg)
+-
+-static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
+-{
+-	u8 __iomem *reg_addr = READ_ONCE(base);
+-
+-	return readl(reg_addr + reg);
+-}
+-
+-#define HCLGE_SEND_SYNC(flag) \
+-	((flag) & HCLGE_CMD_FLAG_NO_INTR)
+ enum HCLGE_WOL_MODE {
+ 	HCLGE_WOL_PHY           = BIT(0),
+ 	HCLGE_WOL_UNICAST       = BIT(1),
+@@ -1338,10 +1277,10 @@ void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
+ 				enum hclge_opcode_type opcode, bool is_read);
+ void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
+ 
+-enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
+-					   struct hclge_desc *desc);
+-enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
+-					  struct hclge_desc *desc);
++enum hclge_comm_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
++						struct hclge_desc *desc);
++enum hclge_comm_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
++					       struct hclge_desc *desc);
+ 
+ void hclge_cmd_uninit(struct hclge_dev *hdev);
+ int hclge_cmd_queue_init(struct hclge_dev *hdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 26054593839a..f680f58451db 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -27,6 +27,7 @@
+ #include "hclge_err.h"
+ #include "hnae3.h"
+ #include "hclge_devlink.h"
++#include "hclge_comm_cmd.h"
+ 
+ #define HCLGE_NAME			"hclge"
+ 
+@@ -1764,8 +1765,17 @@ static int hclge_alloc_tqps(struct hclge_dev *hdev)
+ 		tqp->q.buf_size = hdev->rx_buf_len;
+ 		tqp->q.tx_desc_num = hdev->num_tx_desc;
+ 		tqp->q.rx_desc_num = hdev->num_rx_desc;
+-		tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
+-			i * HCLGE_TQP_REG_SIZE;
++
++		if (i < HCLGE_TQP_MAX_SIZE_DEV_V2)
++			tqp->q.io_base = hdev->hw.hw.io_base +
++					 HCLGE_TQP_REG_OFFSET +
++					 i * HCLGE_TQP_REG_SIZE;
++		else
++			tqp->q.io_base = hdev->hw.hw.io_base +
++					 HCLGE_TQP_REG_OFFSET +
++					 HCLGE_TQP_EXT_REG_OFFSET +
++					 (i - HCLGE_TQP_MAX_SIZE_DEV_V2) *
++					 HCLGE_TQP_REG_SIZE;
+ 
+ 		/* when device supports tx push and has device memory,
+ 		 * the queue can execute push mode or doorbell mode on
+@@ -2598,8 +2608,8 @@ static int hclge_init_roce_base_info(struct hclge_vport *vport)
+ 	roce->rinfo.base_vector = hdev->num_nic_msi;
+ 
+ 	roce->rinfo.netdev = nic->kinfo.netdev;
+-	roce->rinfo.roce_io_base = hdev->hw.io_base;
+-	roce->rinfo.roce_mem_base = hdev->hw.mem_base;
++	roce->rinfo.roce_io_base = hdev->hw.hw.io_base;
++	roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base;
+ 
+ 	roce->pdev = nic->pdev;
+ 	roce->ae_algo = nic->ae_algo;
+@@ -3682,7 +3692,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
+ 	if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & msix_src_reg) {
+ 		dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
+ 		set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
+-		set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
++		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 		*clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
+ 		hdev->rst_stats.imp_rst_cnt++;
+ 		return HCLGE_VECTOR0_EVENT_RST;
+@@ -3690,7 +3700,7 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
+ 
+ 	if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & msix_src_reg) {
+ 		dev_info(&hdev->pdev->dev, "global reset interrupt\n");
+-		set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
++		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 		set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
+ 		*clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
+ 		hdev->rst_stats.global_rst_cnt++;
+@@ -3824,7 +3834,7 @@ static void hclge_get_misc_vector(struct hclge_dev *hdev)
+ 
+ 	vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
+ 
+-	vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
++	vector->addr = hdev->hw.hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
+ 	hdev->vector_status[0] = 0;
+ 
+ 	hdev->num_msi_left -= 1;
+@@ -4016,7 +4026,7 @@ static int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
+ static void hclge_mailbox_service_task(struct hclge_dev *hdev)
+ {
+ 	if (!test_and_clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state) ||
+-	    test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state) ||
++	    test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state) ||
+ 	    test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
+ 		return;
+ 
+@@ -4263,7 +4273,7 @@ static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
+ 		 * any mailbox handling or command to firmware is only valid
+ 		 * after hclge_cmd_init is called.
+ 		 */
+-		set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
++		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 		hdev->rst_stats.pf_rst_cnt++;
+ 		break;
+ 	case HNAE3_FLR_RESET:
+@@ -4983,11 +4993,11 @@ static void hclge_get_vector_info(struct hclge_dev *hdev, u16 idx,
+ 
+ 	/* need an extend offset to config vector >= 64 */
+ 	if (idx - 1 < HCLGE_PF_MAX_VECTOR_NUM_DEV_V2)
+-		vector_info->io_addr = hdev->hw.io_base +
++		vector_info->io_addr = hdev->hw.hw.io_base +
+ 				HCLGE_VECTOR_REG_BASE +
+ 				(idx - 1) * HCLGE_VECTOR_REG_OFFSET;
+ 	else
+-		vector_info->io_addr = hdev->hw.io_base +
++		vector_info->io_addr = hdev->hw.hw.io_base +
+ 				HCLGE_VECTOR_EXT_REG_BASE +
+ 				(idx - 1) / HCLGE_PF_MAX_VECTOR_NUM_DEV_V2 *
+ 				HCLGE_VECTOR_REG_OFFSET_H +
+@@ -5598,7 +5608,7 @@ int hclge_bind_ring_with_vector(struct hclge_vport *vport,
+ 	struct hclge_desc desc;
+ 	struct hclge_ctrl_vector_chain_cmd *req =
+ 		(struct hclge_ctrl_vector_chain_cmd *)desc.data;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	enum hclge_opcode_type op;
+ 	u16 tqp_type_and_id;
+ 	int i;
+@@ -7661,7 +7671,7 @@ static bool hclge_get_cmdq_stat(struct hnae3_handle *handle)
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+ 
+-	return test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
++	return test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ }
+ 
+ static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
+@@ -8864,7 +8874,7 @@ int hclge_rm_mc_addr_common(struct hclge_vport *vport,
+ 	char format_mac_addr[HNAE3_FORMAT_MAC_ADDR_LEN];
+ 	struct hclge_dev *hdev = vport->back;
+ 	struct hclge_mac_vlan_tbl_entry_cmd req;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_desc desc[3];
+ 
+ 	/* mac addr check */
+@@ -11370,11 +11380,12 @@ static int hclge_dev_mem_map(struct hclge_dev *hdev)
+ 	if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGE_MEM_BAR)))
+ 		return 0;
+ 
+-	hw->mem_base = devm_ioremap_wc(&pdev->dev,
+-				       pci_resource_start(pdev, HCLGE_MEM_BAR),
+-				       pci_resource_len(pdev, HCLGE_MEM_BAR));
+-	if (!hw->mem_base) {
+-		dev_err(&pdev->dev, "failed to map device memroy\n");
++	hw->hw.mem_base =
++		devm_ioremap_wc(&pdev->dev,
++				pci_resource_start(pdev, HCLGE_MEM_BAR),
++				pci_resource_len(pdev, HCLGE_MEM_BAR));
++	if (!hw->hw.mem_base) {
++		dev_err(&pdev->dev, "failed to map device memory\n");
+ 		return -EFAULT;
+ 	}
+ 
+@@ -11412,8 +11423,8 @@ static int hclge_pci_init(struct hclge_dev *hdev)
+ 
+ 	pci_set_master(pdev);
+ 	hw = &hdev->hw;
+-	hw->io_base = pcim_iomap(pdev, 2, 0);
+-	if (!hw->io_base) {
++	hw->hw.io_base = pcim_iomap(pdev, 2, 0);
++	if (!hw->hw.io_base) {
+ 		dev_err(&pdev->dev, "Can't map configuration register space\n");
+ 		ret = -ENOMEM;
+ 		goto err_clr_master;
+@@ -11428,7 +11439,7 @@ static int hclge_pci_init(struct hclge_dev *hdev)
+ 	return 0;
+ 
+ err_unmap_io_base:
+-	pcim_iounmap(pdev, hdev->hw.io_base);
++	pcim_iounmap(pdev, hdev->hw.hw.io_base);
+ err_clr_master:
+ 	pci_clear_master(pdev);
+ 	pci_release_regions(pdev);
+@@ -11442,10 +11453,10 @@ static void hclge_pci_uninit(struct hclge_dev *hdev)
+ {
+ 	struct pci_dev *pdev = hdev->pdev;
+ 
+-	if (hdev->hw.mem_base)
+-		devm_iounmap(&pdev->dev, hdev->hw.mem_base);
++	if (hdev->hw.hw.mem_base)
++		devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base);
+ 
+-	pcim_iounmap(pdev, hdev->hw.io_base);
++	pcim_iounmap(pdev, hdev->hw.hw.io_base);
+ 	pci_free_irq_vectors(pdev);
+ 	pci_clear_master(pdev);
+ 	pci_release_mem_regions(pdev);
+@@ -11506,7 +11517,7 @@ static void hclge_reset_prepare_general(struct hnae3_ae_dev *ae_dev,
+ 
+ 	/* disable misc vector before reset done */
+ 	hclge_enable_vector(&hdev->misc_vector, false);
+-	set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
++	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 
+ 	if (hdev->reset_type == HNAE3_FLR_RESET)
+ 		hdev->rst_stats.flr_rst_cnt++;
+@@ -11979,7 +11990,7 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ err_devlink_uninit:
+ 	hclge_devlink_uninit(hdev);
+ err_pci_uninit:
+-	pcim_iounmap(pdev, hdev->hw.io_base);
++	pcim_iounmap(pdev, hdev->hw.hw.io_base);
+ 	pci_clear_master(pdev);
+ 	pci_release_regions(pdev);
+ 	pci_disable_device(pdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 2caf07f80484..87ec658d5cde 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -317,11 +317,8 @@ struct hclge_mac {
+ 
+ struct hclge_hw {
+ 	struct hclge_comm_hw hw;
+-	void __iomem *io_base;
+-	void __iomem *mem_base;
+ 	struct hclge_mac mac;
+ 	int num_vec;
+-	struct hclge_cmq cmq;
+ };
+ 
+ /* TQP stats */
+@@ -683,6 +680,11 @@ struct key_info {
+ #define MAX_FD_FILTER_NUM	4096
+ #define HCLGE_ARFS_EXPIRE_INTERVAL	5UL
+ 
++#define hclge_read_dev(a, reg) \
++	hclge_comm_read_reg((a)->hw.io_base, reg)
++#define hclge_write_dev(a, reg, value) \
++	hclge_comm_write_reg((a)->hw.io_base, reg, value)
++
+ enum HCLGE_FD_ACTIVE_RULE_TYPE {
+ 	HCLGE_FD_RULE_NONE,
+ 	HCLGE_FD_ARFS_ACTIVE,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+index 4c270073c607..eb47d03ad625 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+@@ -46,7 +46,7 @@ static int hclge_gen_resp_to_vf(struct hclge_vport *vport,
+ {
+ 	struct hclge_mbx_pf_to_vf_cmd *resp_pf_to_vf;
+ 	struct hclge_dev *hdev = vport->back;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_desc desc;
+ 
+ 	resp_pf_to_vf = (struct hclge_mbx_pf_to_vf_cmd *)desc.data;
+@@ -93,7 +93,7 @@ static int hclge_send_mbx_msg(struct hclge_vport *vport, u8 *msg, u16 msg_len,
+ {
+ 	struct hclge_mbx_pf_to_vf_cmd *resp_pf_to_vf;
+ 	struct hclge_dev *hdev = vport->back;
+-	enum hclge_cmd_status status;
++	enum hclge_comm_cmd_status status;
+ 	struct hclge_desc desc;
+ 
+ 	resp_pf_to_vf = (struct hclge_mbx_pf_to_vf_cmd *)desc.data;
+@@ -793,7 +793,7 @@ static bool hclge_cmd_crq_empty(struct hclge_hw *hw)
+ {
+ 	u32 tail = hclge_read_dev(hw, HCLGE_NIC_CRQ_TAIL_REG);
+ 
+-	return tail == hw->cmq.crq.next_to_use;
++	return tail == hw->hw.cmq.crq.next_to_use;
+ }
+ 
+ static void hclge_handle_ncsi_error(struct hclge_dev *hdev)
+@@ -1130,7 +1130,7 @@ static void hclge_mbx_request_handling(struct hclge_mbx_ops_param *param)
+ 
+ void hclge_mbx_handler(struct hclge_dev *hdev)
+ {
+-	struct hclge_cmq_ring *crq = &hdev->hw.cmq.crq;
++	struct hclge_comm_cmq_ring *crq = &hdev->hw.hw.cmq.crq;
+ 	struct hclge_respond_to_vf_msg resp_msg;
+ 	struct hclge_mbx_vf_to_pf_cmd *req;
+ 	struct hclge_mbx_ops_param param;
+@@ -1140,7 +1140,8 @@ void hclge_mbx_handler(struct hclge_dev *hdev)
+ 	param.resp_msg = &resp_msg;
+ 	/* handle all the mailbox requests in the queue */
+ 	while (!hclge_cmd_crq_empty(&hdev->hw)) {
+-		if (test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state)) {
++		if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE,
++			     &hdev->hw.hw.comm_state)) {
+ 			dev_warn(&hdev->pdev->dev,
+ 				 "command queue needs re-initializing\n");
+ 			return;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+index 3f2c898b0bf9..11723c13c96a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+@@ -47,7 +47,7 @@ static int hclge_mdio_write(struct mii_bus *bus, int phyid, int regnum,
+ 	struct hclge_desc desc;
+ 	int ret;
+ 
+-	if (test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state))
++	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))
+ 		return 0;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, false);
+@@ -85,7 +85,7 @@ static int hclge_mdio_read(struct mii_bus *bus, int phyid, int regnum)
+ 	struct hclge_desc desc;
+ 	int ret;
+ 
+-	if (test_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state))
++	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))
+ 		return 0;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, true);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+index befa9bcc2f2f..a40b1583f114 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+@@ -464,7 +464,7 @@ static int hclge_ptp_create_clock(struct hclge_dev *hdev)
+ 	}
+ 
+ 	spin_lock_init(&ptp->lock);
+-	ptp->io_base = hdev->hw.io_base + HCLGE_PTP_REG_OFFSET;
++	ptp->io_base = hdev->hw.hw.io_base + HCLGE_PTP_REG_OFFSET;
+ 	ptp->ts_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
+ 	ptp->ts_cfg.tx_type = HWTSTAMP_TX_OFF;
+ 	hdev->ptp = ptp;
+-- 
+2.34.1
+
diff --git a/patches/0606-net-hns3-refactor-hclgevf_cmd_send-with-new-hclge_co.patch b/patches/0606-net-hns3-refactor-hclgevf_cmd_send-with-new-hclge_co.patch
new file mode 100644
index 0000000..37e40bb
--- /dev/null
+++ b/patches/0606-net-hns3-refactor-hclgevf_cmd_send-with-new-hclge_co.patch
@@ -0,0 +1,810 @@
+From 8257751c043c6147204905c816acca0212b10e3e Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:51 +0800
+Subject: [PATCH 245/283] net: hns3: refactor hclgevf_cmd_send with new
+ hclge_comm_cmd_send API
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit 076bb537577f6eae1714613f02a74621c0c1922a
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=076bb537577f6eae1714613f02a74621c0c1922a
+
+----------------------------------------------------------------------
+
+This patch firstly uses new hardware description struct hclge_comm_hw as
+child member of hclgevf_hw and deletes the old hardware description child
+members. All the hclgevf_hw variables used in VF module is modified
+according to the new hclgevf_hw.
+
+Secondly hclgevf_cmd_send is refactored to use hclge_comm_cmd_send APIs.
+The old functions called by hclgevf_cmd_send are all deleted. Still we kept
+hclgevf_cmd_send to avoid too many meaningless modifications.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+---
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       | 299 +++---------------
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       |  74 +----
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |  56 ++--
+ .../hisilicon/hns3/hns3vf/hclgevf_main.h      |  10 +-
+ .../hisilicon/hns3/hns3vf/hclgevf_mbx.c       |  15 +-
+ 5 files changed, 92 insertions(+), 362 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index b0fc21fe3c82..8c959ff64330 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -12,84 +12,12 @@
+ #include "hclgevf_main.h"
+ #include "hnae3.h"
+ 
+-#define cmq_ring_to_dev(ring)   (&(ring)->dev->pdev->dev)
+-
+-static int hclgevf_ring_space(struct hclgevf_cmq_ring *ring)
+-{
+-	int ntc = ring->next_to_clean;
+-	int ntu = ring->next_to_use;
+-	int used;
+-
+-	used = (ntu - ntc + ring->desc_num) % ring->desc_num;
+-
+-	return ring->desc_num - used - 1;
+-}
+-
+-static int hclgevf_is_valid_csq_clean_head(struct hclgevf_cmq_ring *ring,
+-					   int head)
+-{
+-	int ntu = ring->next_to_use;
+-	int ntc = ring->next_to_clean;
+-
+-	if (ntu > ntc)
+-		return head >= ntc && head <= ntu;
+-
+-	return head >= ntc || head <= ntu;
+-}
+-
+-static int hclgevf_cmd_csq_clean(struct hclgevf_hw *hw)
+-{
+-	struct hclgevf_dev *hdev = container_of(hw, struct hclgevf_dev, hw);
+-	struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
+-	int clean;
+-	u32 head;
+-
+-	head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
+-	rmb(); /* Make sure head is ready before touch any data */
+-
+-	if (!hclgevf_is_valid_csq_clean_head(csq, head)) {
+-		dev_warn(&hdev->pdev->dev, "wrong cmd head (%u, %d-%d)\n", head,
+-			 csq->next_to_use, csq->next_to_clean);
+-		dev_warn(&hdev->pdev->dev,
+-			 "Disabling any further commands to IMP firmware\n");
+-		set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
+-		return -EIO;
+-	}
+-
+-	clean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num;
+-	csq->next_to_clean = head;
+-	return clean;
+-}
+-
+-static bool hclgevf_cmd_csq_done(struct hclgevf_hw *hw)
+-{
+-	u32 head;
+-
+-	head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
+-
+-	return head == hw->cmq.csq.next_to_use;
+-}
+-
+-static bool hclgevf_is_special_opcode(u16 opcode)
+-{
+-	const u16 spec_opcode[] = {0x30, 0x31, 0x32};
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
+-		if (spec_opcode[i] == opcode)
+-			return true;
+-	}
+-
+-	return false;
+-}
+-
+-static void hclgevf_cmd_config_regs(struct hclgevf_cmq_ring *ring)
++static void hclgevf_cmd_config_regs(struct hclgevf_hw *hw,
++				    struct hclge_comm_cmq_ring *ring)
+ {
+-	struct hclgevf_dev *hdev = ring->dev;
+-	struct hclgevf_hw *hw = &hdev->hw;
+ 	u32 reg_val;
+ 
+-	if (ring->flag == HCLGEVF_TYPE_CSQ) {
++	if (ring->ring_type == HCLGEVF_TYPE_CSQ) {
+ 		reg_val = lower_32_bits(ring->desc_dma_addr);
+ 		hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val);
+ 		reg_val = upper_32_bits(ring->desc_dma_addr);
+@@ -118,8 +46,8 @@ static void hclgevf_cmd_config_regs(struct hclgevf_cmq_ring *ring)
+ 
+ static void hclgevf_cmd_init_regs(struct hclgevf_hw *hw)
+ {
+-	hclgevf_cmd_config_regs(&hw->cmq.csq);
+-	hclgevf_cmd_config_regs(&hw->cmq.crq);
++	hclgevf_cmd_config_regs(hw, &hw->hw.cmq.csq);
++	hclgevf_cmd_config_regs(hw, &hw->hw.cmq.crq);
+ }
+ 
+ static void hclgevf_cmd_clear_regs(struct hclgevf_hw *hw)
+@@ -136,7 +64,7 @@ static void hclgevf_cmd_clear_regs(struct hclgevf_hw *hw)
+ 	hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
+ }
+ 
+-static int hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring *ring)
++static int hclgevf_alloc_cmd_desc(struct hclge_comm_cmq_ring *ring)
+ {
+ 	int size = ring->desc_num * sizeof(struct hclge_desc);
+ 
+@@ -149,12 +77,12 @@ static int hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring *ring)
+ 	return 0;
+ }
+ 
+-static void hclgevf_free_cmd_desc(struct hclgevf_cmq_ring *ring)
++static void hclgevf_free_cmd_desc(struct hclge_comm_cmq_ring *ring)
+ {
+ 	int size  = ring->desc_num * sizeof(struct hclge_desc);
+ 
+ 	if (ring->desc) {
+-		dma_free_coherent(cmq_ring_to_dev(ring), size,
++		dma_free_coherent(&ring->pdev->dev, size,
+ 				  ring->desc, ring->desc_dma_addr);
+ 		ring->desc = NULL;
+ 	}
+@@ -163,12 +91,13 @@ static void hclgevf_free_cmd_desc(struct hclgevf_cmq_ring *ring)
+ static int hclgevf_alloc_cmd_queue(struct hclgevf_dev *hdev, int ring_type)
+ {
+ 	struct hclgevf_hw *hw = &hdev->hw;
+-	struct hclgevf_cmq_ring *ring =
+-		(ring_type == HCLGEVF_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq;
++	struct hclge_comm_cmq_ring *ring =
++		(ring_type == HCLGEVF_TYPE_CSQ) ? &hw->hw.cmq.csq :
++						  &hw->hw.cmq.crq;
+ 	int ret;
+ 
+-	ring->dev = hdev;
+-	ring->flag = ring_type;
++	ring->pdev = hdev->pdev;
++	ring->ring_type = ring_type;
+ 
+ 	/* allocate CSQ/CRQ descriptor */
+ 	ret = hclgevf_alloc_cmd_desc(ring);
+@@ -192,113 +121,6 @@ void hclgevf_cmd_setup_basic_desc(struct hclge_desc *desc,
+ 		desc->flag &= cpu_to_le16(~HCLGEVF_CMD_FLAG_WR);
+ }
+ 
+-struct vf_errcode {
+-	u32 imp_errcode;
+-	int common_errno;
+-};
+-
+-static void hclgevf_cmd_copy_desc(struct hclgevf_hw *hw,
+-				  struct hclge_desc *desc, int num)
+-{
+-	struct hclge_desc *desc_to_use;
+-	int handle = 0;
+-
+-	while (handle < num) {
+-		desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
+-		*desc_to_use = desc[handle];
+-		(hw->cmq.csq.next_to_use)++;
+-		if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
+-			hw->cmq.csq.next_to_use = 0;
+-		handle++;
+-	}
+-}
+-
+-static int hclgevf_cmd_convert_err_code(u16 desc_ret)
+-{
+-	struct vf_errcode hclgevf_cmd_errcode[] = {
+-		{HCLGEVF_CMD_EXEC_SUCCESS, 0},
+-		{HCLGEVF_CMD_NO_AUTH, -EPERM},
+-		{HCLGEVF_CMD_NOT_SUPPORTED, -EOPNOTSUPP},
+-		{HCLGEVF_CMD_QUEUE_FULL, -EXFULL},
+-		{HCLGEVF_CMD_NEXT_ERR, -ENOSR},
+-		{HCLGEVF_CMD_UNEXE_ERR, -ENOTBLK},
+-		{HCLGEVF_CMD_PARA_ERR, -EINVAL},
+-		{HCLGEVF_CMD_RESULT_ERR, -ERANGE},
+-		{HCLGEVF_CMD_TIMEOUT, -ETIME},
+-		{HCLGEVF_CMD_HILINK_ERR, -ENOLINK},
+-		{HCLGEVF_CMD_QUEUE_ILLEGAL, -ENXIO},
+-		{HCLGEVF_CMD_INVALID, -EBADR},
+-	};
+-	u32 errcode_count = ARRAY_SIZE(hclgevf_cmd_errcode);
+-	u32 i;
+-
+-	for (i = 0; i < errcode_count; i++)
+-		if (hclgevf_cmd_errcode[i].imp_errcode == desc_ret)
+-			return hclgevf_cmd_errcode[i].common_errno;
+-
+-	return -EIO;
+-}
+-
+-static int hclgevf_cmd_check_retval(struct hclgevf_hw *hw,
+-				    struct hclge_desc *desc, int num, int ntc)
+-{
+-	u16 opcode, desc_ret;
+-	int handle;
+-
+-	opcode = le16_to_cpu(desc[0].opcode);
+-	for (handle = 0; handle < num; handle++) {
+-		/* Get the result of hardware write back */
+-		desc[handle] = hw->cmq.csq.desc[ntc];
+-		ntc++;
+-		if (ntc == hw->cmq.csq.desc_num)
+-			ntc = 0;
+-	}
+-	if (likely(!hclgevf_is_special_opcode(opcode)))
+-		desc_ret = le16_to_cpu(desc[num - 1].retval);
+-	else
+-		desc_ret = le16_to_cpu(desc[0].retval);
+-	hw->cmq.last_status = desc_ret;
+-
+-	return hclgevf_cmd_convert_err_code(desc_ret);
+-}
+-
+-static int hclgevf_cmd_check_result(struct hclgevf_hw *hw,
+-				    struct hclge_desc *desc, int num, int ntc)
+-{
+-	struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
+-	bool is_completed = false;
+-	u32 timeout = 0;
+-	int handle, ret;
+-
+-	/* If the command is sync, wait for the firmware to write back,
+-	 * if multi descriptors to be sent, use the first one to check
+-	 */
+-	if (HCLGEVF_SEND_SYNC(le16_to_cpu(desc->flag))) {
+-		do {
+-			if (hclgevf_cmd_csq_done(hw)) {
+-				is_completed = true;
+-				break;
+-			}
+-			udelay(1);
+-			timeout++;
+-		} while (timeout < hw->cmq.tx_timeout);
+-	}
+-
+-	if (!is_completed)
+-		ret = -EBADE;
+-	else
+-		ret = hclgevf_cmd_check_retval(hw, desc, num, ntc);
+-
+-	/* Clean the command send queue */
+-	handle = hclgevf_cmd_csq_clean(hw);
+-	if (handle < 0)
+-		ret = handle;
+-	else if (handle != num)
+-		dev_warn(&hdev->pdev->dev,
+-			 "cleaned %d, need to clean %d\n", handle, num);
+-	return ret;
+-}
+-
+ /* hclgevf_cmd_send - send command to command queue
+  * @hw: pointer to the hw struct
+  * @desc: prefilled descriptor for describing the command
+@@ -309,44 +131,7 @@ static int hclgevf_cmd_check_result(struct hclgevf_hw *hw,
+  */
+ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num)
+ {
+-	struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
+-	struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
+-	int ret;
+-	int ntc;
+-
+-	spin_lock_bh(&hw->cmq.csq.lock);
+-
+-	if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) {
+-		spin_unlock_bh(&hw->cmq.csq.lock);
+-		return -EBUSY;
+-	}
+-
+-	if (num > hclgevf_ring_space(&hw->cmq.csq)) {
+-		/* If CMDQ ring is full, SW HEAD and HW HEAD may be different,
+-		 * need update the SW HEAD pointer csq->next_to_clean
+-		 */
+-		csq->next_to_clean = hclgevf_read_dev(hw,
+-						      HCLGEVF_NIC_CSQ_HEAD_REG);
+-		spin_unlock_bh(&hw->cmq.csq.lock);
+-		return -EBUSY;
+-	}
+-
+-	/* Record the location of desc in the ring for this time
+-	 * which will be use for hardware to write back
+-	 */
+-	ntc = hw->cmq.csq.next_to_use;
+-
+-	hclgevf_cmd_copy_desc(hw, desc, num);
+-
+-	/* Write to hardware */
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG,
+-			  hw->cmq.csq.next_to_use);
+-
+-	ret = hclgevf_cmd_check_result(hw, desc, num, ntc);
+-
+-	spin_unlock_bh(&hw->cmq.csq.lock);
+-
+-	return ret;
++	return hclge_comm_cmd_send(&hw->hw, desc, num);
+ }
+ 
+ static void hclgevf_set_default_capability(struct hclgevf_dev *hdev)
+@@ -410,20 +195,17 @@ static int hclgevf_cmd_query_version_and_capability(struct hclgevf_dev *hdev)
+ 
+ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
+ {
++	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+ 	int ret;
+ 
+ 	/* Setup the lock for command queue */
+-	spin_lock_init(&hdev->hw.cmq.csq.lock);
+-	spin_lock_init(&hdev->hw.cmq.crq.lock);
++	spin_lock_init(&cmdq->csq.lock);
++	spin_lock_init(&cmdq->crq.lock);
+ 
+-	/* clear up all command register,
+-	 * in case there are some residual values
+-	 */
+-	hclgevf_cmd_clear_regs(&hdev->hw);
+-
+-	hdev->hw.cmq.tx_timeout = HCLGEVF_CMDQ_TX_TIMEOUT;
+-	hdev->hw.cmq.csq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
+-	hdev->hw.cmq.crq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
++	cmdq->csq.pdev = hdev->pdev;
++	cmdq->tx_timeout = HCLGEVF_CMDQ_TX_TIMEOUT;
++	cmdq->csq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
++	cmdq->crq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
+ 
+ 	ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CSQ);
+ 	if (ret) {
+@@ -441,7 +223,7 @@ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
+ 
+ 	return 0;
+ err_csq:
+-	hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
++	hclgevf_free_cmd_desc(&cmdq->csq);
+ 	return ret;
+ }
+ 
+@@ -467,27 +249,28 @@ static int hclgevf_firmware_compat_config(struct hclgevf_dev *hdev, bool en)
+ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
++	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+ 	int ret;
+ 
+-	spin_lock_bh(&hdev->hw.cmq.csq.lock);
+-	spin_lock(&hdev->hw.cmq.crq.lock);
++	spin_lock_bh(&cmdq->csq.lock);
++	spin_lock(&cmdq->crq.lock);
+ 
+ 	/* initialize the pointers of async rx queue of mailbox */
+ 	hdev->arq.hdev = hdev;
+ 	hdev->arq.head = 0;
+ 	hdev->arq.tail = 0;
+ 	atomic_set(&hdev->arq.count, 0);
+-	hdev->hw.cmq.csq.next_to_clean = 0;
+-	hdev->hw.cmq.csq.next_to_use = 0;
+-	hdev->hw.cmq.crq.next_to_clean = 0;
+-	hdev->hw.cmq.crq.next_to_use = 0;
++	cmdq->csq.next_to_clean = 0;
++	cmdq->csq.next_to_use = 0;
++	cmdq->crq.next_to_clean = 0;
++	cmdq->crq.next_to_use = 0;
+ 
+ 	hclgevf_cmd_init_regs(&hdev->hw);
+ 
+-	spin_unlock(&hdev->hw.cmq.crq.lock);
+-	spin_unlock_bh(&hdev->hw.cmq.csq.lock);
++	spin_unlock(&cmdq->crq.lock);
++	spin_unlock_bh(&cmdq->csq.lock);
+ 
+-	clear_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
++	clear_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 
+ 	/* Check if there is new reset pending, because the higher level
+ 	 * reset may happen when lower level reset is being processed.
+@@ -530,25 +313,27 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ 	return 0;
+ 
+ err_cmd_init:
+-	set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
++	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 
+ 	return ret;
+ }
+ 
+ void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
+ {
++	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+ 	hclgevf_firmware_compat_config(hdev, false);
+-	set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
++	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
++
+ 	/* wait to ensure that the firmware completes the possible left
+ 	 * over commands.
+ 	 */
+ 	msleep(HCLGEVF_CMDQ_CLEAR_WAIT_TIME);
+-	spin_lock_bh(&hdev->hw.cmq.csq.lock);
+-	spin_lock(&hdev->hw.cmq.crq.lock);
++	spin_lock_bh(&cmdq->csq.lock);
++	spin_lock(&cmdq->crq.lock);
+ 	hclgevf_cmd_clear_regs(&hdev->hw);
+-	spin_unlock(&hdev->hw.cmq.crq.lock);
+-	spin_unlock_bh(&hdev->hw.cmq.csq.lock);
++	spin_unlock(&cmdq->crq.lock);
++	spin_unlock_bh(&cmdq->csq.lock);
+ 
+-	hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
+-	hclgevf_free_cmd_desc(&hdev->hw.cmq.crq);
++	hclgevf_free_cmd_desc(&cmdq->csq);
++	hclgevf_free_cmd_desc(&cmdq->crq);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 96a41f0e2991..6f04ea3bacd6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -22,57 +22,6 @@ struct hclgevf_firmware_compat_cmd {
+ 	u8 rsv[20];
+ };
+ 
+-struct hclgevf_desc_cb {
+-	dma_addr_t dma;
+-	void *va;
+-	u32 length;
+-};
+-
+-struct hclgevf_cmq_ring {
+-	dma_addr_t desc_dma_addr;
+-	struct hclge_desc *desc;
+-	struct hclgevf_desc_cb *desc_cb;
+-	struct hclgevf_dev  *dev;
+-	u32 head;
+-	u32 tail;
+-
+-	u16 buf_size;
+-	u16 desc_num;
+-	int next_to_use;
+-	int next_to_clean;
+-	u8 flag;
+-	spinlock_t lock; /* Command queue lock */
+-};
+-
+-enum hclgevf_cmd_return_status {
+-	HCLGEVF_CMD_EXEC_SUCCESS	= 0,
+-	HCLGEVF_CMD_NO_AUTH		= 1,
+-	HCLGEVF_CMD_NOT_SUPPORTED	= 2,
+-	HCLGEVF_CMD_QUEUE_FULL		= 3,
+-	HCLGEVF_CMD_NEXT_ERR		= 4,
+-	HCLGEVF_CMD_UNEXE_ERR		= 5,
+-	HCLGEVF_CMD_PARA_ERR		= 6,
+-	HCLGEVF_CMD_RESULT_ERR		= 7,
+-	HCLGEVF_CMD_TIMEOUT		= 8,
+-	HCLGEVF_CMD_HILINK_ERR		= 9,
+-	HCLGEVF_CMD_QUEUE_ILLEGAL	= 10,
+-	HCLGEVF_CMD_INVALID		= 11,
+-};
+-
+-enum hclgevf_cmd_status {
+-	HCLGEVF_STATUS_SUCCESS	= 0,
+-	HCLGEVF_ERR_CSQ_FULL	= -1,
+-	HCLGEVF_ERR_CSQ_TIMEOUT	= -2,
+-	HCLGEVF_ERR_CSQ_ERROR	= -3
+-};
+-
+-struct hclgevf_cmq {
+-	struct hclgevf_cmq_ring csq;
+-	struct hclgevf_cmq_ring crq;
+-	u16 tx_timeout; /* Tx timeout */
+-	enum hclgevf_cmd_status last_status;
+-};
+-
+ #define HCLGEVF_CMD_FLAG_IN_VALID_SHIFT		0
+ #define HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT	1
+ #define HCLGEVF_CMD_FLAG_NEXT_SHIFT		2
+@@ -114,6 +63,9 @@ enum hclgevf_opcode_type {
+ #define HCLGEVF_TQP_REG_OFFSET		0x80000
+ #define HCLGEVF_TQP_REG_SIZE		0x200
+ 
++#define HCLGEVF_TQP_MAX_SIZE_DEV_V2	1024
++#define HCLGEVF_TQP_EXT_REG_OFFSET	0x100
++
+ struct hclgevf_tqp_map {
+ 	__le16 tqp_id;	/* Absolute tqp id for in this pf */
+ 	u8 tqp_vf; /* VF id */
+@@ -295,26 +247,6 @@ struct hclgevf_caps_bit_map {
+ 	u16 local_bit;
+ };
+ 
+-static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
+-{
+-	writel(value, base + reg);
+-}
+-
+-static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg)
+-{
+-	u8 __iomem *reg_addr = READ_ONCE(base);
+-
+-	return readl(reg_addr + reg);
+-}
+-
+-#define hclgevf_write_dev(a, reg, value) \
+-	hclgevf_write_reg((a)->io_base, reg, value)
+-#define hclgevf_read_dev(a, reg) \
+-	hclgevf_read_reg((a)->io_base, reg)
+-
+-#define HCLGEVF_SEND_SYNC(flag) \
+-	((flag) & HCLGEVF_CMD_FLAG_NO_INTR)
+-
+ int hclgevf_cmd_init(struct hclgevf_dev *hdev);
+ void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
+ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index b38c903659a6..8fe47f45e4d3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -413,7 +413,7 @@ static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
+ 		tqp->q.buf_size = hdev->rx_buf_len;
+ 		tqp->q.tx_desc_num = hdev->num_tx_desc;
+ 		tqp->q.rx_desc_num = hdev->num_rx_desc;
+-		tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
++		tqp->q.io_base = hdev->hw.hw.io_base + HCLGEVF_TQP_REG_OFFSET +
+ 			i * HCLGEVF_TQP_REG_SIZE;
+ 
+ 		/* when device supports tx push and has device memory,
+@@ -424,6 +424,17 @@ static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
+ 			tqp->q.mem_base = hdev->hw.hw.mem_base +
+ 					  HCLGEVF_TQP_MEM_OFFSET(hdev, i);
+ 
++		if (i < HCLGEVF_TQP_MAX_SIZE_DEV_V2)
++			tqp->q.io_base = hdev->hw.hw.io_base +
++					 HCLGEVF_TQP_REG_OFFSET +
++					 i * HCLGEVF_TQP_REG_SIZE;
++		else
++			tqp->q.io_base = hdev->hw.hw.io_base +
++					 HCLGEVF_TQP_REG_OFFSET +
++					 HCLGEVF_TQP_EXT_REG_OFFSET +
++					 (i - HCLGEVF_TQP_MAX_SIZE_DEV_V2) *
++					 HCLGEVF_TQP_REG_SIZE;
++
+ 		tqp++;
+ 	}
+ 
+@@ -636,7 +647,7 @@ static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
+ 		for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
+ 			if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
+ 				vector->vector = pci_irq_vector(hdev->pdev, i);
+-				vector->io_addr = hdev->hw.io_base +
++				vector->io_addr = hdev->hw.hw.io_base +
+ 					HCLGEVF_VECTOR_REG_BASE +
+ 					(i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
+ 				hdev->vector_status[i] = 0;
+@@ -1882,13 +1893,13 @@ static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
+ 	int ret;
+ 
+ 	if (hdev->reset_type == HNAE3_VF_RESET)
+-		ret = readl_poll_timeout(hdev->hw.io_base +
++		ret = readl_poll_timeout(hdev->hw.hw.io_base +
+ 					 HCLGEVF_VF_RST_ING, val,
+ 					 !(val & HCLGEVF_VF_RST_ING_BIT),
+ 					 HCLGEVF_RESET_WAIT_US,
+ 					 HCLGEVF_RESET_WAIT_TIMEOUT_US);
+ 	else
+-		ret = readl_poll_timeout(hdev->hw.io_base +
++		ret = readl_poll_timeout(hdev->hw.hw.io_base +
+ 					 HCLGEVF_RST_ING, val,
+ 					 !(val & HCLGEVF_RST_ING_BITS),
+ 					 HCLGEVF_RESET_WAIT_US,
+@@ -1974,7 +1985,7 @@ static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
+ 		hdev->rst_stats.vf_func_rst_cnt++;
+ 	}
+ 
+-	set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
++	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 	/* inform hardware that preparatory work is done */
+ 	msleep(HCLGEVF_RESET_SYNC_TIME);
+ 	hclgevf_reset_handshake(hdev, true);
+@@ -2226,7 +2237,7 @@ static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
+ 
+ 	vector->vector_irq = pci_irq_vector(hdev->pdev,
+ 					    HCLGEVF_MISC_VECTOR_NUM);
+-	vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
++	vector->addr = hdev->hw.hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
+ 	/* vector status always valid for Vector 0 */
+ 	hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
+ 	hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
+@@ -2347,7 +2358,7 @@ static void hclgevf_keep_alive(struct hclgevf_dev *hdev)
+ 	struct hclge_vf_to_pf_msg send_msg;
+ 	int ret;
+ 
+-	if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state))
++	if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state))
+ 		return;
+ 
+ 	hclgevf_build_send_msg(&send_msg, HCLGE_MBX_KEEP_ALIVE, 0);
+@@ -2444,7 +2455,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
+ 			 "receive reset interrupt 0x%x!\n", rst_ing_reg);
+ 		set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
+ 		set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
+-		set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
++		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 		*clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
+ 		hdev->rst_stats.vf_rst_cnt++;
+ 		/* set up VF hardware reset status, its PF will clear
+@@ -2567,8 +2578,8 @@ static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
+ 	roce->rinfo.base_vector = hdev->roce_base_msix_offset;
+ 
+ 	roce->rinfo.netdev = nic->kinfo.netdev;
+-	roce->rinfo.roce_io_base = hdev->hw.io_base;
+-	roce->rinfo.roce_mem_base = hdev->hw.mem_base;
++	roce->rinfo.roce_io_base = hdev->hw.hw.io_base;
++	roce->rinfo.roce_mem_base = hdev->hw.hw.mem_base;
+ 
+ 	roce->pdev = nic->pdev;
+ 	roce->ae_algo = nic->ae_algo;
+@@ -3037,12 +3048,12 @@ static int hclgevf_dev_mem_map(struct hclgevf_dev *hdev)
+ 	if (!(pci_select_bars(pdev, IORESOURCE_MEM) & BIT(HCLGEVF_MEM_BAR)))
+ 		return 0;
+ 
+-	hw->mem_base = devm_ioremap_wc(&pdev->dev,
+-				       pci_resource_start(pdev,
+-							  HCLGEVF_MEM_BAR),
+-			pci_resource_len(pdev, HCLGEVF_MEM_BAR));
+-	if (!hw->mem_base) {
+-		dev_err(&pdev->dev, "failed to map device memroy\n");
++	hw->hw.mem_base =
++		devm_ioremap_wc(&pdev->dev,
++				pci_resource_start(pdev, HCLGEVF_MEM_BAR),
++				pci_resource_len(pdev, HCLGEVF_MEM_BAR));
++	if (!hw->hw.mem_base) {
++		dev_err(&pdev->dev, "failed to map device memory\n");
+ 		return -EFAULT;
+ 	}
+ 
+@@ -3075,9 +3086,8 @@ static int hclgevf_pci_init(struct hclgevf_dev *hdev)
+ 
+ 	pci_set_master(pdev);
+ 	hw = &hdev->hw;
+-	hw->hdev = hdev;
+-	hw->io_base = pci_iomap(pdev, 2, 0);
+-	if (!hw->io_base) {
++	hw->hw.io_base = pci_iomap(pdev, 2, 0);
++	if (!hw->hw.io_base) {
+ 		dev_err(&pdev->dev, "can't map configuration register space\n");
+ 		ret = -ENOMEM;
+ 		goto err_clr_master;
+@@ -3090,7 +3100,7 @@ static int hclgevf_pci_init(struct hclgevf_dev *hdev)
+ 	return 0;
+ 
+ err_unmap_io_base:
+-	pci_iounmap(pdev, hdev->hw.io_base);
++	pci_iounmap(pdev, hdev->hw.hw.io_base);
+ err_clr_master:
+ 	pci_clear_master(pdev);
+ 	pci_release_regions(pdev);
+@@ -3104,10 +3114,10 @@ static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
+ {
+ 	struct pci_dev *pdev = hdev->pdev;
+ 
+-	if (hdev->hw.mem_base)
+-		devm_iounmap(&pdev->dev, hdev->hw.mem_base);
++	if (hdev->hw.hw.mem_base)
++		devm_iounmap(&pdev->dev, hdev->hw.hw.mem_base);
+ 
+-	pci_iounmap(pdev, hdev->hw.io_base);
++	pci_iounmap(pdev, hdev->hw.hw.io_base);
+ 	pci_clear_master(pdev);
+ 	pci_release_regions(pdev);
+ 	pci_disable_device(pdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index 3a8feb225b37..b419ac92179f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -139,6 +139,11 @@
+ 
+ #define HCLGEVF_STATS_TIMER_INTERVAL	36U
+ 
++#define hclgevf_read_dev(a, reg) \
++	hclge_comm_read_reg((a)->hw.io_base, reg)
++#define hclgevf_write_dev(a, reg, value) \
++	hclge_comm_write_reg((a)->hw.io_base, reg, value)
++
+ enum hclgevf_evt_cause {
+ 	HCLGEVF_VECTOR0_EVENT_RST,
+ 	HCLGEVF_VECTOR0_EVENT_MBX,
+@@ -159,7 +164,6 @@ enum hclgevf_states {
+ 	HCLGEVF_STATE_RST_HANDLING,
+ 	HCLGEVF_STATE_MBX_SERVICE_SCHED,
+ 	HCLGEVF_STATE_MBX_HANDLING,
+-	HCLGEVF_STATE_CMD_DISABLE,
+ 	HCLGEVF_STATE_LINK_UPDATING,
+ 	HCLGEVF_STATE_PROMISC_CHANGED,
+ 	HCLGEVF_STATE_RST_FAIL,
+@@ -179,12 +183,8 @@ struct hclgevf_mac {
+ 
+ struct hclgevf_hw {
+ 	struct hclge_comm_hw hw;
+-	void __iomem *io_base;
+-	void __iomem *mem_base;
+ 	int num_vec;
+-	struct hclgevf_cmq cmq;
+ 	struct hclgevf_mac mac;
+-	void *hdev; /* hclgevf device it is par of */
+ };
+ 
+ /* TQP stats */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+index ccd45b3c532d..f8678ae46768 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+@@ -75,7 +75,8 @@ static int hclgevf_get_mbx_resp(struct hclgevf_dev *hdev, u16 code0, u16 code1,
+ 	}
+ 
+ 	while ((!hdev->mbx_resp.received_resp) && (i < HCLGEVF_MAX_TRY_TIMES)) {
+-		if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state))
++		if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE,
++			     &hdev->hw.hw.comm_state))
+ 			return -EIO;
+ 
+ 		usleep_range(HCLGEVF_SLEEP_USECOND, HCLGEVF_SLEEP_USECOND * 2);
+@@ -178,7 +179,7 @@ static bool hclgevf_cmd_crq_empty(struct hclgevf_hw *hw)
+ {
+ 	u32 tail = hclgevf_read_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG);
+ 
+-	return tail == hw->cmq.crq.next_to_use;
++	return tail == hw->hw.cmq.crq.next_to_use;
+ }
+ 
+ static void hclgevf_handle_mbx_response(struct hclgevf_dev *hdev,
+@@ -237,14 +238,15 @@ static void hclgevf_handle_mbx_msg(struct hclgevf_dev *hdev,
+ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
+ {
+ 	struct hclge_mbx_pf_to_vf_cmd *req;
+-	struct hclgevf_cmq_ring *crq;
++	struct hclge_comm_cmq_ring *crq;
+ 	struct hclge_desc *desc;
+ 	u16 flag;
+ 
+-	crq = &hdev->hw.cmq.crq;
++	crq = &hdev->hw.hw.cmq.crq;
+ 
+ 	while (!hclgevf_cmd_crq_empty(&hdev->hw)) {
+-		if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) {
++		if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE,
++			     &hdev->hw.hw.comm_state)) {
+ 			dev_info(&hdev->pdev->dev, "vf crq need init\n");
+ 			return;
+ 		}
+@@ -335,7 +337,8 @@ void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev)
+ 
+ 	/* process all the async queue messages */
+ 	while (tail != hdev->arq.head) {
+-		if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) {
++		if (test_bit(HCLGE_COMM_STATE_CMD_DISABLE,
++			     &hdev->hw.hw.comm_state)) {
+ 			dev_info(&hdev->pdev->dev,
+ 				 "vf crq need init in async\n");
+ 			return;
+-- 
+2.34.1
+
diff --git a/patches/0607-net-hns3-create-common-cmdq-resource-allocate-free-q.patch b/patches/0607-net-hns3-create-common-cmdq-resource-allocate-free-q.patch
new file mode 100644
index 0000000..0a3d187
--- /dev/null
+++ b/patches/0607-net-hns3-create-common-cmdq-resource-allocate-free-q.patch
@@ -0,0 +1,697 @@
+From 143cb127cf1ed993e2540e5c43427e6e1ad8106e Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:52 +0800
+Subject: [PATCH 246/283] net: hns3: create common cmdq resource
+ allocate/free/query APIs
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit da77aef9cc58ed820097b3d905e9fa474d42dbd4
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=da77aef9cc58ed820097b3d905e9fa474d42dbd4
+
+----------------------------------------------------------------------
+
+The PF and VF cmdq module resource allocate/free/query APIs are almost the
+same espect the suffixes of API names. These same implementations bring
+double development and bugfix work.
+
+This patch creates common cmdq resource allocate/free/query APIs called by
+PF and VF cmdq init/uninit APIs. The next patch will use the new unified
+APIs to replace init/uninit APIs.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+---
+ .../hns3/hns3_common/hclge_comm_cmd.c         |  70 ++---
+ .../hns3/hns3_common/hclge_comm_cmd.h         | 266 +++++++++++++++++-
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         | 251 -----------------
+ 3 files changed, 292 insertions(+), 295 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index cdfce19de621..c96620269037 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -53,14 +53,47 @@ void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
+ static void hclge_comm_set_default_capability(struct hnae3_ae_dev *ae_dev,
+ 					      bool is_pf)
+ {
++	set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
+ 	set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);
+-	if (is_pf) {
+-		set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
++	if (is_pf && ae_dev->dev_version == HNAE3_DEVICE_VERSION_V2) {
+ 		set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
+ 		set_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps);
+ 	}
+ }
+ 
++void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring)
++{
++	int size  = ring->desc_num * sizeof(struct hclge_desc);
++
++	if (!ring->desc)
++		return;
++
++	dma_free_coherent(&ring->pdev->dev, size,
++			  ring->desc, ring->desc_dma_addr);
++	ring->desc = NULL;
++}
++
++static int hclge_comm_alloc_cmd_desc(struct hclge_comm_cmq_ring *ring)
++{
++	int size  = ring->desc_num * sizeof(struct hclge_desc);
++
++	ring->desc = dma_alloc_coherent(&ring->pdev->dev,
++					size, &ring->desc_dma_addr, GFP_KERNEL);
++	if (!ring->desc)
++		return -ENOMEM;
++
++	return 0;
++}
++
++static __le32 hclge_comm_build_api_caps(void)
++{
++	u32 api_caps = 0;
++
++	hnae3_set_bit(api_caps, HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B, 1);
++
++	return cpu_to_le32(api_caps);
++}
++
+ void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
+ 				     enum hclge_opcode_type opcode,
+ 				     bool is_read)
+@@ -100,39 +133,6 @@ int hclge_comm_firmware_compat_config(struct hnae3_ae_dev *ae_dev,
+ 	return hclge_comm_cmd_send(hw, &desc, 1);
+ }
+ 
+-void hclge_comm_free_cmd_desc(struct hclge_comm_cmq_ring *ring)
+-{
+-	int size  = ring->desc_num * sizeof(struct hclge_desc);
+-
+-	if (!ring->desc)
+-		return;
+-
+-	dma_free_coherent(&ring->pdev->dev, size,
+-			  ring->desc, ring->desc_dma_addr);
+-	ring->desc = NULL;
+-}
+-
+-static int hclge_comm_alloc_cmd_desc(struct hclge_comm_cmq_ring *ring)
+-{
+-	int size  = ring->desc_num * sizeof(struct hclge_desc);
+-
+-	ring->desc = dma_alloc_coherent(&ring->pdev->dev,
+-					size, &ring->desc_dma_addr, GFP_KERNEL);
+-	if (!ring->desc)
+-		return -ENOMEM;
+-
+-	return 0;
+-}
+-
+-static __le32 hclge_comm_build_api_caps(void)
+-{
+-	u32 api_caps = 0;
+-
+-	hnae3_set_bit(api_caps, HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B, 1);
+-
+-	return cpu_to_le32(api_caps);
+-}
+-
+ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = {
+ 	{HCLGE_COMM_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
+ 	{HCLGE_COMM_CAP_PTP_B, HNAE3_DEV_SUPPORT_PTP_B},
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 2b9c92a00049..393953e828af 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -57,8 +57,256 @@
+ #define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT	30000
+ #define HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS	500000
+ 
+-enum hclge_opcode_type;
+-
++enum hclge_opcode_type {
++	/* Generic commands */
++	HCLGE_OPC_QUERY_FW_VER		= 0x0001,
++	HCLGE_OPC_CFG_RST_TRIGGER	= 0x0020,
++	HCLGE_OPC_GBL_RST_STATUS	= 0x0021,
++	HCLGE_OPC_QUERY_FUNC_STATUS	= 0x0022,
++	HCLGE_OPC_QUERY_PF_RSRC		= 0x0023,
++	HCLGE_OPC_QUERY_VF_RSRC		= 0x0024,
++	HCLGE_OPC_GET_CFG_PARAM		= 0x0025,
++	HCLGE_OPC_PF_RST_DONE		= 0x0026,
++	HCLGE_OPC_QUERY_VF_RST_RDY	= 0x0027,
++
++	HCLGE_OPC_STATS_64_BIT		= 0x0030,
++	HCLGE_OPC_STATS_32_BIT		= 0x0031,
++	HCLGE_OPC_STATS_MAC		= 0x0032,
++	HCLGE_OPC_QUERY_MAC_REG_NUM	= 0x0033,
++	HCLGE_OPC_STATS_MAC_ALL		= 0x0034,
++
++	HCLGE_OPC_QUERY_REG_NUM		= 0x0040,
++	HCLGE_OPC_QUERY_32_BIT_REG	= 0x0041,
++	HCLGE_OPC_QUERY_64_BIT_REG	= 0x0042,
++	HCLGE_OPC_DFX_BD_NUM		= 0x0043,
++	HCLGE_OPC_DFX_BIOS_COMMON_REG	= 0x0044,
++	HCLGE_OPC_DFX_SSU_REG_0		= 0x0045,
++	HCLGE_OPC_DFX_SSU_REG_1		= 0x0046,
++	HCLGE_OPC_DFX_IGU_EGU_REG	= 0x0047,
++	HCLGE_OPC_DFX_RPU_REG_0		= 0x0048,
++	HCLGE_OPC_DFX_RPU_REG_1		= 0x0049,
++	HCLGE_OPC_DFX_NCSI_REG		= 0x004A,
++	HCLGE_OPC_DFX_RTC_REG		= 0x004B,
++	HCLGE_OPC_DFX_PPP_REG		= 0x004C,
++	HCLGE_OPC_DFX_RCB_REG		= 0x004D,
++	HCLGE_OPC_DFX_TQP_REG		= 0x004E,
++	HCLGE_OPC_DFX_SSU_REG_2		= 0x004F,
++
++	HCLGE_OPC_QUERY_DEV_SPECS	= 0x0050,
++
++	/* MAC command */
++	HCLGE_OPC_CONFIG_MAC_MODE	= 0x0301,
++	HCLGE_OPC_CONFIG_AN_MODE	= 0x0304,
++	HCLGE_OPC_QUERY_LINK_STATUS	= 0x0307,
++	HCLGE_OPC_CONFIG_MAX_FRM_SIZE	= 0x0308,
++	HCLGE_OPC_CONFIG_SPEED_DUP	= 0x0309,
++	HCLGE_OPC_QUERY_MAC_TNL_INT	= 0x0310,
++	HCLGE_OPC_MAC_TNL_INT_EN	= 0x0311,
++	HCLGE_OPC_CLEAR_MAC_TNL_INT	= 0x0312,
++	HCLGE_OPC_COMMON_LOOPBACK       = 0x0315,
++	HCLGE_OPC_QUERY_FEC_STATS       = 0x0316,
++	HCLGE_OPC_CONFIG_FEC_MODE	= 0x031A,
++	/* check sum command */
++	HCLGE_OPC_CFG_CHECKSUM_EN       = 0x0601,
++
++	/* PTP commands */
++	HCLGE_OPC_PTP_INT_EN		= 0x0501,
++	HCLGE_OPC_PTP_MODE_CFG		= 0x0507,
++
++	/* PFC/Pause commands */
++	HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
++	HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
++	HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
++	HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
++	HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
++	HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
++	HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
++	HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
++	HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
++	HCLGE_OPC_QOS_MAP               = 0x070A,
++
++	/* ETS/scheduler commands */
++	HCLGE_OPC_TM_PG_TO_PRI_LINK	= 0x0804,
++	HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
++	HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
++	HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
++	HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
++	HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
++	HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
++	HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
++	HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
++	HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
++	HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
++	HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
++	HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
++	HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
++	HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
++	HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
++	HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
++	HCLGE_OPC_TM_NODES		= 0x0816,
++	HCLGE_OPC_ETS_TC_WEIGHT		= 0x0843,
++	HCLGE_OPC_QSET_DFX_STS		= 0x0844,
++	HCLGE_OPC_PRI_DFX_STS		= 0x0845,
++	HCLGE_OPC_PG_DFX_STS		= 0x0846,
++	HCLGE_OPC_PORT_DFX_STS		= 0x0847,
++	HCLGE_OPC_SCH_NQ_CNT		= 0x0848,
++	HCLGE_OPC_SCH_RQ_CNT		= 0x0849,
++	HCLGE_OPC_TM_INTERNAL_STS	= 0x0850,
++	HCLGE_OPC_TM_INTERNAL_CNT	= 0x0851,
++	HCLGE_OPC_TM_INTERNAL_STS_1	= 0x0852,
++	HCLGE_OPC_TM_FLUSH		= 0x0872,
++
++	/* Packet buffer allocate commands */
++	HCLGE_OPC_TX_BUFF_ALLOC		= 0x0901,
++	HCLGE_OPC_RX_PRIV_BUFF_ALLOC	= 0x0902,
++	HCLGE_OPC_RX_PRIV_WL_ALLOC	= 0x0903,
++	HCLGE_OPC_RX_COM_THRD_ALLOC	= 0x0904,
++	HCLGE_OPC_RX_COM_WL_ALLOC	= 0x0905,
++	HCLGE_OPC_RX_GBL_PKT_CNT	= 0x0906,
++
++	/* TQP management command */
++	HCLGE_OPC_SET_TQP_MAP		= 0x0A01,
++
++	/* TQP commands */
++	HCLGE_OPC_CFG_TX_QUEUE		= 0x0B01,
++	HCLGE_OPC_QUERY_TX_POINTER	= 0x0B02,
++	HCLGE_OPC_QUERY_TX_STATS	= 0x0B03,
++	HCLGE_OPC_TQP_TX_QUEUE_TC	= 0x0B04,
++	HCLGE_OPC_CFG_RX_QUEUE		= 0x0B11,
++	HCLGE_OPC_QUERY_RX_POINTER	= 0x0B12,
++	HCLGE_OPC_QUERY_RX_STATS	= 0x0B13,
++	HCLGE_OPC_STASH_RX_QUEUE_LRO	= 0x0B16,
++	HCLGE_OPC_CFG_RX_QUEUE_LRO	= 0x0B17,
++	HCLGE_OPC_CFG_COM_TQP_QUEUE	= 0x0B20,
++	HCLGE_OPC_RESET_TQP_QUEUE	= 0x0B22,
++
++	/* PPU commands */
++	HCLGE_OPC_PPU_PF_OTHER_INT_DFX	= 0x0B4A,
++
++	/* TSO command */
++	HCLGE_OPC_TSO_GENERIC_CONFIG	= 0x0C01,
++	HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
++
++	/* RSS commands */
++	HCLGE_OPC_RSS_GENERIC_CONFIG	= 0x0D01,
++	HCLGE_OPC_RSS_INDIR_TABLE	= 0x0D07,
++	HCLGE_OPC_RSS_TC_MODE		= 0x0D08,
++	HCLGE_OPC_RSS_INPUT_TUPLE	= 0x0D02,
++
++	/* Promisuous mode command */
++	HCLGE_OPC_CFG_PROMISC_MODE	= 0x0E01,
++
++	/* Vlan offload commands */
++	HCLGE_OPC_VLAN_PORT_TX_CFG	= 0x0F01,
++	HCLGE_OPC_VLAN_PORT_RX_CFG	= 0x0F02,
++
++	/* Interrupts commands */
++	HCLGE_OPC_ADD_RING_TO_VECTOR	= 0x1503,
++	HCLGE_OPC_DEL_RING_TO_VECTOR	= 0x1504,
++
++	/* MAC commands */
++	HCLGE_OPC_MAC_VLAN_ADD		    = 0x1000,
++	HCLGE_OPC_MAC_VLAN_REMOVE	    = 0x1001,
++	HCLGE_OPC_MAC_VLAN_TYPE_ID	    = 0x1002,
++	HCLGE_OPC_MAC_VLAN_INSERT	    = 0x1003,
++	HCLGE_OPC_MAC_VLAN_ALLOCATE	    = 0x1004,
++	HCLGE_OPC_MAC_ETHTYPE_ADD	    = 0x1010,
++	HCLGE_OPC_MAC_ETHTYPE_REMOVE	= 0x1011,
++
++	/* MAC VLAN commands */
++	HCLGE_OPC_MAC_VLAN_SWITCH_PARAM	= 0x1033,
++
++	/* VLAN commands */
++	HCLGE_OPC_VLAN_FILTER_CTRL	    = 0x1100,
++	HCLGE_OPC_VLAN_FILTER_PF_CFG	= 0x1101,
++	HCLGE_OPC_VLAN_FILTER_VF_CFG	= 0x1102,
++
++	/* Flow Director commands */
++	HCLGE_OPC_FD_MODE_CTRL		= 0x1200,
++	HCLGE_OPC_FD_GET_ALLOCATION	= 0x1201,
++	HCLGE_OPC_FD_KEY_CONFIG		= 0x1202,
++	HCLGE_OPC_FD_TCAM_OP		= 0x1203,
++	HCLGE_OPC_FD_AD_OP		= 0x1204,
++	HCLGE_OPC_FD_CNT_OP		= 0x1205,
++	HCLGE_OPC_FD_USER_DEF_OP	= 0x1207,
++	HCLGE_OPC_FD_QB_CTRL		= 0x1210,
++	HCLGE_OPC_FD_QB_AD_OP		= 0x1211,
++
++	/* MDIO command */
++	HCLGE_OPC_MDIO_CONFIG		= 0x1900,
++
++	/* QCN commands */
++	HCLGE_OPC_QCN_MOD_CFG		= 0x1A01,
++	HCLGE_OPC_QCN_GRP_TMPLT_CFG	= 0x1A02,
++	HCLGE_OPC_QCN_SHAPPING_CFG	= 0x1A03,
++	HCLGE_OPC_QCN_SHAPPING_BS_CFG	= 0x1A04,
++	HCLGE_OPC_QCN_QSET_LINK_CFG	= 0x1A05,
++	HCLGE_OPC_QCN_RP_STATUS_GET	= 0x1A06,
++	HCLGE_OPC_QCN_AJUST_INIT	= 0x1A07,
++	HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
++
++	/* Mailbox command */
++	HCLGEVF_OPC_MBX_PF_TO_VF	= 0x2000,
++
++	/* Led command */
++	HCLGE_OPC_LED_STATUS_CFG	= 0xB000,
++
++	/* clear hardware resource command */
++	HCLGE_OPC_CLEAR_HW_RESOURCE	= 0x700B,
++
++	/* NCL config command */
++	HCLGE_OPC_QUERY_NCL_CONFIG	= 0x7011,
++
++	/* IMP stats command */
++	HCLGE_OPC_IMP_STATS_BD		= 0x7012,
++	HCLGE_OPC_IMP_STATS_INFO		= 0x7013,
++	HCLGE_OPC_IMP_COMPAT_CFG		= 0x701A,
++
++	/* SFP command */
++	HCLGE_OPC_GET_SFP_EEPROM	= 0x7100,
++	HCLGE_OPC_GET_SFP_EXIST		= 0x7101,
++	HCLGE_OPC_GET_SFP_INFO		= 0x7104,
++
++	/* Error INT commands */
++	HCLGE_MAC_COMMON_INT_EN		= 0x030E,
++	HCLGE_TM_SCH_ECC_INT_EN		= 0x0829,
++	HCLGE_SSU_ECC_INT_CMD		= 0x0989,
++	HCLGE_SSU_COMMON_INT_CMD	= 0x098C,
++	HCLGE_PPU_MPF_ECC_INT_CMD	= 0x0B40,
++	HCLGE_PPU_MPF_OTHER_INT_CMD	= 0x0B41,
++	HCLGE_PPU_PF_OTHER_INT_CMD	= 0x0B42,
++	HCLGE_COMMON_ECC_INT_CFG	= 0x1505,
++	HCLGE_QUERY_RAS_INT_STS_BD_NUM	= 0x1510,
++	HCLGE_QUERY_CLEAR_MPF_RAS_INT	= 0x1511,
++	HCLGE_QUERY_CLEAR_PF_RAS_INT	= 0x1512,
++	HCLGE_QUERY_MSIX_INT_STS_BD_NUM	= 0x1513,
++	HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT	= 0x1514,
++	HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT	= 0x1515,
++	HCLGE_QUERY_ALL_ERR_BD_NUM		= 0x1516,
++	HCLGE_QUERY_ALL_ERR_INFO		= 0x1517,
++	HCLGE_CONFIG_ROCEE_RAS_INT_EN	= 0x1580,
++	HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
++	HCLGE_ROCEE_PF_RAS_INT_CMD	= 0x1584,
++	HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD	= 0x1585,
++	HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD	= 0x1586,
++	HCLGE_IGU_EGU_TNL_INT_EN	= 0x1803,
++	HCLGE_IGU_COMMON_INT_EN		= 0x1806,
++	HCLGE_TM_QCN_MEM_INT_CFG	= 0x1A14,
++	HCLGE_PPP_CMD0_INT_CMD		= 0x2100,
++	HCLGE_PPP_CMD1_INT_CMD		= 0x2101,
++	HCLGE_PPP_MAC_VLAN_IDX_RD	= 0x2104,
++	HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
++	HCLGE_OPC_WOL_CFG               = 0x2200,
++	HCLGE_OPC_WOL_GET_SUPPORTED_MODE        = 0x2201,
++	HCLGE_NCSI_INT_EN		= 0x2401,
++
++	/* PHY command */
++	HCLGE_OPC_PHY_LINK_KSETTING	= 0x7025,
++	HCLGE_OPC_PHY_REG		= 0x7026,
++
++	/* Query link diagnosis info command */
++	HCLGE_OPC_QUERY_LINK_DIAGNOSIS	= 0x702A,
++};
+ enum hclge_comm_cmd_return_status {
+ 	HCLGE_COMM_CMD_EXEC_SUCCESS	= 0,
+ 	HCLGE_COMM_CMD_NO_AUTH		= 1,
+@@ -102,13 +350,18 @@ enum HCLGE_COMM_CAP_BITS {
+ 	HCLGE_COMM_CAP_TM_FLUSH_B = 31,
+ };
+ 
++struct hclge_cmdq_tx_timeout_map {
++	u32 opcode;
++	u32 tx_timeout;
++};
++
+ enum HCLGE_COMM_API_CAP_BITS {
+ 	HCLGE_COMM_API_CAP_FLEX_RSS_TBL_B,
+ };
+ 
+ enum hclge_comm_opcode_type {
+-	HCLGE_COMM_OPC_QUERY_FW_VER             = 0x0001,
+-	HCLGE_COMM_OPC_IMP_COMPAT_CFG           = 0x701A,
++	HCLGE_COMM_OPC_QUERY_FW_VER		= 0x0001,
++	HCLGE_COMM_OPC_IMP_COMPAT_CFG		= 0x701A,
+ };
+ 
+ /* capabilities bits map between imp firmware and local driver */
+@@ -117,11 +370,6 @@ struct hclge_comm_caps_bit_map {
+ 	u16 local_bit;
+ };
+ 
+-struct hclge_cmdq_tx_timeout_map {
+-	u32 opcode;
+-	u32 tx_timeout;
+-};
+-
+ struct hclge_comm_firmware_compat_cmd {
+ 	__le32 compat;
+ 	u8 rsv[20];
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 1a980ba5e59d..c2b23b31690e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -30,257 +30,6 @@ struct hclge_misc_vector {
+ #define HCLGE_CMD_FLAG_NO_INTR	BIT(4)
+ #define HCLGE_CMD_FLAG_ERR_INTR	BIT(5)
+ 
+-enum hclge_opcode_type {
+-	/* Generic commands */
+-	HCLGE_OPC_QUERY_FW_VER		= 0x0001,
+-	HCLGE_OPC_CFG_RST_TRIGGER	= 0x0020,
+-	HCLGE_OPC_GBL_RST_STATUS	= 0x0021,
+-	HCLGE_OPC_QUERY_FUNC_STATUS	= 0x0022,
+-	HCLGE_OPC_QUERY_PF_RSRC		= 0x0023,
+-	HCLGE_OPC_QUERY_VF_RSRC		= 0x0024,
+-	HCLGE_OPC_GET_CFG_PARAM		= 0x0025,
+-	HCLGE_OPC_PF_RST_DONE		= 0x0026,
+-	HCLGE_OPC_QUERY_VF_RST_RDY	= 0x0027,
+-
+-	HCLGE_OPC_STATS_64_BIT		= 0x0030,
+-	HCLGE_OPC_STATS_32_BIT		= 0x0031,
+-	HCLGE_OPC_STATS_MAC		= 0x0032,
+-	HCLGE_OPC_QUERY_MAC_REG_NUM	= 0x0033,
+-	HCLGE_OPC_STATS_MAC_ALL		= 0x0034,
+-
+-	HCLGE_OPC_QUERY_REG_NUM		= 0x0040,
+-	HCLGE_OPC_QUERY_32_BIT_REG	= 0x0041,
+-	HCLGE_OPC_QUERY_64_BIT_REG	= 0x0042,
+-	HCLGE_OPC_DFX_BD_NUM		= 0x0043,
+-	HCLGE_OPC_DFX_BIOS_COMMON_REG	= 0x0044,
+-	HCLGE_OPC_DFX_SSU_REG_0		= 0x0045,
+-	HCLGE_OPC_DFX_SSU_REG_1		= 0x0046,
+-	HCLGE_OPC_DFX_IGU_EGU_REG	= 0x0047,
+-	HCLGE_OPC_DFX_RPU_REG_0		= 0x0048,
+-	HCLGE_OPC_DFX_RPU_REG_1		= 0x0049,
+-	HCLGE_OPC_DFX_NCSI_REG		= 0x004A,
+-	HCLGE_OPC_DFX_RTC_REG		= 0x004B,
+-	HCLGE_OPC_DFX_PPP_REG		= 0x004C,
+-	HCLGE_OPC_DFX_RCB_REG		= 0x004D,
+-	HCLGE_OPC_DFX_TQP_REG		= 0x004E,
+-	HCLGE_OPC_DFX_SSU_REG_2		= 0x004F,
+-
+-	HCLGE_OPC_QUERY_DEV_SPECS	= 0x0050,
+-
+-	/* MAC command */
+-	HCLGE_OPC_CONFIG_MAC_MODE	= 0x0301,
+-	HCLGE_OPC_CONFIG_AN_MODE	= 0x0304,
+-	HCLGE_OPC_QUERY_LINK_STATUS	= 0x0307,
+-	HCLGE_OPC_CONFIG_MAX_FRM_SIZE	= 0x0308,
+-	HCLGE_OPC_CONFIG_SPEED_DUP	= 0x0309,
+-	HCLGE_OPC_QUERY_MAC_TNL_INT	= 0x0310,
+-	HCLGE_OPC_MAC_TNL_INT_EN	= 0x0311,
+-	HCLGE_OPC_CLEAR_MAC_TNL_INT	= 0x0312,
+-	HCLGE_OPC_COMMON_LOOPBACK       = 0x0315,
+-	HCLGE_OPC_QUERY_FEC_STATS       = 0x0316,
+-	HCLGE_OPC_CONFIG_FEC_MODE	= 0x031A,
+-	/* check sum command */
+-	HCLGE_OPC_CFG_CHECKSUM_EN       = 0x0601,
+-
+-	/* PTP commands */
+-	HCLGE_OPC_PTP_INT_EN		= 0x0501,
+-	HCLGE_OPC_PTP_MODE_CFG		= 0x0507,
+-
+-	/* PFC/Pause commands */
+-	HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
+-	HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
+-	HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
+-	HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
+-	HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
+-	HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
+-	HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
+-	HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
+-	HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
+-	HCLGE_OPC_QOS_MAP               = 0x070A,
+-
+-	/* ETS/scheduler commands */
+-	HCLGE_OPC_TM_PG_TO_PRI_LINK	= 0x0804,
+-	HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
+-	HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
+-	HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
+-	HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
+-	HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
+-	HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
+-	HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
+-	HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
+-	HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
+-	HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
+-	HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
+-	HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
+-	HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
+-	HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
+-	HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
+-	HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
+-	HCLGE_OPC_TM_NODES		= 0x0816,
+-	HCLGE_OPC_ETS_TC_WEIGHT		= 0x0843,
+-	HCLGE_OPC_QSET_DFX_STS		= 0x0844,
+-	HCLGE_OPC_PRI_DFX_STS		= 0x0845,
+-	HCLGE_OPC_PG_DFX_STS		= 0x0846,
+-	HCLGE_OPC_PORT_DFX_STS		= 0x0847,
+-	HCLGE_OPC_SCH_NQ_CNT		= 0x0848,
+-	HCLGE_OPC_SCH_RQ_CNT		= 0x0849,
+-	HCLGE_OPC_TM_INTERNAL_STS	= 0x0850,
+-	HCLGE_OPC_TM_INTERNAL_CNT	= 0x0851,
+-	HCLGE_OPC_TM_INTERNAL_STS_1	= 0x0852,
+-	HCLGE_OPC_TM_FLUSH		= 0x0872,
+-
+-	/* Packet buffer allocate commands */
+-	HCLGE_OPC_TX_BUFF_ALLOC		= 0x0901,
+-	HCLGE_OPC_RX_PRIV_BUFF_ALLOC	= 0x0902,
+-	HCLGE_OPC_RX_PRIV_WL_ALLOC	= 0x0903,
+-	HCLGE_OPC_RX_COM_THRD_ALLOC	= 0x0904,
+-	HCLGE_OPC_RX_COM_WL_ALLOC	= 0x0905,
+-	HCLGE_OPC_RX_GBL_PKT_CNT	= 0x0906,
+-
+-	/* TQP management command */
+-	HCLGE_OPC_SET_TQP_MAP		= 0x0A01,
+-
+-	/* TQP commands */
+-	HCLGE_OPC_CFG_TX_QUEUE		= 0x0B01,
+-	HCLGE_OPC_QUERY_TX_POINTER	= 0x0B02,
+-	HCLGE_OPC_QUERY_TX_STATS	= 0x0B03,
+-	HCLGE_OPC_TQP_TX_QUEUE_TC	= 0x0B04,
+-	HCLGE_OPC_CFG_RX_QUEUE		= 0x0B11,
+-	HCLGE_OPC_QUERY_RX_POINTER	= 0x0B12,
+-	HCLGE_OPC_QUERY_RX_STATS	= 0x0B13,
+-	HCLGE_OPC_STASH_RX_QUEUE_LRO	= 0x0B16,
+-	HCLGE_OPC_CFG_RX_QUEUE_LRO	= 0x0B17,
+-	HCLGE_OPC_CFG_COM_TQP_QUEUE	= 0x0B20,
+-	HCLGE_OPC_RESET_TQP_QUEUE	= 0x0B22,
+-
+-	/* PPU commands */
+-	HCLGE_OPC_PPU_PF_OTHER_INT_DFX	= 0x0B4A,
+-
+-	/* TSO command */
+-	HCLGE_OPC_TSO_GENERIC_CONFIG	= 0x0C01,
+-	HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
+-
+-	/* RSS commands */
+-	HCLGE_OPC_RSS_GENERIC_CONFIG	= 0x0D01,
+-	HCLGE_OPC_RSS_INDIR_TABLE	= 0x0D07,
+-	HCLGE_OPC_RSS_TC_MODE		= 0x0D08,
+-	HCLGE_OPC_RSS_INPUT_TUPLE	= 0x0D02,
+-
+-	/* Promisuous mode command */
+-	HCLGE_OPC_CFG_PROMISC_MODE	= 0x0E01,
+-
+-	/* Vlan offload commands */
+-	HCLGE_OPC_VLAN_PORT_TX_CFG	= 0x0F01,
+-	HCLGE_OPC_VLAN_PORT_RX_CFG	= 0x0F02,
+-
+-	/* Interrupts commands */
+-	HCLGE_OPC_ADD_RING_TO_VECTOR	= 0x1503,
+-	HCLGE_OPC_DEL_RING_TO_VECTOR	= 0x1504,
+-
+-	/* MAC commands */
+-	HCLGE_OPC_MAC_VLAN_ADD		    = 0x1000,
+-	HCLGE_OPC_MAC_VLAN_REMOVE	    = 0x1001,
+-	HCLGE_OPC_MAC_VLAN_TYPE_ID	    = 0x1002,
+-	HCLGE_OPC_MAC_VLAN_INSERT	    = 0x1003,
+-	HCLGE_OPC_MAC_VLAN_ALLOCATE	    = 0x1004,
+-	HCLGE_OPC_MAC_ETHTYPE_ADD	    = 0x1010,
+-	HCLGE_OPC_MAC_ETHTYPE_REMOVE	= 0x1011,
+-
+-	/* MAC VLAN commands */
+-	HCLGE_OPC_MAC_VLAN_SWITCH_PARAM	= 0x1033,
+-
+-	/* VLAN commands */
+-	HCLGE_OPC_VLAN_FILTER_CTRL	    = 0x1100,
+-	HCLGE_OPC_VLAN_FILTER_PF_CFG	= 0x1101,
+-	HCLGE_OPC_VLAN_FILTER_VF_CFG	= 0x1102,
+-
+-	/* Flow Director commands */
+-	HCLGE_OPC_FD_MODE_CTRL		= 0x1200,
+-	HCLGE_OPC_FD_GET_ALLOCATION	= 0x1201,
+-	HCLGE_OPC_FD_KEY_CONFIG		= 0x1202,
+-	HCLGE_OPC_FD_TCAM_OP		= 0x1203,
+-	HCLGE_OPC_FD_AD_OP		= 0x1204,
+-	HCLGE_OPC_FD_CNT_OP		= 0x1205,
+-	HCLGE_OPC_FD_USER_DEF_OP	= 0x1207,
+-	HCLGE_OPC_FD_QB_CTRL		= 0x1210,
+-	HCLGE_OPC_FD_QB_AD_OP		= 0x1211,
+-
+-	/* MDIO command */
+-	HCLGE_OPC_MDIO_CONFIG		= 0x1900,
+-
+-	/* QCN commands */
+-	HCLGE_OPC_QCN_MOD_CFG		= 0x1A01,
+-	HCLGE_OPC_QCN_GRP_TMPLT_CFG	= 0x1A02,
+-	HCLGE_OPC_QCN_SHAPPING_CFG	= 0x1A03,
+-	HCLGE_OPC_QCN_SHAPPING_BS_CFG	= 0x1A04,
+-	HCLGE_OPC_QCN_QSET_LINK_CFG	= 0x1A05,
+-	HCLGE_OPC_QCN_RP_STATUS_GET	= 0x1A06,
+-	HCLGE_OPC_QCN_AJUST_INIT	= 0x1A07,
+-	HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
+-
+-	/* Mailbox command */
+-	HCLGEVF_OPC_MBX_PF_TO_VF	= 0x2000,
+-
+-	/* Led command */
+-	HCLGE_OPC_LED_STATUS_CFG	= 0xB000,
+-
+-	/* clear hardware resource command */
+-	HCLGE_OPC_CLEAR_HW_RESOURCE	= 0x700B,
+-
+-	/* NCL config command */
+-	HCLGE_OPC_QUERY_NCL_CONFIG	= 0x7011,
+-
+-	/* IMP stats command */
+-	HCLGE_OPC_IMP_STATS_BD		= 0x7012,
+-	HCLGE_OPC_IMP_STATS_INFO		= 0x7013,
+-	HCLGE_OPC_IMP_COMPAT_CFG		= 0x701A,
+-
+-	/* SFP command */
+-	HCLGE_OPC_GET_SFP_EEPROM	= 0x7100,
+-	HCLGE_OPC_GET_SFP_EXIST		= 0x7101,
+-	HCLGE_OPC_GET_SFP_INFO		= 0x7104,
+-
+-	/* Error INT commands */
+-	HCLGE_MAC_COMMON_INT_EN		= 0x030E,
+-	HCLGE_TM_SCH_ECC_INT_EN		= 0x0829,
+-	HCLGE_SSU_ECC_INT_CMD		= 0x0989,
+-	HCLGE_SSU_COMMON_INT_CMD	= 0x098C,
+-	HCLGE_PPU_MPF_ECC_INT_CMD	= 0x0B40,
+-	HCLGE_PPU_MPF_OTHER_INT_CMD	= 0x0B41,
+-	HCLGE_PPU_PF_OTHER_INT_CMD	= 0x0B42,
+-	HCLGE_COMMON_ECC_INT_CFG	= 0x1505,
+-	HCLGE_QUERY_RAS_INT_STS_BD_NUM	= 0x1510,
+-	HCLGE_QUERY_CLEAR_MPF_RAS_INT	= 0x1511,
+-	HCLGE_QUERY_CLEAR_PF_RAS_INT	= 0x1512,
+-	HCLGE_QUERY_MSIX_INT_STS_BD_NUM	= 0x1513,
+-	HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT	= 0x1514,
+-	HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT	= 0x1515,
+-	HCLGE_QUERY_ALL_ERR_BD_NUM		= 0x1516,
+-	HCLGE_QUERY_ALL_ERR_INFO		= 0x1517,
+-	HCLGE_CONFIG_ROCEE_RAS_INT_EN	= 0x1580,
+-	HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
+-	HCLGE_ROCEE_PF_RAS_INT_CMD	= 0x1584,
+-	HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD	= 0x1585,
+-	HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD	= 0x1586,
+-	HCLGE_IGU_EGU_TNL_INT_EN	= 0x1803,
+-	HCLGE_IGU_COMMON_INT_EN		= 0x1806,
+-	HCLGE_TM_QCN_MEM_INT_CFG	= 0x1A14,
+-	HCLGE_PPP_CMD0_INT_CMD		= 0x2100,
+-	HCLGE_PPP_CMD1_INT_CMD		= 0x2101,
+-	HCLGE_PPP_MAC_VLAN_IDX_RD	= 0x2104,
+-	HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
+-	HCLGE_OPC_WOL_CFG               = 0x2200,
+-	HCLGE_OPC_WOL_GET_SUPPORTED_MODE        = 0x2201,
+-	HCLGE_NCSI_INT_EN		= 0x2401,
+-
+-	/* PHY command */
+-	HCLGE_OPC_PHY_LINK_KSETTING	= 0x7025,
+-	HCLGE_OPC_PHY_REG		= 0x7026,
+-
+-	/* Query link diagnosis info command */
+-	HCLGE_OPC_QUERY_LINK_DIAGNOSIS	= 0x702A,
+-};
+-
+ #define HCLGE_TQP_REG_OFFSET		0x80000
+ #define HCLGE_TQP_REG_SIZE		0x200
+ 
+-- 
+2.34.1
+
diff --git a/patches/0608-net-hns3-refactor-PF-cmdq-resource-APIs-with-new-com.patch b/patches/0608-net-hns3-refactor-PF-cmdq-resource-APIs-with-new-com.patch
new file mode 100644
index 0000000..275cbff
--- /dev/null
+++ b/patches/0608-net-hns3-refactor-PF-cmdq-resource-APIs-with-new-com.patch
@@ -0,0 +1,988 @@
+From 69f914597fdb37f7bb74a96e56af0e34c86de375 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:53 +0800
+Subject: [PATCH 247/283] net: hns3: refactor PF cmdq resource APIs with new
+ common APIs
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit d3c69a8812c22d84eb12f1a60f91889a63a5fc51
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d3c69a8812c22d84eb12f1a60f91889a63a5fc51
+
+----------------------------------------------------------------------
+
+This patch uses common cmdq resource allocate/free/query APIs to replace
+the old APIs in PF cmdq module and deletes the old cmdq resource APIs.
+Still we kept hclge_cmd_setup_basic_desc name as a seam API to avoid too
+many meaningless replacement.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+---
+ .../hisilicon/hns3/hns3_cae/hns3_cae_cmd.c    |  10 +-
+ .../hisilicon/hns3/hns3_cae/hns3_cae_fd.c     |   2 +-
+ .../hns3/hns3_cae/hns3_cae_hilink_param.c     |  12 +-
+ .../hisilicon/hns3/hns3_cae/hns3_cae_port.c   |   4 +-
+ .../hisilicon/hns3/hns3_cae/hns3_cae_qos.c    |  16 +-
+ .../hisilicon/hns3/hns3_cae/hns3_cae_xsfp.c   |   4 +-
+ .../hns3/hns3_common/hclge_comm_cmd.c         |   2 +-
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         | 216 ++----------------
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |  64 +-----
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     |  14 +-
+ .../hisilicon/hns3/hns3pf/hclge_err.c         |  25 +-
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  54 ++---
+ 12 files changed, 89 insertions(+), 334 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.c
+index 203ee3135f9d..d26dbfc36c9b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.c
+@@ -137,11 +137,11 @@ static int hns3_cae_cmd_check_retval(struct hclge_hw *hw,
+ 
+ void hns3_cae_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
+ {
+-	desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
++	desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR | HCLGE_COMM_CMD_FLAG_IN);
+ 	if (is_read)
+-		desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
++		desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR);
+ 	else
+-		desc->flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
++		desc->flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_WR);
+ }
+ 
+ void hns3_cae_cmd_setup_basic_desc(struct hclge_desc *desc,
+@@ -149,10 +149,10 @@ void hns3_cae_cmd_setup_basic_desc(struct hclge_desc *desc,
+ {
+ 	memset((void *)desc, 0, sizeof(struct hclge_desc));
+ 	desc->opcode = cpu_to_le16(opcode);
+-	desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
++	desc->flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR | HCLGE_COMM_CMD_FLAG_IN);
+ 
+ 	if (is_read)
+-		desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
++		desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_WR);
+ }
+ 
+ /**
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_fd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_fd.c
+index 21e034153808..2a1b26fbd81b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_fd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_fd.c
+@@ -171,7 +171,7 @@ static int hns3_cae_send_tcam_op_cmd(struct hclge_dev *hdev, u8 *buf_in,
+ 		hns3_cae_cmd_setup_basic_desc(pdesc, HCLGE_OPC_FD_TCAM_OP,
+ 					      param->is_read ? true : false);
+ 		if (i < HNS3_CAE_FD_TCAM_BD_NUM - 1)
+-			pdesc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			pdesc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	}
+ 
+ 	req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_hilink_param.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_hilink_param.c
+index 6aa003ff0a2c..696f31759ee7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_hilink_param.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_hilink_param.c
+@@ -39,10 +39,10 @@ static int hns3_get_hilink_ctle(struct hclge_dev *hdev,
+ 			ctle_desc[0].data[0] = lane_start | (lane_len << 4);
+ 
+ 		if (i < HILINK_PARAM_CMD_BD_LEN - 1)
+-			ctle_desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			ctle_desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+ 			ctle_desc[i].flag &=
+-			    ~(cpu_to_le16(HCLGE_CMD_FLAG_NEXT));
++			    ~(cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT));
+ 	}
+ 
+ 	ret = hns3_cae_cmd_send(hdev, ctle_desc, HILINK_PARAM_CMD_BD_LEN);
+@@ -91,9 +91,9 @@ static int hns3_get_hilink_dfe(struct hclge_dev *hdev,
+ 			dfe_desc[0].data[0] = lane_start | (lane_len << 4);
+ 
+ 		if (i < HILINK_PARAM_CMD_BD_LEN - 1)
+-			dfe_desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			dfe_desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+-			dfe_desc[i].flag &= ~(cpu_to_le16(HCLGE_CMD_FLAG_NEXT));
++			dfe_desc[i].flag &= ~(cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT));
+ 	}
+ 
+ 	ret = hns3_cae_cmd_send(hdev, dfe_desc, HILINK_PARAM_CMD_BD_LEN);
+@@ -138,9 +138,9 @@ static int hns3_get_hilink_ffe(struct hclge_dev *hdev,
+ 			ffe_desc[0].data[0] = lane_start | (lane_len << 4);
+ 
+ 		if (i < HILINK_PARAM_CMD_BD_LEN - 1)
+-			ffe_desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			ffe_desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+-			ffe_desc[i].flag &= ~(cpu_to_le16(HCLGE_CMD_FLAG_NEXT));
++			ffe_desc[i].flag &= ~(cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT));
+ 	}
+ 
+ 	ret = hns3_cae_cmd_send(hdev, ffe_desc, HILINK_PARAM_CMD_BD_LEN);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_port.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_port.c
+index 9af8d019b655..2df2f6a3b158 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_port.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_port.c
+@@ -102,10 +102,10 @@ int hns3_get_port_info(const struct hns3_nic_priv *net_priv,
+ 		hns3_cae_cmd_setup_basic_desc(&port_desc[i],
+ 					      HCLGE_OPC_DUMP_PORT_INFO, true);
+ 		if (i < bd_num - 1)
+-			port_desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			port_desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+ 			port_desc[i].flag &=
+-			    ~(cpu_to_le16(HCLGE_CMD_FLAG_NEXT));
++			    ~(cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT));
+ 	}
+ 
+ 	ret = hns3_cae_cmd_send(hdev, port_desc, bd_num);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_qos.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_qos.c
+index 4bbe8bbcfe03..9778ac07a5f4 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_qos.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_qos.c
+@@ -34,9 +34,9 @@ int hns3_cmd_rx_priv_wl_config(struct hclge_dev *hdev, u16 tc,
+ 		req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
+ 		/* The first descriptor set the NEXT bit to 1 */
+ 		if (i == 0)
+-			desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+-			desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 
+ 		for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
+ 			idx = i * HCLGE_TC_NUM_ONE_DESC + j;
+@@ -107,9 +107,9 @@ int hns3_cmd_common_thrd_config(struct hclge_dev *hdev, u16 tc,
+ 		req = (struct hclge_rx_com_thrd *)desc[i].data;
+ 
+ 		if (i == 0)
+-			desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+-			desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 
+ 		for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
+ 			idx = i * HCLGE_TC_NUM_ONE_DESC + j;
+@@ -353,9 +353,9 @@ int hns3_cae_show_comm_thres(const struct hns3_nic_priv *net_priv,
+ 					      HCLGE_OPC_RX_COM_THRD_ALLOC,
+ 					      true);
+ 		if (i == 0)
+-			desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+-			desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	}
+ 
+ 	status = hns3_cae_cmd_send(hdev, desc, HNS3_CAE_THRD_ALLOC_BD_NUM);
+@@ -404,9 +404,9 @@ int hns3_cae_show_rx_priv_wl(const struct hns3_nic_priv *net_priv,
+ 					      HCLGE_OPC_RX_PRIV_WL_ALLOC,
+ 					      true);
+ 		if (i == 0)
+-			desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+-			desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	}
+ 
+ 	status = hns3_cae_cmd_send(hdev, desc, HNS3_CAE_WL_ALLOC_BD_NUM);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_xsfp.c b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_xsfp.c
+index d6295d9e7427..71a4bd22c4ba 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_xsfp.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_xsfp.c
+@@ -57,9 +57,9 @@ static int _hns3_get_sfpinfo(struct hnae3_handle *handle, u8 *buff,
+ 			desc[0].data[0] = offset | (size << 16);
+ 
+ 		if (i < HCLGE_SFP_INFO_LEN - 1)
+-			desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+-			desc[i].flag &= ~(cpu_to_le16(HCLGE_CMD_FLAG_NEXT));
++			desc[i].flag &= ~(cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT));
+ 	}
+ 
+ 	ret = hns3_cae_cmd_send(hdev, desc, HCLGE_SFP_INFO_LEN);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index c96620269037..67c084f7dce0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -77,7 +77,7 @@ static int hclge_comm_alloc_cmd_desc(struct hclge_comm_cmq_ring *ring)
+ {
+ 	int size  = ring->desc_num * sizeof(struct hclge_desc);
+ 
+-	ring->desc = dma_alloc_coherent(&ring->pdev->dev,
++	ring->desc = dma_zalloc_coherent(&ring->pdev->dev,
+ 					size, &ring->desc_dma_addr, GFP_KERNEL);
+ 	if (!ring->desc)
+ 		return -ENOMEM;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index dc73c90605dc..3e06eba7a90c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -12,100 +12,6 @@
+ #include "hnae3.h"
+ #include "hclge_main.h"
+ 
+-static int hclge_alloc_cmd_desc(struct hclge_comm_cmq_ring *ring)
+-{
+-	int size  = ring->desc_num * sizeof(struct hclge_desc);
+-
+-	ring->desc = dma_zalloc_coherent(cmq_ring_to_dev(ring),
+-					 size, &ring->desc_dma_addr,
+-					 GFP_KERNEL);
+-	if (!ring->desc)
+-		return -ENOMEM;
+-
+-	return 0;
+-}
+-
+-static void hclge_free_cmd_desc(struct hclge_comm_cmq_ring *ring)
+-{
+-	int size  = ring->desc_num * sizeof(struct hclge_desc);
+-
+-	if (ring->desc) {
+-		dma_free_coherent(&ring->pdev->dev, size,
+-				  ring->desc, ring->desc_dma_addr);
+-		ring->desc = NULL;
+-	}
+-}
+-
+-static int hclge_alloc_cmd_queue(struct hclge_dev *hdev, int ring_type)
+-{
+-	struct hclge_hw *hw = &hdev->hw;
+-	struct hclge_comm_cmq_ring *ring =
+-		(ring_type == HCLGE_TYPE_CSQ) ? &hw->hw.cmq.csq :
+-						&hw->hw.cmq.crq;
+-	int ret;
+-
+-	ring->ring_type = ring_type;
+-	ring->pdev = hdev->pdev;
+-
+-	ret = hclge_alloc_cmd_desc(ring);
+-	if (ret) {
+-		dev_err(&hdev->pdev->dev, "descriptor %s alloc error %d\n",
+-			(ring_type == HCLGE_TYPE_CSQ) ? "CSQ" : "CRQ", ret);
+-		return ret;
+-	}
+-
+-	return 0;
+-}
+-
+-void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read)
+-{
+-	desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
+-	if (is_read)
+-		desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
+-	else
+-		desc->flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
+-}
+-
+-void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
+-				enum hclge_opcode_type opcode, bool is_read)
+-{
+-	memset((void *)desc, 0, sizeof(struct hclge_desc));
+-	desc->opcode = cpu_to_le16(opcode);
+-	desc->flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
+-
+-	if (is_read)
+-		desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_WR);
+-}
+-
+-static void hclge_cmd_config_regs(struct hclge_hw *hw,
+-				  struct hclge_comm_cmq_ring *ring)
+-{
+-	dma_addr_t dma = ring->desc_dma_addr;
+-	u32 reg_val;
+-
+-	if (ring->ring_type == HCLGE_TYPE_CSQ) {
+-		hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_L_REG,
+-				lower_32_bits(dma));
+-		hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_H_REG,
+-				upper_32_bits(dma));
+-		reg_val = hclge_read_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG);
+-		reg_val &= HCLGE_NIC_SW_RST_RDY;
+-		reg_val |= ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S;
+-		hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG, reg_val);
+-		hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0);
+-		hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0);
+-	} else {
+-		hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG,
+-				lower_32_bits(dma));
+-		hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_H_REG,
+-				upper_32_bits(dma));
+-		hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG,
+-				ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S);
+-		hclge_write_dev(hw, HCLGE_NIC_CRQ_HEAD_REG, 0);
+-		hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
+-	}
+-}
+-
+ static void hclge_cmd_clear_regs(struct hclge_hw *hw)
+ {
+ 	hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_L_REG, 0);
+@@ -120,12 +26,6 @@ static void hclge_cmd_clear_regs(struct hclge_hw *hw)
+ 	hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
+ }
+ 
+-static void hclge_cmd_init_regs(struct hclge_hw *hw)
+-{
+-	hclge_cmd_config_regs(hw, &hw->hw.cmq.csq);
+-	hclge_cmd_config_regs(hw, &hw->hw.cmq.crq);
+-}
+-
+ /**
+  * hclge_cmd_send - send command to command queue
+  * @hw: pointer to the hw struct
+@@ -140,74 +40,6 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
+ 	return hclge_comm_cmd_send(&hw->hw, desc, num);
+ }
+ 
+-static void hclge_set_default_capability(struct hclge_dev *hdev)
+-{
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+-
+-	set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
+-	set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);
+-	set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
+-}
+-
+-static const struct hclge_caps_bit_map hclge_cmd_caps_bit_map0[] = {
+-	{HCLGE_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
+-	{HCLGE_CAP_PTP_B, HNAE3_DEV_SUPPORT_PTP_B},
+-	{HCLGE_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
+-	{HCLGE_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
+-	{HCLGE_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
+-	{HCLGE_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
+-	{HCLGE_CAP_FD_FORWARD_TC_B, HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B},
+-	{HCLGE_CAP_FEC_B, HNAE3_DEV_SUPPORT_FEC_B},
+-	{HCLGE_CAP_PAUSE_B, HNAE3_DEV_SUPPORT_PAUSE_B},
+-	{HCLGE_CAP_PHY_IMP_B, HNAE3_DEV_SUPPORT_PHY_IMP_B},
+-	{HCLGE_CAP_RAS_IMP_B, HNAE3_DEV_SUPPORT_RAS_IMP_B},
+-	{HCLGE_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
+-	{HCLGE_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B},
+-	{HCLGE_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B},
+-};
+-
+-static void hclge_parse_capability(struct hclge_dev *hdev,
+-				   struct hclge_query_version_cmd *cmd)
+-{
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+-	u32 caps, i;
+-
+-	caps = __le32_to_cpu(cmd->caps[0]);
+-	for (i = 0; i < ARRAY_SIZE(hclge_cmd_caps_bit_map0); i++)
+-		if (hnae3_get_bit(caps, hclge_cmd_caps_bit_map0[i].imp_bit))
+-			set_bit(hclge_cmd_caps_bit_map0[i].local_bit,
+-				ae_dev->caps);
+-}
+-
+-static enum hclge_comm_cmd_status
+-hclge_cmd_query_version_and_capability(struct hclge_dev *hdev)
+-{
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+-	struct hclge_query_version_cmd *resp;
+-	struct hclge_desc desc;
+-	int ret;
+-
+-	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FW_VER, 1);
+-	resp = (struct hclge_query_version_cmd *)desc.data;
+-
+-	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+-	if (ret)
+-		return ret;
+-
+-	hdev->fw_version = le32_to_cpu(resp->firmware);
+-
+-	ae_dev->dev_version = le32_to_cpu(resp->hardware) <<
+-					  HNAE3_PCI_REVISION_BIT_SIZE;
+-	ae_dev->dev_version |= hdev->pdev->revision;
+-
+-	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+-		hclge_set_default_capability(hdev);
+-
+-	hclge_parse_capability(hdev, resp);
+-
+-	return ret;
+-}
+-
+ int hclge_cmd_queue_init(struct hclge_dev *hdev)
+ {
+ 	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+@@ -233,14 +65,14 @@ int hclge_cmd_queue_init(struct hclge_dev *hdev)
+ 	cmdq->tx_timeout = HCLGE_CMDQ_TX_TIMEOUT;
+ 
+ 	/* Setup queue rings */
+-	ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CSQ);
++	ret = hclge_comm_alloc_cmd_queue(&hdev->hw.hw, HCLGE_COMM_TYPE_CSQ);
+ 	if (ret) {
+ 		dev_err(&hdev->pdev->dev,
+ 			"CSQ ring setup error %d\n", ret);
+ 		return ret;
+ 	}
+ 
+-	ret = hclge_alloc_cmd_queue(hdev, HCLGE_TYPE_CRQ);
++	ret = hclge_comm_alloc_cmd_queue(&hdev->hw.hw, HCLGE_COMM_TYPE_CRQ);
+ 	if (ret) {
+ 		dev_err(&hdev->pdev->dev,
+ 			"CRQ ring setup error %d\n", ret);
+@@ -249,35 +81,10 @@ int hclge_cmd_queue_init(struct hclge_dev *hdev)
+ 
+ 	return 0;
+ err_csq:
+-	hclge_free_cmd_desc(&hdev->hw.hw.cmq.csq);
++	hclge_comm_free_cmd_desc(&hdev->hw.hw.cmq.csq);
+ 	return ret;
+ }
+ 
+-/* ask the firmware to enable some features, driver can work without it. */
+-static int hclge_firmware_compat_config(struct hclge_dev *hdev, bool en)
+-{
+-	struct hclge_firmware_compat_cmd *req;
+-	struct hclge_desc desc;
+-	u32 compat = 0;
+-
+-	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_IMP_COMPAT_CFG, false);
+-
+-	if (en) {
+-		req = (struct hclge_firmware_compat_cmd *)desc.data;
+-
+-		hnae3_set_bit(compat, HCLGE_LINK_EVENT_REPORT_EN_B, 1);
+-		hnae3_set_bit(compat, HCLGE_NCSI_ERROR_REPORT_EN_B, 1);
+-		if (hnae3_dev_phy_imp_supported(hdev))
+-			hnae3_set_bit(compat, HCLGE_PHY_IMP_EN_B, 1);
+-		hnae3_set_bit(compat, HCLGE_MAC_STATS_EXT_EN_B, 1);
+-		hnae3_set_bit(compat, HCLGE_SYNC_RX_RING_HEAD_EN_B, 1);
+-
+-		req->compat = cpu_to_le32(compat);
+-	}
+-
+-	return hclge_cmd_send(&hdev->hw, &desc, 1);
+-}
+-
+ int hclge_cmd_init(struct hclge_dev *hdev)
+ {
+ 	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+@@ -291,7 +98,7 @@ int hclge_cmd_init(struct hclge_dev *hdev)
+ 	cmdq->crq.next_to_clean = 0;
+ 	cmdq->crq.next_to_use = 0;
+ 
+-	hclge_cmd_init_regs(&hdev->hw);
++	hclge_comm_cmd_init_regs(&hdev->hw.hw);
+ 
+ 	spin_unlock(&cmdq->crq.lock);
+ 	spin_unlock_bh(&cmdq->csq.lock);
+@@ -310,7 +117,10 @@ int hclge_cmd_init(struct hclge_dev *hdev)
+ 	}
+ 
+ 	/* get version and device capabilities */
+-	ret = hclge_cmd_query_version_and_capability(hdev);
++	ret = hclge_comm_cmd_query_version_and_capability(hdev->ae_dev,
++							  &hdev->hw.hw,
++							  &hdev->fw_version,
++							  true);
+ 	if (ret) {
+ 		dev_err(&hdev->pdev->dev,
+ 			"failed to query version and capabilities, ret = %d\n",
+@@ -331,7 +141,8 @@ int hclge_cmd_init(struct hclge_dev *hdev)
+ 	/* ask the firmware to enable some features, driver can work without
+ 	 * it.
+ 	 */
+-	ret = hclge_firmware_compat_config(hdev, true);
++	ret = hclge_comm_firmware_compat_config(hdev->ae_dev,
++						&hdev->hw.hw, true);
+ 	if (ret)
+ 		dev_warn(&hdev->pdev->dev,
+ 			 "Firmware compatible features not enabled(%d).\n",
+@@ -351,7 +162,8 @@ void hclge_cmd_uninit(struct hclge_dev *hdev)
+ 
+ 	cmdq->csq.pdev = hdev->pdev;
+ 
+-	hclge_firmware_compat_config(hdev, false);
++	hclge_comm_firmware_compat_config(hdev->ae_dev, &hdev->hw.hw,
++					  false);
+ 
+ 	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 	/* wait to ensure that the firmware completes the possible left
+@@ -364,6 +176,6 @@ void hclge_cmd_uninit(struct hclge_dev *hdev)
+ 	spin_unlock(&cmdq->crq.lock);
+ 	spin_unlock_bh(&cmdq->csq.lock);
+ 
+-	hclge_free_cmd_desc(&cmdq->csq);
+-	hclge_free_cmd_desc(&cmdq->crq);
++	hclge_comm_free_cmd_desc(&cmdq->csq);
++	hclge_comm_free_cmd_desc(&cmdq->crq);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index c2b23b31690e..1262d708a9ff 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -23,12 +23,9 @@ struct hclge_misc_vector {
+ 	char name[HNAE3_INT_NAME_LEN];
+ };
+ 
+-#define HCLGE_CMD_FLAG_IN	BIT(0)
+-#define HCLGE_CMD_FLAG_OUT	BIT(1)
+-#define HCLGE_CMD_FLAG_NEXT	BIT(2)
+-#define HCLGE_CMD_FLAG_WR	BIT(3)
+-#define HCLGE_CMD_FLAG_NO_INTR	BIT(4)
+-#define HCLGE_CMD_FLAG_ERR_INTR	BIT(5)
++#define hclge_cmd_setup_basic_desc(desc, opcode, is_read) \
++	hclge_comm_cmd_setup_basic_desc(desc, (enum hclge_comm_opcode_type)opcode, \
++					is_read)
+ 
+ #define HCLGE_TQP_REG_OFFSET		0x80000
+ #define HCLGE_TQP_REG_SIZE		0x200
+@@ -96,34 +93,6 @@ struct hclge_rx_priv_buff_cmd {
+ 	u8 rsv[6];
+ };
+ 
+-enum HCLGE_CAP_BITS {
+-	HCLGE_CAP_UDP_GSO_B,
+-	HCLGE_CAP_QB_B,
+-	HCLGE_CAP_FD_FORWARD_TC_B,
+-	HCLGE_CAP_PTP_B,
+-	HCLGE_CAP_INT_QL_B,
+-	HCLGE_CAP_HW_TX_CSUM_B,
+-	HCLGE_CAP_TX_PUSH_B,
+-	HCLGE_CAP_PHY_IMP_B,
+-	HCLGE_CAP_TQP_TXRX_INDEP_B,
+-	HCLGE_CAP_HW_PAD_B,
+-	HCLGE_CAP_STASH_B,
+-	HCLGE_CAP_UDP_TUNNEL_CSUM_B,
+-	HCLGE_CAP_RAS_IMP_B = 12,
+-	HCLGE_CAP_FEC_B = 13,
+-	HCLGE_CAP_PAUSE_B = 14,
+-	HCLGE_CAP_RXD_ADV_LAYOUT_B = 15,
+-	HCLGE_CAP_PORT_VLAN_BYPASS_B = 17,
+-};
+-
+-#define HCLGE_QUERY_CAP_LENGTH		3
+-struct hclge_query_version_cmd {
+-	__le32 firmware;
+-	__le32 hardware;
+-	__le32 rsv;
+-	__le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
+-};
+-
+ #define HCLGE_RX_PRIV_EN_B	15
+ #define HCLGE_TC_NUM_ONE_DESC	4
+ struct hclge_priv_wl {
+@@ -747,13 +716,6 @@ struct hclge_common_lb_cmd {
+ #define HCLGE_DEFAULT_NON_DCB_DV	0x7800	/* 30K byte */
+ #define HCLGE_NON_DCB_ADDITIONAL_BUF	0x1400	/* 5120 byte */
+ 
+-#define HCLGE_TYPE_CRQ			0
+-#define HCLGE_TYPE_CSQ			1
+-
+-/* this bit indicates that the driver is ready for hardware reset */
+-#define HCLGE_NIC_SW_RST_RDY_B		16
+-#define HCLGE_NIC_SW_RST_RDY		BIT(HCLGE_NIC_SW_RST_RDY_B)
+-
+ #define HCLGE_NIC_CMQ_DESC_NUM		1024
+ #define HCLGE_NIC_CMQ_DESC_NUM_S	3
+ 
+@@ -894,16 +856,6 @@ struct hclge_query_ppu_pf_other_int_dfx_cmd {
+ 	u8 rsv[4];
+ };
+ 
+-#define HCLGE_LINK_EVENT_REPORT_EN_B	0
+-#define HCLGE_NCSI_ERROR_REPORT_EN_B	1
+-#define HCLGE_PHY_IMP_EN_B		2
+-#define HCLGE_MAC_STATS_EXT_EN_B	3
+-#define HCLGE_SYNC_RX_RING_HEAD_EN_B	4
+-struct hclge_firmware_compat_cmd {
+-	__le32 compat;
+-	u8 rsv[20];
+-};
+-
+ #define HCLGE_SFP_INFO_CMD_NUM	6
+ #define HCLGE_SFP_INFO_BD0_LEN	20
+ #define HCLGE_SFP_INFO_BDX_LEN	24
+@@ -989,12 +941,6 @@ struct hclge_phy_reg_cmd {
+ 	u8 rsv2[12];
+ };
+ 
+-/* capabilities bits map between imp firmware and local driver */
+-struct hclge_caps_bit_map {
+-	u16 imp_bit;
+-	u16 local_bit;
+-};
+-
+ int hclge_cmd_init(struct hclge_dev *hdev);
+ enum HCLGE_WOL_MODE {
+ 	HCLGE_WOL_PHY           = BIT(0),
+@@ -1022,10 +968,6 @@ struct hclge_query_wol_supported_cmd {
+ 
+ struct hclge_hw;
+ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
+-void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
+-				enum hclge_opcode_type opcode, bool is_read);
+-void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
+-
+ enum hclge_comm_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
+ 						struct hclge_desc *desc);
+ enum hclge_comm_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index 087079070353..407ba8d9a10c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -165,7 +165,7 @@ static int hclge_dbg_cmd_send(struct hclge_dev *hdev,
+ 	desc->data[0] = cpu_to_le32(index);
+ 
+ 	for (i = 1; i < bd_num; i++) {
+-		desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++		desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		desc++;
+ 		hclge_cmd_setup_basic_desc(desc, cmd, true);
+ 	}
+@@ -1259,7 +1259,7 @@ static int hclge_dbg_dump_rx_priv_wl_buf_cfg(struct hclge_dev *hdev, char *buf,
+ 	int i, ret;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_PRIV_WL_ALLOC, true);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_RX_PRIV_WL_ALLOC, true);
+ 	ret = hclge_cmd_send(&hdev->hw, desc, 2);
+ 	if (ret) {
+@@ -1295,7 +1295,7 @@ static int hclge_dbg_dump_rx_common_threshold_cfg(struct hclge_dev *hdev,
+ 	int i, ret;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_COM_THRD_ALLOC, true);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_RX_COM_THRD_ALLOC, true);
+ 	ret = hclge_cmd_send(&hdev->hw, desc, 2);
+ 	if (ret) {
+@@ -1397,10 +1397,10 @@ static int hclge_dbg_dump_mac_table(struct hclge_dev *hdev, char *buf, int len)
+ 
+ 		hclge_cmd_setup_basic_desc(&desc[0], HCLGE_PPP_MAC_VLAN_IDX_RD,
+ 								true);
+-		desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++		desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		hclge_cmd_setup_basic_desc(&desc[1], HCLGE_PPP_MAC_VLAN_IDX_RD,
+ 								   true);
+-		desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++		desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		hclge_cmd_setup_basic_desc(&desc[2], HCLGE_PPP_MAC_VLAN_IDX_RD,
+ 								   true);
+ 
+@@ -1555,9 +1555,9 @@ static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, bool sel_x,
+ 	u32 *req;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, true);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, true);
+-	desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, true);
+ 
+ 	req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 5733f7c25bde..68b53d4020f7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -1399,7 +1399,7 @@ static int hclge_config_common_hw_err_int(struct hclge_dev *hdev, bool en)
+ 
+ 	/* configure common error interrupts */
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_COMMON_ECC_INT_CFG, false);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_COMMON_ECC_INT_CFG, false);
+ 
+ 	if (en) {
+@@ -1498,7 +1498,7 @@ static int hclge_config_ppp_error_interrupt(struct hclge_dev *hdev, u32 cmd,
+ 
+ 	/* configure PPP error interrupts */
+ 	hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[1], cmd, false);
+ 
+ 	if (cmd == HCLGE_PPP_CMD0_INT_CMD) {
+@@ -1630,7 +1630,7 @@ static int hclge_config_ppu_error_interrupts(struct hclge_dev *hdev, u32 cmd,
+ 	/* configure PPU error interrupts */
+ 	if (cmd == HCLGE_PPU_MPF_ECC_INT_CMD) {
+ 		hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
+-		desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++		desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		hclge_cmd_setup_basic_desc(&desc[1], cmd, false);
+ 		if (en) {
+ 			desc[0].data[0] =
+@@ -1715,7 +1715,7 @@ static int hclge_config_ssu_hw_err_int(struct hclge_dev *hdev, bool en)
+ 
+ 	/* configure SSU ecc error interrupts */
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_ECC_INT_CMD, false);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_ECC_INT_CMD, false);
+ 	if (en) {
+ 		desc[0].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN);
+@@ -1737,7 +1737,7 @@ static int hclge_config_ssu_hw_err_int(struct hclge_dev *hdev, bool en)
+ 
+ 	/* configure SSU common error interrupts */
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_COMMON_INT_CMD, false);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_COMMON_INT_CMD, false);
+ 
+ 	if (en) {
+@@ -1960,7 +1960,7 @@ static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev,
+ 				&ae_dev->hw_err_reset_req);
+ 
+ 	/* clear all main PF RAS errors */
+-	hclge_cmd_reuse_desc(&desc[0], false);
++	hclge_comm_cmd_reuse_desc(&desc[0], false);
+ 	ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
+ 	if (ret)
+ 		dev_err(dev, "clear all mpf ras int cmd failed (%d)\n", ret);
+@@ -2033,7 +2033,7 @@ static int hclge_handle_pf_ras_error(struct hclge_dev *hdev,
+ 	}
+ 
+ 	/* clear all PF RAS errors */
+-	hclge_cmd_reuse_desc(&desc[0], false);
++	hclge_comm_cmd_reuse_desc(&desc[0], false);
+ 	ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
+ 	if (ret)
+ 		dev_err(dev, "clear all pf ras int cmd failed (%d)\n", ret);
+@@ -2084,8 +2084,8 @@ static int hclge_log_rocee_axi_error(struct hclge_dev *hdev)
+ 				   true);
+ 	hclge_cmd_setup_basic_desc(&desc[2], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD,
+ 				   true);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
+-	desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
++	desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, &desc[0], 3);
+ 	if (ret) {
+@@ -2116,7 +2116,7 @@ static int hclge_log_rocee_ecc_error(struct hclge_dev *hdev)
+ 
+ 	ret = hclge_cmd_query_error(hdev, &desc[0],
+ 				    HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD,
+-				    HCLGE_CMD_FLAG_NEXT);
++				    HCLGE_COMM_CMD_FLAG_NEXT);
+ 	if (ret) {
+ 		dev_err(dev, "failed(%d) to query ROCEE ECC error sts\n", ret);
+ 		return ret;
+@@ -2232,7 +2232,7 @@ hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev)
+ 	}
+ 
+ 	/* clear error status */
+-	hclge_cmd_reuse_desc(&desc[0], false);
++	hclge_comm_cmd_reuse_desc(&desc[0], false);
+ 	ret = hclge_cmd_send(&hdev->hw, &desc[0], 1);
+ 	if (ret) {
+ 		dev_err(dev, "failed(%d) to clear ROCEE RAS error\n", ret);
+@@ -2405,7 +2405,8 @@ static int hclge_clear_hw_msix_error(struct hclge_dev *hdev,
+ 	else
+ 		desc[0].opcode = cpu_to_le16(HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT);
+ 
+-	desc[0].flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
++	desc[0].flag = cpu_to_le16(HCLGE_COMM_CMD_FLAG_NO_INTR |
++				   HCLGE_COMM_CMD_FLAG_IN);
+ 
+ 	return hclge_cmd_send(&hdev->hw, &desc[0], bd_num);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index f680f58451db..7a218cd6c37c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1581,7 +1581,7 @@ static int hclge_query_dev_specs(struct hclge_dev *hdev)
+ 	for (i = 0; i < HCLGE_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
+ 		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS,
+ 					   true);
+-		desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++		desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	}
+ 	hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_QUERY_DEV_SPECS, true);
+ 
+@@ -2432,9 +2432,9 @@ static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
+ 
+ 		/* The first descriptor set the NEXT bit to 1 */
+ 		if (i == 0)
+-			desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+-			desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 
+ 		for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
+ 			u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
+@@ -2477,9 +2477,9 @@ static int hclge_common_thrd_config(struct hclge_dev *hdev,
+ 
+ 		/* The first descriptor set the NEXT bit to 1 */
+ 		if (i == 0)
+-			desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		else
+-			desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag &= ~cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 
+ 		for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
+ 			tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
+@@ -3424,7 +3424,7 @@ static int hclge_get_phy_link_ksettings(struct hnae3_handle *handle,
+ 
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
+ 				   true);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
+ 				   true);
+ 
+@@ -3481,7 +3481,7 @@ hclge_set_phy_link_ksettings(struct hnae3_handle *handle,
+ 
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_PHY_LINK_KSETTING,
+ 				   false);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_PHY_LINK_KSETTING,
+ 				   false);
+ 
+@@ -4071,7 +4071,7 @@ static void hclge_func_reset_sync_vf(struct hclge_dev *hdev)
+ 			return;
+ 		}
+ 		msleep(HCLGE_PF_RESET_SYNC_TIME);
+-		hclge_cmd_reuse_desc(&desc, true);
++		hclge_comm_cmd_reuse_desc(&desc, true);
+ 	} while (cnt++ < HCLGE_PF_RESET_SYNC_CNT);
+ 
+ 	dev_warn(&hdev->pdev->dev, "sync with VF timeout!\n");
+@@ -4230,9 +4230,9 @@ static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable)
+ 
+ 	reg_val = hclge_read_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG);
+ 	if (enable)
+-		reg_val |= HCLGE_NIC_SW_RST_RDY;
++		reg_val |= HCLGE_COMM_NIC_SW_RST_RDY;
+ 	else
+-		reg_val &= ~HCLGE_NIC_SW_RST_RDY;
++		reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY;
+ 
+ 	hclge_write_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG, reg_val);
+ }
+@@ -5971,9 +5971,9 @@ static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
+ 	int ret;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
+-	desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
+ 
+ 	req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
+@@ -7774,7 +7774,7 @@ static int hclge_config_switch_param(struct hclge_dev *hdev, int vfid,
+ 	}
+ 
+ 	/* modify and write new config parameter */
+-	hclge_cmd_reuse_desc(&desc, false);
++	hclge_comm_cmd_reuse_desc(&desc, false);
+ 	req->switch_param = (req->switch_param & param_mask) | switch_param;
+ 	req->param_mask = param_mask;
+ 
+@@ -7870,7 +7870,7 @@ static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
+ 	/* 3 Config mac work mode with loopback flag
+ 	 * and its original configure parameters
+ 	 */
+-	hclge_cmd_reuse_desc(&desc, false);
++	hclge_comm_cmd_reuse_desc(&desc, false);
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret)
+ 		dev_err(&hdev->pdev->dev,
+@@ -8448,10 +8448,10 @@ hclge_lookup_mc_mac_vlan_tbl(struct hclge_vport *vport,
+ 	int ret;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	memcpy(desc[0].data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
+ 	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_MAC_VLAN_ADD, true);
+-	desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_MAC_VLAN_ADD, true);
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, desc, 3);
+@@ -8495,12 +8495,12 @@ static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
+ 							   resp_code,
+ 							   HCLGE_MAC_VLAN_ADD);
+ 	} else {
+-		hclge_cmd_reuse_desc(&mc_desc[0], false);
+-		mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
+-		hclge_cmd_reuse_desc(&mc_desc[1], false);
+-		mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
+-		hclge_cmd_reuse_desc(&mc_desc[2], false);
+-		mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
++		hclge_comm_cmd_reuse_desc(&mc_desc[0], false);
++		mc_desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
++		hclge_comm_cmd_reuse_desc(&mc_desc[1], false);
++		mc_desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
++		hclge_comm_cmd_reuse_desc(&mc_desc[2], false);
++		mc_desc[2].flag &= cpu_to_le16(~HCLGE_COMM_CMD_FLAG_NEXT);
+ 		memcpy(mc_desc[0].data, req,
+ 		       sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
+ 		ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
+@@ -9549,7 +9549,7 @@ static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
+ 	}
+ 
+ 	/* modify and write new config parameter */
+-	hclge_cmd_reuse_desc(&desc, false);
++	hclge_comm_cmd_reuse_desc(&desc, false);
+ 	req->vlan_fe = filter_en ?
+ 			(req->vlan_fe | fe_type) : (req->vlan_fe & ~fe_type);
+ 
+@@ -9672,7 +9672,7 @@ static int hclge_set_vf_vlan_filter_cmd(struct hclge_dev *hdev, u16 vfid,
+ 	hclge_cmd_setup_basic_desc(&desc[1],
+ 				   HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
+ 
+-	desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 
+ 	vf_byte_off = vfid / 8;
+ 	vf_byte_val = 1 << (vfid % 8);
+@@ -12638,7 +12638,7 @@ int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc)
+ 	for (i = 0; i < HCLGE_GET_DFX_REG_TYPE_CNT - 1; i++) {
+ 		hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_DFX_BD_NUM,
+ 					   true);
+-		desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++		desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	}
+ 
+ 	/* initialize the last command BD */
+@@ -12682,7 +12682,7 @@ static int hclge_dfx_reg_cmd_send(struct hclge_dev *hdev,
+ 
+ 	hclge_cmd_setup_basic_desc(desc, cmd, true);
+ 	for (i = 0; i < bd_num - 1; i++) {
+-		desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++		desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 		desc++;
+ 		hclge_cmd_setup_basic_desc(desc, cmd, true);
+ 	}
+@@ -13124,7 +13124,7 @@ static u16 hclge_get_sfp_eeprom_info(struct hclge_dev *hdev, u32 offset,
+ 
+ 		/* bd0~bd4 need next flag */
+ 		if (i < HCLGE_SFP_INFO_CMD_NUM - 1)
+-			desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
++			desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	}
+ 
+ 	/* setup bd0, this bd contains offset and read length. */
+-- 
+2.34.1
+
diff --git a/patches/0609-net-hns3-refactor-VF-cmdq-resource-APIs-with-new-com.patch b/patches/0609-net-hns3-refactor-VF-cmdq-resource-APIs-with-new-com.patch
new file mode 100644
index 0000000..9a55bf6
--- /dev/null
+++ b/patches/0609-net-hns3-refactor-VF-cmdq-resource-APIs-with-new-com.patch
@@ -0,0 +1,398 @@
+From af6a92cbd2c67b8ae4a2a065d814ebe174d530cd Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:54 +0800
+Subject: [PATCH 248/283] net: hns3: refactor VF cmdq resource APIs with new
+ common APIs
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit 745f0a19ee9abee4bf0dc9676f4cfdc67c541061
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=745f0a19ee9abee4bf0dc9676f4cfdc67c541061
+
+----------------------------------------------------------------------
+
+This patch uses common cmdq resource allocate/free/query APIs to replace
+the old APIs in VF cmdq module and deletes the old cmdq resource APIs.
+Still we kept hclgevf_cmd_setup_basic_desc name as a seam API to avoid too
+many meaningless replacement.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+---
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       | 197 ++----------------
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       |  40 +---
+ 2 files changed, 19 insertions(+), 218 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 8c959ff64330..6fdd35628b2d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -12,44 +12,6 @@
+ #include "hclgevf_main.h"
+ #include "hnae3.h"
+ 
+-static void hclgevf_cmd_config_regs(struct hclgevf_hw *hw,
+-				    struct hclge_comm_cmq_ring *ring)
+-{
+-	u32 reg_val;
+-
+-	if (ring->ring_type == HCLGEVF_TYPE_CSQ) {
+-		reg_val = lower_32_bits(ring->desc_dma_addr);
+-		hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val);
+-		reg_val = upper_32_bits(ring->desc_dma_addr);
+-		hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, reg_val);
+-
+-		reg_val = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG);
+-		reg_val &= HCLGEVF_NIC_SW_RST_RDY;
+-		reg_val |= (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
+-		hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, reg_val);
+-
+-		hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
+-		hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
+-	} else {
+-		reg_val = lower_32_bits(ring->desc_dma_addr);
+-		hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, reg_val);
+-		reg_val = upper_32_bits(ring->desc_dma_addr);
+-		hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, reg_val);
+-
+-		reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
+-		hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, reg_val);
+-
+-		hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
+-		hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
+-	}
+-}
+-
+-static void hclgevf_cmd_init_regs(struct hclgevf_hw *hw)
+-{
+-	hclgevf_cmd_config_regs(hw, &hw->hw.cmq.csq);
+-	hclgevf_cmd_config_regs(hw, &hw->hw.cmq.crq);
+-}
+-
+ static void hclgevf_cmd_clear_regs(struct hclgevf_hw *hw)
+ {
+ 	hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, 0);
+@@ -64,63 +26,6 @@ static void hclgevf_cmd_clear_regs(struct hclgevf_hw *hw)
+ 	hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
+ }
+ 
+-static int hclgevf_alloc_cmd_desc(struct hclge_comm_cmq_ring *ring)
+-{
+-	int size = ring->desc_num * sizeof(struct hclge_desc);
+-
+-	ring->desc = dma_zalloc_coherent(cmq_ring_to_dev(ring),
+-					 size, &ring->desc_dma_addr,
+-					 GFP_KERNEL);
+-	if (!ring->desc)
+-		return -ENOMEM;
+-
+-	return 0;
+-}
+-
+-static void hclgevf_free_cmd_desc(struct hclge_comm_cmq_ring *ring)
+-{
+-	int size  = ring->desc_num * sizeof(struct hclge_desc);
+-
+-	if (ring->desc) {
+-		dma_free_coherent(&ring->pdev->dev, size,
+-				  ring->desc, ring->desc_dma_addr);
+-		ring->desc = NULL;
+-	}
+-}
+-
+-static int hclgevf_alloc_cmd_queue(struct hclgevf_dev *hdev, int ring_type)
+-{
+-	struct hclgevf_hw *hw = &hdev->hw;
+-	struct hclge_comm_cmq_ring *ring =
+-		(ring_type == HCLGEVF_TYPE_CSQ) ? &hw->hw.cmq.csq :
+-						  &hw->hw.cmq.crq;
+-	int ret;
+-
+-	ring->pdev = hdev->pdev;
+-	ring->ring_type = ring_type;
+-
+-	/* allocate CSQ/CRQ descriptor */
+-	ret = hclgevf_alloc_cmd_desc(ring);
+-	if (ret)
+-		dev_err(&hdev->pdev->dev, "failed(%d) to alloc %s desc\n", ret,
+-			(ring_type == HCLGEVF_TYPE_CSQ) ? "CSQ" : "CRQ");
+-
+-	return ret;
+-}
+-
+-void hclgevf_cmd_setup_basic_desc(struct hclge_desc *desc,
+-				  enum hclgevf_opcode_type opcode, bool is_read)
+-{
+-	memset(desc, 0, sizeof(struct hclge_desc));
+-	desc->opcode = cpu_to_le16(opcode);
+-	desc->flag = cpu_to_le16(HCLGEVF_CMD_FLAG_NO_INTR |
+-				 HCLGEVF_CMD_FLAG_IN);
+-	if (is_read)
+-		desc->flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_WR);
+-	else
+-		desc->flag &= cpu_to_le16(~HCLGEVF_CMD_FLAG_WR);
+-}
+-
+ /* hclgevf_cmd_send - send command to command queue
+  * @hw: pointer to the hw struct
+  * @desc: prefilled descriptor for describing the command
+@@ -134,65 +39,6 @@ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num)
+ 	return hclge_comm_cmd_send(&hw->hw, desc, num);
+ }
+ 
+-static void hclgevf_set_default_capability(struct hclgevf_dev *hdev)
+-{
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+-
+-	set_bit(HNAE3_DEV_SUPPORT_FD_B, ae_dev->caps);
+-	set_bit(HNAE3_DEV_SUPPORT_GRO_B, ae_dev->caps);
+-	set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
+-}
+-
+-static const struct hclgevf_caps_bit_map hclgevf_cmd_caps_bit_map0[] = {
+-	{HCLGEVF_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
+-	{HCLGEVF_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
+-	{HCLGEVF_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
+-	{HCLGEVF_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
+-	{HCLGEVF_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
+-	{HCLGEVF_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
+-};
+-
+-static void hclgevf_parse_capability(struct hclgevf_dev *hdev,
+-				     struct hclgevf_query_version_cmd *cmd)
+-{
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+-	u32 caps, i;
+-
+-	caps = __le32_to_cpu(cmd->caps[0]);
+-	for (i = 0; i < ARRAY_SIZE(hclgevf_cmd_caps_bit_map0); i++)
+-		if (hnae3_get_bit(caps, hclgevf_cmd_caps_bit_map0[i].imp_bit))
+-			set_bit(hclgevf_cmd_caps_bit_map0[i].local_bit,
+-				ae_dev->caps);
+-}
+-
+-static int hclgevf_cmd_query_version_and_capability(struct hclgevf_dev *hdev)
+-{
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+-	struct hclgevf_query_version_cmd *resp;
+-	struct hclge_desc desc;
+-	int status;
+-
+-	resp = (struct hclgevf_query_version_cmd *)desc.data;
+-
+-	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_FW_VER, 1);
+-	status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
+-	if (status)
+-		return status;
+-
+-	hdev->fw_version = le32_to_cpu(resp->firmware);
+-
+-	ae_dev->dev_version = le32_to_cpu(resp->hardware) <<
+-				HNAE3_PCI_REVISION_BIT_SIZE;
+-	ae_dev->dev_version |= hdev->pdev->revision;
+-
+-	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
+-		hclgevf_set_default_capability(hdev);
+-
+-	hclgevf_parse_capability(hdev, resp);
+-
+-	return status;
+-}
+-
+ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
+ {
+ 	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+@@ -203,18 +49,19 @@ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
+ 	spin_lock_init(&cmdq->crq.lock);
+ 
+ 	cmdq->csq.pdev = hdev->pdev;
++	cmdq->crq.pdev = hdev->pdev;
+ 	cmdq->tx_timeout = HCLGEVF_CMDQ_TX_TIMEOUT;
+ 	cmdq->csq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
+ 	cmdq->crq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
+ 
+-	ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CSQ);
++	ret = hclge_comm_alloc_cmd_queue(&hdev->hw.hw, HCLGE_COMM_TYPE_CSQ);
+ 	if (ret) {
+ 		dev_err(&hdev->pdev->dev,
+ 			"CSQ ring setup error %d\n", ret);
+ 		return ret;
+ 	}
+ 
+-	ret = hclgevf_alloc_cmd_queue(hdev, HCLGEVF_TYPE_CRQ);
++	ret = hclge_comm_alloc_cmd_queue(&hdev->hw.hw, HCLGE_COMM_TYPE_CRQ);
+ 	if (ret) {
+ 		dev_err(&hdev->pdev->dev,
+ 			"CRQ ring setup error %d\n", ret);
+@@ -223,29 +70,10 @@ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
+ 
+ 	return 0;
+ err_csq:
+-	hclgevf_free_cmd_desc(&cmdq->csq);
++	hclge_comm_free_cmd_desc(&cmdq->csq);
+ 	return ret;
+ }
+ 
+-static int hclgevf_firmware_compat_config(struct hclgevf_dev *hdev, bool en)
+-{
+-	struct hclgevf_firmware_compat_cmd *req;
+-	struct hclge_desc desc;
+-	u32 compat = 0;
+-
+-	hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_IMP_COMPAT_CFG, false);
+-
+-	if (en) {
+-		req = (struct hclgevf_firmware_compat_cmd *)desc.data;
+-
+-		hnae3_set_bit(compat, HCLGEVF_SYNC_RX_RING_HEAD_EN_B, 1);
+-
+-		req->compat = cpu_to_le32(compat);
+-	}
+-
+-	return hclgevf_cmd_send(&hdev->hw, &desc, 1);
+-}
+-
+ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ {
+ 	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+@@ -265,7 +93,7 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ 	cmdq->crq.next_to_clean = 0;
+ 	cmdq->crq.next_to_use = 0;
+ 
+-	hclgevf_cmd_init_regs(&hdev->hw);
++	hclge_comm_cmd_init_regs(&hdev->hw.hw);
+ 
+ 	spin_unlock(&cmdq->crq.lock);
+ 	spin_unlock_bh(&cmdq->csq.lock);
+@@ -281,7 +109,10 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ 	}
+ 
+ 	/* get version and device capabilities */
+-	ret = hclgevf_cmd_query_version_and_capability(hdev);
++	ret = hclge_comm_cmd_query_version_and_capability(hdev->ae_dev,
++							  &hdev->hw.hw,
++							  &hdev->fw_version,
++							  false);
+ 	if (ret) {
+ 		dev_err(&hdev->pdev->dev,
+ 			"failed to query version and capabilities, ret = %d\n",
+@@ -303,7 +134,8 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ 		/* ask the firmware to enable some features, driver can work
+ 		 * without it.
+ 		 */
+-		ret = hclgevf_firmware_compat_config(hdev, true);
++		ret = hclge_comm_firmware_compat_config(hdev->ae_dev,
++							&hdev->hw.hw, true);
+ 		if (ret)
+ 			dev_warn(&hdev->pdev->dev,
+ 				 "Firmware compatible features not enabled(%d).\n",
+@@ -321,7 +153,8 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
+ void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
+ {
+ 	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+-	hclgevf_firmware_compat_config(hdev, false);
++	hclge_comm_firmware_compat_config(hdev->ae_dev, &hdev->hw.hw,
++					  false);
+ 	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 
+ 	/* wait to ensure that the firmware completes the possible left
+@@ -334,6 +167,6 @@ void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
+ 	spin_unlock(&cmdq->crq.lock);
+ 	spin_unlock_bh(&cmdq->csq.lock);
+ 
+-	hclgevf_free_cmd_desc(&cmdq->csq);
+-	hclgevf_free_cmd_desc(&cmdq->crq);
++	hclge_comm_free_cmd_desc(&cmdq->csq);
++	hclge_comm_free_cmd_desc(&cmdq->crq);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 6f04ea3bacd6..5ed3e27d6a27 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -98,30 +98,6 @@ struct hclgevf_ctrl_vector_chain {
+ 	u8 resv;
+ };
+ 
+-enum HCLGEVF_CAP_BITS {
+-	HCLGEVF_CAP_UDP_GSO_B,
+-	HCLGEVF_CAP_QB_B,
+-	HCLGEVF_CAP_FD_FORWARD_TC_B,
+-	HCLGEVF_CAP_PTP_B,
+-	HCLGEVF_CAP_INT_QL_B,
+-	HCLGEVF_CAP_HW_TX_CSUM_B,
+-	HCLGEVF_CAP_TX_PUSH_B,
+-	HCLGEVF_CAP_PHY_IMP_B,
+-	HCLGEVF_CAP_TQP_TXRX_INDEP_B,
+-	HCLGEVF_CAP_HW_PAD_B,
+-	HCLGEVF_CAP_STASH_B,
+-	HCLGEVF_CAP_UDP_TUNNEL_CSUM_B,
+-	HCLGEVF_CAP_RXD_ADV_LAYOUT_B = 15,
+-};
+-
+-#define HCLGEVF_QUERY_CAP_LENGTH		3
+-struct hclgevf_query_version_cmd {
+-	__le32 firmware;
+-	__le32 hardware;
+-	__le32 rsv;
+-	__le32 caps[HCLGEVF_QUERY_CAP_LENGTH]; /* capabilities of device */
+-};
+-
+ #define HCLGEVF_MSIX_OFT_ROCEE_S       0
+ #define HCLGEVF_MSIX_OFT_ROCEE_M       (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
+ #define HCLGEVF_VEC_NUM_S              0
+@@ -208,9 +184,6 @@ struct hclgevf_cfg_tx_queue_pointer_cmd {
+ 	u8 rsv[14];
+ };
+ 
+-#define HCLGEVF_TYPE_CRQ		0
+-#define HCLGEVF_TYPE_CSQ		1
+-
+ /* this bit indicates that the driver is ready for hardware reset */
+ #define HCLGEVF_NIC_SW_RST_RDY_B	16
+ #define HCLGEVF_NIC_SW_RST_RDY		BIT(HCLGEVF_NIC_SW_RST_RDY_B)
+@@ -222,6 +195,10 @@ struct hclgevf_cfg_tx_queue_pointer_cmd {
+ 
+ #define HCLGEVF_QUERY_DEV_SPECS_BD_NUM		4
+ 
++#define hclgevf_cmd_setup_basic_desc(desc, opcode, is_read) \
++	hclge_comm_cmd_setup_basic_desc(desc, (enum hclge_comm_opcode_type)opcode, \
++					is_read)
++
+ struct hclgevf_dev_specs_0_cmd {
+ 	__le32 rsv0;
+ 	__le32 mac_entry_num;
+@@ -241,18 +218,9 @@ struct hclgevf_dev_specs_1_cmd {
+        u8 rsv1[18];
+ };
+ 
+-/* capabilities bits map between imp firmware and local driver */
+-struct hclgevf_caps_bit_map {
+-	u16 imp_bit;
+-	u16 local_bit;
+-};
+-
+ int hclgevf_cmd_init(struct hclgevf_dev *hdev);
+ void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
+ int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
+ 
+ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num);
+-void hclgevf_cmd_setup_basic_desc(struct hclge_desc *desc,
+-				  enum hclgevf_opcode_type opcode,
+-				  bool is_read);
+ #endif
+-- 
+2.34.1
+
diff --git a/patches/0610-net-hns3-create-common-cmdq-init-and-uninit-APIs.patch b/patches/0610-net-hns3-create-common-cmdq-init-and-uninit-APIs.patch
new file mode 100644
index 0000000..ecde563
--- /dev/null
+++ b/patches/0610-net-hns3-create-common-cmdq-init-and-uninit-APIs.patch
@@ -0,0 +1,89 @@
+From 33ab1700e50e7becea5c5824d122b0fb8ae8b343 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:55 +0800
+Subject: [PATCH 249/283] net: hns3: create common cmdq init and uninit APIs
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit 0b04224c131269efeab0571dcff9377f9c6d911c
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0b04224c131269efeab0571dcff9377f9c6d911c
+
+----------------------------------------------------------------------
+
+The PF and VF cmdq init and uninit APIs are also almost same espect the
+suffixes of API names.
+
+This patch creates common cmdq init and uninit APIs needed by PF and VF
+cmdq modules. The next patch will use the new unified APIs to replace init
+and uninit APIs in PF module.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+---
+ .../ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c | 4 ++--
+ .../ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h | 9 ++++++++-
+ 2 files changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index 67c084f7dce0..78321511798a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -526,7 +526,7 @@ static void hclge_comm_cmd_uninit_regs(struct hclge_comm_hw *hw)
+ 	hclge_comm_write_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG, 0);
+ }
+ 
+-void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev,
++void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev, bool is_pf,
+ 			   struct hclge_comm_hw *hw)
+ {
+ 	struct hclge_comm_cmq *cmdq = &hw->cmq;
+@@ -565,7 +565,7 @@ int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw)
+ 	cmdq->crq.desc_num = HCLGE_COMM_NIC_CMQ_DESC_NUM;
+ 
+ 	/* Setup Tx write back timeout */
+-	cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT;
++	cmdq->tx_timeout = HCLGE_COMM_CMDQ_TX_TIMEOUT;
+ 
+ 	/* Setup queue rings */
+ 	ret = hclge_comm_alloc_cmd_queue(hw, HCLGE_COMM_TYPE_CSQ);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 393953e828af..1e5448ee4744 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -54,7 +54,7 @@
+ #define HCLGE_COMM_NIC_SW_RST_RDY		BIT(HCLGE_COMM_NIC_SW_RST_RDY_B)
+ #define HCLGE_COMM_NIC_CMQ_DESC_NUM_S		3
+ #define HCLGE_COMM_NIC_CMQ_DESC_NUM		1024
+-#define HCLGE_COMM_CMDQ_TX_TIMEOUT_DEFAULT	30000
++#define HCLGE_COMM_CMDQ_TX_TIMEOUT		30000
+ #define HCLGE_COMM_CMDQ_TX_TIMEOUT_500MS	500000
+ 
+ enum hclge_opcode_type {
+@@ -468,4 +468,11 @@ void hclge_comm_cmd_setup_basic_desc(struct hclge_desc *desc,
+ 				     enum hclge_opcode_type opcode,
+ 				     bool is_read);
+ void hclge_comm_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
++void hclge_comm_cmd_uninit(struct hnae3_ae_dev *ae_dev, bool is_pf,
++			   struct hclge_comm_hw *hw);
++int hclge_comm_cmd_queue_init(struct pci_dev *pdev, struct hclge_comm_hw *hw);
++int hclge_comm_cmd_init(struct hnae3_ae_dev *ae_dev, struct hclge_comm_hw *hw,
++			u32 *fw_version, bool is_pf,
++			unsigned long reset_pending);
++
+ #endif
+-- 
+2.34.1
+
diff --git a/patches/0611-net-hns3-refactor-PF-cmdq-init-and-uninit-APIs-with-.patch b/patches/0611-net-hns3-refactor-PF-cmdq-init-and-uninit-APIs-with-.patch
new file mode 100644
index 0000000..0168858
--- /dev/null
+++ b/patches/0611-net-hns3-refactor-PF-cmdq-init-and-uninit-APIs-with-.patch
@@ -0,0 +1,413 @@
+From 23c5a4f38a47e19b0d565b2485c3d9095298c7ab Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:56 +0800
+Subject: [PATCH 250/283] net: hns3: refactor PF cmdq init and uninit APIs with
+ new common APIs
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit 8e2288cad6cb9863a38048140297f5ce8a9b00d3
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8e2288cad6cb9863a38048140297f5ce8a9b00d3
+
+----------------------------------------------------------------------
+
+This patch uses common cmdq init and uninit APIs to replace the old APIs in
+PF cmdq module init and uninit modules. Then the old PF init and uninit
+APIs is deleted.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+---
+ .../hisilicon/hns3/hns3_cae/hns3_cae_cmd.h    |   3 +
+ .../hisilicon/hns3/hns3pf/hclge_cmd.c         | 154 ------------------
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |   9 -
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  46 +++---
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |  13 --
+ .../hisilicon/hns3/hns3pf/hclge_mbx.c         |   5 +-
+ 6 files changed, 30 insertions(+), 200 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.h
+index c1160e507f1b..1175e19e1b7f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_cae/hns3_cae_cmd.h
+@@ -24,6 +24,9 @@
+ #define HCLGE_OPC_DCQCN_TEMPLATE_CFG	0x7014
+ #define HCLGE_OPC_DCQCN_GET_MSG_CNT	0x7017
+ 
++#define HCLGE_NIC_CSQ_TAIL_REG		0x27010
++#define HCLGE_NIC_CSQ_HEAD_REG		0x27014
++
+ #define HNS3_CAE_DESC_DATA_LEN		6
+ 
+ struct hns3_cae_desc {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+index 3e06eba7a90c..ee665661acdb 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+@@ -12,20 +12,6 @@
+ #include "hnae3.h"
+ #include "hclge_main.h"
+ 
+-static void hclge_cmd_clear_regs(struct hclge_hw *hw)
+-{
+-	hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_L_REG, 0);
+-	hclge_write_dev(hw, HCLGE_NIC_CSQ_BASEADDR_H_REG, 0);
+-	hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG, 0);
+-	hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0);
+-	hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0);
+-	hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG, 0);
+-	hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_H_REG, 0);
+-	hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG, 0);
+-	hclge_write_dev(hw, HCLGE_NIC_CRQ_HEAD_REG, 0);
+-	hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0);
+-}
+-
+ /**
+  * hclge_cmd_send - send command to command queue
+  * @hw: pointer to the hw struct
+@@ -39,143 +25,3 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
+ {
+ 	return hclge_comm_cmd_send(&hw->hw, desc, num);
+ }
+-
+-int hclge_cmd_queue_init(struct hclge_dev *hdev)
+-{
+-	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+-	int ret;
+-
+-	/* Setup the lock for command queue */
+-	spin_lock_init(&cmdq->csq.lock);
+-	spin_lock_init(&cmdq->crq.lock);
+-
+-	cmdq->csq.pdev = hdev->pdev;
+-	cmdq->crq.pdev = hdev->pdev;
+-
+-	/* clear up all command register,
+-	 * in case there are some residual values
+-	 */
+-	hclge_cmd_clear_regs(&hdev->hw);
+-
+-	/* Setup the queue entries for use cmd queue */
+-	cmdq->csq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
+-	cmdq->crq.desc_num = HCLGE_NIC_CMQ_DESC_NUM;
+-
+-	/* Setup Tx write back timeout */
+-	cmdq->tx_timeout = HCLGE_CMDQ_TX_TIMEOUT;
+-
+-	/* Setup queue rings */
+-	ret = hclge_comm_alloc_cmd_queue(&hdev->hw.hw, HCLGE_COMM_TYPE_CSQ);
+-	if (ret) {
+-		dev_err(&hdev->pdev->dev,
+-			"CSQ ring setup error %d\n", ret);
+-		return ret;
+-	}
+-
+-	ret = hclge_comm_alloc_cmd_queue(&hdev->hw.hw, HCLGE_COMM_TYPE_CRQ);
+-	if (ret) {
+-		dev_err(&hdev->pdev->dev,
+-			"CRQ ring setup error %d\n", ret);
+-		goto err_csq;
+-	}
+-
+-	return 0;
+-err_csq:
+-	hclge_comm_free_cmd_desc(&hdev->hw.hw.cmq.csq);
+-	return ret;
+-}
+-
+-int hclge_cmd_init(struct hclge_dev *hdev)
+-{
+-	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+-	int ret;
+-
+-	spin_lock_bh(&cmdq->csq.lock);
+-	spin_lock(&cmdq->crq.lock);
+-
+-	cmdq->csq.next_to_clean = 0;
+-	cmdq->csq.next_to_use = 0;
+-	cmdq->crq.next_to_clean = 0;
+-	cmdq->crq.next_to_use = 0;
+-
+-	hclge_comm_cmd_init_regs(&hdev->hw.hw);
+-
+-	spin_unlock(&cmdq->crq.lock);
+-	spin_unlock_bh(&cmdq->csq.lock);
+-
+-	clear_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+-
+-	/* Check if there is new reset pending, because the higher level
+-	 * reset may happen when lower level reset is being processed.
+-	 */
+-	if ((hclge_is_reset_pending(hdev))) {
+-		dev_err(&hdev->pdev->dev,
+-			"failed to init cmd since reset %#lx pending\n",
+-			hdev->reset_pending);
+-		ret = -EBUSY;
+-		goto err_cmd_init;
+-	}
+-
+-	/* get version and device capabilities */
+-	ret = hclge_comm_cmd_query_version_and_capability(hdev->ae_dev,
+-							  &hdev->hw.hw,
+-							  &hdev->fw_version,
+-							  true);
+-	if (ret) {
+-		dev_err(&hdev->pdev->dev,
+-			"failed to query version and capabilities, ret = %d\n",
+-			ret);
+-		goto err_cmd_init;
+-	}
+-
+-	dev_info(&hdev->pdev->dev, "The firmware version is %lu.%lu.%lu.%lu\n",
+-		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE3_MASK,
+-				HNAE3_FW_VERSION_BYTE3_SHIFT),
+-		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE2_MASK,
+-				HNAE3_FW_VERSION_BYTE2_SHIFT),
+-		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE1_MASK,
+-				HNAE3_FW_VERSION_BYTE1_SHIFT),
+-		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE0_MASK,
+-				HNAE3_FW_VERSION_BYTE0_SHIFT));
+-
+-	/* ask the firmware to enable some features, driver can work without
+-	 * it.
+-	 */
+-	ret = hclge_comm_firmware_compat_config(hdev->ae_dev,
+-						&hdev->hw.hw, true);
+-	if (ret)
+-		dev_warn(&hdev->pdev->dev,
+-			 "Firmware compatible features not enabled(%d).\n",
+-			 ret);
+-
+-	return 0;
+-
+-err_cmd_init:
+-	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+-
+-	return ret;
+-}
+-
+-void hclge_cmd_uninit(struct hclge_dev *hdev)
+-{
+-	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+-
+-	cmdq->csq.pdev = hdev->pdev;
+-
+-	hclge_comm_firmware_compat_config(hdev->ae_dev, &hdev->hw.hw,
+-					  false);
+-
+-	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+-	/* wait to ensure that the firmware completes the possible left
+-	 * over commands.
+-	 */
+-	msleep(HCLGE_CMDQ_CLEAR_WAIT_TIME);
+-	spin_lock_bh(&cmdq->csq.lock);
+-	spin_lock(&cmdq->crq.lock);
+-	hclge_cmd_clear_regs(&hdev->hw);
+-	spin_unlock(&cmdq->crq.lock);
+-	spin_unlock_bh(&cmdq->csq.lock);
+-
+-	hclge_comm_free_cmd_desc(&cmdq->csq);
+-	hclge_comm_free_cmd_desc(&cmdq->crq);
+-}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 1262d708a9ff..3773a9ff6301 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -9,9 +9,6 @@
+ #include "hnae3.h"
+ #include "hclge_comm_cmd.h"
+ 
+-#define HCLGE_CMDQ_TX_TIMEOUT		30000
+-#define HCLGE_CMDQ_CLEAR_WAIT_TIME	200
+-
+ struct hclge_dev;
+ 
+ #define HCLGE_CMDQ_RX_INVLD_B		0
+@@ -716,9 +713,6 @@ struct hclge_common_lb_cmd {
+ #define HCLGE_DEFAULT_NON_DCB_DV	0x7800	/* 30K byte */
+ #define HCLGE_NON_DCB_ADDITIONAL_BUF	0x1400	/* 5120 byte */
+ 
+-#define HCLGE_NIC_CMQ_DESC_NUM		1024
+-#define HCLGE_NIC_CMQ_DESC_NUM_S	3
+-
+ #define HCLGE_LED_LOCATE_STATE_S	0
+ #define HCLGE_LED_LOCATE_STATE_M	GENMASK(1, 0)
+ 
+@@ -972,7 +966,4 @@ enum hclge_comm_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
+ 						struct hclge_desc *desc);
+ enum hclge_comm_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
+ 					       struct hclge_desc *desc);
+-
+-void hclge_cmd_uninit(struct hclge_dev *hdev);
+-int hclge_cmd_queue_init(struct hclge_dev *hdev);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 7a218cd6c37c..459051a01506 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -96,20 +96,20 @@ static const struct pci_device_id ae_algo_pci_tbl[] = {
+ 
+ MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
+ 
+-static const u32 cmdq_reg_addr_list[] = {HCLGE_NIC_CSQ_BASEADDR_L_REG,
+-					 HCLGE_NIC_CSQ_BASEADDR_H_REG,
+-					 HCLGE_NIC_CSQ_DEPTH_REG,
+-					 HCLGE_NIC_CSQ_TAIL_REG,
+-					 HCLGE_NIC_CSQ_HEAD_REG,
+-					 HCLGE_NIC_CRQ_BASEADDR_L_REG,
+-					 HCLGE_NIC_CRQ_BASEADDR_H_REG,
+-					 HCLGE_NIC_CRQ_DEPTH_REG,
+-					 HCLGE_NIC_CRQ_TAIL_REG,
+-					 HCLGE_NIC_CRQ_HEAD_REG,
+-					 HCLGE_VECTOR0_CMDQ_SRC_REG,
+-					 HCLGE_CMDQ_INTR_STS_REG,
+-					 HCLGE_CMDQ_INTR_EN_REG,
+-					 HCLGE_CMDQ_INTR_GEN_REG};
++static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG,
++					 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG,
++					 HCLGE_COMM_NIC_CSQ_DEPTH_REG,
++					 HCLGE_COMM_NIC_CSQ_TAIL_REG,
++					 HCLGE_COMM_NIC_CSQ_HEAD_REG,
++					 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG,
++					 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG,
++					 HCLGE_COMM_NIC_CRQ_DEPTH_REG,
++					 HCLGE_COMM_NIC_CRQ_TAIL_REG,
++					 HCLGE_COMM_NIC_CRQ_HEAD_REG,
++					 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG,
++					 HCLGE_COMM_CMDQ_INTR_STS_REG,
++					 HCLGE_COMM_CMDQ_INTR_EN_REG,
++					 HCLGE_COMM_CMDQ_INTR_GEN_REG};
+ 
+ static const u32 common_reg_addr_list[] = {HCLGE_MISC_VECTOR_REG_BASE,
+ 					   HCLGE_PF_OTHER_INT_REG,
+@@ -4228,13 +4228,13 @@ static void hclge_reset_handshake(struct hclge_dev *hdev, bool enable)
+ {
+ 	u32 reg_val;
+ 
+-	reg_val = hclge_read_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG);
++	reg_val = hclge_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
+ 	if (enable)
+ 		reg_val |= HCLGE_COMM_NIC_SW_RST_RDY;
+ 	else
+ 		reg_val &= ~HCLGE_COMM_NIC_SW_RST_RDY;
+ 
+-	hclge_write_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG, reg_val);
++	hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG, reg_val);
+ }
+ 
+ static int hclge_func_reset_notify_vf(struct hclge_dev *hdev)
+@@ -4271,7 +4271,7 @@ static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
+ 		/* After performaning pf reset, it is not necessary to do the
+ 		 * mailbox handling or send any command to firmware, because
+ 		 * any mailbox handling or command to firmware is only valid
+-		 * after hclge_cmd_init is called.
++		 * after hclge_comm_cmd_init is called.
+ 		 */
+ 		set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+ 		hdev->rst_stats.pf_rst_cnt++;
+@@ -11797,12 +11797,13 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 		goto err_pci_uninit;
+ 
+ 	/* Firmware command queue initialize */
+-	ret = hclge_cmd_queue_init(hdev);
++	ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);
+ 	if (ret)
+ 		goto err_devlink_uninit;
+ 
+ 	/* Firmware command initialize */
+-	ret = hclge_cmd_init(hdev);
++	ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
++				  true, hdev->reset_pending);
+ 	if (ret)
+ 		goto err_cmd_uninit;
+ 
+@@ -11986,7 +11987,7 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+ err_msi_uninit:
+ 	pci_free_irq_vectors(pdev);
+ err_cmd_uninit:
+-	hclge_cmd_uninit(hdev);
++	hclge_comm_cmd_uninit(hdev->ae_dev, true, &hdev->hw.hw);
+ err_devlink_uninit:
+ 	hclge_devlink_uninit(hdev);
+ err_pci_uninit:
+@@ -12240,7 +12241,8 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 		hclge_reset_umv_space(hdev);
+ 	}
+ 
+-	ret = hclge_cmd_init(hdev);
++	ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw, &hdev->fw_version,
++				  true, hdev->reset_pending);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "Cmd queue init failed\n");
+ 		return ret;
+@@ -12384,7 +12386,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
+ 	hclge_config_nic_hw_error(hdev, false);
+ 	hclge_config_rocee_ras_interrupt(hdev, false);
+ 
+-	hclge_cmd_uninit(hdev);
++	hclge_comm_cmd_uninit(hdev->ae_dev, true, &hdev->hw.hw);
+ 	hclge_misc_irq_uninit(hdev);
+ 	hclge_devlink_uninit(hdev);
+ 	hclge_pci_uninit(hdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 87ec658d5cde..067eb8dcde51 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -38,20 +38,7 @@
+ #define HCLGE_VECTOR_REG_OFFSET_H	0x1000
+ #define HCLGE_VECTOR_VF_OFFSET		0x100000
+ 
+-#define HCLGE_NIC_CSQ_BASEADDR_L_REG	0x27000
+-#define HCLGE_NIC_CSQ_BASEADDR_H_REG	0x27004
+ #define HCLGE_NIC_CSQ_DEPTH_REG		0x27008
+-#define HCLGE_NIC_CSQ_TAIL_REG		0x27010
+-#define HCLGE_NIC_CSQ_HEAD_REG		0x27014
+-#define HCLGE_NIC_CRQ_BASEADDR_L_REG	0x27018
+-#define HCLGE_NIC_CRQ_BASEADDR_H_REG	0x2701C
+-#define HCLGE_NIC_CRQ_DEPTH_REG		0x27020
+-#define HCLGE_NIC_CRQ_TAIL_REG		0x27024
+-#define HCLGE_NIC_CRQ_HEAD_REG		0x27028
+-
+-#define HCLGE_CMDQ_INTR_STS_REG		0x27104
+-#define HCLGE_CMDQ_INTR_EN_REG		0x27108
+-#define HCLGE_CMDQ_INTR_GEN_REG		0x2710C
+ 
+ /* bar registers for common func */
+ #define HCLGE_GRO_EN_REG		0x28000
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+index eb47d03ad625..64e081202245 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
+@@ -791,7 +791,7 @@ static void hclge_handle_link_change_event(struct hclge_dev *hdev,
+ 
+ static bool hclge_cmd_crq_empty(struct hclge_hw *hw)
+ {
+-	u32 tail = hclge_read_dev(hw, HCLGE_NIC_CRQ_TAIL_REG);
++	u32 tail = hclge_read_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG);
+ 
+ 	return tail == hw->hw.cmq.crq.next_to_use;
+ }
+@@ -1176,5 +1176,6 @@ void hclge_mbx_handler(struct hclge_dev *hdev)
+ 	}
+ 
+ 	/* Write back CMDQ_RQ header pointer, M7 need this pointer */
+-	hclge_write_dev(&hdev->hw, HCLGE_NIC_CRQ_HEAD_REG, crq->next_to_use);
++	hclge_write_dev(&hdev->hw, HCLGE_COMM_NIC_CRQ_HEAD_REG,
++			crq->next_to_use);
+ }
+-- 
+2.34.1
+
diff --git a/patches/0612-net-hns3-refactor-VF-cmdq-init-and-uninit-APIs-with-.patch b/patches/0612-net-hns3-refactor-VF-cmdq-init-and-uninit-APIs-with-.patch
new file mode 100644
index 0000000..06ef647
--- /dev/null
+++ b/patches/0612-net-hns3-refactor-VF-cmdq-init-and-uninit-APIs-with-.patch
@@ -0,0 +1,453 @@
+From b6ef73f0cf4a8d85ca13bb4ea313541262d25537 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:57 +0800
+Subject: [PATCH 251/283] net: hns3: refactor VF cmdq init and uninit APIs with
+ new common APIs
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit cb413bfa6e8b8198a08f2f9ce0ef3c567e3d26eb
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=cb413bfa6e8b8198a08f2f9ce0ef3c567e3d26eb
+
+----------------------------------------------------------------------
+
+This patch uses common cmdq init and uninit APIs to replace the old APIs in
+VF cmdq module init and uninit module. Then the old VF init and uninit
+APIs is deleted.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+---
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.c       | 135 +-----------------
+ .../hisilicon/hns3/hns3vf/hclgevf_cmd.h       |  25 +---
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |  59 ++++----
+ .../hisilicon/hns3/hns3vf/hclgevf_main.h      |  19 ---
+ .../hisilicon/hns3/hns3vf/hclgevf_mbx.c       |   4 +-
+ 5 files changed, 37 insertions(+), 205 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+index 6fdd35628b2d..9ef99a9fa5a3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+@@ -12,20 +12,6 @@
+ #include "hclgevf_main.h"
+ #include "hnae3.h"
+ 
+-static void hclgevf_cmd_clear_regs(struct hclgevf_hw *hw)
+-{
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, 0);
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, 0);
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, 0);
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, 0);
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, 0);
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, 0);
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
+-	hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
+-}
+-
+ /* hclgevf_cmd_send - send command to command queue
+  * @hw: pointer to the hw struct
+  * @desc: prefilled descriptor for describing the command
+@@ -39,134 +25,15 @@ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num)
+ 	return hclge_comm_cmd_send(&hw->hw, desc, num);
+ }
+ 
+-int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev)
+-{
+-	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+-	int ret;
+-
+-	/* Setup the lock for command queue */
+-	spin_lock_init(&cmdq->csq.lock);
+-	spin_lock_init(&cmdq->crq.lock);
+-
+-	cmdq->csq.pdev = hdev->pdev;
+-	cmdq->crq.pdev = hdev->pdev;
+-	cmdq->tx_timeout = HCLGEVF_CMDQ_TX_TIMEOUT;
+-	cmdq->csq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
+-	cmdq->crq.desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
+-
+-	ret = hclge_comm_alloc_cmd_queue(&hdev->hw.hw, HCLGE_COMM_TYPE_CSQ);
+-	if (ret) {
+-		dev_err(&hdev->pdev->dev,
+-			"CSQ ring setup error %d\n", ret);
+-		return ret;
+-	}
+-
+-	ret = hclge_comm_alloc_cmd_queue(&hdev->hw.hw, HCLGE_COMM_TYPE_CRQ);
+-	if (ret) {
+-		dev_err(&hdev->pdev->dev,
+-			"CRQ ring setup error %d\n", ret);
+-		goto err_csq;
+-	}
+-
+-	return 0;
+-err_csq:
+-	hclge_comm_free_cmd_desc(&cmdq->csq);
+-	return ret;
+-}
+-
+-int hclgevf_cmd_init(struct hclgevf_dev *hdev)
++void hclgevf_arq_init(struct hclgevf_dev *hdev)
+ {
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
+ 	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+-	int ret;
+ 
+-	spin_lock_bh(&cmdq->csq.lock);
+ 	spin_lock(&cmdq->crq.lock);
+-
+ 	/* initialize the pointers of async rx queue of mailbox */
+ 	hdev->arq.hdev = hdev;
+ 	hdev->arq.head = 0;
+ 	hdev->arq.tail = 0;
+ 	atomic_set(&hdev->arq.count, 0);
+-	cmdq->csq.next_to_clean = 0;
+-	cmdq->csq.next_to_use = 0;
+-	cmdq->crq.next_to_clean = 0;
+-	cmdq->crq.next_to_use = 0;
+-
+-	hclge_comm_cmd_init_regs(&hdev->hw.hw);
+-
+ 	spin_unlock(&cmdq->crq.lock);
+-	spin_unlock_bh(&cmdq->csq.lock);
+-
+-	clear_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+-
+-	/* Check if there is new reset pending, because the higher level
+-	 * reset may happen when lower level reset is being processed.
+-	 */
+-	if (hclgevf_is_reset_pending(hdev)) {
+-		ret = -EBUSY;
+-		goto err_cmd_init;
+-	}
+-
+-	/* get version and device capabilities */
+-	ret = hclge_comm_cmd_query_version_and_capability(hdev->ae_dev,
+-							  &hdev->hw.hw,
+-							  &hdev->fw_version,
+-							  false);
+-	if (ret) {
+-		dev_err(&hdev->pdev->dev,
+-			"failed to query version and capabilities, ret = %d\n",
+-			ret);
+-		goto err_cmd_init;
+-	}
+-
+-	dev_info(&hdev->pdev->dev, "The firmware version is %lu.%lu.%lu.%lu\n",
+-		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE3_MASK,
+-				HNAE3_FW_VERSION_BYTE3_SHIFT),
+-		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE2_MASK,
+-				HNAE3_FW_VERSION_BYTE2_SHIFT),
+-		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE1_MASK,
+-				HNAE3_FW_VERSION_BYTE1_SHIFT),
+-		hnae3_get_field(hdev->fw_version, HNAE3_FW_VERSION_BYTE0_MASK,
+-				HNAE3_FW_VERSION_BYTE0_SHIFT));
+-
+-	if (ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V3) {
+-		/* ask the firmware to enable some features, driver can work
+-		 * without it.
+-		 */
+-		ret = hclge_comm_firmware_compat_config(hdev->ae_dev,
+-							&hdev->hw.hw, true);
+-		if (ret)
+-			dev_warn(&hdev->pdev->dev,
+-				 "Firmware compatible features not enabled(%d).\n",
+-				 ret);
+-	}
+-
+-	return 0;
+-
+-err_cmd_init:
+-	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+-
+-	return ret;
+-}
+-
+-void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
+-{
+-	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
+-	hclge_comm_firmware_compat_config(hdev->ae_dev, &hdev->hw.hw,
+-					  false);
+-	set_bit(HCLGE_COMM_STATE_CMD_DISABLE, &hdev->hw.hw.comm_state);
+-
+-	/* wait to ensure that the firmware completes the possible left
+-	 * over commands.
+-	 */
+-	msleep(HCLGEVF_CMDQ_CLEAR_WAIT_TIME);
+-	spin_lock_bh(&cmdq->csq.lock);
+-	spin_lock(&cmdq->crq.lock);
+-	hclgevf_cmd_clear_regs(&hdev->hw);
+-	spin_unlock(&cmdq->crq.lock);
+-	spin_unlock_bh(&cmdq->csq.lock);
+-
+-	hclge_comm_free_cmd_desc(&cmdq->csq);
+-	hclge_comm_free_cmd_desc(&cmdq->crq);
+ }
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+index 5ed3e27d6a27..d36004628bd5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+@@ -8,8 +8,6 @@
+ #include "hnae3.h"
+ #include "hclge_comm_cmd.h"
+ 
+-#define HCLGEVF_CMDQ_TX_TIMEOUT		30000
+-#define HCLGEVF_CMDQ_CLEAR_WAIT_TIME	200
+ #define HCLGEVF_CMDQ_RX_INVLD_B		0
+ #define HCLGEVF_CMDQ_RX_OUTVLD_B	1
+ 
+@@ -17,24 +15,6 @@ struct hclgevf_hw;
+ struct hclgevf_dev;
+ 
+ #define HCLGEVF_SYNC_RX_RING_HEAD_EN_B	4
+-struct hclgevf_firmware_compat_cmd {
+-	__le32 compat;
+-	u8 rsv[20];
+-};
+-
+-#define HCLGEVF_CMD_FLAG_IN_VALID_SHIFT		0
+-#define HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT	1
+-#define HCLGEVF_CMD_FLAG_NEXT_SHIFT		2
+-#define HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT		3
+-#define HCLGEVF_CMD_FLAG_NO_INTR_SHIFT		4
+-#define HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT		5
+-
+-#define HCLGEVF_CMD_FLAG_IN		BIT(HCLGEVF_CMD_FLAG_IN_VALID_SHIFT)
+-#define HCLGEVF_CMD_FLAG_OUT		BIT(HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT)
+-#define HCLGEVF_CMD_FLAG_NEXT		BIT(HCLGEVF_CMD_FLAG_NEXT_SHIFT)
+-#define HCLGEVF_CMD_FLAG_WR		BIT(HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT)
+-#define HCLGEVF_CMD_FLAG_NO_INTR	BIT(HCLGEVF_CMD_FLAG_NO_INTR_SHIFT)
+-#define HCLGEVF_CMD_FLAG_ERR_INTR	BIT(HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT)
+ 
+ enum hclgevf_opcode_type {
+ 	/* Generic command */
+@@ -218,9 +198,6 @@ struct hclgevf_dev_specs_1_cmd {
+        u8 rsv1[18];
+ };
+ 
+-int hclgevf_cmd_init(struct hclgevf_dev *hdev);
+-void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
+-int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
+-
+ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num);
++void hclgevf_arq_init(struct hclgevf_dev *hdev);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 8fe47f45e4d3..3d72c2a3a59c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -40,20 +40,20 @@ static const u8 hclgevf_hash_key[] = {
+ 
+ MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
+ 
+-static const u32 cmdq_reg_addr_list[] = {HCLGEVF_NIC_CSQ_BASEADDR_L_REG,
+-					 HCLGEVF_NIC_CSQ_BASEADDR_H_REG,
+-					 HCLGEVF_NIC_CSQ_DEPTH_REG,
+-					 HCLGEVF_NIC_CSQ_TAIL_REG,
+-					 HCLGEVF_NIC_CSQ_HEAD_REG,
+-					 HCLGEVF_NIC_CRQ_BASEADDR_L_REG,
+-					 HCLGEVF_NIC_CRQ_BASEADDR_H_REG,
+-					 HCLGEVF_NIC_CRQ_DEPTH_REG,
+-					 HCLGEVF_NIC_CRQ_TAIL_REG,
+-					 HCLGEVF_NIC_CRQ_HEAD_REG,
+-					 HCLGEVF_VECTOR0_CMDQ_SRC_REG,
+-					 HCLGEVF_VECTOR0_CMDQ_STATE_REG,
+-					 HCLGEVF_CMDQ_INTR_EN_REG,
+-					 HCLGEVF_CMDQ_INTR_GEN_REG};
++static const u32 cmdq_reg_addr_list[] = {HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG,
++					 HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG,
++					 HCLGE_COMM_NIC_CSQ_DEPTH_REG,
++					 HCLGE_COMM_NIC_CSQ_TAIL_REG,
++					 HCLGE_COMM_NIC_CSQ_HEAD_REG,
++					 HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG,
++					 HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG,
++					 HCLGE_COMM_NIC_CRQ_DEPTH_REG,
++					 HCLGE_COMM_NIC_CRQ_TAIL_REG,
++					 HCLGE_COMM_NIC_CRQ_HEAD_REG,
++					 HCLGE_COMM_VECTOR0_CMDQ_SRC_REG,
++					 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG,
++					 HCLGE_COMM_CMDQ_INTR_EN_REG,
++					 HCLGE_COMM_CMDQ_INTR_GEN_REG};
+ 
+ static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
+ 					   HCLGEVF_RST_ING,
+@@ -1928,13 +1928,13 @@ static void hclgevf_reset_handshake(struct hclgevf_dev *hdev, bool enable)
+ {
+ 	u32 reg_val;
+ 
+-	reg_val = hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG);
++	reg_val = hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG);
+ 	if (enable)
+ 		reg_val |= HCLGEVF_NIC_SW_RST_RDY;
+ 	else
+ 		reg_val &= ~HCLGEVF_NIC_SW_RST_RDY;
+ 
+-	hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG,
++	hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG,
+ 			  reg_val);
+ }
+ 
+@@ -2014,9 +2014,10 @@ static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
+ 	dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
+ 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
+ 	dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
+-		 hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STATE_REG));
++		 hclgevf_read_dev(&hdev->hw,
++				  HCLGE_COMM_VECTOR0_CMDQ_STATE_REG));
+ 	dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
+-		 hclgevf_read_dev(&hdev->hw, HCLGEVF_NIC_CSQ_DEPTH_REG));
++		 hclgevf_read_dev(&hdev->hw, HCLGE_COMM_NIC_CSQ_DEPTH_REG));
+ 	dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
+ 		 hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
+ 	dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
+@@ -2438,7 +2439,7 @@ static void hclgevf_service_task(struct work_struct *work)
+ 
+ static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
+ {
+-	hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
++	hclgevf_write_dev(&hdev->hw, HCLGE_COMM_VECTOR0_CMDQ_SRC_REG, regclr);
+ }
+ 
+ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
+@@ -2448,7 +2449,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
+ 
+ 	/* fetch the events from their corresponding regs */
+ 	cmdq_stat_reg = hclgevf_read_dev(&hdev->hw,
+-					 HCLGEVF_VECTOR0_CMDQ_STATE_REG);
++					 HCLGE_COMM_VECTOR0_CMDQ_STATE_REG);
+ 	if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
+ 		rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
+ 		dev_info(&hdev->pdev->dev,
+@@ -3222,7 +3223,7 @@ static int hclgevf_query_dev_specs(struct hclgevf_dev *hdev)
+ 	for (i = 0; i < HCLGEVF_QUERY_DEV_SPECS_BD_NUM - 1; i++) {
+ 		hclgevf_cmd_setup_basic_desc(&desc[i],
+ 					     HCLGEVF_OPC_QUERY_DEV_SPECS, true);
+-		desc[i].flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_NEXT);
++		desc[i].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
+ 	}
+ 	hclgevf_cmd_setup_basic_desc(&desc[i], HCLGEVF_OPC_QUERY_DEV_SPECS,
+ 				     true);
+@@ -3291,7 +3292,10 @@ static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
+ 		return ret;
+ 	}
+ 
+-	ret = hclgevf_cmd_init(hdev);
++	hclgevf_arq_init(hdev);
++	ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw,
++				  &hdev->fw_version, false,
++				  hdev->reset_pending);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "cmd failed %d\n", ret);
+ 		return ret;
+@@ -3336,11 +3340,14 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
+ 	if (ret)
+ 		goto err_devlink_init;
+ 
+-	ret = hclgevf_cmd_queue_init(hdev);
++	ret = hclge_comm_cmd_queue_init(hdev->pdev, &hdev->hw.hw);
+ 	if (ret)
+ 		goto err_cmd_queue_init;
+ 
+-	ret = hclgevf_cmd_init(hdev);
++	hclgevf_arq_init(hdev);
++	ret = hclge_comm_cmd_init(hdev->ae_dev, &hdev->hw.hw,
++				  &hdev->fw_version, false,
++				  hdev->reset_pending);
+ 	if (ret)
+ 		goto err_cmd_init;
+ 
+@@ -3434,7 +3441,7 @@ static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
+ 	hclgevf_state_uninit(hdev);
+ 	hclgevf_uninit_msi(hdev);
+ err_cmd_init:
+-	hclgevf_cmd_uninit(hdev);
++	hclge_comm_cmd_uninit(hdev->ae_dev, false, &hdev->hw.hw);
+ err_cmd_queue_init:
+ 	hclgevf_devlink_uninit(hdev);
+ err_devlink_init:
+@@ -3457,7 +3464,7 @@ static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
+ 		hclgevf_uninit_msi(hdev);
+ 	}
+ 
+-	hclgevf_cmd_uninit(hdev);
++	hclge_comm_cmd_uninit(hdev->ae_dev, false, &hdev->hw.hw);
+ 	hclgevf_devlink_uninit(hdev);
+ 	hclgevf_pci_uninit(hdev);
+ 	hclgevf_uninit_mac_list(hdev);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+index b419ac92179f..a8f2d01b15b8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+@@ -32,21 +32,6 @@
+ #define HCLGEVF_VECTOR_REG_OFFSET	0x4
+ #define HCLGEVF_VECTOR_VF_OFFSET		0x100000
+ 
+-/* bar registers for cmdq */
+-#define HCLGEVF_NIC_CSQ_BASEADDR_L_REG		0x27000
+-#define HCLGEVF_NIC_CSQ_BASEADDR_H_REG		0x27004
+-#define HCLGEVF_NIC_CSQ_DEPTH_REG		0x27008
+-#define HCLGEVF_NIC_CSQ_TAIL_REG		0x27010
+-#define HCLGEVF_NIC_CSQ_HEAD_REG		0x27014
+-#define HCLGEVF_NIC_CRQ_BASEADDR_L_REG		0x27018
+-#define HCLGEVF_NIC_CRQ_BASEADDR_H_REG		0x2701C
+-#define HCLGEVF_NIC_CRQ_DEPTH_REG		0x27020
+-#define HCLGEVF_NIC_CRQ_TAIL_REG		0x27024
+-#define HCLGEVF_NIC_CRQ_HEAD_REG		0x27028
+-
+-#define HCLGEVF_CMDQ_INTR_EN_REG		0x27108
+-#define HCLGEVF_CMDQ_INTR_GEN_REG		0x2710C
+-
+ /* bar registers for common func */
+ #define HCLGEVF_GRO_EN_REG			0x28000
+ 
+@@ -85,10 +70,6 @@
+ #define HCLGEVF_TQP_INTR_GL2_REG		0x20300
+ #define HCLGEVF_TQP_INTR_RL_REG			0x20900
+ 
+-/* Vector0 interrupt CMDQ event source register(RW) */
+-#define HCLGEVF_VECTOR0_CMDQ_SRC_REG	0x27100
+-/* Vector0 interrupt CMDQ event status register(RO) */
+-#define HCLGEVF_VECTOR0_CMDQ_STATE_REG	0x27104
+ /* CMDQ register bits for RX event(=MBX event) */
+ #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B	1
+ /* RST register bits for RESET event */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+index f8678ae46768..5d30ed7dac21 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
+@@ -177,7 +177,7 @@ int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev,
+ 
+ static bool hclgevf_cmd_crq_empty(struct hclgevf_hw *hw)
+ {
+-	u32 tail = hclgevf_read_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG);
++	u32 tail = hclgevf_read_dev(hw, HCLGE_COMM_NIC_CRQ_TAIL_REG);
+ 
+ 	return tail == hw->hw.cmq.crq.next_to_use;
+ }
+@@ -297,7 +297,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
+ 	}
+ 
+ 	/* Write back CMDQ_RQ header pointer, M7 need this pointer */
+-	hclgevf_write_dev(&hdev->hw, HCLGEVF_NIC_CRQ_HEAD_REG,
++	hclgevf_write_dev(&hdev->hw, HCLGE_COMM_NIC_CRQ_HEAD_REG,
+ 			  crq->next_to_use);
+ }
+ 
+-- 
+2.34.1
+
diff --git a/patches/0613-net-hns3-delete-the-hclge_cmd.c-and-hclgevf_cmd.c.patch b/patches/0613-net-hns3-delete-the-hclge_cmd.c-and-hclgevf_cmd.c.patch
new file mode 100644
index 0000000..0166d8b
--- /dev/null
+++ b/patches/0613-net-hns3-delete-the-hclge_cmd.c-and-hclgevf_cmd.c.patch
@@ -0,0 +1,127 @@
+From 19316ba0f96e49c2d5f67c49f10d656b99a1cd99 Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Wed, 12 Jan 2022 15:16:58 +0800
+Subject: [PATCH 252/283] net: hns3: delete the hclge_cmd.c and hclgevf_cmd.c
+
+mainline inclusion
+from mainline-v5.17-rc1
+commit aab8d1c6a5e3aaf67c4c18f6b03cf6486c435755
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aab8d1c6a5e3aaf67c4c18f6b03cf6486c435755
+
+----------------------------------------------------------------------
+
+currently most cmdq APIs are unified in hclge_comm_cmd.c. Newly developed
+cmdq APIs should also be placed in hclge_comm_cmd.c. So there is no need to
+keep hclge_cmd.c and hclgevf_cmd.c.
+
+This patch moves the hclge(vf)_cmd_send to hclge(vf)_main.c and deletes
+the source files and makefile scripts.
+
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/Makefile
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+	drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
+---
+ drivers/net/ethernet/hisilicon/hns3/Makefile  |  3 +--
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 14 ++++++++++
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      | 26 +++++++++++++++++++
+ 3 files changed, 41 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile
+index 95069b38ab65..f95ddaedd3a5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/Makefile
++++ b/drivers/net/ethernet/hisilicon/hns3/Makefile
+@@ -32,7 +32,6 @@ hns3-$(CONFIG_HNS3_DCB) += hns3_dcbnl.o
+ 
+ #### compile hclge.ko
+ HCLGE_OBJ = 	hns3pf/hclge_main.o \
+-			hns3pf/hclge_cmd.o \
+ 			hns3pf/hclge_mdio.o \
+ 			hns3pf/hclge_debugfs.o \
+ 			hns3pf/hclge_tm.o \
+@@ -52,7 +51,7 @@ hclge-objs += hns3_common/hclge_comm_cmd.o
+ hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o
+ #### compile hclgevf.ko
+ obj-$(CONFIG_HNS3_HCLGEVF) += hclgevf.o
+-hclgevf-objs := hns3vf/hclgevf_main.o hns3vf/hclgevf_cmd.o hns3vf/hclgevf_mbx.o hns3vf/hclgevf_devlink.o hns3_common/hclge_comm_cmd.o
++hclgevf-objs := hns3vf/hclgevf_main.o hns3vf/hclgevf_mbx.o hns3vf/hclgevf_devlink.o hns3_common/hclge_comm_cmd.o
+ 
+ #### compile hns3_cae.ko
+ #add rally code
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 459051a01506..a18a9ffba130 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -481,6 +481,20 @@ static const struct key_info tuple_key_info[] = {
+ 	{ INNER_L4_RSV, 32, KEY_OPT_LE32, -1, -1 },
+ };
+ 
++/**
++ * hclge_cmd_send - send command to command queue
++ * @hw: pointer to the hw struct
++ * @desc: prefilled descriptor for describing the command
++ * @num : the number of descriptors to be sent
++ *
++ * This is the main send command for command queue, it
++ * sends the queue, cleans the queue, etc
++ **/
++int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
++{
++	return hclge_comm_cmd_send(&hw->hw, desc, num);
++}
++
+ static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
+ {
+ #define HCLGE_MAC_CMD_NUM 21
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 3d72c2a3a59c..271321f02a0e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -92,6 +92,32 @@ static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
+ 					     HCLGEVF_TQP_INTR_GL2_REG,
+ 					     HCLGEVF_TQP_INTR_RL_REG};
+ 
++/* hclgevf_cmd_send - send command to command queue
++ * @hw: pointer to the hw struct
++ * @desc: prefilled descriptor for describing the command
++ * @num : the number of descriptors to be sent
++ *
++ * This is the main send command for command queue, it
++ * sends the queue, cleans the queue, etc
++ */
++int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclge_desc *desc, int num)
++{
++	return hclge_comm_cmd_send(&hw->hw, desc, num);
++}
++
++void hclgevf_arq_init(struct hclgevf_dev *hdev)
++{
++	struct hclge_comm_cmq *cmdq = &hdev->hw.hw.cmq;
++
++	spin_lock(&cmdq->crq.lock);
++	/* initialize the pointers of async rx queue of mailbox */
++	hdev->arq.hdev = hdev;
++	hdev->arq.head = 0;
++	hdev->arq.tail = 0;
++	atomic_set(&hdev->arq.count, 0);
++	spin_unlock(&cmdq->crq.lock);
++}
++
+ static struct hclgevf_dev *hclgevf_ae_get_hdev(struct hnae3_handle *handle)
+ {
+ 	if (!handle->client)
+-- 
+2.34.1
+
diff --git a/patches/0614-net-hns3-add-debugfs-support-for-interrupt-coalesce.patch b/patches/0614-net-hns3-add-debugfs-support-for-interrupt-coalesce.patch
new file mode 100644
index 0000000..de40ba6
--- /dev/null
+++ b/patches/0614-net-hns3-add-debugfs-support-for-interrupt-coalesce.patch
@@ -0,0 +1,217 @@
+From 2a1e73290fad59f6de2535591b2aa6ef6218a9f0 Mon Sep 17 00:00:00 2001
+From: Huazhong Tan <tanhuazhong@huawei.com>
+Date: Thu, 18 Nov 2021 20:44:40 +0800
+Subject: [PATCH 253/283] net: hns3: add debugfs support for interrupt coalesce
+
+mainline inclusion
+from mainline-v5.16-rc1
+commit c99fead7cb07979f5db38035ccb5f02ad2c7106a
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c99fead7cb07979f5db38035ccb5f02ad2c7106a
+
+----------------------------------------------------------------------
+
+Since user may need to check the current configuration of the
+interrupt coalesce, so add debugfs support for query this info.
+
+Create a single file "coalesce_info" for it, and query it by
+"cat coalesce_info", return the result to userspace.
+
+For device whose version is above V3(include V3), the GL's register
+contains usecs and 1us unit configuration. When get the usecs
+configuration from this register, it will include the confusing unit
+configuration, so add a GL mask to get the correct value, and add
+a QL mask for the frames configuration as well.
+
+The display style is below:
+$ cat coalesce_info
+tx interrupt coalesce info:
+VEC_ID  ALGO_STATE  PROFILE_ID  CQE_MODE  TUNE_STATE  STEPS_LEFT...
+0       IN_PROG     4           EQE       ON_TOP      0...
+1       START       3           EQE       LEFT        1...
+
+rx interrupt coalesce info:
+VEC_ID  ALGO_STATE  PROFILE_ID  CQE_MODE  TUNE_STATE  STEPS_LEFT...
+0       IN_PROG     3           EQE       LEFT        1...
+1       IN_PROG     0           EQE       ON_TOP      0...
+
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Reviewed-by: Yongxin Li <liyongxin1@huawei.com>
+Signed-off-by: Junxin Chen <chenjunxin1@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+---
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    | 108 ++++++++++++++++++
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |   2 +
+ 2 files changed, 110 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 5e4be179cf99..e96d44e3e716 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -322,6 +322,13 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
+ 		.buf_len = HNS3_DBG_READ_LEN,
+ 		.init = hns3_dbg_common_file_init,
+ 	},
++	{
++		.name = "coalesce_info",
++		.cmd = HNAE3_DBG_CMD_COAL_INFO,
++		.dentry = HNS3_DBG_DENTRY_COMMON,
++		.buf_len = HNS3_DBG_READ_LEN_1MB,
++		.init = hns3_dbg_common_file_init,
++	},
+ };
+ 
+ static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
+@@ -379,6 +386,26 @@ static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
+ 	}
+ };
+ 
++static const struct hns3_dbg_item coal_info_items[] = {
++	{ "VEC_ID", 2 },
++	{ "ALGO_STATE", 2 },
++	{ "PROFILE_ID", 2 },
++	{ "CQE_MODE", 2 },
++	{ "TUNE_STATE", 2 },
++	{ "STEPS_LEFT", 2 },
++	{ "STEPS_RIGHT", 2 },
++	{ "TIRED", 2 },
++	{ "SW_GL", 2 },
++	{ "SW_QL", 2 },
++	{ "HW_GL", 2 },
++	{ "HW_QL", 2 },
++};
++
++static const char * const dim_cqe_mode_str[] = { "EQE", "CQE" };
++static const char * const dim_state_str[] = { "START", "IN_PROG", "APPLY" };
++static const char * const
++dim_tune_stat_str[] = { "ON_TOP", "TIRED", "RIGHT", "LEFT" };
++
+ static void hns3_dbg_fill_content(char *content, u16 len,
+ 				  const struct hns3_dbg_item *items,
+ 				  const char **result, u16 size)
+@@ -417,6 +444,83 @@ static void hns3_dbg_fill_content(char *content, u16 len,
+ 	*pos++ = '\0';
+ }
+ 
++static void hns3_get_coal_info(struct hns3_enet_tqp_vector *tqp_vector,
++			       char **result, int i, bool is_tx)
++{
++	unsigned int gl_offset, ql_offset;
++	struct hns3_enet_coalesce *coal;
++	unsigned int reg_val;
++	unsigned int j = 0;
++	bool ql_enable;
++
++	if (is_tx) {
++		coal = &tqp_vector->tx_group.coal;
++		gl_offset = HNS3_VECTOR_GL1_OFFSET;
++		ql_offset = HNS3_VECTOR_TX_QL_OFFSET;
++		ql_enable = tqp_vector->tx_group.coal.ql_enable;
++	} else {
++		coal = &tqp_vector->rx_group.coal;
++		gl_offset = HNS3_VECTOR_GL0_OFFSET;
++		ql_offset = HNS3_VECTOR_RX_QL_OFFSET;
++		ql_enable = tqp_vector->rx_group.coal.ql_enable;
++	}
++
++	sprintf(result[j++], "%d", i);
++	sprintf(result[j++], "%u", coal->int_gl);
++	sprintf(result[j++], "%u", coal->int_ql);
++	reg_val = readl(tqp_vector->mask_addr + gl_offset) &
++		  HNS3_VECTOR_GL_MASK;
++	sprintf(result[j++], "%u", reg_val);
++	if (ql_enable) {
++		reg_val = readl(tqp_vector->mask_addr + ql_offset) &
++			  HNS3_VECTOR_QL_MASK;
++		sprintf(result[j++], "%u", reg_val);
++	} else {
++		sprintf(result[j++], "NA");
++	}
++}
++
++static void hns3_dump_coal_info(struct hnae3_handle *h, char *buf, int len,
++				int *pos, bool is_tx)
++{
++	char data_str[ARRAY_SIZE(coal_info_items)][HNS3_DBG_DATA_STR_LEN];
++	char *result[ARRAY_SIZE(coal_info_items)];
++	struct hns3_enet_tqp_vector *tqp_vector;
++	struct hns3_nic_priv *priv = h->priv;
++	char content[HNS3_DBG_INFO_LEN];
++	unsigned int i;
++
++	for (i = 0; i < ARRAY_SIZE(coal_info_items); i++)
++		result[i] = &data_str[i][0];
++
++	*pos += scnprintf(buf + *pos, len - *pos,
++			  "%s interrupt coalesce info:\n",
++			  is_tx ? "tx" : "rx");
++	hns3_dbg_fill_content(content, sizeof(content), coal_info_items,
++			      NULL, ARRAY_SIZE(coal_info_items));
++	*pos += scnprintf(buf + *pos, len - *pos, "%s", content);
++
++	for (i = 0; i < priv->vector_num; i++) {
++		tqp_vector = &priv->tqp_vector[i];
++		hns3_get_coal_info(tqp_vector, result, i, is_tx);
++		hns3_dbg_fill_content(content, sizeof(content), coal_info_items,
++				      (const char **)result,
++				      ARRAY_SIZE(coal_info_items));
++		*pos += scnprintf(buf + *pos, len - *pos, "%s", content);
++	}
++}
++
++static int hns3_dbg_coal_info(struct hnae3_handle *h, char *buf, int len)
++{
++	int pos = 0;
++
++	hns3_dump_coal_info(h, buf, len, &pos, true);
++	pos += scnprintf(buf + pos, len - pos, "\n");
++	hns3_dump_coal_info(h, buf, len, &pos, false);
++
++	return 0;
++}
++
+ static const struct hns3_dbg_item tx_spare_info_items[] = {
+ 	{ "QUEUE_ID", 2 },
+ 	{ "COPYBREAK", 2 },
+@@ -976,6 +1080,10 @@ static const struct hns3_dbg_func hns3_dbg_cmd_func[] = {
+ 		.cmd = HNAE3_DBG_CMD_DEV_INFO,
+ 		.dbg_dump = hns3_dbg_dev_info,
+ 	},
++	{
++		.cmd = HNAE3_DBG_CMD_COAL_INFO,
++		.dbg_dump = hns3_dbg_coal_info,
++	},
+ };
+ 
+ static int hns3_dbg_read_cmd(struct hns3_dbg_data *dbg_data,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 163f7cdadd54..36342762f85d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -200,11 +200,13 @@ enum hns3_nic_state {
+ #define HNS3_MAX_NON_TSO_SIZE			9728U
+ #define HNS3_MAX_BD_SIZE_OFFSET			16
+ 
++#define HNS3_VECTOR_GL_MASK			GENMASK(11, 0)
+ #define HNS3_VECTOR_GL0_OFFSET			0x100
+ #define HNS3_VECTOR_GL1_OFFSET			0x200
+ #define HNS3_VECTOR_GL2_OFFSET			0x300
+ #define HNS3_VECTOR_RL_OFFSET			0x900
+ #define HNS3_VECTOR_RL_EN_B			6
++#define HNS3_VECTOR_QL_MASK			GENMASK(9, 0)
+ #define HNS3_VECTOR_TX_QL_OFFSET		0xe00
+ #define HNS3_VECTOR_RX_QL_OFFSET		0xf00
+ 
+-- 
+2.34.1
+
diff --git a/patches/0615-net-hns3-support-debugfs-for-wake-on-lan.patch b/patches/0615-net-hns3-support-debugfs-for-wake-on-lan.patch
new file mode 100644
index 0000000..ee4cdd7
--- /dev/null
+++ b/patches/0615-net-hns3-support-debugfs-for-wake-on-lan.patch
@@ -0,0 +1,140 @@
+From cebd54f2c4dc565c825a73e981eb09d897a603ab Mon Sep 17 00:00:00 2001
+From: Hao Lan <lanhao@huawei.com>
+Date: Wed, 30 Nov 2022 18:23:58 +0800
+Subject: [PATCH 254/283] net: hns3: support debugfs for wake on lan
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+Implement debugfs for wake on lan to hns3. The debugfs
+support verify the firmware wake on lan configuration.
+
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Yue Haibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+---
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    | 10 +++
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     | 62 +++++++++++++++++++
+ 2 files changed, 72 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index e96d44e3e716..07c4ed3f0766 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -329,6 +329,13 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
+ 		.buf_len = HNS3_DBG_READ_LEN_1MB,
+ 		.init = hns3_dbg_common_file_init,
+ 	},
++	{
++		.name = "wol_info",
++		.cmd = HNAE3_DBG_CMD_WOL_INFO,
++		.dentry = HNS3_DBG_DENTRY_COMMON,
++		.buf_len = HNS3_DBG_READ_LEN,
++		.init = hns3_dbg_common_file_init,
++	},
+ };
+ 
+ static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
+@@ -383,6 +390,9 @@ static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
+ 	}, {
+ 		.name = "support tm flush",
+ 		.cap_bit = HNAE3_DEV_SUPPORT_TM_FLUSH_B,
++	}, {
++		.name = "support wake on lan",
++		.cap_bit = HNAE3_DEV_SUPPORT_WOL_B,
+ 	}
+ };
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index 407ba8d9a10c..e847a7398c0b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -2427,6 +2427,64 @@ static int hclge_dbg_dump_umv_info(struct hclge_dev *hdev, char *buf, int len)
+ 	return 0;
+ }
+ 
++static void hclge_dump_wol_mode(u32 mode, char *buf, int len, int *pos)
++{
++	if (mode & HCLGE_WOL_PHY)
++		*pos += scnprintf(buf + *pos, len - *pos, "  [p]phy\n");
++
++	if (mode & HCLGE_WOL_UNICAST)
++		*pos += scnprintf(buf + *pos, len - *pos, "  [u]unicast\n");
++
++	if (mode & HCLGE_WOL_MULTICAST)
++		*pos += scnprintf(buf + *pos, len - *pos, "  [m]multicast\n");
++
++	if (mode & HCLGE_WOL_BROADCAST)
++		*pos += scnprintf(buf + *pos, len - *pos, "  [b]broadcast\n");
++
++	if (mode & HCLGE_WOL_ARP)
++		*pos += scnprintf(buf + *pos, len - *pos, "  [a]arp\n");
++
++	if (mode & HCLGE_WOL_MAGIC)
++		*pos += scnprintf(buf + *pos, len - *pos, "  [g]magic\n");
++
++	if (mode & HCLGE_WOL_MAGICSECURED)
++		*pos += scnprintf(buf + *pos, len - *pos,
++				 "  [s]magic secured\n");
++
++	if (mode & HCLGE_WOL_FILTER)
++		*pos += scnprintf(buf + *pos, len - *pos, "  [f]filter\n");
++}
++
++static int hclge_dbg_dump_wol_info(struct hclge_dev *hdev, char *buf, int len)
++{
++	u32 wol_supported;
++	int pos = 0;
++	u32 mode;
++
++	if (!hnae3_ae_dev_wol_supported(hdev->ae_dev)) {
++		pos += scnprintf(buf + pos, len - pos,
++				 "wake-on-lan is unsupported\n");
++		return 0;
++	}
++
++	pos += scnprintf(buf + pos, len - pos, "wake-on-lan mode:\n");
++	pos += scnprintf(buf + pos, len - pos, " supported:\n");
++	if (hclge_get_wol_supported_mode(hdev, &wol_supported))
++		return -EINVAL;
++
++	hclge_dump_wol_mode(wol_supported, buf, len, &pos);
++
++	pos += scnprintf(buf + pos, len - pos, " current:\n");
++	if (hclge_get_wol_cfg(hdev, &mode))
++		return -EINVAL;
++	if (mode)
++		hclge_dump_wol_mode(mode, buf, len, &pos);
++	else
++		pos += scnprintf(buf + pos, len - pos, "  [d]disabled\n");
++
++	return 0;
++}
++
+ static const struct hclge_dbg_func hclge_dbg_cmd_func[] = {
+ 	{
+ 		.cmd = HNAE3_DBG_CMD_TM_PRI,
+@@ -2568,6 +2626,10 @@ static const struct hclge_dbg_func hclge_dbg_cmd_func[] = {
+ 		.cmd = HNAE3_DBG_CMD_FD_COUNTER,
+ 		.dbg_dump = hclge_dbg_dump_fd_counter,
+ 	},
++	{
++		.cmd = HNAE3_DBG_CMD_WOL_INFO,
++		.dbg_dump = hclge_dbg_dump_wol_info,
++	},
+ };
+ 
+ int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
+-- 
+2.34.1
+
diff --git a/patches/0616-net-hns3-debugfs-add-dump-dscp-map-info.patch b/patches/0616-net-hns3-debugfs-add-dump-dscp-map-info.patch
new file mode 100644
index 0000000..ba32928
--- /dev/null
+++ b/patches/0616-net-hns3-debugfs-add-dump-dscp-map-info.patch
@@ -0,0 +1,147 @@
+From 90e2ea49f7135dae42b2c57b5d44446bbe9a923c Mon Sep 17 00:00:00 2001
+From: Guangbin Huang <huangguangbin2@huawei.com>
+Date: Tue, 11 Oct 2022 23:14:17 +0800
+Subject: [PATCH 255/283] net: hns3: debugfs add dump dscp map info
+
+mainline inclusion
+from mainline-v6.0-rc3
+commit fddc02eb583ada2b2d8f35ef41630da5959e8d4b
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=fddc02eb583a
+
+----------------------------------------------------------------------
+
+This patch add dump the map relation for dscp, priority and TC, and
+the current tc map mode.
+
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Reviewed-by: YueHaibing <yuehaibing@huawei.com>
+Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    |  7 +++
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     | 60 ++++++++++++++++++-
+ 2 files changed, 66 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index 07c4ed3f0766..c5234d1d078f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -98,6 +98,13 @@ static struct hns3_dbg_cmd_info hns3_dbg_cmd[] = {
+ 		.buf_len = HNS3_DBG_READ_LEN,
+ 		.init = hns3_dbg_common_file_init,
+ 	},
++	{
++		.name = "qos_dscp_map",
++		.cmd = HNAE3_DBG_CMD_QOS_DSCP_MAP,
++		.dentry = HNS3_DBG_DENTRY_TM,
++		.buf_len = HNS3_DBG_READ_LEN,
++		.init = hns3_dbg_common_file_init,
++	},
+ 	{
+ 		.name = "qos_buf_cfg",
+ 		.cmd = HNAE3_DBG_CMD_QOS_BUF_CFG,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index e847a7398c0b..862efe4cce85 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -14,6 +14,8 @@ static const char * const hclge_mac_state_str[] = {
+ 	"TO_ADD", "TO_DEL", "ACTIVE"
+ };
+ 
++static const char * const tc_map_mode_str[] = { "PRIO", "DSCP" };
++
+ static const struct hclge_dbg_reg_type_info hclge_dbg_reg_info[] = {
+ 	{ .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,
+ 	  .dfx_msg = &hclge_dbg_bios_common_reg[0],
+@@ -1108,10 +1110,11 @@ static int hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev, char *buf,
+ 	return 0;
+ }
+ 
++#define HCLGE_DBG_TC_MASK		0x0F
++
+ static int hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev, char *buf,
+ 				      int len)
+ {
+-#define HCLGE_DBG_TC_MASK		0x0F
+ #define HCLGE_DBG_TC_BIT_WIDTH		4
+ 
+ 	struct hclge_qos_pri_map_cmd *pri_map;
+@@ -1145,6 +1148,57 @@ static int hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev, char *buf,
+ 	return 0;
+ }
+ 
++static int hclge_dbg_dump_qos_dscp_map(struct hclge_dev *hdev, char *buf,
++				       int len)
++{
++	struct hclge_desc desc[HCLGE_DSCP_MAP_TC_BD_NUM];
++	u8 *req0 = (u8 *)desc[0].data;
++	u8 *req1 = (u8 *)desc[1].data;
++	u8 dscp_tc[HCLGE_MAX_DSCP];
++	int pos, ret;
++	u8 i, j;
++
++	pos = scnprintf(buf, len, "tc map mode: %s\n",
++			tc_map_mode_str[hdev->vport[0].nic.kinfo.tc_map_mode]);
++
++	if (hdev->vport[0].nic.kinfo.tc_map_mode != HNAE3_TC_MAP_MODE_DSCP)
++		return 0;
++
++	hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QOS_MAP, true);
++	desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
++	hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_QOS_MAP, true);
++	ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_DSCP_MAP_TC_BD_NUM);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to dump qos dscp map, ret = %d\n", ret);
++		return ret;
++	}
++
++	pos += scnprintf(buf + pos, len - pos, "\nDSCP  PRIO  TC\n");
++
++	/* The low 32 dscp setting use bd0, high 32 dscp setting use bd1 */
++	for (i = 0; i < HCLGE_MAX_DSCP / HCLGE_DSCP_MAP_TC_BD_NUM; i++) {
++		j = i + HCLGE_MAX_DSCP / HCLGE_DSCP_MAP_TC_BD_NUM;
++		/* Each dscp setting has 4 bits, so each byte saves two dscp
++		 * setting
++		 */
++		dscp_tc[i] = req0[i >> 1] >> HCLGE_DSCP_TC_SHIFT(i);
++		dscp_tc[j] = req1[i >> 1] >> HCLGE_DSCP_TC_SHIFT(i);
++		dscp_tc[i] &= HCLGE_DBG_TC_MASK;
++		dscp_tc[j] &= HCLGE_DBG_TC_MASK;
++	}
++
++	for (i = 0; i < HCLGE_MAX_DSCP; i++) {
++		if (hdev->tm_info.dscp_prio[i] == HCLGE_PRIO_ID_INVALID)
++			continue;
++
++		pos += scnprintf(buf + pos, len - pos, " %2u    %u    %u\n",
++				 i, hdev->tm_info.dscp_prio[i], dscp_tc[i]);
++	}
++
++	return 0;
++}
++
+ static int hclge_dbg_dump_tx_buf_cfg(struct hclge_dev *hdev, char *buf, int len)
+ {
+ 	struct hclge_tx_buff_alloc_cmd *tx_buf_cmd;
+@@ -2518,6 +2572,10 @@ static const struct hclge_dbg_func hclge_dbg_cmd_func[] = {
+ 		.cmd = HNAE3_DBG_CMD_QOS_PRI_MAP,
+ 		.dbg_dump = hclge_dbg_dump_qos_pri_map,
+ 	},
++	{
++		.cmd = HNAE3_DBG_CMD_QOS_DSCP_MAP,
++		.dbg_dump = hclge_dbg_dump_qos_dscp_map,
++	},
+ 	{
+ 		.cmd = HNAE3_DBG_CMD_QOS_BUF_CFG,
+ 		.dbg_dump = hclge_dbg_dump_qos_buf_cfg,
+-- 
+2.34.1
+
diff --git a/patches/0617-net-hns3-add-supports-pfc-storm-detection-and-suppre.patch b/patches/0617-net-hns3-add-supports-pfc-storm-detection-and-suppre.patch
new file mode 100644
index 0000000..11555c8
--- /dev/null
+++ b/patches/0617-net-hns3-add-supports-pfc-storm-detection-and-suppre.patch
@@ -0,0 +1,210 @@
+From b863e1ccdb78ffba61a54078e45e5aabb4a45837 Mon Sep 17 00:00:00 2001
+From: Tian Jiang <jiangtian6@h-partners.com>
+Date: Thu, 16 Mar 2023 14:05:22 +0800
+Subject: [PATCH 256/283] net: hns3: add supports pfc storm detection and
+ suppression
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+To solve the problem of abnormal transmission of pauses or PFC frames,
+the IMP periodically checks the transmission and reception status of
+packets. If a pause frame storm occurs, the pause storm response of
+the MAC address is disabled for a period of time.
+
+Signed-off-by: Tian Jiang <jiangtian6@h-partners.com>
+Signed-off-by: shaojijie <shaojijie@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+	drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.h
+---
+ .../net/ethernet/hisilicon/hns3/hns3_ext.c    | 70 +++++++++++++++++++
+ .../net/ethernet/hisilicon/hns3/hns3_ext.h    |  4 ++
+ .../hisilicon/hns3/hns3pf/hclge_ext.c         | 60 ++++++++++++++++
+ 3 files changed, 134 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+index 45189aaea9a3..e51a281844b9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.c
+@@ -462,6 +462,76 @@ int nic_get_phy_reg(struct net_device *ndev, u32 page_select_addr,
+ }
+ EXPORT_SYMBOL(nic_get_phy_reg);
+ 
++static int nic_check_pfc_storm_para(int dir, int enable, int period_ms,
++				    int times, int recovery_period_ms)
++{
++	if ((dir != HNS3_PFC_STORM_PARA_DIR_RX &&
++	     dir != HNS3_PFC_STORM_PARA_DIR_TX) ||
++	     (enable != HNS3_PFC_STORM_PARA_DISABLE &&
++	      enable != HNS3_PFC_STORM_PARA_ENABLE))
++		return -EINVAL;
++
++	if (period_ms < HNS3_PFC_STORM_PARA_PERIOD_MIN ||
++	    period_ms > HNS3_PFC_STORM_PARA_PERIOD_MAX ||
++	    recovery_period_ms < HNS3_PFC_STORM_PARA_PERIOD_MIN ||
++	    recovery_period_ms > HNS3_PFC_STORM_PARA_PERIOD_MAX ||
++	    times <= 0)
++		return -EINVAL;
++
++	return 0;
++}
++
++int nic_set_pfc_storm_para(struct net_device *ndev, int dir, int enable,
++			   int period_ms, int times, int recovery_period_ms)
++{
++	struct hnae3_pfc_storm_para para;
++
++	if (nic_check_pfc_storm_para(dir, enable, period_ms, times,
++				     recovery_period_ms)) {
++		dev_err(&ndev->dev,
++			"set pfc storm para failed because invalid input param.\n");
++		return -EINVAL;
++	}
++
++	para.dir = dir;
++	para.enable = enable;
++	para.period_ms = period_ms;
++	para.times = times;
++	para.recovery_period_ms = recovery_period_ms;
++
++	return nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_SET_PFC_STORM_PARA,
++				  &para, sizeof(para));
++}
++EXPORT_SYMBOL(nic_set_pfc_storm_para);
++
++int nic_get_pfc_storm_para(struct net_device *ndev, int dir, int *enable,
++			   int *period_ms, int *times, int *recovery_period_ms)
++{
++	struct hnae3_pfc_storm_para para;
++	int ret;
++
++	if (!enable || !period_ms || !times || !recovery_period_ms ||
++	    (dir != HNS3_PFC_STORM_PARA_DIR_RX &&
++	     dir != HNS3_PFC_STORM_PARA_DIR_TX)) {
++		dev_err(&ndev->dev,
++			"get pfc storm para failed because invalid input param.\n");
++		return -EINVAL;
++	}
++
++	para.dir = dir;
++	ret = nic_invoke_pri_ops(ndev, HNAE3_EXT_OPC_GET_PFC_STORM_PARA,
++				 &para, sizeof(para));
++	if (ret)
++		return ret;
++
++	*enable = para.enable;
++	*period_ms = para.period_ms;
++	*times = para.times;
++	*recovery_period_ms = para.recovery_period_ms;
++	return 0;
++}
++EXPORT_SYMBOL(nic_get_pfc_storm_para);
++
+ int nic_set_phy_reg(struct net_device *ndev, u32 page_select_addr,
+ 		    u16 page, u32 reg_addr, u16 data)
+ {
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+index f883beae8bf4..b1e358173819 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ext.h
+@@ -70,4 +70,8 @@ int nic_get_phy_reg(struct net_device *ndev, u32 page_select_addr,
+ 		    u16 page, u32 reg_addr, u16 *data);
+ int nic_set_phy_reg(struct net_device *ndev, u32 page_select_addr,
+ 		    u16 page, u32 reg_addr, u16 data);
++int nic_set_pfc_storm_para(struct net_device *ndev, int dir, int enable,
++			   int period_ms, int times, int recovery_period_ms);
++int nic_get_pfc_storm_para(struct net_device *ndev, int dir, int *enable,
++			   int *period_ms, int *times, int *recovery_period_ms);
+ #endif
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+index 4f93ad1ac62e..7b9d6d861b42 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c
+@@ -1249,6 +1249,64 @@ static void hclge_ext_resotre_config(struct hclge_dev *hdev)
+ 			      sizeof(hdev->torus_param));
+ }
+ 
++static int hclge_set_pfc_storm_para(struct hclge_dev *hdev, void *data,
++				    size_t length)
++{
++	struct hclge_pfc_storm_para_cmd *para_cmd;
++	struct hnae3_pfc_storm_para *para;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(struct hnae3_pfc_storm_para))
++		return -EINVAL;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PAUSE_STORM_PARA,
++				   false);
++	para = (struct hnae3_pfc_storm_para *)data;
++	para_cmd = (struct hclge_pfc_storm_para_cmd *)desc.data;
++	para_cmd->dir = cpu_to_le32(para->dir);
++	para_cmd->enable = cpu_to_le32(para->enable);
++	para_cmd->period_ms = cpu_to_le32(para->period_ms);
++	para_cmd->times = cpu_to_le32(para->times);
++	para_cmd->recovery_period_ms = cpu_to_le32(para->recovery_period_ms);
++
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret)
++		dev_err(&hdev->pdev->dev,
++			"failed to set pfc storm para, ret = %d\n", ret);
++	return ret;
++}
++
++static int hclge_get_pfc_storm_para(struct hclge_dev *hdev, void *data,
++				    size_t length)
++{
++	struct hclge_pfc_storm_para_cmd *para_cmd;
++	struct hnae3_pfc_storm_para *para;
++	struct hclge_desc desc;
++	int ret;
++
++	if (length != sizeof(struct hnae3_pfc_storm_para))
++		return -EINVAL;
++
++	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PAUSE_STORM_PARA, true);
++	para = (struct hnae3_pfc_storm_para *)data;
++	para_cmd = (struct hclge_pfc_storm_para_cmd *)desc.data;
++	para_cmd->dir = cpu_to_le32(para->dir);
++	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
++	if (ret) {
++		dev_err(&hdev->pdev->dev,
++			"failed to get pfc storm para, ret = %d\n", ret);
++		return ret;
++	}
++
++	para->enable = le32_to_cpu(para_cmd->enable);
++	para->period_ms = le32_to_cpu(para_cmd->period_ms);
++	para->times = le32_to_cpu(para_cmd->times);
++	para->recovery_period_ms = le32_to_cpu(para_cmd->recovery_period_ms);
++
++	return 0;
++}
++
+ static int hclge_set_reset_task(struct hclge_dev *hdev, void *data,
+ 				size_t length)
+ {
+@@ -1408,6 +1466,8 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = {
+ 	[HNAE3_EXT_OPC_GET_LED_SIGNAL] = hclge_get_led_signal,
+ 	[HNAE3_EXT_OPC_GET_PHY_REG] = hclge_get_phy_reg,
+ 	[HNAE3_EXT_OPC_SET_PHY_REG] = hclge_set_phy_reg,
++	[HNAE3_EXT_OPC_GET_PFC_STORM_PARA] = hclge_get_pfc_storm_para,
++	[HNAE3_EXT_OPC_SET_PFC_STORM_PARA] = hclge_set_pfc_storm_para,
+ };
+ 
+ int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,
+-- 
+2.34.1
+
diff --git a/patches/0618-net-hns3-fix-getting-supported-parameter-from-driver.patch b/patches/0618-net-hns3-fix-getting-supported-parameter-from-driver.patch
new file mode 100644
index 0000000..e3a963a
--- /dev/null
+++ b/patches/0618-net-hns3-fix-getting-supported-parameter-from-driver.patch
@@ -0,0 +1,45 @@
+From f55a7a0c8985a1570e82bfe3e1ff3fb0a533ee4b Mon Sep 17 00:00:00 2001
+From: Hao Lan <lanhao@huawei.com>
+Date: Fri, 9 Dec 2022 10:54:46 +0800
+Subject: [PATCH 257/283] net: hns3: fix getting supported parameter from
+ driver in hclge_set_wol
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+The driver should use the supported parameter got from firmware,
+not from user,to validate the wol mode.
+
+Fixes: c3c5f044b7dc ("net: hns3: support wake on lan configuration and query")
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index a18a9ffba130..5b4014d808cb 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -11760,12 +11760,10 @@ static int hclge_set_wol(struct hnae3_handle *handle,
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+ 	struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
+-	u32 wol_supported;
+ 	u32 wol_mode;
+ 
+-	wol_supported = hclge_wol_mode_from_ethtool(wol->supported);
+ 	wol_mode = hclge_wol_mode_from_ethtool(wol->wolopts);
+-	if (wol_mode & ~wol_supported)
++	if (wol_mode & ~wol_info->wol_support_mode)
+ 		return -EINVAL;
+ 
+ 	wol_info->wol_current_mode = wol_mode;
+-- 
+2.34.1
+
diff --git a/patches/0619-net-hns3-fix-the-HCLGE_OPC_WOL_CFG-opcode-id-for-wol.patch b/patches/0619-net-hns3-fix-the-HCLGE_OPC_WOL_CFG-opcode-id-for-wol.patch
new file mode 100644
index 0000000..6c6bc31
--- /dev/null
+++ b/patches/0619-net-hns3-fix-the-HCLGE_OPC_WOL_CFG-opcode-id-for-wol.patch
@@ -0,0 +1,41 @@
+From 295004d0f2255eaff1cad492c77d7b03ebc5df05 Mon Sep 17 00:00:00 2001
+From: Hao Lan <lanhao@huawei.com>
+Date: Fri, 9 Dec 2022 11:01:58 +0800
+Subject: [PATCH 258/283] net: hns3: fix the HCLGE_OPC_WOL_CFG opcode id for
+ wol
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+Fix the HCLGE_OPC_WOL_CFG opcode id for wol.
+
+Fixes: c3c5f044b7dc ("net: hns3: support wake on lan configuration and query")
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Jiantao Xiao <xiaojiantao1@h-partners.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h  | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 1e5448ee4744..8477e9f1a3d7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -296,8 +296,8 @@ enum hclge_opcode_type {
+ 	HCLGE_PPP_CMD1_INT_CMD		= 0x2101,
+ 	HCLGE_PPP_MAC_VLAN_IDX_RD	= 0x2104,
+ 	HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
+-	HCLGE_OPC_WOL_CFG               = 0x2200,
+-	HCLGE_OPC_WOL_GET_SUPPORTED_MODE        = 0x2201,
++	HCLGE_OPC_WOL_GET_SUPPORTED_MODE	= 0x2201,
++	HCLGE_OPC_WOL_CFG		= 0x2202,
+ 	HCLGE_NCSI_INT_EN		= 0x2401,
+ 
+ 	/* PHY command */
+-- 
+2.34.1
+
diff --git a/patches/0620-net-hns3-fix-pointer-cast-to-different-type-for-wol.patch b/patches/0620-net-hns3-fix-pointer-cast-to-different-type-for-wol.patch
new file mode 100644
index 0000000..38c5bb8
--- /dev/null
+++ b/patches/0620-net-hns3-fix-pointer-cast-to-different-type-for-wol.patch
@@ -0,0 +1,56 @@
+From 14f15981fd8f619fda39b563dc7f3e8fecfb28f8 Mon Sep 17 00:00:00 2001
+From: Hao Lan <lanhao@huawei.com>
+Date: Tue, 13 Dec 2022 11:46:36 +0800
+Subject: [PATCH 259/283] net: hns3: fix pointer cast to different type for wol
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+The pointer to decs.data is __le32 (*)[6], is incompatible to
+"struct hclge_wol_cfg_cmd *". So fix the pointer cast to
+correct type for decs.data.
+
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 5b4014d808cb..989cb20a72d0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -11656,7 +11656,7 @@ int hclge_get_wol_supported_mode(struct hclge_dev *hdev, u32 *wol_supported)
+ 
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_GET_SUPPORTED_MODE,
+ 				   true);
+-	wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)&desc.data;
++	wol_supported_cmd = (struct hclge_query_wol_supported_cmd *)desc.data;
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret) {
+@@ -11684,7 +11684,7 @@ int hclge_get_wol_cfg(struct hclge_dev *hdev, u32 *mode)
+ 		return ret;
+ 	}
+ 
+-	wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)&desc.data;
++	wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data;
+ 	*mode = le32_to_cpu(wol_cfg_cmd->wake_on_lan_mode);
+ 
+ 	return 0;
+@@ -11698,7 +11698,7 @@ static int hclge_set_wol_cfg(struct hclge_dev *hdev,
+ 	int ret;
+ 
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_WOL_CFG, false);
+-	wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)&desc.data;
++	wol_cfg_cmd = (struct hclge_wol_cfg_cmd *)desc.data;
+ 	wol_cfg_cmd->wake_on_lan_mode = cpu_to_le32(wol_info->wol_current_mode);
+ 	wol_cfg_cmd->sopass_size = wol_info->wol_sopass_size;
+ 	memcpy(&wol_cfg_cmd->sopass, wol_info->wol_sopass, SOPASS_MAX);
+-- 
+2.34.1
+
diff --git a/patches/0621-net-hns3-sync-linux-kernel-hns3-wol-to-openeuler.patch b/patches/0621-net-hns3-sync-linux-kernel-hns3-wol-to-openeuler.patch
new file mode 100644
index 0000000..c473cde
--- /dev/null
+++ b/patches/0621-net-hns3-sync-linux-kernel-hns3-wol-to-openeuler.patch
@@ -0,0 +1,284 @@
+From a02834dcb2048d141619f785615008493c6b072a Mon Sep 17 00:00:00 2001
+From: Hao Lan <lanhao@huawei.com>
+Date: Wed, 26 Apr 2023 17:40:13 +0800
+Subject: [PATCH 260/283] net: hns3: sync linux kernel hns3 wol to openeuler
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+After the wol is commit to the linux community,
+the code is different from the openEuler.
+This patch synchronizes the kernel differences to the openEuler.
+
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.h   |  6 ++
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 12 +--
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         | 11 ---
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     | 16 ++--
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 95 ++++---------------
+ 5 files changed, 41 insertions(+), 99 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 36342762f85d..19670ff928ce 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -689,6 +689,12 @@ static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
+ #define hns3_get_handle(ndev) \
+ 	(((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
+ 
++#define hns3_get_ae_dev(handle) \
++	(pci_get_drvdata((handle)->pdev))
++
++#define hns3_get_ops(handle) \
++	((handle)->ae_algo->ops)
++
+ #define hns3_gl_usec_to_reg(int_gl) ((int_gl) >> 1)
+ #define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 2a6de6297446..a6f339c6046d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1990,10 +1990,10 @@ static int hns3_get_link_ext_state(struct net_device *netdev,
+ static void hns3_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
+ {
+ 	struct hnae3_handle *handle = hns3_get_handle(netdev);
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+-	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
++	const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
++	struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
+ 
+-	if (!hnae3_ae_dev_wol_supported(ae_dev) || !ops->get_wol)
++	if (!hnae3_ae_dev_wol_supported(ae_dev))
+ 		return;
+ 
+ 	ops->get_wol(handle, wol);
+@@ -2003,10 +2003,10 @@ static int hns3_set_wol(struct net_device *netdev,
+ 			struct ethtool_wolinfo *wol)
+ {
+ 	struct hnae3_handle *handle = hns3_get_handle(netdev);
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev);
+-	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
++	const struct hnae3_ae_ops *ops = hns3_get_ops(handle);
++	struct hnae3_ae_dev *ae_dev = hns3_get_ae_dev(handle);
+ 
+-	if (!hnae3_ae_dev_wol_supported(ae_dev) || !ops->set_wol)
++	if (!hnae3_ae_dev_wol_supported(ae_dev))
+ 		return -EOPNOTSUPP;
+ 
+ 	return ops->set_wol(handle, wol);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 3773a9ff6301..16ba7e0d8d71 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -936,17 +936,6 @@ struct hclge_phy_reg_cmd {
+ };
+ 
+ int hclge_cmd_init(struct hclge_dev *hdev);
+-enum HCLGE_WOL_MODE {
+-	HCLGE_WOL_PHY           = BIT(0),
+-	HCLGE_WOL_UNICAST       = BIT(1),
+-	HCLGE_WOL_MULTICAST     = BIT(2),
+-	HCLGE_WOL_BROADCAST     = BIT(3),
+-	HCLGE_WOL_ARP           = BIT(4),
+-	HCLGE_WOL_MAGIC         = BIT(5),
+-	HCLGE_WOL_MAGICSECURED  = BIT(6),
+-	HCLGE_WOL_FILTER        = BIT(7),
+-	HCLGE_WOL_DISABLE       = 0,
+-};
+ 
+ struct hclge_wol_cfg_cmd {
+ 	__le32 wake_on_lan_mode;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index 862efe4cce85..32f4245dfd6d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -2483,29 +2483,29 @@ static int hclge_dbg_dump_umv_info(struct hclge_dev *hdev, char *buf, int len)
+ 
+ static void hclge_dump_wol_mode(u32 mode, char *buf, int len, int *pos)
+ {
+-	if (mode & HCLGE_WOL_PHY)
++	if (mode & WAKE_PHY)
+ 		*pos += scnprintf(buf + *pos, len - *pos, "  [p]phy\n");
+ 
+-	if (mode & HCLGE_WOL_UNICAST)
++	if (mode & WAKE_UCAST)
+ 		*pos += scnprintf(buf + *pos, len - *pos, "  [u]unicast\n");
+ 
+-	if (mode & HCLGE_WOL_MULTICAST)
++	if (mode & WAKE_MCAST)
+ 		*pos += scnprintf(buf + *pos, len - *pos, "  [m]multicast\n");
+ 
+-	if (mode & HCLGE_WOL_BROADCAST)
++	if (mode & WAKE_BCAST)
+ 		*pos += scnprintf(buf + *pos, len - *pos, "  [b]broadcast\n");
+ 
+-	if (mode & HCLGE_WOL_ARP)
++	if (mode & WAKE_ARP)
+ 		*pos += scnprintf(buf + *pos, len - *pos, "  [a]arp\n");
+ 
+-	if (mode & HCLGE_WOL_MAGIC)
++	if (mode & WAKE_MAGIC)
+ 		*pos += scnprintf(buf + *pos, len - *pos, "  [g]magic\n");
+ 
+-	if (mode & HCLGE_WOL_MAGICSECURED)
++	if (mode & WAKE_MAGICSECURE)
+ 		*pos += scnprintf(buf + *pos, len - *pos,
+ 				 "  [s]magic secured\n");
+ 
+-	if (mode & HCLGE_WOL_FILTER)
++	if (mode & WAKE_FILTER)
+ 		*pos += scnprintf(buf + *pos, len - *pos, "  [f]filter\n");
+ }
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 989cb20a72d0..17468e2b8bc2 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -11586,69 +11586,15 @@ static void hclge_clear_hw_resource(struct hclge_dev *hdev)
+ 			 "clear hw resource incomplete, ret = %d\n", ret);
+ }
+ 
+-static __u32 hclge_wol_mode_to_ethtool(u32 mode)
++static struct hclge_wol_info *hclge_get_wol_info(struct hnae3_handle *handle)
+ {
+-	__u32 ret = 0;
+-
+-	if (mode & HCLGE_WOL_PHY)
+-		ret |= WAKE_PHY;
+-
+-	if (mode & HCLGE_WOL_UNICAST)
+-		ret |= WAKE_UCAST;
+-
+-	if (mode & HCLGE_WOL_MULTICAST)
+-		ret |= WAKE_MCAST;
+-
+-	if (mode & HCLGE_WOL_BROADCAST)
+-		ret |= WAKE_BCAST;
+-
+-	if (mode & HCLGE_WOL_ARP)
+-		ret |= WAKE_ARP;
+-
+-	if (mode & HCLGE_WOL_MAGIC)
+-		ret |= WAKE_MAGIC;
+-
+-	if (mode & HCLGE_WOL_MAGICSECURED)
+-		ret |= WAKE_MAGICSECURE;
+-
+-	if (mode & HCLGE_WOL_FILTER)
+-		ret |= WAKE_FILTER;
+-
+-	return ret;
+-}
+-
+-static u32 hclge_wol_mode_from_ethtool(__u32 mode)
+-{
+-	u32 ret = HCLGE_WOL_DISABLE;
+-
+-	if (mode & WAKE_PHY)
+-		ret |= HCLGE_WOL_PHY;
+-
+-	if (mode & WAKE_UCAST)
+-		ret |= HCLGE_WOL_UNICAST;
+-
+-	if (mode & WAKE_MCAST)
+-		ret |= HCLGE_WOL_MULTICAST;
+-
+-	if (mode & WAKE_BCAST)
+-		ret |= HCLGE_WOL_BROADCAST;
+-
+-	if (mode & WAKE_ARP)
+-		ret |= HCLGE_WOL_ARP;
+-
+-	if (mode & WAKE_MAGIC)
+-		ret |= HCLGE_WOL_MAGIC;
+-
+-	if (mode & WAKE_MAGICSECURE)
+-		ret |= HCLGE_WOL_MAGICSECURED;
+-
+-	if (mode & WAKE_FILTER)
+-		ret |= HCLGE_WOL_FILTER;
++	struct hclge_vport *vport = hclge_get_vport(handle);
+ 
+-	return ret;
++	return &vport->back->hw.mac.wol;
+ }
+ 
+-int hclge_get_wol_supported_mode(struct hclge_dev *hdev, u32 *wol_supported)
++int hclge_get_wol_supported_mode(struct hclge_dev *hdev,
++				 u32 *wol_supported)
+ {
+ 	struct hclge_query_wol_supported_cmd *wol_supported_cmd;
+ 	struct hclge_desc desc;
+@@ -11733,7 +11679,7 @@ static int hclge_init_wol(struct hclge_dev *hdev)
+ 	ret = hclge_get_wol_supported_mode(hdev,
+ 					   &wol_info->wol_support_mode);
+ 	if (ret) {
+-		wol_info->wol_support_mode = HCLGE_WOL_DISABLE;
++		wol_info->wol_support_mode = 0;
+ 		return ret;
+ 	}
+ 
+@@ -11743,38 +11689,39 @@ static int hclge_init_wol(struct hclge_dev *hdev)
+ static void hclge_get_wol(struct hnae3_handle *handle,
+ 			  struct ethtool_wolinfo *wol)
+ {
+-	struct hclge_vport *vport = hclge_get_vport(handle);
+-	struct hclge_dev *hdev = vport->back;
+-	struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
++	struct hclge_wol_info *wol_info = hclge_get_wol_info(handle);
+ 
+-	wol->supported = hclge_wol_mode_to_ethtool(wol_info->wol_support_mode);
+-	wol->wolopts =
+-		hclge_wol_mode_to_ethtool(wol_info->wol_current_mode);
+-	if (wol_info->wol_current_mode & HCLGE_WOL_MAGICSECURED)
+-		memcpy(&wol->sopass, wol_info->wol_sopass, SOPASS_MAX);
++	wol->supported = wol_info->wol_support_mode;
++	wol->wolopts = wol_info->wol_current_mode;
++	if (wol_info->wol_current_mode & WAKE_MAGICSECURE)
++		memcpy(wol->sopass, wol_info->wol_sopass, SOPASS_MAX);
+ }
+ 
+ static int hclge_set_wol(struct hnae3_handle *handle,
+ 			 struct ethtool_wolinfo *wol)
+ {
++	struct hclge_wol_info *wol_info = hclge_get_wol_info(handle);
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+-	struct hclge_dev *hdev = vport->back;
+-	struct hclge_wol_info *wol_info = &hdev->hw.mac.wol;
+ 	u32 wol_mode;
++	int ret;
+ 
+-	wol_mode = hclge_wol_mode_from_ethtool(wol->wolopts);
++	wol_mode = wol->wolopts;
+ 	if (wol_mode & ~wol_info->wol_support_mode)
+ 		return -EINVAL;
+ 
+ 	wol_info->wol_current_mode = wol_mode;
+-	if (wol_mode & HCLGE_WOL_MAGICSECURED) {
+-		memcpy(wol_info->wol_sopass, &wol->sopass, SOPASS_MAX);
++	if (wol_mode & WAKE_MAGICSECURE) {
++		memcpy(wol_info->wol_sopass, wol->sopass, SOPASS_MAX);
+ 		wol_info->wol_sopass_size = SOPASS_MAX;
+ 	} else {
+ 		wol_info->wol_sopass_size = 0;
+ 	}
+ 
+-	return hclge_set_wol_cfg(hdev, wol_info);
++	ret = hclge_set_wol_cfg(vport->back, wol_info);
++	if (ret)
++		wol_info->wol_current_mode = 0;
++
++	return ret;
+ }
+ 
+ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
+-- 
+2.34.1
+
diff --git a/patches/0622-net-hns3-add-support-for-Hisilicon-ptp-sync-device.patch b/patches/0622-net-hns3-add-support-for-Hisilicon-ptp-sync-device.patch
new file mode 100644
index 0000000..46100fa
--- /dev/null
+++ b/patches/0622-net-hns3-add-support-for-Hisilicon-ptp-sync-device.patch
@@ -0,0 +1,1127 @@
+From f66e1e7c65e4b9d11334e16fdc609ac8b989dcb5 Mon Sep 17 00:00:00 2001
+From: Yonglong Liu <liuyonglong@huawei.com>
+Date: Sat, 8 Oct 2022 11:34:55 +0800
+Subject: [PATCH 261/283] net: hns3: add support for Hisilicon ptp sync device
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+CVE: NA
+
+----------------------------------------------------------------------
+
+The hns3 driver provide ptp driver to get 1588 clock from
+ethernet, but only the first PF on main chip can support this,
+so, if getting ptp time from other chip, may have some bus
+latency. The PTP sync device use to eliminate the bus latency.
+
+Signed-off-by: Yonglong Liu <liuyonglong@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	arch/arm64/configs/openeuler_defconfig
+	drivers/ptp/Kconfig
+	drivers/ptp/Makefile
+---
+ MAINTAINERS                            |    5 +
+ arch/arm64/configs/openeuler_defconfig |    1 +
+ drivers/ptp/Kconfig                    |   11 +
+ drivers/ptp/Makefile                   |    1 +
+ drivers/ptp/ptp_hisi.c                 | 1028 ++++++++++++++++++++++++
+ 5 files changed, 1046 insertions(+)
+ create mode 100644 drivers/ptp/ptp_hisi.c
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 476609d754c3..de12e08442b4 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -6694,6 +6694,11 @@ S:	Supported
+ F:	drivers/scsi/hisi_sas/
+ F:	Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
+ 
++HISILICON HNS3 PTP SYNC DRIVER
++M:	Yonglong Liu <liuyonglong@huawei.com>
++S:	Supported
++F:	drivers/ptp/ptp_hisi.c
++
+ HMM - Heterogeneous Memory Management
+ M:	Jérôme Glisse <jglisse@redhat.com>
+ L:	linux-mm@kvack.org
+diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig
+index b89c386c1bc7..3e0417c995e7 100644
+--- a/arch/arm64/configs/openeuler_defconfig
++++ b/arch/arm64/configs/openeuler_defconfig
+@@ -3241,6 +3241,7 @@ CONFIG_PPS_CLIENT_GPIO=m
+ #
+ CONFIG_PTP_1588_CLOCK=y
+ CONFIG_DP83640_PHY=m
++CONFIG_PTP_HISI=m
+ CONFIG_PINCTRL=y
+ CONFIG_PINMUX=y
+ CONFIG_PINCONF=y
+diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
+index d137c480db46..e4fcadc22243 100644
+--- a/drivers/ptp/Kconfig
++++ b/drivers/ptp/Kconfig
+@@ -118,4 +118,15 @@ config PTP_1588_CLOCK_KVM
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called ptp_kvm.
+ 
++config PTP_HISI
++	tristate "HiSilicon PTP sync platform driver"
++	help
++	  PTP sync driver work on multichip system, eliminates the bus latency
++	  between multichip, and provide a higher precision clock source. But
++	  the clock source of PTP sync device is from the RTC of HNS3 ethernet
++	  device, so, if you want the PTP sync device works, you must enable
++	  HNS3 driver also.
++
++	  If unsure, say N.
++
+ endmenu
+diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
+index 19efa9cfa950..0368dd837921 100644
+--- a/drivers/ptp/Makefile
++++ b/drivers/ptp/Makefile
+@@ -10,3 +10,4 @@ obj-$(CONFIG_PTP_1588_CLOCK_IXP46X)	+= ptp_ixp46x.o
+ obj-$(CONFIG_PTP_1588_CLOCK_PCH)	+= ptp_pch.o
+ obj-$(CONFIG_PTP_1588_CLOCK_KVM)	+= ptp_kvm.o
+ obj-$(CONFIG_PTP_1588_CLOCK_QORIQ)	+= ptp_qoriq.o
++obj-$(CONFIG_PTP_HISI)		+= ptp_hisi.o
+diff --git a/drivers/ptp/ptp_hisi.c b/drivers/ptp/ptp_hisi.c
+new file mode 100644
+index 000000000000..1fcff3c9a90b
+--- /dev/null
++++ b/drivers/ptp/ptp_hisi.c
+@@ -0,0 +1,1028 @@
++// SPDX-License-Identifier: GPL-2.0+
++// Copyright (c) 2022 Hisilicon Limited.
++#include <linux/mm.h>
++#include <linux/acpi.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/ptp_clock_kernel.h>
++#include <linux/net_tstamp.h>
++#include <linux/debugfs.h>
++#include <linux/uaccess.h>
++
++#ifndef PTP_CLOCK_NAME_LEN
++#define PTP_CLOCK_NAME_LEN	32
++#endif
++
++#define HISI_PTP_VERSION	"22.10.2"
++
++#define HISI_PTP_NAME		"hisi_ptp"
++#define HISI_PTP_INT_NAME_LEN	32
++
++#define HISI_PTP_DBGFS_STS_LEN	2048
++#define HISI_PTP_DBGFS_REG_LEN	0x10000
++
++#define HISI_RES_T_PERI_SC	0
++#define HISI_RES_N_NET_SC	0
++#define HISI_RES_N_IO_SC	1
++
++#define HISI_PTP_INIT_DONE	0
++
++/* peri subctrl reg offset */
++#define PERI_SC_PTP_RESET_REQ			0xE18
++#define PERI_SC_PTP_RESET_DREQ			0xE1C
++#define PERI_SC_LOCAL_TIMER_COMP_HIGH_ADDR	0x5000
++#define PERI_SC_LOCAL_TIMER_COMP_LOW_ADDR	0x5004
++#define PERI_SC_BAUD_VALUE_ADDR			0x5008
++#define PERI_SC_LOCAL_CNT_EN_ADDR		0x500C
++#define PERI_SC_SYNC_ERR_COMP_HIGH_ADDR		0x5010
++#define PERI_SC_SYNC_ERR_COMP_LOW_ADDR		0x5014
++#define PERI_SC_CRC_EN_ADDR			0x5018
++#define PERI_SC_ONE_CYCLE_NUM_ADDR		0x5020
++#define PERI_SC_SYNC_ERR_CLR_ADDR		0x5024
++#define PERI_SC_RX_SHIFT_EN_ADDR		0x5028
++#define PERI_SC_TIMEL_CY_NUM_ADDR		0x502C
++#define PERI_SC_INT_PTP_SYNC_ERR_ADDR		0x5044
++#define PERI_SC_INT_PTP_SYNC_ERR_MASK_ADDR	0x5048
++#define PERI_SC_INT_ORIGIN			0x504C
++#define PERI_SC_CRC_ERR_COUNT			0x5050
++#define PERI_SC_CRC_INT_CONTRL_ADDR		0x5054
++#define PERI_SC_CAPTURE_PTP_TIME_COMP_HIGH	0x5058
++#define PERI_SC_CAPTURE_PTP_TIME_COMP_LOW	0x505C
++#define PERI_SC_CAPTURE_SYSTEM_COUNTER_BIN_HIGH	0x5060
++#define PERI_SC_CAPTURE_SYSTEM_COUNTER_BIN_LOW	0x5064
++#define PERI_SC_CAPTURE_VLD			0x5068
++#define PERI_SC_LOCAL_TIME_LOW_ADDR		0x5070
++#define PERI_SC_LOCAL_TIME_HIGH_ADDR		0x5074
++
++/* net subctrl reg offset */
++#define NET_SC_PTP_BAUD_VALUE_ADDR		0x2008
++#define NET_SC_PTP_COUNTER_EN_ADDR		0x200C
++#define NET_SC_PTP_NORMAL_MODE_EN		0x2010
++#define NET_SC_PTP_WIRE_DELAY_CAL_EN		0x2014
++#define NET_SC_SAMPLE_DELAY_CFG_ADDR		0x2018
++#define NET_SC_PTP_TX_DFXBUS0_ADDR		0x201C
++#define NET_SC_PTP_TX_DFXBUS1_ADDR		0x2020
++#define NET_SC_PTP_TX_DFXBUS2_ADDR		0x2024
++#define NET_SC_PTP_TX_DFXBUS3_ADDR		0x2028
++
++/* io subctrl reg offset */
++#define IO_SC_PTP_BAUD_VALUE_ADDR		0x2008
++#define IO_SC_PTP_COUNTER_EN_ADDR		0x200C
++#define IO_SC_PTP_NORMAL_MODE_EN		0x2010
++#define IO_SC_PTP_WIRE_DELAY_CAL_EN		0x2014
++#define IO_SC_SAMPLE_DELAY_CFG_ADDR		0x2018
++#define IO_SC_PTP_TX_DFXBUS0_ADDR		0x201C
++#define IO_SC_PTP_TX_DFXBUS1_ADDR		0x2020
++#define IO_SC_PTP_TX_DFXBUS2_ADDR		0x2024
++#define IO_SC_PTP_TX_DFXBUS3_ADDR		0x2028
++
++/* default values */
++#define HISI_DEF_BAUD				0x1388
++#define HISI_DEF_TIME_COMP			0xB2432
++#define HISI_DEF_ERR_COMP			0xFFFFFFFF
++#define HISI_DEF_ONE_CYCLE_NUM			0x50
++
++#define HISI_PTP_TX_IDLE_MASK			GENMASK(26, 23)
++
++#define HISI_PTP_RX_CRC_INT_EN			BIT(0)
++#define HISI_PTP_RX_CRC_CLR			BIT(1)
++#define HISI_PTP_RX_CRC_CLR_AND_EN \
++	(HISI_PTP_RX_CRC_INT_EN | HISI_PTP_RX_CRC_INT_EN)
++#define HISI_PTP_RX_CRC_CLR_AND_DISABLE		HISI_PTP_RX_CRC_CLR
++
++#define HISI_PTP_SUP_CHK_CNT			32
++/* suppress check window and suppress time, unit: ms */
++#define HISI_PTP_SUP_CHK_THR			10
++#define HISI_PTP_SUP_TIME			100
++
++enum HISI_PTP_TX_MODE {
++	HISI_PTP_CAL_MODE,
++	HISI_PTP_NORMAL_MODE,
++};
++
++struct hisi_ptp_rx {
++	struct list_head node;
++	char name[HISI_PTP_INT_NAME_LEN];
++	struct device *dev;
++	u64 time_comp; /* internal wire time compensation value */
++	int irq;
++	void __iomem *base;
++};
++
++struct hisi_ptp_tx {
++	struct device *dev;
++	void __iomem *base;
++	void __iomem *io_sc_base;
++};
++
++struct hisi_ptp_pdev {
++	struct list_head ptp_rx_list;
++	struct hisi_ptp_tx *ptp_tx;
++	u32 tx_cnt;
++	u32 rx_total;
++	u32 rx_cnt;
++	unsigned long flag;
++	void __iomem *rx_base; /* peri subctl base of chip 0 */
++	u32 irq_cnt;
++	unsigned long last_jiffies; /* record last irq jiffies */
++	struct timer_list suppress_timer;
++	struct ptp_clock *clock;
++	struct ptp_clock_info info;
++	rwlock_t rw_lock;
++	struct dentry *dbgfs_root;
++};
++
++struct hisi_ptp_reg {
++	const char *name;
++	u32 offset;
++};
++
++static struct hisi_ptp_pdev g_ptpdev;
++
++static uint err_threshold = HISI_DEF_ERR_COMP;
++module_param(err_threshold, uint, 0644);
++MODULE_PARM_DESC(err_threshold, "PTP time sync error threshold");
++
++static struct hisi_ptp_pdev *hisi_ptp_get_pdev(struct ptp_clock_info *info)
++{
++	struct hisi_ptp_pdev *ptp =
++		container_of(info, struct hisi_ptp_pdev, info);
++	return ptp;
++}
++
++/* This function should call under rw_lock */
++static void hisi_ptp_disable(struct hisi_ptp_pdev *ptp)
++{
++	struct hisi_ptp_rx *rx;
++	void __iomem *base;
++
++	/* disable tx */
++	if (ptp->ptp_tx && ptp->ptp_tx->base) {
++		base = ptp->ptp_tx->base;
++		writel(0, base + NET_SC_PTP_COUNTER_EN_ADDR);
++	}
++
++	/* disable all totem rx and interrupt */
++	list_for_each_entry(rx, &ptp->ptp_rx_list, node) {
++		base = rx->base;
++		writel(0, base + PERI_SC_RX_SHIFT_EN_ADDR);
++		writel(1, base + PERI_SC_INT_PTP_SYNC_ERR_MASK_ADDR);
++		writel(HISI_PTP_RX_CRC_CLR_AND_DISABLE,
++		       base + PERI_SC_CRC_INT_CONTRL_ADDR);
++	}
++}
++
++/* This function should call under rw_lock */
++static void hisi_ptp_unmask_irq(struct hisi_ptp_pdev *ptp)
++{
++	struct hisi_ptp_rx *rx;
++	void __iomem *base;
++
++	/* clear CRC errors and unmask all totem interrupt */
++	list_for_each_entry(rx, &ptp->ptp_rx_list, node) {
++		base = rx->base;
++		writel(HISI_PTP_RX_CRC_INT_EN,
++		       base + PERI_SC_CRC_INT_CONTRL_ADDR);
++		writel(0, base + PERI_SC_INT_PTP_SYNC_ERR_MASK_ADDR);
++	}
++}
++
++/* This function should call under rw_lock */
++static void hisi_ptp_wait_and_enable(struct hisi_ptp_pdev *ptp)
++{
++#define HISI_PTP_TX_IDLE_WAIT_CNT 20
++	void __iomem *nimbus_base;
++	struct hisi_ptp_rx *rx;
++	void __iomem *base;
++	int delay_cnt = 0;
++
++	if (!ptp->ptp_tx || !ptp->ptp_tx->base)
++		return;
++
++	/* wait for tx idle */
++	nimbus_base = ptp->ptp_tx->base;
++	while (delay_cnt++ < HISI_PTP_TX_IDLE_WAIT_CNT) {
++		u32 dfx_bus0 = readl(nimbus_base + NET_SC_PTP_TX_DFXBUS0_ADDR);
++
++		/* wait bit26:23 to 0 */
++		if ((dfx_bus0 & HISI_PTP_TX_IDLE_MASK) == 0)
++			break;
++
++		udelay(1);
++	}
++
++	/* enable all totem interrupt and rx */
++	list_for_each_entry(rx, &ptp->ptp_rx_list, node) {
++		base = rx->base;
++		writel(1, base + PERI_SC_SYNC_ERR_CLR_ADDR);
++		writel(0, base + PERI_SC_SYNC_ERR_CLR_ADDR);
++		writel(1, base + PERI_SC_INT_PTP_SYNC_ERR_ADDR);
++		writel(1, base + PERI_SC_RX_SHIFT_EN_ADDR);
++	}
++
++	/* enable tx */
++	writel(1, nimbus_base + NET_SC_PTP_COUNTER_EN_ADDR);
++
++	hisi_ptp_unmask_irq(ptp);
++}
++
++/* This function should call under rw_lock */
++static bool hisi_ptp_need_suppress(struct hisi_ptp_pdev *ptp)
++{
++	if (time_is_before_jiffies(ptp->last_jiffies +
++				   msecs_to_jiffies(HISI_PTP_SUP_CHK_THR))) {
++		ptp->last_jiffies = jiffies;
++		ptp->irq_cnt = 0;
++		return false;
++	}
++
++	if (ptp->irq_cnt++ < HISI_PTP_SUP_CHK_CNT)
++		return false;
++
++	return true;
++}
++
++static irqreturn_t hisi_ptp_irq_handle(int irq, void *data)
++{
++	struct hisi_ptp_pdev *ptp = (struct hisi_ptp_pdev *)data;
++
++	dev_dbg(ptp->ptp_tx->dev, "ptp time sync error, irq:%d\n", irq);
++
++	write_lock(&ptp->rw_lock);
++
++	hisi_ptp_disable(ptp);
++
++	if (hisi_ptp_need_suppress(ptp)) {
++		mod_timer(&ptp->suppress_timer,
++			  jiffies + msecs_to_jiffies(HISI_PTP_SUP_TIME));
++		write_unlock(&ptp->rw_lock);
++		return IRQ_HANDLED;
++	}
++
++	hisi_ptp_wait_and_enable(ptp);
++
++	write_unlock(&ptp->rw_lock);
++
++	return IRQ_HANDLED;
++}
++
++static int hisi_ptp_get_rx_resource(struct platform_device *pdev,
++				    struct hisi_ptp_pdev *ptp)
++{
++	struct hisi_ptp_rx *rx;
++	struct resource *peri;
++	unsigned long flags;
++	u32 rx_total = 0;
++	bool is_base_rx;
++	int ret;
++
++	ret = device_property_read_u32(&pdev->dev, "rx_num", &rx_total);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to read rx total property\n");
++		return ret;
++	}
++
++	rx = devm_kzalloc(&pdev->dev, sizeof(struct hisi_ptp_rx), GFP_KERNEL);
++	if (!rx)
++		return -ENOMEM;
++
++	peri = platform_get_resource(pdev, IORESOURCE_MEM, HISI_RES_T_PERI_SC);
++	if (!peri) {
++		dev_err(&pdev->dev, "failed to get rx peri resource\n");
++		return -EINVAL;
++	}
++
++	rx->base = devm_ioremap(&pdev->dev, peri->start, resource_size(peri));
++	if (!rx->base) {
++		dev_err(&pdev->dev, "failed to remap rx peri resource\n");
++		return -ENOMEM;
++	}
++
++	rx->irq = platform_get_irq(pdev, 0);
++	if (rx->irq < 0) {
++		dev_err(&pdev->dev, "failed to get irq, ret = %d\n", rx->irq);
++		return rx->irq;
++	}
++	snprintf(rx->name, HISI_PTP_INT_NAME_LEN, "%s-%d", HISI_PTP_NAME,
++		 rx->irq);
++	ret = devm_request_irq(&pdev->dev, rx->irq, hisi_ptp_irq_handle, 0,
++			       rx->name, ptp);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to request irq(%d), ret = %d\n",
++			rx->irq, ret);
++		return ret;
++	}
++
++	is_base_rx = device_property_present(&pdev->dev, "base_rx");
++
++	rx->dev = &pdev->dev;
++
++	write_lock_irqsave(&ptp->rw_lock, flags);
++
++	if (is_base_rx)
++		ptp->rx_base = rx->base;
++
++	ptp->rx_cnt++;
++
++	/* use the first rx device to init the global rx_total */
++	if (ptp->rx_total == 0)
++		ptp->rx_total = rx_total;
++
++	if (ptp->rx_total != rx_total || ptp->rx_cnt > ptp->rx_total) {
++		write_unlock_irqrestore(&ptp->rw_lock, flags);
++		dev_err(&pdev->dev,
++			"failed to probe rx device, please check the asl file!\n");
++		dev_err(&pdev->dev,
++			"rx_total:%u, current rx_total:%u, rx_cnt:%u\n",
++			ptp->rx_total, rx_total, ptp->rx_cnt);
++
++		return -EINVAL;
++	}
++
++	list_add_tail(&rx->node, &ptp->ptp_rx_list);
++
++	write_unlock_irqrestore(&ptp->rw_lock, flags);
++
++	return 0;
++}
++
++static int hisi_ptp_get_tx_resource(struct platform_device *pdev,
++				    struct hisi_ptp_pdev *ptp)
++{
++	struct hisi_ptp_tx *tx;
++	struct resource *mem;
++	unsigned long flags;
++
++	write_lock_irqsave(&ptp->rw_lock, flags);
++	/* use have only one tx device */
++	if (ptp->tx_cnt) {
++		write_unlock_irqrestore(&ptp->rw_lock, flags);
++		dev_err(&pdev->dev,
++			"failed to probe tx device, more than one tx device found, please check the asl file!\n");
++		return -EINVAL;
++	}
++	write_unlock_irqrestore(&ptp->rw_lock, flags);
++
++	tx = devm_kzalloc(&pdev->dev, sizeof(struct hisi_ptp_tx), GFP_KERNEL);
++	if (!tx)
++		return -ENOMEM;
++
++	mem = platform_get_resource(pdev, IORESOURCE_MEM, HISI_RES_N_NET_SC);
++	if (!mem) {
++		dev_err(&pdev->dev, "failed to get tx net sc resource\n");
++		return -EINVAL;
++	}
++
++	tx->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
++	if (!tx->base) {
++		dev_err(&pdev->dev, "failed to remap tx net sc resource\n");
++		return -ENOMEM;
++	}
++
++	mem = platform_get_resource(pdev, IORESOURCE_MEM, HISI_RES_N_IO_SC);
++	if (!mem) {
++		dev_err(&pdev->dev, "failed to get tx nimbus io sc resource\n");
++		return -EINVAL;
++	}
++
++	tx->io_sc_base = devm_ioremap(&pdev->dev, mem->start,
++				      resource_size(mem));
++	if (!tx->io_sc_base) {
++		dev_err(&pdev->dev, "failed to remap tx nimbus io resource\n");
++		return -ENOMEM;
++	}
++
++	tx->dev = &pdev->dev;
++
++	write_lock_irqsave(&ptp->rw_lock, flags);
++	ptp->tx_cnt++;
++	ptp->ptp_tx = tx;
++	write_unlock_irqrestore(&ptp->rw_lock, flags);
++
++	return 0;
++}
++
++static void hisi_ptp_cal_time_start(struct hisi_ptp_pdev *ptp)
++{
++	void __iomem *io_sc_base;
++	struct hisi_ptp_rx *rx;
++	void __iomem *base;
++
++	/* config all rx to enter calculation mode. */
++	list_for_each_entry(rx, &ptp->ptp_rx_list, node) {
++		base = rx->base;
++		writel(1, base + PERI_SC_PTP_RESET_REQ);
++		writel(1, base + PERI_SC_PTP_RESET_DREQ);
++		writel(0, base + PERI_SC_LOCAL_TIMER_COMP_HIGH_ADDR);
++		writel(0, base + PERI_SC_LOCAL_TIMER_COMP_LOW_ADDR);
++		writel(1, base + PERI_SC_CRC_EN_ADDR);
++		writel(0, base + PERI_SC_LOCAL_CNT_EN_ADDR);
++		writel(1, base + PERI_SC_RX_SHIFT_EN_ADDR);
++	}
++
++	/* config tx to enter calculation mode. */
++	base = ptp->ptp_tx->base;
++	io_sc_base = ptp->ptp_tx->io_sc_base;
++	writel(HISI_PTP_CAL_MODE, io_sc_base + IO_SC_PTP_NORMAL_MODE_EN);
++	writel(HISI_PTP_CAL_MODE, base + NET_SC_PTP_NORMAL_MODE_EN);
++
++	writel(HISI_DEF_BAUD, io_sc_base + IO_SC_PTP_BAUD_VALUE_ADDR);
++	writel(1, io_sc_base + IO_SC_PTP_COUNTER_EN_ADDR);
++	writel(0, io_sc_base + IO_SC_PTP_WIRE_DELAY_CAL_EN);
++	writel(1, io_sc_base + IO_SC_PTP_WIRE_DELAY_CAL_EN);
++}
++
++static void hisi_ptp_cal_time_get(struct hisi_ptp_pdev *ptp)
++{
++#define HISI_PTP_MAX_WAIT_CNT 60
++	struct hisi_ptp_rx *rx;
++	void __iomem *base;
++	int cnt;
++	u32 rd_l;
++	u32 rd_h;
++	u32 td_l;
++	u32 td_h;
++	u64 rd;
++	u64 td;
++
++	list_for_each_entry(rx, &ptp->ptp_rx_list, node) {
++		base = rx->base;
++		rx->time_comp = HISI_DEF_TIME_COMP;
++
++		cnt = 0;
++		do {
++			if (readl(base + PERI_SC_CAPTURE_VLD) == 0) {
++				mdelay(1);
++				continue;
++			}
++
++			rd_h = readl(base +
++				     PERI_SC_CAPTURE_SYSTEM_COUNTER_BIN_HIGH);
++			rd_l = readl(base +
++				     PERI_SC_CAPTURE_SYSTEM_COUNTER_BIN_LOW);
++			td_h = readl(base + PERI_SC_CAPTURE_PTP_TIME_COMP_HIGH);
++			td_l = readl(base + PERI_SC_CAPTURE_PTP_TIME_COMP_LOW);
++
++			rd = (u64)rd_h << 32 | rd_l;
++			td = (u64)td_h << 32 | td_l;
++
++			if (!rd || !td || rd < td) {
++				mdelay(1);
++				continue;
++			}
++
++			rx->time_comp = rd - td;
++			break;
++		} while (cnt++ <= HISI_PTP_MAX_WAIT_CNT);
++	}
++}
++
++static void hisi_ptp_cal_time_end(struct hisi_ptp_pdev *ptp)
++{
++	void __iomem *io_sc_base;
++	struct hisi_ptp_rx *rx;
++	void __iomem *base;
++
++	/* config all rx to exit calculation mode. */
++	list_for_each_entry(rx, &ptp->ptp_rx_list, node) {
++		base = rx->base;
++		writel(0, base + PERI_SC_RX_SHIFT_EN_ADDR);
++	}
++
++	/* config tx to exit calculation mode. */
++	base = ptp->ptp_tx->base;
++	io_sc_base = ptp->ptp_tx->io_sc_base;
++
++	writel(0, io_sc_base + IO_SC_PTP_COUNTER_EN_ADDR);
++	writel(HISI_PTP_NORMAL_MODE, io_sc_base + IO_SC_PTP_NORMAL_MODE_EN);
++	writel(HISI_PTP_NORMAL_MODE, base + NET_SC_PTP_NORMAL_MODE_EN);
++}
++
++/* This function should call under rw_lock */
++static void hisi_ptp_cal_time_comp(struct hisi_ptp_pdev *ptp)
++{
++	hisi_ptp_cal_time_start(ptp);
++	hisi_ptp_cal_time_get(ptp);
++	hisi_ptp_cal_time_end(ptp);
++}
++
++/* This function should call under rw_lock */
++static void hisi_ptp_peri_rx_init(struct hisi_ptp_pdev *ptp)
++{
++	struct hisi_ptp_rx *rx;
++	void __iomem *base;
++
++	list_for_each_entry(rx, &ptp->ptp_rx_list, node) {
++		base = rx->base;
++		writel(1, base + PERI_SC_CRC_EN_ADDR);
++		writel(upper_32_bits(rx->time_comp),
++		       base + PERI_SC_LOCAL_TIMER_COMP_HIGH_ADDR);
++		writel(lower_32_bits(rx->time_comp),
++		       base + PERI_SC_LOCAL_TIMER_COMP_LOW_ADDR);
++		writel(err_threshold,
++		       base + PERI_SC_SYNC_ERR_COMP_LOW_ADDR);
++		writel(1, base + PERI_SC_CRC_INT_CONTRL_ADDR);
++		writel(0, base + PERI_SC_SYNC_ERR_CLR_ADDR);
++		writel(1, base + PERI_SC_LOCAL_CNT_EN_ADDR);
++		writel(1, base + PERI_SC_RX_SHIFT_EN_ADDR);
++	}
++}
++
++/* This function should call under rw_lock */
++static void hisi_ptp_net_tx_init(struct hisi_ptp_pdev *ptp)
++{
++	void __iomem *base;
++
++	base = ptp->ptp_tx->base;
++	writel(1, base + NET_SC_PTP_COUNTER_EN_ADDR);
++}
++
++static int hisi_ptp_adjfine(struct ptp_clock_info *ptp_info, long delta)
++{
++	return -EOPNOTSUPP;
++}
++
++static int hisi_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
++{
++	return -EOPNOTSUPP;
++}
++
++static int hisi_ptp_settime(struct ptp_clock_info *ptp_info,
++			    const struct timespec64 *ts)
++{
++	return -EOPNOTSUPP;
++}
++
++static int hisi_ptp_gettime(struct ptp_clock_info *ptp_info,
++			     struct timespec64 *ts,
++			     struct ptp_system_timestamp *sts)
++{
++	struct hisi_ptp_pdev *ptp = hisi_ptp_get_pdev(ptp_info);
++	unsigned long flags;
++	u32 hi = UINT_MAX;
++	u32 lo = UINT_MAX;
++	u64 ns;
++
++	read_lock_irqsave(&ptp->rw_lock, flags);
++
++	if (ptp->rx_base) {
++		hi = readl(ptp->rx_base + PERI_SC_LOCAL_TIME_HIGH_ADDR);
++		lo = readl(ptp->rx_base + PERI_SC_LOCAL_TIME_LOW_ADDR);
++	}
++
++	read_unlock_irqrestore(&ptp->rw_lock, flags);
++
++	ns = (u64)hi * NSEC_PER_SEC + lo;
++	*ts = ns_to_timespec64(ns);
++
++	return 0;
++}
++
++static int hisi_ptp_create_clock(struct hisi_ptp_pdev *ptp)
++{
++	dev_info(ptp->ptp_tx->dev, "register ptp clock\n");
++
++	snprintf(ptp->info.name, PTP_CLOCK_NAME_LEN, "%s", HISI_PTP_NAME);
++	ptp->info.owner = THIS_MODULE;
++	ptp->info.adjfine = hisi_ptp_adjfine;
++	ptp->info.adjtime = hisi_ptp_adjtime;
++	ptp->info.settime64 = hisi_ptp_settime;
++	ptp->info.gettimex64 = hisi_ptp_gettime;
++	ptp->clock = ptp_clock_register(&ptp->info, ptp->ptp_tx->dev);
++	if (IS_ERR(ptp->clock)) {
++		dev_err(ptp->ptp_tx->dev,
++			"failed to register ptp clock, ret = %ld\n",
++			PTR_ERR(ptp->clock));
++		return PTR_ERR(ptp->clock);
++	}
++
++	return 0;
++}
++
++static void hisi_ptp_timer(struct timer_list *t)
++{
++	struct hisi_ptp_pdev *ptp = from_timer(ptp, t, suppress_timer);
++	unsigned long flags;
++
++	write_lock_irqsave(&ptp->rw_lock, flags);
++
++	dev_dbg(ptp->ptp_tx->dev, "ptp timer timeout handler.\n");
++
++	ptp->last_jiffies = jiffies;
++	ptp->irq_cnt = 0;
++
++	hisi_ptp_wait_and_enable(ptp);
++
++	write_unlock_irqrestore(&ptp->rw_lock, flags);
++}
++
++static int hisi_ptp_probe(struct platform_device *pdev)
++{
++	struct hisi_ptp_pdev *ptp = &g_ptpdev;
++	unsigned long flags;
++	const char *type;
++	int ret;
++
++	dev_info(&pdev->dev, "ptp probe start\n");
++
++	ret = device_property_read_string(&pdev->dev, "type", &type);
++	if (ret) {
++		dev_err(&pdev->dev, "failed to read device type, ret = %d\n",
++			ret);
++		return ret;
++	}
++
++	if (!memcmp(type, "rx", strlen("rx"))) {
++		ret = hisi_ptp_get_rx_resource(pdev, ptp);
++	} else if (!memcmp(type, "tx", strlen("tx"))) {
++		ret = hisi_ptp_get_tx_resource(pdev, ptp);
++	} else {
++		dev_err(&pdev->dev,
++			"failed to probe unknown device, type: %s\n",
++			type);
++		ret = -EINVAL;
++	}
++	if (ret)
++		return ret;
++
++	write_lock_irqsave(&ptp->rw_lock, flags);
++
++	if (ptp->rx_total == 0 || ptp->rx_total != ptp->rx_cnt ||
++	    ptp->tx_cnt != 1) {
++		write_unlock_irqrestore(&ptp->rw_lock, flags);
++		dev_info(&pdev->dev,
++			 "waiting for devices...rx total:%u, now:%u. tx total:1, now:%u\n",
++			 ptp->rx_total, ptp->rx_cnt, ptp->tx_cnt);
++		return 0;
++	}
++
++	if (!ptp->rx_base) {
++		write_unlock_irqrestore(&ptp->rw_lock, flags);
++		dev_err(&pdev->dev,
++			"failed to probe, no base rx device, please check the asl file!\n");
++		return -EINVAL;
++	}
++
++	hisi_ptp_disable(ptp);
++	hisi_ptp_cal_time_comp(ptp);
++	hisi_ptp_peri_rx_init(ptp);
++	hisi_ptp_net_tx_init(ptp);
++	hisi_ptp_unmask_irq(ptp);
++
++	write_unlock_irqrestore(&ptp->rw_lock, flags);
++
++	ret = hisi_ptp_create_clock(ptp);
++	if (ret) {
++		write_lock_irqsave(&ptp->rw_lock, flags);
++		hisi_ptp_disable(ptp);
++		write_unlock_irqrestore(&ptp->rw_lock, flags);
++		return ret;
++	}
++
++	set_bit(HISI_PTP_INIT_DONE, &ptp->flag);
++
++	dev_info(&pdev->dev, "ptp probe end\n");
++	return 0;
++}
++
++static int hisi_ptp_remove(struct platform_device *pdev)
++{
++	struct hisi_ptp_pdev *ptp = &g_ptpdev;
++	struct hisi_ptp_rx *rx;
++	unsigned long flags;
++
++	if (test_and_clear_bit(HISI_PTP_INIT_DONE, &ptp->flag)) {
++		ptp_clock_unregister(ptp->clock);
++		ptp->clock = NULL;
++
++		write_lock_irqsave(&ptp->rw_lock, flags);
++		hisi_ptp_disable(ptp);
++		write_unlock_irqrestore(&ptp->rw_lock, flags);
++
++		dev_info(&pdev->dev, "unregister ptp clock\n");
++	}
++
++	write_lock_irqsave(&ptp->rw_lock, flags);
++	if (ptp->ptp_tx && ptp->ptp_tx->dev == &pdev->dev) {
++		ptp->tx_cnt--;
++		ptp->ptp_tx = NULL;
++		dev_info(&pdev->dev, "remove tx ptp device\n");
++	} else {
++		list_for_each_entry(rx, &ptp->ptp_rx_list, node) {
++			if (rx->dev == &pdev->dev) {
++				ptp->rx_cnt--;
++				list_del(&rx->node);
++				dev_info(&pdev->dev, "remove rx ptp device\n");
++				break;
++			}
++		}
++	}
++	write_unlock_irqrestore(&ptp->rw_lock, flags);
++
++	return 0;
++}
++
++static const struct acpi_device_id hisi_ptp_acpi_match[] = {
++	{ "HISI0411", 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(acpi, hisi_ptp_acpi_match);
++
++static struct platform_driver hisi_ptp_driver = {
++	.probe = hisi_ptp_probe,
++	.remove = hisi_ptp_remove,
++	.driver	= {
++		.name = HISI_PTP_NAME,
++		.acpi_match_table = ACPI_PTR(hisi_ptp_acpi_match),
++	},
++};
++
++static ssize_t hisi_ptp_dbg_read_state(struct file *filp, char __user *buf,
++				       size_t cnt, loff_t *ppos)
++{
++	struct hisi_ptp_pdev *ptp = filp->private_data;
++	struct hisi_ptp_rx *rx;
++	unsigned long flags;
++	ssize_t size = 0;
++	char *read_buf;
++	int pos = 0;
++	int len;
++
++	if (*ppos < 0)
++		return -EINVAL;
++	if (cnt <= 0)
++		return 0;
++	if (!access_ok(buf, cnt))
++		return -EFAULT;
++
++	read_buf = kvzalloc(HISI_PTP_DBGFS_STS_LEN, GFP_KERNEL);
++	if (!read_buf)
++		return -ENOMEM;
++
++	len = HISI_PTP_DBGFS_STS_LEN;
++
++	write_lock_irqsave(&ptp->rw_lock, flags);
++	pos += scnprintf(read_buf + pos, len - pos, "error threshold: %#x\n",
++			 err_threshold);
++	pos += scnprintf(read_buf + pos, len - pos, "tx count: %u\n",
++			 ptp->tx_cnt);
++	pos += scnprintf(read_buf + pos, len - pos, "rx total: %u\n",
++			 ptp->rx_total);
++	pos += scnprintf(read_buf + pos, len - pos, "rx count: %u\n",
++			 ptp->rx_cnt);
++	pos += scnprintf(read_buf + pos, len - pos, "irq count: %u\n",
++			 ptp->irq_cnt);
++	pos += scnprintf(read_buf + pos, len - pos, "irq last jiffies: %lu\n",
++			 ptp->last_jiffies);
++
++	list_for_each_entry(rx, &ptp->ptp_rx_list, node) {
++		pos += scnprintf(read_buf + pos, len - pos, "name: %s\n",
++				 rx->name);
++		pos += scnprintf(read_buf + pos, len - pos, "time comp: %#llx\n",
++				 rx->time_comp);
++		pos += scnprintf(read_buf + pos, len - pos, "irq: %d\n",
++				 rx->irq);
++	}
++	write_unlock_irqrestore(&ptp->rw_lock, flags);
++
++	size = simple_read_from_buffer(buf, cnt, ppos, read_buf,
++				       strlen(read_buf));
++
++	kvfree(read_buf);
++
++	return size;
++}
++
++static const struct hisi_ptp_reg hisi_ptp_tx_reg[] = {
++	{"NET_SC_PTP_BAUD_VALUE_ADDR  ",
++	 NET_SC_PTP_BAUD_VALUE_ADDR},
++	{"NET_SC_PTP_COUNTER_EN_ADDR  ",
++	 NET_SC_PTP_COUNTER_EN_ADDR},
++	{"NET_SC_PTP_NORMAL_MODE_EN   ",
++	 NET_SC_PTP_NORMAL_MODE_EN},
++	{"NET_SC_PTP_WIRE_DELAY_CAL_EN",
++	 NET_SC_PTP_WIRE_DELAY_CAL_EN},
++	{"NET_SC_SAMPLE_DELAY_CFG_ADDR",
++	 NET_SC_SAMPLE_DELAY_CFG_ADDR},
++	{"NET_SC_PTP_TX_DFXBUS0_ADDR  ",
++	 NET_SC_PTP_TX_DFXBUS0_ADDR},
++	{"NET_SC_PTP_TX_DFXBUS1_ADDR  ",
++	 NET_SC_PTP_TX_DFXBUS1_ADDR},
++	{"NET_SC_PTP_TX_DFXBUS2_ADDR  ",
++	 NET_SC_PTP_TX_DFXBUS2_ADDR},
++	{"NET_SC_PTP_TX_DFXBUS3_ADDR  ",
++	 NET_SC_PTP_TX_DFXBUS3_ADDR}
++};
++
++static const struct hisi_ptp_reg hisi_ptp_tx_io_reg[] = {
++	{"IO_SC_PTP_BAUD_VALUE_ADDR  ",
++	 IO_SC_PTP_BAUD_VALUE_ADDR},
++	{"IO_SC_PTP_COUNTER_EN_ADDR  ",
++	 IO_SC_PTP_COUNTER_EN_ADDR},
++	{"IO_SC_PTP_NORMAL_MODE_EN   ",
++	 IO_SC_PTP_NORMAL_MODE_EN},
++	{"IO_SC_PTP_WIRE_DELAY_CAL_EN",
++	 IO_SC_PTP_WIRE_DELAY_CAL_EN},
++	{"IO_SC_SAMPLE_DELAY_CFG_ADDR",
++	 IO_SC_SAMPLE_DELAY_CFG_ADDR},
++	{"IO_SC_PTP_TX_DFXBUS0_ADDR  ",
++	 IO_SC_PTP_TX_DFXBUS0_ADDR},
++	{"IO_SC_PTP_TX_DFXBUS1_ADDR  ",
++	 IO_SC_PTP_TX_DFXBUS1_ADDR},
++	{"IO_SC_PTP_TX_DFXBUS2_ADDR  ",
++	 IO_SC_PTP_TX_DFXBUS2_ADDR},
++	{"IO_SC_PTP_TX_DFXBUS3_ADDR  ",
++	 IO_SC_PTP_TX_DFXBUS3_ADDR}
++};
++
++static const struct hisi_ptp_reg hisi_ptp_rx_reg[] = {
++	{"PERI_SC_LOCAL_TIMER_COMP_HIGH_ADDR     ",
++	 PERI_SC_LOCAL_TIMER_COMP_HIGH_ADDR},
++	{"PERI_SC_LOCAL_TIMER_COMP_LOW_ADDR      ",
++	 PERI_SC_LOCAL_TIMER_COMP_LOW_ADDR},
++	{"PERI_SC_BAUD_VALUE_ADDR                ",
++	 PERI_SC_BAUD_VALUE_ADDR},
++	{"PERI_SC_LOCAL_CNT_EN_ADDR              ",
++	 PERI_SC_LOCAL_CNT_EN_ADDR},
++	{"PERI_SC_SYNC_ERR_COMP_HIGH_ADDR        ",
++	 PERI_SC_SYNC_ERR_COMP_HIGH_ADDR},
++	{"PERI_SC_SYNC_ERR_COMP_LOW_ADDR         ",
++	 PERI_SC_SYNC_ERR_COMP_LOW_ADDR},
++	{"PERI_SC_CRC_EN_ADDR                    ",
++	 PERI_SC_CRC_EN_ADDR},
++	{"PERI_SC_ONE_CYCLE_NUM_ADDR             ",
++	 PERI_SC_ONE_CYCLE_NUM_ADDR},
++	{"PERI_SC_SYNC_ERR_CLR_ADDR              ",
++	 PERI_SC_SYNC_ERR_CLR_ADDR},
++	{"PERI_SC_RX_SHIFT_EN_ADDR               ",
++	 PERI_SC_RX_SHIFT_EN_ADDR},
++	{"PERI_SC_TIMEL_CY_NUM_ADDR              ",
++	 PERI_SC_TIMEL_CY_NUM_ADDR},
++	{"PERI_SC_INT_PTP_SYNC_ERR_ADDR          ",
++	 PERI_SC_INT_PTP_SYNC_ERR_ADDR},
++	{"PERI_SC_INT_PTP_SYNC_ERR_MASK_ADDR     ",
++	 PERI_SC_INT_PTP_SYNC_ERR_MASK_ADDR},
++	{"PERI_SC_INT_ORIGIN                     ",
++	 PERI_SC_INT_ORIGIN},
++	{"PERI_SC_CRC_ERR_COUNT                  ",
++	 PERI_SC_CRC_ERR_COUNT},
++	{"PERI_SC_CRC_INT_CONTRL_ADDR            ",
++	 PERI_SC_CRC_INT_CONTRL_ADDR},
++	{"PERI_SC_CAPTURE_PTP_TIME_COMP_HIGH     ",
++	 PERI_SC_CAPTURE_PTP_TIME_COMP_HIGH},
++	{"PERI_SC_CAPTURE_PTP_TIME_COMP_LOW      ",
++	 PERI_SC_CAPTURE_PTP_TIME_COMP_LOW},
++	{"PERI_SC_CAPTURE_SYSTEM_COUNTER_BIN_HIGH",
++	 PERI_SC_CAPTURE_SYSTEM_COUNTER_BIN_HIGH},
++	{"PERI_SC_CAPTURE_SYSTEM_COUNTER_BIN_LOW ",
++	 PERI_SC_CAPTURE_SYSTEM_COUNTER_BIN_LOW},
++	{"PERI_SC_CAPTURE_VLD                    ",
++	 PERI_SC_CAPTURE_VLD},
++	{"PERI_SC_LOCAL_TIME_LOW_ADDR            ",
++	 PERI_SC_LOCAL_TIME_LOW_ADDR},
++	{"PERI_SC_LOCAL_TIME_HIGH_ADDR           ",
++	 PERI_SC_LOCAL_TIME_HIGH_ADDR}
++};
++
++static void hisi_ptp_dump_reg(void __iomem *base,
++			      const struct hisi_ptp_reg *reg, int reg_len,
++			      char *buf, int len, int *pos)
++{
++	int i;
++
++	for (i = 0; i < reg_len; i++)
++		*pos += scnprintf(buf + *pos, len - *pos, "%s : 0x%08x\n",
++				  reg[i].name, readl(base + reg[i].offset));
++}
++
++static ssize_t hisi_ptp_dbg_read_reg(struct file *filp, char __user *buf,
++				     size_t cnt, loff_t *ppos)
++{
++	struct hisi_ptp_pdev *ptp = filp->private_data;
++	struct hisi_ptp_rx *rx;
++	unsigned long flags;
++	ssize_t size = 0;
++	char *read_buf;
++	int pos = 0;
++	int len;
++
++	if (*ppos < 0)
++		return -EINVAL;
++	if (cnt <= 0)
++		return 0;
++	if (!access_ok(buf, cnt))
++		return -EFAULT;
++
++	read_buf = kvzalloc(HISI_PTP_DBGFS_REG_LEN, GFP_KERNEL);
++	if (!read_buf)
++		return -ENOMEM;
++
++	len = HISI_PTP_DBGFS_REG_LEN;
++
++	write_lock_irqsave(&ptp->rw_lock, flags);
++	if (ptp->ptp_tx && ptp->ptp_tx->base)
++		hisi_ptp_dump_reg(ptp->ptp_tx->base, hisi_ptp_tx_reg,
++				  ARRAY_SIZE(hisi_ptp_tx_reg),
++				  read_buf, len, &pos);
++
++	if (ptp->ptp_tx && ptp->ptp_tx->io_sc_base)
++		hisi_ptp_dump_reg(ptp->ptp_tx->io_sc_base, hisi_ptp_tx_io_reg,
++				  ARRAY_SIZE(hisi_ptp_tx_io_reg),
++				  read_buf, len, &pos);
++
++	list_for_each_entry(rx, &ptp->ptp_rx_list, node)
++		hisi_ptp_dump_reg(rx->base, hisi_ptp_rx_reg,
++				  ARRAY_SIZE(hisi_ptp_rx_reg),
++				  read_buf, len, &pos);
++
++	write_unlock_irqrestore(&ptp->rw_lock, flags);
++
++	size = simple_read_from_buffer(buf, cnt, ppos, read_buf,
++				       strlen(read_buf));
++
++	kvfree(read_buf);
++
++	return size;
++}
++
++static const struct file_operations hisi_ptp_dbg_state_ops = {
++	.owner = THIS_MODULE,
++	.open  = simple_open,
++	.read  = hisi_ptp_dbg_read_state,
++};
++
++static const struct file_operations hisi_ptp_dbg_reg_ops = {
++	.owner = THIS_MODULE,
++	.open  = simple_open,
++	.read  = hisi_ptp_dbg_read_reg,
++};
++
++static void hisi_ptp_dbgfs_init(struct hisi_ptp_pdev *ptp)
++{
++	ptp->dbgfs_root = debugfs_create_dir(HISI_PTP_NAME, NULL);
++	debugfs_create_file("state", 0400, ptp->dbgfs_root, ptp,
++			    &hisi_ptp_dbg_state_ops);
++	debugfs_create_file("reg", 0400, ptp->dbgfs_root, ptp,
++			    &hisi_ptp_dbg_reg_ops);
++}
++
++static void hisi_ptp_dbgfs_uninit(struct hisi_ptp_pdev *ptp)
++{
++	debugfs_remove_recursive(ptp->dbgfs_root);
++}
++
++static int __init hisi_ptp_module_init(void)
++{
++	struct hisi_ptp_pdev *ptp = &g_ptpdev;
++	int ret;
++
++	memset(ptp, 0, sizeof(struct hisi_ptp_pdev));
++	rwlock_init(&ptp->rw_lock);
++	INIT_LIST_HEAD(&ptp->ptp_rx_list);
++
++	timer_setup(&ptp->suppress_timer, hisi_ptp_timer, 0);
++
++	ret = platform_driver_register(&hisi_ptp_driver);
++	if (ret) {
++		del_timer_sync(&ptp->suppress_timer);
++		pr_err("failed to register ptp platform driver, ret = %d\n",
++		       ret);
++		return ret;
++	}
++
++	hisi_ptp_dbgfs_init(ptp);
++
++	pr_info("hisi ptp platform driver inited, version: %s\n",
++		HISI_PTP_VERSION);
++
++	return 0;
++}
++module_init(hisi_ptp_module_init);
++
++static void __exit hisi_ptp_module_exit(void)
++{
++	struct hisi_ptp_pdev *ptp = &g_ptpdev;
++
++	pr_info("hisi ptp platform driver exit\n");
++
++	hisi_ptp_dbgfs_uninit(ptp);
++
++	platform_driver_unregister(&hisi_ptp_driver);
++
++	if (ptp->suppress_timer.function)
++		del_timer_sync(&ptp->suppress_timer);
++
++	memset(ptp, 0, sizeof(struct hisi_ptp_pdev));
++}
++module_exit(hisi_ptp_module_exit);
++
++MODULE_DESCRIPTION("HiSilicon PTP driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION(HISI_PTP_VERSION);
+-- 
+2.34.1
+
diff --git a/patches/0623-ptp-deprecate-gettime64-in-favor-of-gettimex64.patch b/patches/0623-ptp-deprecate-gettime64-in-favor-of-gettimex64.patch
new file mode 100644
index 0000000..0912a60
--- /dev/null
+++ b/patches/0623-ptp-deprecate-gettime64-in-favor-of-gettimex64.patch
@@ -0,0 +1,111 @@
+From 9a0a8fc9785f4947c4e72cd3088ef43521900ddc Mon Sep 17 00:00:00 2001
+From: Miroslav Lichvar <mlichvar@redhat.com>
+Date: Fri, 9 Nov 2018 11:14:45 +0100
+Subject: [PATCH 262/283] ptp: deprecate gettime64() in favor of gettimex64()
+
+mainline inclusion
+from mainline-v5.0-rc1
+commit 916444df305ef5b8a7d824aac7dd2aeba3a4db3b
+category: feature
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=916444df305ef5b8a7d824aac7dd2aeba3a4db3b
+
+--------------------------------
+
+When a driver provides gettimex64(), use it in the PTP_SYS_OFFSET ioctl
+and POSIX clock's gettime() instead of gettime64(). Drivers should
+provide only one of the functions.
+
+Cc: Richard Cochran <richardcochran@gmail.com>
+Cc: Jacob Keller <jacob.e.keller@intel.com>
+Signed-off-by: Miroslav Lichvar <mlichvar@redhat.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 7 +++++--
+ drivers/ptp/ptp_chardev.c                       | 5 ++++-
+ drivers/ptp/ptp_clock.c                         | 5 ++++-
+ include/linux/ptp_clock_kernel.h                | 2 ++
+ 4 files changed, 15 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 5b7bf29f0934..56dbad4f85a6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -2054,7 +2054,8 @@ netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
+ 	struct hns3_enet_ring *ring = &priv->ring[skb->queue_mapping];
+ 	struct hns3_desc_cb *desc_cb = &ring->desc_cb[ring->next_to_use];
+ 	struct netdev_queue *dev_queue;
+-	int pre_ntu, ret;
++	int pre_ntu, next_to_use_head;
++	int ret;
+ 
+ 	/* Hardware can only handle short frames above 32 bytes */
+ 	if (skb_put_padto(skb, HNS3_MIN_TX_LEN)) {
+@@ -2119,6 +2120,9 @@ netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev)
+ 
+ 	return NETDEV_TX_OK;
+ 
++fill_err:
++	hns3_clear_desc(ring, next_to_use_head);
++
+ out_err_tx_ok:
+ 	dev_kfree_skb_any(skb);
+ 	hns3_tx_doorbell(ring, 0, !netdev_xmit_more());
+@@ -4879,7 +4883,6 @@ static void hns3_state_init(struct hnae3_handle *handle)
+ static int hns3_client_init(struct hnae3_handle *handle)
+ {
+ 	struct pci_dev *pdev = handle->pdev;
+-	struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
+ 	u16 alloc_tqps, max_rss_size;
+ 	struct hns3_nic_priv *priv;
+ 	struct net_device *netdev;
+diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c
+index 796eeffdf93b..28e589b794bb 100644
+--- a/drivers/ptp/ptp_chardev.c
++++ b/drivers/ptp/ptp_chardev.c
+@@ -228,7 +228,10 @@ long ptp_ioctl(struct posix_clock *pc, unsigned int cmd, unsigned long arg)
+ 			pct->sec = ts.tv_sec;
+ 			pct->nsec = ts.tv_nsec;
+ 			pct++;
+-			err = ptp->info->gettime64(ptp->info, &ts);
++			if (ops->gettimex64)
++				err = ops->gettimex64(ops, &ts, NULL);
++			else
++				err = ops->gettime64(ops, &ts);
+ 			if (err)
+ 				goto out;
+ 			pct->sec = ts.tv_sec;
+diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c
+index e232233beb8f..e865cfdef360 100644
+--- a/drivers/ptp/ptp_clock.c
++++ b/drivers/ptp/ptp_clock.c
+@@ -117,7 +117,10 @@ static int ptp_clock_gettime(struct posix_clock *pc, struct timespec64 *tp)
+ 	struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+ 	int err;
+ 
+-	err = ptp->info->gettime64(ptp->info, tp);
++	if (ptp->info->gettimex64)
++		err = ptp->info->gettimex64(ptp->info, tp, NULL);
++	else
++		err = ptp->info->gettime64(ptp->info, tp);
+ 	return err;
+ }
+ 
+diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h
+index cd0570c2b501..9d7afc71a2e7 100644
+--- a/include/linux/ptp_clock_kernel.h
++++ b/include/linux/ptp_clock_kernel.h
+@@ -82,6 +82,8 @@ struct ptp_system_timestamp {
+  *            parameter delta: Desired change in nanoseconds.
+  *
+  * @gettime64:  Reads the current time from the hardware clock.
++ *              This method is deprecated.  New drivers should implement
++ *              the @gettimex64 method instead.
+  *              parameter ts: Holds the result.
+  *
+  * @getcrosststamp:  Reads the current time from the hardware clock and
+-- 
+2.34.1
+
diff --git a/patches/0624-NIC-hns3-fix-kabi.patch b/patches/0624-NIC-hns3-fix-kabi.patch
new file mode 100644
index 0000000..e17c2ac
--- /dev/null
+++ b/patches/0624-NIC-hns3-fix-kabi.patch
@@ -0,0 +1,132 @@
+From 2f15bd4d4c16f498e7086581aa7a24757368bdf0 Mon Sep 17 00:00:00 2001
+From: Xiaodong Li <lixiaodong67@huawei.com>
+Date: Sun, 5 Nov 2023 17:22:16 +0800
+Subject: [PATCH 263/283] NIC: hns3: fix kabi
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+--------------------------------
+
+Remove unnecessary kabi issues from hnae3. h file and fix them.
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h | 32 +--------------------
+ 1 file changed, 1 insertion(+), 31 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index e085e384501c..3658c2b7247c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -285,9 +285,6 @@ enum hnae3_reset_type {
+ 	HNAE3_FUNC_RESET,
+ 	HNAE3_GLOBAL_RESET,
+ 	HNAE3_IMP_RESET,
+-#ifdef __GENKSYMS__
+-	HNAE3_UNKNOWN_RESET,
+-#endif
+ 	HNAE3_NONE_RESET,
+ 	HNAE3_MAX_RESET,
+ };
+@@ -429,11 +426,9 @@ struct hnae3_ae_dev {
+ 	struct list_head node;
+ 	u32 flag;
+ 	unsigned long hw_err_reset_req;
+-#ifndef __GENKSYMS__
+ 	struct hnae3_dev_specs dev_specs;
+ 	u32 dev_version;
+ 	DECLARE_BITMAP(caps, HNAE3_DEV_CAPS_MAX_NUM);
+-#endif
+ 	void *priv;
+ };
+ 
+@@ -623,18 +618,11 @@ struct hnae3_ae_ops {
+ 	int (*client_start)(struct hnae3_handle *handle);
+ 	void (*client_stop)(struct hnae3_handle *handle);
+ 	int (*get_status)(struct hnae3_handle *handle);
+-#ifndef __GENKSYMS__
+ 	void (*get_ksettings_an_result)(struct hnae3_handle *handle,
+ 					u8 *auto_neg, u32 *speed, u8 *duplex,
+ 					u32 *lane_num);
+ 	int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
+ 				   u8 duplex, u8 lane_num);
+-#else
+-	void (*get_ksettings_an_result)(struct hnae3_handle *handle,
+-					u8 *auto_neg, u32 *speed, u8 *duplex);
+-	int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
+-				   u8 duplex);
+-#endif
+ 
+ 	void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
+ 			       u8 *module_type);
+@@ -821,6 +809,7 @@ struct hnae3_ae_ops {
+ 		       struct ethtool_wolinfo *wol);
+ 	int (*priv_ops)(struct hnae3_handle *handle, int opcode,
+ 			void *data, size_t length);
++
+ /* Notice! If the function is not for test, the definition must before
+  * CONFIG_HNS3_TEST! Because RoCE will use this head file, and it won't
+  * set CONFIG_HNS3_TEST, that may cause RoCE calling the wrong function.
+@@ -829,8 +818,6 @@ struct hnae3_ae_ops {
+ 	int (*send_cmdq)(struct hnae3_handle *handle, void *data, int num);
+ 	int (*test_cmdq)(struct hnae3_handle *handle, void *data, int *len);
+ 	int (*ecc_handle)(struct hnae3_ae_dev *ae_dev);
+-	int (*priv_ops)(struct hnae3_handle *handle, int opcode,
+-			void *data, int length);
+ 	void (*ext_init)(struct hnae3_handle *handle);
+ 	void (*ext_uninit)(struct hnae3_handle *handle);
+ 	void (*ext_reset_done)(struct hnae3_handle *handle);
+@@ -895,9 +882,7 @@ struct hnae3_knic_private_info {
+ 	u16 rx_buf_len;
+ 	u16 num_tx_desc;
+ 	u16 num_rx_desc;
+-#ifndef __GENKSYMS__
+ 	u32 tx_spare_buf_size;
+-#endif
+ 
+ 	struct hnae3_tc_info tc_info;
+ 	u8 tc_map_mode;
+@@ -925,17 +910,7 @@ struct hnae3_roce_private_info {
+ 	unsigned long instance_state;
+ 	unsigned long state;
+ };
+-#ifdef __GENKSYMS__
+-struct hnae3_unic_private_info {
+-	struct net_device *netdev;
+-	u16 rx_buf_len;
+-	u16 num_tx_desc;
+-	u16 num_rx_desc;
+ 
+-	u16 num_tqps;   /* total number of tqps in this handle */
+-	struct hnae3_queue **tqp;  /* array base of all TQPs of this instance */
+-};
+-#endif
+ #define HNAE3_SUPPORT_APP_LOOPBACK    BIT(0)
+ #define HNAE3_SUPPORT_PHY_LOOPBACK    BIT(1)
+ #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK	BIT(2)
+@@ -970,9 +945,6 @@ struct hnae3_handle {
+ 	union {
+ 		struct net_device *netdev; /* first member */
+ 		struct hnae3_knic_private_info kinfo;
+-#ifdef __GENKSYMS__
+-		struct hnae3_unic_private_info uinfo;
+-#endif
+ 		struct hnae3_roce_private_info rinfo;
+ 	};
+ 
+@@ -993,10 +965,8 @@ struct hnae3_handle {
+ 	struct kobject *kobj;
+ #endif
+ 
+-#ifndef __GENKSYMS__
+ 	unsigned long supported_pflags;
+ 	unsigned long priv_flags;
+-#endif
+ };
+ 
+ #define hnae3_set_field(origin, mask, shift, val) \
+-- 
+2.34.1
+
diff --git a/patches/0625-net-hns3-fix-for-not-calculating-TX-BD-send-size-cor.patch b/patches/0625-net-hns3-fix-for-not-calculating-TX-BD-send-size-cor.patch
new file mode 100644
index 0000000..d6976a3
--- /dev/null
+++ b/patches/0625-net-hns3-fix-for-not-calculating-TX-BD-send-size-cor.patch
@@ -0,0 +1,68 @@
+From eb399d8cd180ee25caa9e915d2e7aebf8352bd2e Mon Sep 17 00:00:00 2001
+From: Yunsheng Lin <linyunsheng@huawei.com>
+Date: Tue, 21 Jul 2020 19:03:52 +0800
+Subject: [PATCH 264/283] net: hns3: fix for not calculating TX BD send size
+ correctly
+
+mainline inclusion
+from mainline-v5.8-rc7
+commit 48ae74c9d89f827b39b5c07a1f02fc13637a3cd6
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=48ae74c9d89f827b39b5c07a1f02fc13637a3cd6
+
+--------------------------------
+
+With GRO and fraglist support, the SKB can be aggregated to
+a total size of 65535, and when that SKB is forwarded through
+a bridge, the size of the SKB may be pushed to exceed the size
+of 65535 when br_dev_queue_push_xmit() is called.
+
+The max send size of BD supported by the HW is 65535, when a SKB
+with a headlen of over 65535 is sent to the driver, the driver
+needs to use multi BD to send the linear data, and the send size
+of the last BD is calculated incorrectly by the driver who is
+using '&' operation, which causes a TX error.
+
+Use '%' operation to fix this problem.
+
+Fixes: 3fe13ed95dd3 ("net: hns3: avoid mult + div op in critical data path")
+Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
+Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 2 +-
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 2 --
+ 2 files changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 56dbad4f85a6..43bd0c4b6108 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -1468,7 +1468,7 @@ static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
+ 	}
+ 
+ 	frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) >> HNS3_MAX_BD_SIZE_OFFSET;
+-	sizeoflast = size & HNS3_TX_LAST_SIZE_M;
++	sizeoflast = size % HNS3_MAX_BD_SIZE;
+ 	sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
+ 
+ 	/* When frag size is bigger than hardware limit, split this frag */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+index 19670ff928ce..6bee2971eb3f 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+@@ -185,8 +185,6 @@ enum hns3_nic_state {
+ #define HNS3_TXD_MSS_M				(0x3fff << HNS3_TXD_MSS_S)
+ #define HNS3_TXD_HW_CS_B			14
+ 
+-#define HNS3_TX_LAST_SIZE_M                    0xffff
+-
+ #define HNS3_VECTOR_TX_IRQ			BIT_ULL(0)
+ #define HNS3_VECTOR_RX_IRQ			BIT_ULL(1)
+ 
+-- 
+2.34.1
+
diff --git a/patches/0626-ethtool-fix-application-of-verbose-no_mask-bitset.patch b/patches/0626-ethtool-fix-application-of-verbose-no_mask-bitset.patch
new file mode 100644
index 0000000..d6ba20b
--- /dev/null
+++ b/patches/0626-ethtool-fix-application-of-verbose-no_mask-bitset.patch
@@ -0,0 +1,69 @@
+From 95fb63a77fd9069ce7c8d70eb947a3168b3f1869 Mon Sep 17 00:00:00 2001
+From: Michal Kubecek <mkubecek@suse.cz>
+Date: Sat, 15 Feb 2020 01:55:53 +0100
+Subject: [PATCH 265/283] ethtool: fix application of verbose no_mask bitset
+
+mainline inclusion
+from mainline-v5.6-rc3
+commit 6699170376ab941c1cc5c3bcefa766efc3575c73
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6699170376ab941c1cc5c3bcefa766efc3575c73
+
+--------------------------------
+
+A bitset without mask in a _SET request means we want exactly the bits in
+the bitset to be set. This works correctly for compact format but when
+verbose format is parsed, ethnl_update_bitset32_verbose() only sets the
+bits present in the request bitset but does not clear the rest. This can
+cause incorrect results like
+
+  lion:~ # ethtool eth0 | grep Wake
+          Supports Wake-on: pumbg
+          Wake-on: g
+  lion:~ # ethtool -s eth0 wol u
+  lion:~ # ethtool eth0 | grep Wake
+          Supports Wake-on: pumbg
+          Wake-on: ug
+
+when the second ethtool command issues request
+
+ETHTOOL_MSG_WOL_SET
+    ETHTOOL_A_WOL_HEADER
+        ETHTOOL_A_HEADER_DEV_NAME = "eth0"
+    ETHTOOL_A_WOL_MODES
+        ETHTOOL_A_BITSET_NOMASK
+        ETHTOOL_A_BITSET_BITS
+            ETHTOOL_A_BITSET_BITS_BIT
+                ETHTOOL_BITSET_BIT_INDEX = 1
+
+Fix the logic by clearing the whole target bitmap before we start iterating
+through the request bits.
+
+Fixes: 10b518d4e6dd ("ethtool: netlink bitset handling")
+Signed-off-by: Michal Kubecek <mkubecek@suse.cz>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ net/ethtool/bitset.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/net/ethtool/bitset.c b/net/ethtool/bitset.c
+index 61a9de207020..69db5f8d94b8 100644
+--- a/net/ethtool/bitset.c
++++ b/net/ethtool/bitset.c
+@@ -448,7 +448,10 @@ ethnl_update_bitset32_verbose(u32 *bitmap, unsigned int nbits,
+ 				    "mask only allowed in compact bitset");
+ 		return -EINVAL;
+ 	}
++
+ 	no_mask = tb[ETHTOOL_A_BITSET_NOMASK];
++	if (no_mask)
++		ethnl_bitmap32_clear(bitmap, 0, nbits, mod);
+ 
+ 	nla_for_each_nested(bit_attr, tb[ETHTOOL_A_BITSET_BITS], rem) {
+ 		bool old_val, new_val;
+-- 
+2.34.1
+
diff --git a/patches/0627-ethtool-limit-bitset-size.patch b/patches/0627-ethtool-limit-bitset-size.patch
new file mode 100644
index 0000000..909330d
--- /dev/null
+++ b/patches/0627-ethtool-limit-bitset-size.patch
@@ -0,0 +1,73 @@
+From fb46ba0f56afd29f8b43542be21507a3ed572185 Mon Sep 17 00:00:00 2001
+From: Michal Kubecek <mkubecek@suse.cz>
+Date: Mon, 24 Feb 2020 20:42:12 +0100
+Subject: [PATCH 266/283] ethtool: limit bitset size
+
+mainline inclusion
+from mainline-v5.6-rc4
+commit e34f1753eebc428c312527662eb1b529cf260240
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e34f1753eebc428c312527662eb1b529cf260240
+
+--------------------------------
+
+Syzbot reported that ethnl_compact_sanity_checks() can be tricked into
+reading past the end of ETHTOOL_A_BITSET_VALUE and ETHTOOL_A_BITSET_MASK
+attributes and even the message by passing a value between (u32)(-31)
+and (u32)(-1) as ETHTOOL_A_BITSET_SIZE.
+
+The problem is that DIV_ROUND_UP(attr_nbits, 32) is 0 for such values so
+that zero length ETHTOOL_A_BITSET_VALUE will pass the length check but
+ethnl_bitmap32_not_zero() check would try to access up to 512 MB of
+attribute "payload".
+
+Prevent this overflow byt limiting the bitset size. Technically, compact
+bitset format would allow bitset sizes up to almost 2^18 (so that the
+nest size does not exceed U16_MAX) but bitsets used by ethtool are much
+shorter. S16_MAX, the largest value which can be directly used as an
+upper limit in policy, should be a reasonable compromise.
+
+Fixes: 10b518d4e6dd ("ethtool: netlink bitset handling")
+Reported-by: syzbot+7fd4ed5b4234ab1fdccd@syzkaller.appspotmail.com
+Reported-by: syzbot+709b7a64d57978247e44@syzkaller.appspotmail.com
+Reported-by: syzbot+983cb8fb2d17a7af549d@syzkaller.appspotmail.com
+Signed-off-by: Michal Kubecek <mkubecek@suse.cz>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ net/ethtool/bitset.c | 3 ++-
+ net/ethtool/bitset.h | 2 ++
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/net/ethtool/bitset.c b/net/ethtool/bitset.c
+index 69db5f8d94b8..674cbe6f421e 100644
+--- a/net/ethtool/bitset.c
++++ b/net/ethtool/bitset.c
+@@ -306,7 +306,8 @@ int ethnl_put_bitset32(struct sk_buff *skb, int attrtype, const u32 *val,
+ static const struct nla_policy bitset_policy[ETHTOOL_A_BITSET_MAX + 1] = {
+ 	[ETHTOOL_A_BITSET_UNSPEC]	= { .type = NLA_REJECT },
+ 	[ETHTOOL_A_BITSET_NOMASK]	= { .type = NLA_FLAG },
+-	[ETHTOOL_A_BITSET_SIZE]		= { .type = NLA_U32 },
++	[ETHTOOL_A_BITSET_SIZE]		= NLA_POLICY_MAX(NLA_U32,
++							 ETHNL_MAX_BITSET_SIZE),
+ 	[ETHTOOL_A_BITSET_BITS]		= { .type = NLA_NESTED },
+ 	[ETHTOOL_A_BITSET_VALUE]	= { .type = NLA_BINARY },
+ 	[ETHTOOL_A_BITSET_MASK]		= { .type = NLA_BINARY },
+diff --git a/net/ethtool/bitset.h b/net/ethtool/bitset.h
+index b8247e34109d..b849f9d19676 100644
+--- a/net/ethtool/bitset.h
++++ b/net/ethtool/bitset.h
+@@ -3,6 +3,8 @@
+ #ifndef _NET_ETHTOOL_BITSET_H
+ #define _NET_ETHTOOL_BITSET_H
+ 
++#define ETHNL_MAX_BITSET_SIZE S16_MAX
++
+ typedef const char (*const ethnl_string_array_t)[ETH_GSTRING_LEN];
+ 
+ int ethnl_bitset_is_compact(const struct nlattr *bitset, bool *compact);
+-- 
+2.34.1
+
diff --git a/patches/0628-ethtool-reset-lanes-when-lanes-is-omitted.patch b/patches/0628-ethtool-reset-lanes-when-lanes-is-omitted.patch
new file mode 100644
index 0000000..008dd6f
--- /dev/null
+++ b/patches/0628-ethtool-reset-lanes-when-lanes-is-omitted.patch
@@ -0,0 +1,103 @@
+From 88036ea56a902643af30e249843e49ff61d6604d Mon Sep 17 00:00:00 2001
+From: Andy Roulin <aroulin@nvidia.com>
+Date: Mon, 3 Apr 2023 14:20:53 -0700
+Subject: [PATCH 267/283] ethtool: reset #lanes when lanes is omitted
+
+mainline inclusion
+from mainline-v6.3-rc6
+commit e847c7675e19ef344913724dc68f83df31ad6a17
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e847c7675e19ef344913724dc68f83df31ad6a17
+
+--------------------------------
+
+If the number of lanes was forced and then subsequently the user
+omits this parameter, the ksettings->lanes is reset. The driver
+should then reset the number of lanes to the device's default
+for the specified speed.
+
+However, although the ksettings->lanes is set to 0, the mod variable
+is not set to true to indicate the driver and userspace should be
+notified of the changes.
+
+The consequence is that the same ethtool operation will produce
+different results based on the initial state.
+
+If the initial state is:
+$ ethtool swp1 | grep -A 3 'Speed: '
+        Speed: 500000Mb/s
+        Lanes: 2
+        Duplex: Full
+        Auto-negotiation: on
+
+then executing 'ethtool -s swp1 speed 50000 autoneg off' will yield:
+$ ethtool swp1 | grep -A 3 'Speed: '
+        Speed: 500000Mb/s
+        Lanes: 2
+        Duplex: Full
+        Auto-negotiation: off
+
+While if the initial state is:
+$ ethtool swp1 | grep -A 3 'Speed: '
+        Speed: 500000Mb/s
+        Lanes: 1
+        Duplex: Full
+        Auto-negotiation: off
+
+executing the same 'ethtool -s swp1 speed 50000 autoneg off' results in:
+$ ethtool swp1 | grep -A 3 'Speed: '
+        Speed: 500000Mb/s
+        Lanes: 1
+        Duplex: Full
+        Auto-negotiation: off
+
+This patch fixes this behavior. Omitting lanes will always results in
+the driver choosing the default lane width for the chosen speed. In this
+scenario, regardless of the initial state, the end state will be, e.g.,
+
+$ ethtool swp1 | grep -A 3 'Speed: '
+        Speed: 500000Mb/s
+        Lanes: 2
+        Duplex: Full
+        Auto-negotiation: off
+
+Fixes: 012ce4dd3102 ("ethtool: Extend link modes settings uAPI with lanes")
+Signed-off-by: Andy Roulin <aroulin@nvidia.com>
+Reviewed-by: Danielle Ratson <danieller@nvidia.com>
+Reviewed-by: Ido Schimmel <idosch@nvidia.com>
+Link: https://lore.kernel.org/r/ac238d6b-8726-8156-3810-6471291dbc7f@nvidia.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+
+ Conflicts:
+	net/ethtool/linkmodes.c
+---
+ net/ethtool/linkmodes.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
+index b632e14d6c27..f8f3fc74ac78 100644
+--- a/net/ethtool/linkmodes.c
++++ b/net/ethtool/linkmodes.c
+@@ -425,12 +425,12 @@ static int ethnl_update_linkmodes(struct genl_info *info, struct nlattr **tb,
+ 					    "lanes configuration not supported by device");
+ 			return -EOPNOTSUPP;
+ 		}
+-	} else if (!lsettings->autoneg) {
+-		/* If autoneg is off and lanes parameter is
+-		 * not passed from user,
+-		 * set the lanes parameter to 0.
++	} else if (!lsettings->autoneg && ksettings->lanes) {
++		/* If autoneg is off and lanes parameter is not passed from user but
++		 * it was defined previously then set the lanes parameter to 0.
+ 		 */
+ 		ksettings->lanes = 0;
++		*mod = true;
+ 	}
+ 
+ 	ret = ethnl_update_bitset(ksettings->link_modes.advertising,
+-- 
+2.34.1
+
diff --git a/patches/0629-ethtool-Fix-uninitialized-number-of-lanes.patch b/patches/0629-ethtool-Fix-uninitialized-number-of-lanes.patch
new file mode 100644
index 0000000..f35d18d
--- /dev/null
+++ b/patches/0629-ethtool-Fix-uninitialized-number-of-lanes.patch
@@ -0,0 +1,136 @@
+From 0aa68a0296434cc55cb33277d5d7de0fc807d14b Mon Sep 17 00:00:00 2001
+From: Ido Schimmel <idosch@nvidia.com>
+Date: Tue, 2 May 2023 15:20:50 +0300
+Subject: [PATCH 268/283] ethtool: Fix uninitialized number of lanes
+
+mainline inclusion
+from mainline-v6.4-rc1
+commit 9ad685dbfe7e856bbf17a7177b64676d324d6ed7
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9ad685dbfe7e856bbf17a7177b64676d324d6ed7
+
+--------------------------------
+
+It is not possible to set the number of lanes when setting link modes
+using the legacy IOCTL ethtool interface. Since 'struct
+ethtool_link_ksettings' is not initialized in this path, drivers receive
+an uninitialized number of lanes in 'struct
+ethtool_link_ksettings::lanes'.
+
+When this information is later queried from drivers, it results in the
+ethtool code making decisions based on uninitialized memory, leading to
+the following KMSAN splat [1]. In practice, this most likely only
+happens with the tun driver that simply returns whatever it got in the
+set operation.
+
+As far as I can tell, this uninitialized memory is not leaked to user
+space thanks to the 'ethtool_ops->cap_link_lanes_supported' check in
+linkmodes_prepare_data().
+
+Fix by initializing the structure in the IOCTL path. Did not find any
+more call sites that pass an uninitialized structure when calling
+'ethtool_ops::set_link_ksettings()'.
+
+[1]
+BUG: KMSAN: uninit-value in ethnl_update_linkmodes net/ethtool/linkmodes.c:273 [inline]
+BUG: KMSAN: uninit-value in ethnl_set_linkmodes+0x190b/0x19d0 net/ethtool/linkmodes.c:333
+ ethnl_update_linkmodes net/ethtool/linkmodes.c:273 [inline]
+ ethnl_set_linkmodes+0x190b/0x19d0 net/ethtool/linkmodes.c:333
+ ethnl_default_set_doit+0x88d/0xde0 net/ethtool/netlink.c:640
+ genl_family_rcv_msg_doit net/netlink/genetlink.c:968 [inline]
+ genl_family_rcv_msg net/netlink/genetlink.c:1048 [inline]
+ genl_rcv_msg+0x141a/0x14c0 net/netlink/genetlink.c:1065
+ netlink_rcv_skb+0x3f8/0x750 net/netlink/af_netlink.c:2577
+ genl_rcv+0x40/0x60 net/netlink/genetlink.c:1076
+ netlink_unicast_kernel net/netlink/af_netlink.c:1339 [inline]
+ netlink_unicast+0xf41/0x1270 net/netlink/af_netlink.c:1365
+ netlink_sendmsg+0x127d/0x1430 net/netlink/af_netlink.c:1942
+ sock_sendmsg_nosec net/socket.c:724 [inline]
+ sock_sendmsg net/socket.c:747 [inline]
+ ____sys_sendmsg+0xa24/0xe40 net/socket.c:2501
+ ___sys_sendmsg+0x2a1/0x3f0 net/socket.c:2555
+ __sys_sendmsg net/socket.c:2584 [inline]
+ __do_sys_sendmsg net/socket.c:2593 [inline]
+ __se_sys_sendmsg net/socket.c:2591 [inline]
+ __x64_sys_sendmsg+0x36b/0x540 net/socket.c:2591
+ do_syscall_x64 arch/x86/entry/common.c:50 [inline]
+ do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80
+ entry_SYSCALL_64_after_hwframe+0x63/0xcd
+
+Uninit was stored to memory at:
+ tun_get_link_ksettings+0x37/0x60 drivers/net/tun.c:3544
+ __ethtool_get_link_ksettings+0x17b/0x260 net/ethtool/ioctl.c:441
+ ethnl_set_linkmodes+0xee/0x19d0 net/ethtool/linkmodes.c:327
+ ethnl_default_set_doit+0x88d/0xde0 net/ethtool/netlink.c:640
+ genl_family_rcv_msg_doit net/netlink/genetlink.c:968 [inline]
+ genl_family_rcv_msg net/netlink/genetlink.c:1048 [inline]
+ genl_rcv_msg+0x141a/0x14c0 net/netlink/genetlink.c:1065
+ netlink_rcv_skb+0x3f8/0x750 net/netlink/af_netlink.c:2577
+ genl_rcv+0x40/0x60 net/netlink/genetlink.c:1076
+ netlink_unicast_kernel net/netlink/af_netlink.c:1339 [inline]
+ netlink_unicast+0xf41/0x1270 net/netlink/af_netlink.c:1365
+ netlink_sendmsg+0x127d/0x1430 net/netlink/af_netlink.c:1942
+ sock_sendmsg_nosec net/socket.c:724 [inline]
+ sock_sendmsg net/socket.c:747 [inline]
+ ____sys_sendmsg+0xa24/0xe40 net/socket.c:2501
+ ___sys_sendmsg+0x2a1/0x3f0 net/socket.c:2555
+ __sys_sendmsg net/socket.c:2584 [inline]
+ __do_sys_sendmsg net/socket.c:2593 [inline]
+ __se_sys_sendmsg net/socket.c:2591 [inline]
+ __x64_sys_sendmsg+0x36b/0x540 net/socket.c:2591
+ do_syscall_x64 arch/x86/entry/common.c:50 [inline]
+ do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80
+ entry_SYSCALL_64_after_hwframe+0x63/0xcd
+
+Uninit was stored to memory at:
+ tun_set_link_ksettings+0x37/0x60 drivers/net/tun.c:3553
+ ethtool_set_link_ksettings+0x600/0x690 net/ethtool/ioctl.c:609
+ __dev_ethtool net/ethtool/ioctl.c:3024 [inline]
+ dev_ethtool+0x1db9/0x2a70 net/ethtool/ioctl.c:3078
+ dev_ioctl+0xb07/0x1270 net/core/dev_ioctl.c:524
+ sock_do_ioctl+0x295/0x540 net/socket.c:1213
+ sock_ioctl+0x729/0xd90 net/socket.c:1316
+ vfs_ioctl fs/ioctl.c:51 [inline]
+ __do_sys_ioctl fs/ioctl.c:870 [inline]
+ __se_sys_ioctl+0x222/0x400 fs/ioctl.c:856
+ __x64_sys_ioctl+0x96/0xe0 fs/ioctl.c:856
+ do_syscall_x64 arch/x86/entry/common.c:50 [inline]
+ do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80
+ entry_SYSCALL_64_after_hwframe+0x63/0xcd
+
+Local variable link_ksettings created at:
+ ethtool_set_link_ksettings+0x54/0x690 net/ethtool/ioctl.c:577
+ __dev_ethtool net/ethtool/ioctl.c:3024 [inline]
+ dev_ethtool+0x1db9/0x2a70 net/ethtool/ioctl.c:3078
+
+Fixes: 012ce4dd3102 ("ethtool: Extend link modes settings uAPI with lanes")
+Reported-and-tested-by: syzbot+ef6edd9f1baaa54d6235@syzkaller.appspotmail.com
+Link: https://lore.kernel.org/netdev/0000000000004bb41105fa70f361@google.com/
+Reviewed-by: Danielle Ratson <danieller@nvidia.com>
+Signed-off-by: Ido Schimmel <idosch@nvidia.com>
+Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ net/ethtool/ioctl.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/net/ethtool/ioctl.c b/net/ethtool/ioctl.c
+index 4fdfb3e40dea..c7f67750ecc4 100644
+--- a/net/ethtool/ioctl.c
++++ b/net/ethtool/ioctl.c
+@@ -640,8 +640,8 @@ static int ethtool_get_link_ksettings(struct net_device *dev,
+ static int ethtool_set_link_ksettings(struct net_device *dev,
+ 				      void __user *useraddr)
+ {
++	struct ethtool_link_ksettings link_ksettings = {};
+ 	int err;
+-	struct ethtool_link_ksettings link_ksettings;
+ 
+ 	ASSERT_RTNL();
+ 
+-- 
+2.34.1
+
diff --git a/patches/0630-net-hns3-fix-deadlock-issue-when-externel_lb-and-res.patch b/patches/0630-net-hns3-fix-deadlock-issue-when-externel_lb-and-res.patch
new file mode 100644
index 0000000..e4e1cff
--- /dev/null
+++ b/patches/0630-net-hns3-fix-deadlock-issue-when-externel_lb-and-res.patch
@@ -0,0 +1,96 @@
+From 18dc0ad80f9c8eb7e4f34d6da219072b88a9b046 Mon Sep 17 00:00:00 2001
+From: Yonglong Liu <liuyonglong@huawei.com>
+Date: Mon, 7 Aug 2023 19:34:52 +0800
+Subject: [PATCH 269/283] net: hns3: fix deadlock issue when externel_lb and
+ reset are executed together
+
+mainline inclusion
+from mainline-v6.5-rc6
+commit ac6257a3ae5db5193b1f19c268e4f72d274ddb88
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ac6257a3ae5db5193b1f19c268e4f72d274ddb88
+
+--------------------------------
+
+When externel_lb and reset are executed together, a deadlock may
+occur:
+[ 3147.217009] INFO: task kworker/u321:0:7 blocked for more than 120 seconds.
+[ 3147.230483] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
+[ 3147.238999] task:kworker/u321:0  state:D stack:    0 pid:    7 ppid:     2 flags:0x00000008
+[ 3147.248045] Workqueue: hclge hclge_service_task [hclge]
+[ 3147.253957] Call trace:
+[ 3147.257093]  __switch_to+0x7c/0xbc
+[ 3147.261183]  __schedule+0x338/0x6f0
+[ 3147.265357]  schedule+0x50/0xe0
+[ 3147.269185]  schedule_preempt_disabled+0x18/0x24
+[ 3147.274488]  __mutex_lock.constprop.0+0x1d4/0x5dc
+[ 3147.279880]  __mutex_lock_slowpath+0x1c/0x30
+[ 3147.284839]  mutex_lock+0x50/0x60
+[ 3147.288841]  rtnl_lock+0x20/0x2c
+[ 3147.292759]  hclge_reset_prepare+0x68/0x90 [hclge]
+[ 3147.298239]  hclge_reset_subtask+0x88/0xe0 [hclge]
+[ 3147.303718]  hclge_reset_service_task+0x84/0x120 [hclge]
+[ 3147.309718]  hclge_service_task+0x2c/0x70 [hclge]
+[ 3147.315109]  process_one_work+0x1d0/0x490
+[ 3147.319805]  worker_thread+0x158/0x3d0
+[ 3147.324240]  kthread+0x108/0x13c
+[ 3147.328154]  ret_from_fork+0x10/0x18
+
+In externel_lb process, the hns3 driver call napi_disable()
+first, then the reset happen, then the restore process of the
+externel_lb will fail, and will not call napi_enable(). When
+doing externel_lb again, napi_disable() will be double call,
+cause a deadlock of rtnl_lock().
+
+This patch use the HNS3_NIC_STATE_DOWN state to protect the
+calling of napi_disable() and napi_enable() in externel_lb
+process, just as the usage in ndo_stop() and ndo_start().
+
+Fixes: 04b6ba143521 ("net: hns3: add support for external loopback test")
+Signed-off-by: Yonglong Liu <liuyonglong@huawei.com>
+Signed-off-by: Jijie Shao <shaojijie@huawei.com>
+Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
+Link: https://lore.kernel.org/r/20230807113452.474224-5-shaojijie@huawei.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 43bd0c4b6108..18d0a218040a 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -5467,6 +5467,9 @@ void hns3_external_lb_prepare(struct net_device *ndev, bool if_running)
+ 	if (!if_running)
+ 		return;
+ 
++	if (test_and_set_bit(HNS3_NIC_STATE_DOWN, &priv->state))
++		return;
++
+ 	netif_carrier_off(ndev);
+ 	netif_tx_disable(ndev);
+ 
+@@ -5495,7 +5498,16 @@ void hns3_external_lb_restore(struct net_device *ndev, bool if_running)
+ 	if (!if_running)
+ 		return;
+ 
+-	hns3_nic_reset_all_ring(priv->ae_handle);
++	if (hns3_nic_resetting(ndev))
++		return;
++
++	if (!test_bit(HNS3_NIC_STATE_DOWN, &priv->state))
++		return;
++
++	if (hns3_nic_reset_all_ring(priv->ae_handle))
++		return;
++
++	clear_bit(HNS3_NIC_STATE_DOWN, &priv->state);
+ 
+ 	for (i = 0; i < priv->vector_num; i++)
+ 		hns3_vector_enable(&priv->tqp_vector[i]);
+-- 
+2.34.1
+
diff --git a/patches/0631-net-hns3-fix-ethtool-tx-copybreak-buf-size-indicatin.patch b/patches/0631-net-hns3-fix-ethtool-tx-copybreak-buf-size-indicatin.patch
new file mode 100644
index 0000000..f04bac0
--- /dev/null
+++ b/patches/0631-net-hns3-fix-ethtool-tx-copybreak-buf-size-indicatin.patch
@@ -0,0 +1,116 @@
+From 0585219f59a01f01b116e47a9cd5b90bf6bba025 Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Sat, 26 Mar 2022 17:51:00 +0800
+Subject: [PATCH 270/283] net: hns3: fix ethtool tx copybreak buf size
+ indicating not aligned issue
+
+mainline inclusion
+from mainline-v5.18-rc1
+commit 8778372118023e2258612c03573c47efef41d755
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8778372118023e2258612c03573c47efef41d755
+
+--------------------------------
+
+When use ethtoool set tx copybreak buf size to a large value
+which causes order exceeding 10 or memory is not enough,
+it causes allocating tx copybreak buffer failed and print
+"the active tx spare buf is 0, not enabled tx spare buffer",
+however, use --get-tunable parameter query tx copybreak buf
+size and it indicates setting value not 0.
+
+So, it's necessary to change the print value from setting
+value to 0.
+
+Set kinfo.tx_spare_buf_size to 0 when set tx copybreak buf size failed.
+
+Fixes: e445f08af2b1 ("net: hns3: add support to set/get tx copybreak buf size via ethtool for hns3 driver")
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   | 20 +++++++++++--------
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  3 ++-
+ 2 files changed, 14 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 18d0a218040a..f9dacf01ddd6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -736,13 +736,12 @@ static bool hns3_can_use_tx_sgl(struct hns3_enet_ring *ring,
+ 
+ static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
+ {
++	u32 alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
+ 	struct hns3_tx_spare *tx_spare;
+ 	struct page *page;
+-	u32 alloc_size;
+ 	dma_addr_t dma;
+ 	int order;
+ 
+-	alloc_size = ring->tqp->handle->kinfo.tx_spare_buf_size;
+ 	if (!alloc_size)
+ 		return;
+ 
+@@ -752,30 +751,35 @@ static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
+ 	if (!tx_spare) {
+ 		/* The driver still work without the tx spare buffer */
+ 		dev_warn(ring_to_dev(ring), "failed to allocate hns3_tx_spare\n");
+-		return;
++		goto devm_kzalloc_error;
+ 	}
+ 
+ 	page = alloc_pages_node(dev_to_node(ring_to_dev(ring)),
+ 				GFP_KERNEL, order);
+ 	if (!page) {
+ 		dev_warn(ring_to_dev(ring), "failed to allocate tx spare pages\n");
+-		devm_kfree(ring_to_dev(ring), tx_spare);
+-		return;
++		goto alloc_pages_error;
+ 	}
+ 
+ 	dma = dma_map_page(ring_to_dev(ring), page, 0,
+ 			   PAGE_SIZE << order, DMA_TO_DEVICE);
+ 	if (dma_mapping_error(ring_to_dev(ring), dma)) {
+ 		dev_warn(ring_to_dev(ring), "failed to map pages for tx spare\n");
+-		put_page(page);
+-		devm_kfree(ring_to_dev(ring), tx_spare);
+-		return;
++		goto dma_mapping_error;
+ 	}
+ 
+ 	tx_spare->dma = dma;
+ 	tx_spare->buf = page_address(page);
+ 	tx_spare->len = PAGE_SIZE << order;
+ 	ring->tx_spare = tx_spare;
++	return;
++
++dma_mapping_error:
++	put_page(page);
++alloc_pages_error:
++	devm_kfree(ring_to_dev(ring), tx_spare);
++devm_kzalloc_error:
++	ring->tqp->handle->kinfo.tx_spare_buf_size = 0;
+ }
+ 
+ /* Use hns3_tx_spare_space() to make sure there is enough buffer
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index a6f339c6046d..8ac71b53ddf0 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1879,7 +1879,8 @@ static int hns3_set_tunable(struct net_device *netdev,
+ 		old_tx_spare_buf_size = h->kinfo.tx_spare_buf_size;
+ 		new_tx_spare_buf_size = *(u32 *)data;
+ 		ret = hns3_set_tx_spare_buf_size(netdev, new_tx_spare_buf_size);
+-		if (ret) {
++		if (ret ||
++		    (!priv->ring->tx_spare && new_tx_spare_buf_size != 0)) {
+ 			int ret1;
+ 
+ 			netdev_warn(netdev,
+-- 
+2.34.1
+
diff --git a/patches/0632-net-hns3-add-max-order-judgement-for-tx-spare-buffer.patch b/patches/0632-net-hns3-add-max-order-judgement-for-tx-spare-buffer.patch
new file mode 100644
index 0000000..56498c8
--- /dev/null
+++ b/patches/0632-net-hns3-add-max-order-judgement-for-tx-spare-buffer.patch
@@ -0,0 +1,50 @@
+From e01061aeb9fc278e1c9f0b2c6d667a7edaea41ec Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Sat, 26 Mar 2022 17:51:01 +0800
+Subject: [PATCH 271/283] net: hns3: add max order judgement for tx spare
+ buffer
+
+mainline inclusion
+from mainline-v5.18-rc1
+commit a89cbb16995bf15582e0d1bdb922ad1a54a2fa8c
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a89cbb16995bf15582e0d1bdb922ad1a54a2fa8c
+
+--------------------------------
+
+Add max order judgement for tx spare buffer to avoid triggering
+call trace, print related fail information instead, when user
+set tx spare buf size to a large value which causes order
+exceeding 10.
+
+Fixes: e445f08af2b1 ("net: hns3: add support to set/get tx copybreak buf size via ethtool for hns3 driver")
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index f9dacf01ddd6..5c723c532289 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -746,6 +746,12 @@ static void hns3_init_tx_spare_buffer(struct hns3_enet_ring *ring)
+ 		return;
+ 
+ 	order = get_order(alloc_size);
++	if (order >= MAX_ORDER) {
++		if (net_ratelimit())
++			dev_warn(ring_to_dev(ring), "failed to allocate tx spare buffer, exceed to max order\n");
++		return;
++	}
++
+ 	tx_spare = devm_kzalloc(ring_to_dev(ring), sizeof(*tx_spare),
+ 				GFP_KERNEL);
+ 	if (!tx_spare) {
+-- 
+2.34.1
+
diff --git a/patches/0633-ethtool-mark-netlink-family-as-__ro_after_init.patch b/patches/0633-ethtool-mark-netlink-family-as-__ro_after_init.patch
new file mode 100644
index 0000000..44bc5f8
--- /dev/null
+++ b/patches/0633-ethtool-mark-netlink-family-as-__ro_after_init.patch
@@ -0,0 +1,48 @@
+From cb1b6b70aa8a365a507acf6cf2f7ba1c30d6cd02 Mon Sep 17 00:00:00 2001
+From: Jakub Kicinski <kuba@kernel.org>
+Date: Mon, 28 Sep 2020 17:58:41 -0700
+Subject: [PATCH 272/283] ethtool: mark netlink family as __ro_after_init
+
+mainline inclusion
+from mainline-v5.9
+commit 78b70155dc73280be2c7084a3be591161cdc6d0c
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=78b70155dc73280be2c7084a3be591161cdc6d0c
+
+--------------------------------
+
+Like all genl families ethtool_genl_family needs to not
+be a straight up constant, because it's modified/initialized
+by genl_register_family(). After init, however, it's only
+passed to genlmsg_put() & co. therefore we can mark it
+as __ro_after_init.
+
+Since genl_family structure contains function pointers
+mark this as a fix.
+
+Fixes: 2b4a8990b7df ("ethtool: introduce ethtool netlink interface")
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ net/ethtool/netlink.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/net/ethtool/netlink.c b/net/ethtool/netlink.c
+index 1fdf23c0a6ec..c5fa38fad466 100644
+--- a/net/ethtool/netlink.c
++++ b/net/ethtool/netlink.c
+@@ -811,7 +811,7 @@ static const struct genl_multicast_group ethtool_nl_mcgrps[] = {
+ 	[ETHNL_MCGRP_MONITOR] = { .name = ETHTOOL_MCGRP_MONITOR_NAME },
+ };
+ 
+-static struct genl_family ethtool_genl_family = {
++static struct genl_family ethtool_genl_family __ro_after_init = {
+ 	.name		= ETHTOOL_GENL_NAME,
+ 	.version	= ETHTOOL_GENL_VERSION,
+ 	.netnsok	= true,
+-- 
+2.34.1
+
diff --git a/patches/0634-net-hns3-add-netdev-reset-check-for-hns3_set_tunable.patch b/patches/0634-net-hns3-add-netdev-reset-check-for-hns3_set_tunable.patch
new file mode 100644
index 0000000..947d2ef
--- /dev/null
+++ b/patches/0634-net-hns3-add-netdev-reset-check-for-hns3_set_tunable.patch
@@ -0,0 +1,59 @@
+From d1032c11f5df2a5e1fa2f6868cc40f6b944747db Mon Sep 17 00:00:00 2001
+From: Hao Chen <chenhao288@hisilicon.com>
+Date: Sat, 26 Mar 2022 17:51:03 +0800
+Subject: [PATCH 273/283] net: hns3: add netdev reset check for
+ hns3_set_tunable()
+
+mainline inclusion
+from mainline-v5.18
+commit f5cd60169f981ca737c9e49c446506dfafc90a35
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f5cd60169f981ca737c9e49c446506dfafc90a35
+
+--------------------------------
+
+When pci device reset failed, it does uninit operation and priv->ring
+is NULL, it causes accessing NULL pointer error.
+
+Add netdev reset check for hns3_set_tunable() to fix it.
+
+Fixes: 99f6b5fb5f63 ("net: hns3: use bounce buffer when rx page can not be reused")
+Signed-off-by: Hao Chen <chenhao288@hisilicon.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 8ac71b53ddf0..21675ff52380 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -1827,9 +1827,6 @@ static int hns3_set_tx_spare_buf_size(struct net_device *netdev,
+ 	struct hnae3_handle *h = priv->ae_handle;
+ 	int ret;
+ 
+-	if (hns3_nic_resetting(netdev))
+-		return -EBUSY;
+-
+ 	h->kinfo.tx_spare_buf_size = data;
+ 
+ 	ret = hns3_reset_notify(h, HNAE3_DOWN_CLIENT);
+@@ -1860,6 +1857,11 @@ static int hns3_set_tunable(struct net_device *netdev,
+ 	struct hnae3_handle *h = priv->ae_handle;
+ 	int i, ret = 0;
+ 
++	if (hns3_nic_resetting(netdev) || !priv->ring) {
++		netdev_err(netdev, "failed to set tunable value, dev resetting!");
++		return -EBUSY;
++	}
++
+ 	switch (tuna->id) {
+ 	case ETHTOOL_TX_COPYBREAK:
+ 		priv->tx_copybreak = *(u32 *)data;
+-- 
+2.34.1
+
diff --git a/patches/0635-net-hns3-fix-return-value-check-bug-of-rx-copybreak.patch b/patches/0635-net-hns3-fix-return-value-check-bug-of-rx-copybreak.patch
new file mode 100644
index 0000000..dfd3305
--- /dev/null
+++ b/patches/0635-net-hns3-fix-return-value-check-bug-of-rx-copybreak.patch
@@ -0,0 +1,46 @@
+From fcb841404f3420fd2ab21cc546ff3e34579bec1b Mon Sep 17 00:00:00 2001
+From: Jie Wang <wangjie125@huawei.com>
+Date: Mon, 14 Nov 2022 16:20:47 +0800
+Subject: [PATCH 274/283] net: hns3: fix return value check bug of rx copybreak
+
+mainline inclusion
+from mainline-v6.1-rc6
+commit 29df7c695ed67a8fa32bb7805bad8fe2a76c1f88
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=29df7c695ed67a8fa32bb7805bad8fe2a76c1f88
+
+--------------------------------
+
+The refactoring of rx copybreak modifies the original return logic, which
+will make this feature unavailable. So this patch fixes the return logic of
+rx copybreak.
+
+Fixes: e74a726da2c4 ("net: hns3: refactor hns3_nic_reuse_page()")
+Fixes: 99f6b5fb5f63 ("net: hns3: use bounce buffer when rx page can not be reused")
+Signed-off-by: Jie Wang <wangjie125@huawei.com>
+Signed-off-by: Hao Lan <lanhao@huawei.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 5c723c532289..644d76278cc7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -3462,7 +3462,8 @@ static void hns3_nic_reuse_page(struct sk_buff *skb, int i,
+ 		desc_cb->reuse_flag = 1;
+ 	} else if (frag_size <= ring->rx_copybreak) {
+ 		ret = hns3_handle_rx_copybreak(skb, i, ring, pull_len, desc_cb);
+-		return;
++		if (!ret)
++			return;
+ 	}
+ 
+ out:
+-- 
+2.34.1
+
diff --git a/patches/0636-net-hns3-Add-configuration-of-TM-QCN-error-event.patch b/patches/0636-net-hns3-Add-configuration-of-TM-QCN-error-event.patch
new file mode 100644
index 0000000..548cf3a
--- /dev/null
+++ b/patches/0636-net-hns3-Add-configuration-of-TM-QCN-error-event.patch
@@ -0,0 +1,62 @@
+From 5b605d666ba0de955a3910003ecba670b3864fb2 Mon Sep 17 00:00:00 2001
+From: Jiaran Zhang <zhangjiaran@huawei.com>
+Date: Tue, 19 Oct 2021 22:16:28 +0800
+Subject: [PATCH 275/283] net: hns3: Add configuration of TM QCN error event
+
+mainline inclusion
+from mainline-v5.15-rc7
+commit 60484103d5c387df49bd60de4b16c88022747048
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+
+Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=60484103d5c387df49bd60de4b16c88022747048
+
+--------------------------------
+
+Add configuration of interrupt type and fifo interrupt enable of TM QCN
+error event if enabled, otherwise this event will not be reported when
+there is error.
+
+Fixes: d914971df022 ("net: hns3: remove redundant query in hclge_config_tm_hw_err_int()")
+Signed-off-by: Jiaran Zhang <zhangjiaran@huawei.com>
+Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 5 ++++-
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | 2 ++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+index 68b53d4020f7..263e60f5fe80 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+@@ -1572,8 +1572,11 @@ static int hclge_config_tm_hw_err_int(struct hclge_dev *hdev, bool en)
+ 
+ 	/* configure TM QCN hw errors */
+ 	hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_QCN_MEM_INT_CFG, false);
+-	if (en)
++	desc.data[0] = cpu_to_le32(HCLGE_TM_QCN_ERR_INT_TYPE);
++	if (en) {
++		desc.data[0] |= cpu_to_le32(HCLGE_TM_QCN_FIFO_INT_EN);
+ 		desc.data[1] = cpu_to_le32(HCLGE_TM_QCN_MEM_ERR_INT_EN);
++	}
+ 
+ 	ret = hclge_cmd_send(&hdev->hw, &desc, 1);
+ 	if (ret)
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+index f36d73cd3abd..2e3b33423cda 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+@@ -53,6 +53,8 @@
+ #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN	0x003F
+ #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK	0x003F
+ #define HCLGE_TM_SCH_ECC_ERR_INT_EN	0x3
++#define HCLGE_TM_QCN_ERR_INT_TYPE	0x29
++#define HCLGE_TM_QCN_FIFO_INT_EN	0xFFFF00
+ #define HCLGE_TM_QCN_MEM_ERR_INT_EN	0xFFFFFF
+ #define HCLGE_NCSI_ERR_INT_EN	0x3
+ #define HCLGE_NCSI_ERR_INT_TYPE	0x9
+-- 
+2.34.1
+
diff --git a/patches/0637-net-hns3-add-ROH-MAC-type-definitions-and-support-qu.patch b/patches/0637-net-hns3-add-ROH-MAC-type-definitions-and-support-qu.patch
new file mode 100644
index 0000000..45b8f2f
--- /dev/null
+++ b/patches/0637-net-hns3-add-ROH-MAC-type-definitions-and-support-qu.patch
@@ -0,0 +1,148 @@
+From f55274aa83fb48f046a3b3abd5d924d6be0ba147 Mon Sep 17 00:00:00 2001
+From: Ke Chen <chenke54@huawei.com>
+Date: Mon, 7 Nov 2022 19:53:02 +0800
+Subject: [PATCH 276/283] net: hns3: add ROH MAC type definitions and support
+ query MAC type
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/openeuler/kernel/issues/I5WKYW
+
+-----------------------------------------------------------------------
+
+HNAE3 framework add MAC type definitions for NIC or RoCE or ROH clients.
+
+There are two types of MAC in Hip09, ethernet and ROH. In ROH
+type, some operations are different, such as setting MAC address.
+This type will be used as the judgment condition in subsequent
+patches.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Ke Chen <chenke54@huawei.com>
+Reviewed-by: Gang Zhang <gang.zhang@huawei.com>
+Reviewed-by: Yefeng Yan <yanyefeng@huawei.com>
+Reviewed-by: Jingchao Dai <daijingchao1@huawei.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h    | 12 ++++++++++++
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c      | 18 +++++++++++++++++-
+ .../hisilicon/hns3/hns3pf/hclge_main.c         | 17 ++++++++++++++++-
+ 3 files changed, 45 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 3658c2b7247c..eebe7a4edaee 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -233,6 +233,11 @@ enum hnae3_client_type {
+ 	HNAE3_CLIENT_ROCE,
+ };
+ 
++enum hnae3_mac_type {
++	HNAE3_MAC_ETH,
++	HNAE3_MAC_ROH,
++};
++
+ /* mac media type */
+ enum hnae3_media_type {
+ 	HNAE3_MEDIA_TYPE_UNKNOWN,
+@@ -967,6 +972,8 @@ struct hnae3_handle {
+ 
+ 	unsigned long supported_pflags;
+ 	unsigned long priv_flags;
++
++	enum hnae3_mac_type mac_type;
+ };
+ 
+ #define hnae3_set_field(origin, mask, shift, val) \
+@@ -981,6 +988,11 @@ struct hnae3_handle {
+ #define hnae3_get_bit(origin, shift) \
+ 	hnae3_get_field(origin, 0x1 << (shift), shift)
+ 
++static inline bool hnae3_check_roh_mac_type(struct hnae3_handle *handle)
++{
++	return handle->mac_type == HNAE3_MAC_ROH;
++}
++
+ int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev);
+ void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev);
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index 32f4245dfd6d..cf3bbfa2bac5 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -393,6 +393,16 @@ static int hclge_dbg_dump_mac_speed_duplex(struct hclge_dev *hdev, char *buf,
+ 	return 0;
+ }
+ 
++static void hclge_dbg_dump_mac_type(struct hclge_dev *hdev, char *buf, int len,
++				    int *pos)
++{
++	struct hclge_vport *vport = &hdev->vport[0];
++	struct hnae3_handle *handle = &vport->nic;
++
++	*pos += scnprintf(buf + *pos, len - *pos, "type: %s\n",
++			  handle->mac_type ? "ROH" : "Ethernet");
++}
++
+ static int hclge_dbg_dump_mac(struct hclge_dev *hdev, char *buf, int len)
+ {
+ 	int pos = 0;
+@@ -406,7 +416,13 @@ static int hclge_dbg_dump_mac(struct hclge_dev *hdev, char *buf, int len)
+ 	if (ret)
+ 		return ret;
+ 
+-	return hclge_dbg_dump_mac_speed_duplex(hdev, buf, len, &pos);
++	ret = hclge_dbg_dump_mac_speed_duplex(hdev, buf, len, &pos);
++	if (ret)
++		return ret;
++
++	hclge_dbg_dump_mac_type(hdev, buf, len, &pos);
++
++	return 0;
+ }
+ 
+ static int hclge_dbg_dump_dcb_qset(struct hclge_dev *hdev, char *buf, int len,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 17468e2b8bc2..827d0e63ac1c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -1608,6 +1608,20 @@ static int hclge_query_dev_specs(struct hclge_dev *hdev)
+ 	return 0;
+ }
+ 
++static void hclge_mac_type_init(struct hclge_dev *hdev)
++{
++	struct hclge_vport *vport = &hdev->vport[0];
++	struct hnae3_handle *handle = &vport->nic;
++	u32 dev_id = hdev->pdev->device;
++
++	if (dev_id == HNAE3_DEV_ID_100G_ROH ||
++	    dev_id == HNAE3_DEV_ID_200G_ROH ||
++	    dev_id == HNAE3_DEV_ID_400G_ROH)
++		handle->mac_type = HNAE3_MAC_ROH;
++	else
++		handle->mac_type = HNAE3_MAC_ETH;
++}
++
+ static int hclge_get_cap(struct hclge_dev *hdev)
+ {
+ 	int ret;
+@@ -3074,12 +3088,13 @@ static void hclge_get_fec(struct hnae3_handle *handle, u8 *fec_ability,
+ 	if (fec_mode)
+ 		*fec_mode = mac->fec_mode;
+ }
+-
+ static int hclge_mac_init(struct hclge_dev *hdev)
+ {
+ 	struct hclge_mac *mac = &hdev->hw.mac;
+ 	int ret;
+ 
++	hclge_mac_type_init(hdev);
++
+ 	hdev->support_sfp_query = true;
+ 	hdev->hw.mac.duplex = HCLGE_MAC_FULL;
+ 	ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
+-- 
+2.34.1
+
diff --git a/patches/0638-net-hns3-HNAE3-framework-add-support-for-ROH-client.patch b/patches/0638-net-hns3-HNAE3-framework-add-support-for-ROH-client.patch
new file mode 100644
index 0000000..c53f253
--- /dev/null
+++ b/patches/0638-net-hns3-HNAE3-framework-add-support-for-ROH-client.patch
@@ -0,0 +1,463 @@
+From 11d284377f6cfdc34fccbd87a6bed5a058fa9379 Mon Sep 17 00:00:00 2001
+From: Ke Chen <chenke54@huawei.com>
+Date: Mon, 7 Nov 2022 19:53:01 +0800
+Subject: [PATCH 277/283] net: hns3: HNAE3 framework add support for ROH client
+
+driver inclusion
+category: feature
+bugzilla: https://gitee.com/openeuler/kernel/issues/I5WKYW
+
+-----------------------------------------------------------------------
+
+HNAE3 framework supports ROH clients to register with HNAE3
+devices and their associated operations.
+
+The ROH driver works as a client at the HNAE layer. The NIC
+driver needs to provide some necessary information, such as
+the vector base address, and suppor the registration of the
+ROH client.
+
+This patch also supports roh device IDs in the hns3 and hclge
+modules.
+
+Signed-off-by: Yufeng Mo <moyufeng@huawei.com>
+Signed-off-by: Ke Chen <chenke54@huawei.com>
+Reviewed-by: Gang Zhang <gang.zhang@huawei.com>
+Reviewed-by: Yefeng Yan <yanyefeng@huawei.com>
+Reviewed-by: Jingchao Dai <daijingchao1@huawei.com>
+Reviewed-by: Jian Shen <shenjian15@huawei.com>
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hnae3.c   |  10 +-
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  13 ++-
+ .../net/ethernet/hisilicon/hns3/hns3_enet.c   |  22 +++-
+ .../hisilicon/hns3/hns3pf/hclge_cmd.h         |   4 +-
+ .../hisilicon/hns3/hns3pf/hclge_debugfs.c     |   2 +
+ .../hisilicon/hns3/hns3pf/hclge_main.c        | 104 +++++++++++++++++-
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   4 +
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |   4 +-
+ include/net/devlink.h                         |   4 +-
+ include/uapi/linux/if_ether.h                 |   2 +-
+ 10 files changed, 154 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.c b/drivers/net/ethernet/hisilicon/hns3/hnae3.c
+index a90921bd07e7..945200a3b02c 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.c
+@@ -40,7 +40,8 @@ static DEFINE_MUTEX(hnae3_common_lock);
+ static bool hnae3_client_match(enum hnae3_client_type client_type)
+ {
+ 	if (client_type == HNAE3_CLIENT_KNIC ||
+-	    client_type == HNAE3_CLIENT_ROCE)
++	    client_type == HNAE3_CLIENT_ROCE ||
++	    client_type == HNAE3_CLIENT_ROH)
+ 		return true;
+ 
+ 	return false;
+@@ -60,6 +61,9 @@ void hnae3_set_client_init_flag(struct hnae3_client *client,
+ 	case HNAE3_CLIENT_ROCE:
+ 		hnae3_set_bit(ae_dev->flag, HNAE3_ROCE_CLIENT_INITED_B, inited);
+ 		break;
++	case HNAE3_CLIENT_ROH:
++		hnae3_set_bit(ae_dev->flag, HNAE3_ROH_CLIENT_INITED_B, inited);
++		break;
+ 	default:
+ 		break;
+ 	}
+@@ -80,6 +84,10 @@ static int hnae3_get_client_init_flag(struct hnae3_client *client,
+ 		inited = hnae3_get_bit(ae_dev->flag,
+ 				       HNAE3_ROCE_CLIENT_INITED_B);
+ 		break;
++	case HNAE3_CLIENT_ROH:
++		inited = hnae3_get_bit(ae_dev->flag,
++				       HNAE3_ROH_CLIENT_INITED_B);
++		break;
+ 	default:
+ 		break;
+ 	}
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index eebe7a4edaee..422f50b36c22 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -55,8 +55,8 @@
+ #define HNAE3_DEV_ID_200G_RDMA			0xA228
+ #define HNAE3_DEV_ID_200G_ROH			0xA22C
+ #define HNAE3_DEV_ID_400G_ROH			0xA22D
+-#define HNAE3_DEV_ID_100G_VF			0xA22E
+-#define HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF	0xA22F
++#define HNAE3_DEV_ID_VF				0xA22E
++#define HNAE3_DEV_ID_RDMA_DCB_PFC_VF		0xA22F
+ 
+ #define HNAE3_CLASS_NAME_SIZE 16
+ 
+@@ -69,6 +69,7 @@
+ #define HNAE3_KNIC_CLIENT_INITED_B		0x3
+ #define HNAE3_UNIC_CLIENT_INITED_B		0x4
+ #define HNAE3_ROCE_CLIENT_INITED_B		0x5
++#define HNAE3_ROH_CLIENT_INITED_B		0x6
+ 
+ #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) | \
+ 		BIT(HNAE3_DEV_SUPPORT_ROCE_B))
+@@ -231,6 +232,7 @@ enum hnae3_loop {
+ enum hnae3_client_type {
+ 	HNAE3_CLIENT_KNIC,
+ 	HNAE3_CLIENT_ROCE,
++	HNAE3_CLIENT_ROH,
+ };
+ 
+ enum hnae3_mac_type {
+@@ -916,6 +918,12 @@ struct hnae3_roce_private_info {
+ 	unsigned long state;
+ };
+ 
++struct hnae3_roh_private_info {
++	struct net_device *netdev;
++	void __iomem *roh_io_base;
++	int base_vector;
++};
++
+ #define HNAE3_SUPPORT_APP_LOOPBACK    BIT(0)
+ #define HNAE3_SUPPORT_PHY_LOOPBACK    BIT(1)
+ #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK	BIT(2)
+@@ -951,6 +959,7 @@ struct hnae3_handle {
+ 		struct net_device *netdev; /* first member */
+ 		struct hnae3_knic_private_info kinfo;
+ 		struct hnae3_roce_private_info rinfo;
++		struct hnae3_roh_private_info rohinfo;
+ 	};
+ 
+ 	u32 numa_node_mask;	/* for multi-chip support */
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+index 644d76278cc7..4c21a95b5838 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+@@ -91,8 +91,16 @@ const struct pci_device_id hns3_pci_tbl[] = {
+ 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
+ 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC),
+ 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
+-	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
+-	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF),
++	 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_ROH),
++	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA),
++	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_ROH),
++	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_400G_ROH),
++	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF),
+ 	 HNAE3_DEV_SUPPORT_ROCE_DCB_BITS},
+ 	/* required last entry */
+ 	{0,}
+@@ -1477,7 +1485,7 @@ static int hns3_fill_desc(struct hns3_enet_ring *ring, dma_addr_t dma,
+ 		return HNS3_LIKELY_BD_NUM;
+ 	}
+ 
+-	frag_buf_num = (size + HNS3_MAX_BD_SIZE - 1) >> HNS3_MAX_BD_SIZE_OFFSET;
++	frag_buf_num = hns3_tx_bd_count(size);
+ 	sizeoflast = size % HNS3_MAX_BD_SIZE;
+ 	sizeoflast = sizeoflast ? sizeoflast : HNS3_MAX_BD_SIZE;
+ 
+@@ -2764,9 +2772,13 @@ bool hns3_is_phys_func(struct pci_dev *pdev)
+ 	case HNAE3_DEV_ID_50GE_RDMA:
+ 	case HNAE3_DEV_ID_50GE_RDMA_MACSEC:
+ 	case HNAE3_DEV_ID_100G_RDMA_MACSEC:
++	case HNAE3_DEV_ID_100G_ROH:
++	case HNAE3_DEV_ID_200G_RDMA:
++	case HNAE3_DEV_ID_200G_ROH:
++	case HNAE3_DEV_ID_400G_ROH:
+ 		return true;
+-	case HNAE3_DEV_ID_100G_VF:
+-	case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
++	case HNAE3_DEV_ID_VF:
++	case HNAE3_DEV_ID_RDMA_DCB_PFC_VF:
+ 		return false;
+ 	default:
+ 		dev_warn(&pdev->dev, "un-recognized pci device-id %u",
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+index 16ba7e0d8d71..d7887e49c109 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+@@ -180,7 +180,9 @@ struct hclge_pf_res_cmd {
+ 	__le16 pf_own_fun_number;
+ 	__le16 tx_buf_size;
+ 	__le16 dv_buf_size;
+-	__le32 rsv[2];
++	__le16 ext_tqp_num;
++	__le16 pf_intr_vector_number_roh;
++	u8 rsv[4];
+ };
+ 
+ #define HCLGE_CFG_OFFSET_S	0
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+index cf3bbfa2bac5..4d927e327c23 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+@@ -1935,6 +1935,8 @@ static int hclge_dbg_dump_interrupt(struct hclge_dev *hdev, char *buf, int len)
+ 			 hdev->num_nic_msi);
+ 	pos += scnprintf(buf + pos, len - pos, "num_roce_msi: %u\n",
+ 			 hdev->num_roce_msi);
++	pos += scnprintf(buf + pos, len - pos, "num_roh_msi: %u\n",
++			 hdev->num_roh_msi);
+ 	pos += scnprintf(buf + pos, len - pos, "num_msi_used: %u\n",
+ 			 hdev->num_msi_used);
+ 	pos += scnprintf(buf + pos, len - pos, "num_msi_left: %u\n",
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index 827d0e63ac1c..bcc28501475d 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -89,7 +89,10 @@ static const struct pci_device_id ae_algo_pci_tbl[] = {
+ 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
+ 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
+ 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_ROH), 0},
+ 	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_RDMA), 0},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_200G_ROH), 0},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_400G_ROH), 0},
+ 	/* required last entry */
+ 	{0, }
+ };
+@@ -1036,11 +1039,14 @@ static int hclge_query_pf_resource(struct hclge_dev *hdev)
+ 	if (hnae3_dev_roce_supported(hdev)) {
+ 		hdev->num_roce_msi =
+ 			le16_to_cpu(req->pf_intr_vector_number_roce);
++		hdev->num_roh_msi =
++			le16_to_cpu(req->pf_intr_vector_number_roh);
+ 
+ 		/* PF should have NIC vectors and Roce vectors,
+ 		 * NIC vectors are queued before Roce vectors.
+ 		 */
+-		hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi;
++		hdev->num_msi = hdev->num_nic_msi + hdev->num_roce_msi +
++				hdev->num_roh_msi;
+ 	} else {
+ 		hdev->num_msi = hdev->num_nic_msi;
+ 	}
+@@ -2646,6 +2652,25 @@ static int hclge_init_roce_base_info(struct hclge_vport *vport)
+ 	return 0;
+ }
+ 
++static int hclge_init_roh_base_info(struct hclge_vport *vport)
++{
++	struct hnae3_handle *roh = &vport->roh;
++	struct hnae3_handle *nic = &vport->nic;
++	struct hclge_dev *hdev = vport->back;
++
++	if (hdev->num_msi < hdev->num_nic_msi + hdev->num_roce_msi +
++		hdev->num_roh_msi)
++		return -EINVAL;
++
++	roh->rohinfo.netdev = nic->kinfo.netdev;
++	roh->rohinfo.roh_io_base = hdev->hw.hw.io_base;
++
++	roh->pdev = nic->pdev;
++	roh->ae_algo = nic->ae_algo;
++
++	return 0;
++}
++
+ static int hclge_init_msi(struct hclge_dev *hdev)
+ {
+ 	struct pci_dev *pdev = hdev->pdev;
+@@ -5009,6 +5034,8 @@ struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
+ 		return container_of(handle, struct hclge_vport, nic);
+ 	else if (handle->client->type == HNAE3_CLIENT_ROCE)
+ 		return container_of(handle, struct hclge_vport, roce);
++	else if (handle->client->type == HNAE3_CLIENT_ROH)
++		return container_of(handle, struct hclge_vport, roh);
+ 	else
+ 		return container_of(handle, struct hclge_vport, nic);
+ }
+@@ -11323,6 +11350,47 @@ static int hclge_init_roce_client_instance(struct hnae3_ae_dev *ae_dev,
+ 	return ret;
+ }
+ 
++static int hclge_init_roh_client_instance(struct hnae3_ae_dev *ae_dev,
++					  struct hclge_vport *vport)
++{
++	struct hclge_dev *hdev = ae_dev->priv;
++	struct hnae3_client *client;
++	int rst_cnt;
++	int ret;
++
++	if (!hdev->roh_client || !hdev->nic_client)
++		return 0;
++
++	client = hdev->roh_client;
++	ret = hclge_init_roh_base_info(vport);
++	if (ret)
++		return ret;
++
++	rst_cnt = hdev->rst_stats.reset_cnt;
++	ret = client->ops->init_instance(&vport->roh);
++	if (ret)
++		return ret;
++
++	if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) ||
++	    rst_cnt != hdev->rst_stats.reset_cnt) {
++		ret = -EBUSY;
++		goto init_roh_err;
++	}
++
++	set_bit(HCLGE_STATE_ROH_REGISTERED, &hdev->state);
++	hnae3_set_client_init_flag(client, ae_dev, 1);
++
++	return 0;
++
++init_roh_err:
++	while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
++		msleep(HCLGE_WAIT_RESET_DONE);
++
++	hdev->roh_client->ops->uninit_instance(&vport->roh, 0);
++
++	return ret;
++}
++
+ static int hclge_init_client_instance(struct hnae3_client *client,
+ 				      struct hnae3_ae_dev *ae_dev)
+ {
+@@ -11338,6 +11406,14 @@ static int hclge_init_client_instance(struct hnae3_client *client,
+ 		if (ret)
+ 			goto clear_nic;
+ 
++		ret = hclge_init_roh_client_instance(ae_dev, vport);
++		if (ret) {
++			dev_err(&hdev->pdev->dev,
++				"failed to init roh client, ret = %d\n", ret);
++			hdev->roh_client = NULL;
++			vport->roh.client = NULL;
++		}
++
+ 		ret = hclge_init_roce_client_instance(ae_dev, vport);
+ 		if (ret)
+ 			goto clear_roce;
+@@ -11353,6 +11429,15 @@ static int hclge_init_client_instance(struct hnae3_client *client,
+ 		if (ret)
+ 			goto clear_roce;
+ 
++		break;
++	case HNAE3_CLIENT_ROH:
++		hdev->roh_client = client;
++		vport->roh.client = client;
++
++		ret = hclge_init_roh_client_instance(ae_dev, vport);
++		if (ret)
++			goto clear_roh;
++
+ 		break;
+ 	default:
+ 		return -EINVAL;
+@@ -11368,6 +11453,10 @@ static int hclge_init_client_instance(struct hnae3_client *client,
+ 	hdev->roce_client = NULL;
+ 	vport->roce.client = NULL;
+ 	return ret;
++clear_roh:
++	hdev->roh_client = NULL;
++	vport->roh.client = NULL;
++	return ret;
+ }
+ 
+ static void hclge_uninit_client_instance(struct hnae3_client *client,
+@@ -11376,6 +11465,19 @@ static void hclge_uninit_client_instance(struct hnae3_client *client,
+ 	struct hclge_dev *hdev = ae_dev->priv;
+ 	struct hclge_vport *vport = &hdev->vport[0];
+ 
++	if (hdev->roh_client && (client->type == HNAE3_CLIENT_ROH ||
++				 client->type == HNAE3_CLIENT_KNIC)) {
++		clear_bit(HCLGE_STATE_ROH_REGISTERED, &hdev->state);
++		while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
++			msleep(HCLGE_WAIT_RESET_DONE);
++
++		hdev->roh_client->ops->uninit_instance(&vport->roh, 0);
++		hdev->roh_client = NULL;
++		vport->roh.client = NULL;
++	}
++	if (client->type == HNAE3_CLIENT_ROH)
++		return;
++
+ 	if (hdev->roce_client) {
+ 		clear_bit(HCLGE_STATE_ROCE_REGISTERED, &hdev->state);
+ 		while (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 067eb8dcde51..2311dc45ff6e 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -217,6 +217,7 @@ enum HCLGE_DEV_STATE {
+ 	HCLGE_STATE_REMOVING,
+ 	HCLGE_STATE_NIC_REGISTERED,
+ 	HCLGE_STATE_ROCE_REGISTERED,
++	HCLGE_STATE_ROH_REGISTERED,
+ 	HCLGE_STATE_SERVICE_INITED,
+ 	HCLGE_STATE_RST_SERVICE_SCHED,
+ 	HCLGE_STATE_RST_HANDLING,
+@@ -910,6 +911,7 @@ struct hclge_dev {
+ 	int *vector_irq;
+ 	u16 num_nic_msi;	/* Num of nic vectors for this PF */
+ 	u16 num_roce_msi;	/* Num of roce vectors for this PF */
++	u16 num_roh_msi;	/* Num of roh vectors for this PF */
+ 
+ 	unsigned long service_timer_period;
+ 	unsigned long service_timer_previous;
+@@ -926,6 +928,7 @@ struct hclge_dev {
+ 
+ 	struct hnae3_client *nic_client;
+ 	struct hnae3_client *roce_client;
++	struct hnae3_client *roh_client;
+ 
+ #define HCLGE_FLAG_MAIN			BIT(0)
+ #define HCLGE_FLAG_DCB_CAPABLE		BIT(1)
+@@ -1085,6 +1088,7 @@ struct hclge_vport {
+ 	struct hclge_dev *back;  /* Back reference to associated dev */
+ 	struct hnae3_handle nic;
+ 	struct hnae3_handle roce;
++	struct hnae3_handle roh;
+ 
+ 	unsigned long state;
+ 	unsigned long need_notify;
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 271321f02a0e..22f8dfe86df8 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -24,8 +24,8 @@ static struct hnae3_ae_algo ae_algovf;
+ static struct workqueue_struct *hclgevf_wq;
+ 
+ static const struct pci_device_id ae_algovf_pci_tbl[] = {
+-	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
+-	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_VF), 0},
++	{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_RDMA_DCB_PFC_VF), 0},
+ 	/* required last entry */
+ 	{0, }
+ };
+diff --git a/include/net/devlink.h b/include/net/devlink.h
+index a943659a705e..e85e71e7851a 100644
+--- a/include/net/devlink.h
++++ b/include/net/devlink.h
+@@ -37,8 +37,8 @@ struct devlink {
+ 	struct mutex lock;
+ #ifndef __GENKSYMS__
+ 	u8 reload_failed:1,
+-	   reload_enabled:1,
+-	   registered:1;
++	reload_enabled:1,
++	registered:1;
+ #endif
+ 	char priv[0] __aligned(NETDEV_ALIGN);
+ };
+diff --git a/include/uapi/linux/if_ether.h b/include/uapi/linux/if_ether.h
+index 0e706a76418c..d8eff3062de8 100644
+--- a/include/uapi/linux/if_ether.h
++++ b/include/uapi/linux/if_ether.h
+@@ -91,7 +91,7 @@
+ #define ETH_P_802_EX1	0x88B5		/* 802.1 Local Experimental 1.  */
+ #define ETH_P_PREAUTH	0x88C7		/* 802.11 Preauthentication */
+ #define ETH_P_TIPC	0x88CA		/* TIPC 			*/
+-#define ETH_P_LLDP     0x88CC          /* Link Layer Discovery Protocol */
++#define ETH_P_LLDP	0x88CC          /* Link Layer Discovery Protocol */
+ #define ETH_P_MACSEC	0x88E5		/* 802.1ae MACsec */
+ #define ETH_P_8021AH	0x88E7          /* 802.1ah Backbone Service Tag */
+ #define ETH_P_MVRP	0x88F5          /* 802.1Q MVRP                  */
+-- 
+2.34.1
+
diff --git a/patches/0639-net-hns3-Fallback-ethtool-s-modification-of-lane.patch b/patches/0639-net-hns3-Fallback-ethtool-s-modification-of-lane.patch
new file mode 100644
index 0000000..8a4dfa6
--- /dev/null
+++ b/patches/0639-net-hns3-Fallback-ethtool-s-modification-of-lane.patch
@@ -0,0 +1,1000 @@
+From e1a9fa83f9821d0b04c8da94d6f355c54a307541 Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Wed, 15 Nov 2023 11:08:12 +0800
+Subject: [PATCH 278/283] net: hns3: Fallback ethtool's modification of lane
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+--------------------------------
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ Documentation/networking/ethtool-netlink.rst  |  26 -
+ drivers/net/ethernet/hisilicon/hns3/hnae3.h   |  11 +-
+ .../hns3/hns3_common/hclge_comm_cmd.c         |   1 -
+ .../hns3/hns3_common/hclge_comm_cmd.h         |   1 -
+ .../ethernet/hisilicon/hns3/hns3_debugfs.c    |   3 -
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    |  27 +-
+ .../hisilicon/hns3/hns3pf/hclge_main.c        |  22 +-
+ .../hisilicon/hns3/hns3pf/hclge_main.h        |   3 +-
+ .../hisilicon/hns3/hns3pf/hclge_mdio.c        |   2 +-
+ .../hisilicon/hns3/hns3pf/hclge_sysfs.c       |   3 -
+ .../hisilicon/hns3/hns3vf/hclgevf_main.c      |   2 +-
+ include/linux/ethtool.h                       |   6 -
+ include/net/netlink.h                         |   7 -
+ include/uapi/linux/ethtool.h                  |  14 -
+ include/uapi/linux/ethtool_netlink.h          |   3 -
+ net/ethtool/Makefile                          |   2 +-
+ net/ethtool/linkmodes.c                       | 512 ------------------
+ net/ethtool/netlink.h                         |   2 -
+ 18 files changed, 24 insertions(+), 623 deletions(-)
+ delete mode 100644 net/ethtool/linkmodes.c
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+index 01da978de86d..c0c33704aa96 100644
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -224,32 +224,6 @@ an ``ACT_REPLY`` message. Performing an action also triggers a notification
+ 
+ Later sections describe the format and semantics of these messages.
+ 
+-LINKMODES_SET
+-=============
+-
+-Request contents:
+-
+-  ==========================================  ======  ==========================
+-  ``ETHTOOL_A_LINKMODES_HEADER``              nested  request header
+-  ``ETHTOOL_A_LINKMODES_AUTONEG``             u8      autonegotiation status
+-  ``ETHTOOL_A_LINKMODES_OURS``                bitset  advertised link modes
+-  ``ETHTOOL_A_LINKMODES_PEER``                bitset  partner link modes
+-  ``ETHTOOL_A_LINKMODES_SPEED``               u32     link speed (Mb/s)
+-  ``ETHTOOL_A_LINKMODES_DUPLEX``              u8      duplex mode
+-  ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG``    u8      Master/slave port mode
+-  ``ETHTOOL_A_LINKMODES_LANES``               u32     lanes
+-  ==========================================  ======  ==========================
+-
+-``ETHTOOL_A_LINKMODES_OURS`` bit set allows setting advertised link modes. If
+-autonegotiation is on (either set now or kept from before), advertised modes
+-are not changed (no ``ETHTOOL_A_LINKMODES_OURS`` attribute) and at least one
+-of speed, duplex and lanes is specified, kernel adjusts advertised modes to all
+-supported modes matching speed, duplex, lanes or all (whatever is specified).
+-This autoselection is done on ethtool side with ioctl interface, netlink
+-interface is supposed to allow requesting changes without knowing what exactly
+-kernel supports.
+-
+-
+ RINGS_GET
+ =========
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+index 422f50b36c22..a4353ef510dd 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+@@ -104,7 +104,6 @@ enum HNAE3_DEV_CAP_BITS {
+ 	HNAE3_DEV_SUPPORT_MC_MAC_MNG_B,
+ 	HNAE3_DEV_SUPPORT_CQ_B,
+ 	HNAE3_DEV_SUPPORT_FEC_STATS_B,
+-	HNAE3_DEV_SUPPORT_LANE_NUM_B,
+ 	HNAE3_DEV_SUPPORT_WOL_B,
+ 	HNAE3_DEV_SUPPORT_VF_FAULT_B,
+ 	HNAE3_DEV_SUPPORT_NOTIFY_PKT_B,
+@@ -177,17 +176,12 @@ enum HNAE3_DEV_CAP_BITS {
+ #define hnae3_ae_dev_cq_supported(ae_dev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_CQ_B, (ae_dev)->caps)
+ 
+-#define hnae3_ae_dev_lane_num_supported(ae_dev) \
+-	test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)
+-
+ #define hnae3_ae_dev_wol_supported(ae_dev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_WOL_B, (ae_dev)->caps)
+ 
+ #define hnae3_ae_dev_notify_pkt_supported(ae_dev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_NOTIFY_PKT_B, (ae_dev)->caps)
+ 
+-#define hnae3_ae_dev_lane_num_supported(ae_dev) \
+-	test_bit(HNAE3_DEV_SUPPORT_LANE_NUM_B, (ae_dev)->caps)
+ #define hnae3_ae_dev_fec_stats_supported(ae_dev) \
+ 	test_bit(HNAE3_DEV_SUPPORT_FEC_STATS_B, (ae_dev)->caps)
+ #define hnae3_ae_dev_tm_flush_supported(hdev) \
+@@ -626,10 +620,9 @@ struct hnae3_ae_ops {
+ 	void (*client_stop)(struct hnae3_handle *handle);
+ 	int (*get_status)(struct hnae3_handle *handle);
+ 	void (*get_ksettings_an_result)(struct hnae3_handle *handle,
+-					u8 *auto_neg, u32 *speed, u8 *duplex,
+-					u32 *lane_num);
++					u8 *auto_neg, u32 *speed, u8 *duplex);
+ 	int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed,
+-				   u8 duplex, u8 lane_num);
++				   u8 duplex);
+ 
+ 	void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type,
+ 			       u8 *module_type);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+index 78321511798a..756627abd5fe 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.c
+@@ -155,7 +155,6 @@ static const struct hclge_comm_caps_bit_map hclge_pf_cmd_caps[] = {
+ 	{HCLGE_COMM_CAP_GRO_B, HNAE3_DEV_SUPPORT_GRO_B},
+ 	{HCLGE_COMM_CAP_FD_B, HNAE3_DEV_SUPPORT_FD_B},
+ 	{HCLGE_COMM_CAP_FEC_STATS_B, HNAE3_DEV_SUPPORT_FEC_STATS_B},
+-	{HCLGE_COMM_CAP_LANE_NUM_B, HNAE3_DEV_SUPPORT_LANE_NUM_B},
+ 	{HCLGE_COMM_CAP_WOL_B, HNAE3_DEV_SUPPORT_WOL_B},
+ 	{HCLGE_COMM_CAP_NOTIFY_PKT_B, HNAE3_DEV_SUPPORT_NOTIFY_PKT_B},
+ 	{HCLGE_COMM_CAP_TM_FLUSH_B, HNAE3_DEV_SUPPORT_TM_FLUSH_B},
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+index 8477e9f1a3d7..248fab27931b 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_common/hclge_comm_cmd.h
+@@ -344,7 +344,6 @@ enum HCLGE_COMM_CAP_BITS {
+ 	HCLGE_COMM_CAP_GRO_B = 20,
+ 	HCLGE_COMM_CAP_FD_B = 21,
+ 	HCLGE_COMM_CAP_FEC_STATS_B = 25,
+-	HCLGE_COMM_CAP_LANE_NUM_B = 27,
+ 	HCLGE_COMM_CAP_WOL_B = 28,
+ 	HCLGE_COMM_CAP_NOTIFY_PKT_B = 29,
+ 	HCLGE_COMM_CAP_TM_FLUSH_B = 31,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+index c5234d1d078f..23fc3897a662 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
+@@ -391,9 +391,6 @@ static struct hns3_dbg_cap_info hns3_dbg_cap[] = {
+ 	}, {
+ 		.name = "support FEC statistics",
+ 		.cap_bit = HNAE3_DEV_SUPPORT_FEC_STATS_B,
+-	}, {
+-		.name = "support lane num",
+-		.cap_bit = HNAE3_DEV_SUPPORT_LANE_NUM_B,
+ 	}, {
+ 		.name = "support tm flush",
+ 		.cap_bit = HNAE3_DEV_SUPPORT_TM_FLUSH_B,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index 21675ff52380..c951f7c4eea9 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -766,8 +766,7 @@ static void hns3_get_ksettings(struct hnae3_handle *h,
+ 		ops->get_ksettings_an_result(h,
+ 					     &cmd->base.autoneg,
+ 					     &cmd->base.speed,
+-					     &cmd->base.duplex,
+-					     &cmd->lanes);
++					     &cmd->base.duplex);
+ 
+ 	/* 2.get link mode */
+ 	if (ops->get_link_mode)
+@@ -849,7 +848,6 @@ static int hns3_check_ksettings_param(const struct net_device *netdev,
+ 	const struct hnae3_ae_ops *ops = handle->ae_algo->ops;
+ 	u8 module_type = HNAE3_MODULE_TYPE_UNKNOWN;
+ 	u8 media_type = HNAE3_MEDIA_TYPE_UNKNOWN;
+-	u32 lane_num;
+ 	u8 autoneg;
+ 	u32 speed;
+ 	u8 duplex;
+@@ -862,10 +860,9 @@ static int hns3_check_ksettings_param(const struct net_device *netdev,
+ 		return 0;
+ 
+ 	if (ops->get_ksettings_an_result) {
+-		ops->get_ksettings_an_result(handle, &autoneg, &speed,
+-						&duplex, &lane_num);
++		ops->get_ksettings_an_result(handle, &autoneg, &speed, &duplex);
+ 		if (cmd->base.autoneg == autoneg && cmd->base.speed == speed &&
+-		    cmd->base.duplex == duplex && cmd->lanes == lane_num)
++		    cmd->base.duplex == duplex)
+ 			return 0;
+ 	}
+ 
+@@ -902,14 +899,12 @@ static int hns3_set_link_ksettings(struct net_device *netdev,
+ 	if (cmd->base.speed == SPEED_1000 && cmd->base.duplex == DUPLEX_HALF)
+ 		return -EINVAL;
+ 
+-	if (cmd->lanes && !hnae3_ae_dev_lane_num_supported(ae_dev))
+-		return -EOPNOTSUPP;
+-
+-	netif_dbg(handle, drv, netdev,
+-		  "set link(%s): autoneg=%u, speed=%u, duplex=%u, lanes=%u\n",
+-		  netdev->phydev ? "phy" : "mac",
+-		  cmd->base.autoneg, cmd->base.speed, cmd->base.duplex,
+-		  cmd->lanes);
++	if (netif_msg_ifdown(handle))
++		netdev_info(netdev,
++			    "set link(%s): autoneg=%u, speed=%u, duplex=%u\n",
++			    netdev->phydev ? "phy" : "mac",
++			    cmd->base.autoneg, cmd->base.speed,
++			    cmd->base.duplex);
+ 
+ 	/* Only support ksettings_set for netdev with phy attached for now */
+ 	if (netdev->phydev) {
+@@ -947,8 +942,7 @@ static int hns3_set_link_ksettings(struct net_device *netdev,
+ 
+ 	if (ops->cfg_mac_speed_dup_h)
+ 		ret = ops->cfg_mac_speed_dup_h(handle, cmd->base.speed,
+-					       cmd->base.duplex,
+-						   (u8)(cmd->lanes));
++					       cmd->base.duplex);
+ 
+ 	return ret;
+ }
+@@ -2050,7 +2044,6 @@ static const struct ethtool_ops hns3vf_ethtool_ops = {
+ static const struct ethtool_ops hns3_ethtool_ops = {
+ 	.supported_coalesce_params = HNS3_ETHTOOL_COALESCE,
+ 	.supported_ring_params = HNS3_ETHTOOL_RING,
+-	.cap_link_lanes_supported = true,
+ 	.self_test = hns3_self_test,
+ 	.get_drvinfo = hns3_get_drvinfo,
+ 	.get_link = hns3_get_link,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+index bcc28501475d..0e24115ad161 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+@@ -2792,37 +2792,33 @@ int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
+ 	return 0;
+ }
+ 
+-int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed,
+-			    u8 duplex, u8 lane_num)
++int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
+ {
+ 	struct hclge_mac *mac = &hdev->hw.mac;
+ 	int ret;
+ 
+ 	duplex = hclge_check_speed_dup(duplex, speed);
+ 	if (!mac->support_autoneg && mac->speed == speed &&
+-	    mac->duplex == duplex &&
+-		(mac->lane_num == lane_num || lane_num == 0))
++	    mac->duplex == duplex)
+ 		return 0;
+ 
+-	ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, lane_num);
++	ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex, 0);
+ 	if (ret)
+ 		return ret;
+ 
+ 	hdev->hw.mac.speed = speed;
+ 	hdev->hw.mac.duplex = duplex;
+-	if (!lane_num)
+-		hdev->hw.mac.lane_num = lane_num;
+ 
+ 	return 0;
+ }
+ 
+ static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
+-				     u8 duplex, u8 lane_num)
++				     u8 duplex)
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+ 
+-	return hclge_cfg_mac_speed_dup(hdev, speed, duplex, lane_num);
++	return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
+ }
+ 
+ static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
+@@ -3633,13 +3629,13 @@ static int hclge_update_port_info(struct hclge_dev *hdev)
+ 			return 0;
+ 		}
+ 		return hclge_cfg_mac_speed_dup(hdev, mac->speed,
+-					       HCLGE_MAC_FULL, mac->lane_num);
++					       HCLGE_MAC_FULL);
+ 	} else {
+ 		if (speed == HCLGE_MAC_SPEED_UNKNOWN)
+ 			return 0; /* do nothing if no SFP */
+ 
+ 		/* must config full duplex for SFP */
+-		return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL, 0);
++		return hclge_cfg_mac_speed_dup(hdev, speed, HCLGE_MAC_FULL);
+ 	}
+ }
+ 
+@@ -11139,7 +11135,7 @@ static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
+ 
+ static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
+ 					  u8 *auto_neg, u32 *speed,
+-					  u8 *duplex, u32 *lane_num)
++					  u8 *duplex)
+ {
+ 	struct hclge_vport *vport = hclge_get_vport(handle);
+ 	struct hclge_dev *hdev = vport->back;
+@@ -11150,8 +11146,6 @@ static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
+ 		*duplex = hdev->hw.mac.duplex;
+ 	if (auto_neg)
+ 		*auto_neg = hdev->hw.mac.autoneg;
+-	if (lane_num)
+-		*lane_num = hdev->hw.mac.lane_num;
+ }
+ 
+ void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+index 2311dc45ff6e..be2f888209f3 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+@@ -1153,8 +1153,7 @@ static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
+ }
+ 
+ int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
+-int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed,
+-			    u8 duplex, u8 lane_num);
++int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
+ int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
+ 			  u16 vlan_id, bool is_kill);
+ int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+index 11723c13c96a..79e6760b3fc7 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
+@@ -187,7 +187,7 @@ static void hclge_mac_adjust_link(struct net_device *netdev)
+ 	speed = netdev->phydev->speed;
+ 	duplex = netdev->phydev->duplex;
+ 
+-	ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex, 0);
++	ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
+ 	if (ret)
+ 		netdev_err(netdev, "failed to adjust link.\n");
+ 
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c
+index 6840d7bda82e..3bbc33761254 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_sysfs.c
+@@ -78,9 +78,6 @@ int hclge_register_sysfs(struct hclge_dev *hdev)
+ {
+ 	int ret;
+ 
+-	if (!hnae3_ae_dev_lane_num_supported(hdev->ae_dev))
+-		return 0;
+-
+ 	ret = device_create_file(&hdev->pdev->dev, hclge_hw_attrs_list[0]);
+ 	if (ret)
+ 		dev_err(&hdev->pdev->dev,
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+index 22f8dfe86df8..091240208893 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+@@ -3649,7 +3649,7 @@ static int hclgevf_get_status(struct hnae3_handle *handle)
+ 
+ static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
+ 					    u8 *auto_neg, u32 *speed,
+-					    u8 *duplex, u32 *lane_num)
++					    u8 *duplex)
+ {
+ 	struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
+ 
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 4bc3cd4060da..bf14a439afc2 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -149,9 +149,6 @@ struct ethtool_link_ksettings {
+ 		__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
+ 		__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising);
+ 	} link_modes;
+-#ifndef __GENKSYMS__
+-	u32	lanes;
+-#endif
+ };
+ 
+ /**
+@@ -295,8 +292,6 @@ struct ethtool_fec_stats {
+ 
+ /**
+  * struct ethtool_ops - optional netdev operations
+- * @cap_link_lanes_supported: indicates if the driver supports lanes
+- *	parameter.
+  * @supported_coalesce_params: supported types of interrupt coalescing.
+  * @supported_ring_params: supported ring params.
+  * @get_drvinfo: Report driver/device information.  Should only set the
+@@ -442,7 +437,6 @@ struct ethtool_fec_stats {
+  */
+ struct ethtool_ops {
+ #ifndef __GENKSYMS__
+-	u32     cap_link_lanes_supported:1;
+ 	u32     supported_coalesce_params;
+ 	u32     supported_ring_params;
+ #endif
+diff --git a/include/net/netlink.h b/include/net/netlink.h
+index e91076f81d3e..d9c642558255 100644
+--- a/include/net/netlink.h
++++ b/include/net/netlink.h
+@@ -278,13 +278,6 @@ struct nla_policy {
+ 		      tp == NLA_MSECS ||		\
+ 		      tp == NLA_BINARY) + tp)
+ 
+-#define NLA_POLICY_RANGE(tp, _min, _max) {		 \
+-	.type = NLA_ENSURE_INT_OR_BINARY_TYPE(tp),		\
+-	.validation_type = NLA_VALIDATE_RANGE,		\
+-	.min = _min,				\
+-	.max = _max					\
+-}
+-
+ #define NLA_POLICY_MIN(tp, _min) {			\
+ 	.type = NLA_ENSURE_INT_OR_BINARY_TYPE(tp),	\
+ 	.validation_type = NLA_VALIDATE_MIN,		\
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index 4f19dca5fcfa..0649b8295feb 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -1742,8 +1742,6 @@ enum ethtool_link_mode_bit_indices {
+ #define SPEED_50000		50000
+ #define SPEED_56000		56000
+ #define SPEED_100000		100000
+-#define SPEED_200000		200000
+-#define SPEED_400000		400000
+ 
+ #define SPEED_UNKNOWN		-1
+ 
+@@ -1769,18 +1767,6 @@ static inline int ethtool_validate_duplex(__u8 duplex)
+ 	return 0;
+ }
+ 
+-#define MASTER_SLAVE_CFG_UNSUPPORTED			0
+-#define MASTER_SLAVE_CFG_UNKNOWN 				1
+-#define MASTER_SLAVE_CFG_MASTER_PREFERRED		2
+-#define MASTER_SLAVE_CFG_SLAVE_PREFERRED		3
+-#define MASTER_SLAVE_CFG_MASTER_FORCE			4
+-#define MASTER_SLAVE_CFG_SLAVE_FORCE			5
+-#define MASTER_SLAVE_STATE_UNSUPPORTED			0
+-#define MASTER_SLAVE_STATE_UNKNOWN				1
+-#define MASTER_SLAVE_STATE_MASTER				2
+-#define MASTER_SLAVE_STATE_SLAVE				3
+-#define MASTER_SLAVE_STATE_ERR					4
+-
+ /* Which connector port. */
+ #define PORT_TP			0x00
+ #define PORT_AUI		0x01
+diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
+index 3b7ed0fe545a..a616a033c5be 100644
+--- a/include/uapi/linux/ethtool_netlink.h
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -203,9 +203,6 @@ enum {
+ 	ETHTOOL_A_LINKMODES_PEER,		/* bitset */
+ 	ETHTOOL_A_LINKMODES_SPEED,		/* u32 */
+ 	ETHTOOL_A_LINKMODES_DUPLEX,		/* u8 */
+-	ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG,	/* u8 */
+-	ETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE,	/* u8 */
+-	ETHTOOL_A_LINKMODES_LANES,		/* u32 */
+ 
+ 	/* add new constants above here */
+ 	__ETHTOOL_A_LINKMODES_CNT,
+diff --git a/net/ethtool/Makefile b/net/ethtool/Makefile
+index 8900e8ff22f8..892eb657f722 100644
+--- a/net/ethtool/Makefile
++++ b/net/ethtool/Makefile
+@@ -4,4 +4,4 @@ obj-y				+= ioctl.o common.o
+ 
+ obj-$(CONFIG_ETHTOOL_NETLINK)	+= ethtool_nl.o
+ 
+-ethtool_nl-y	:= netlink.o rings.o linkmodes.o bitset.o fec.o
+\ No newline at end of file
++ethtool_nl-y	:= netlink.o rings.o bitset.o fec.o
+diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c
+deleted file mode 100644
+index f8f3fc74ac78..000000000000
+--- a/net/ethtool/linkmodes.c
++++ /dev/null
+@@ -1,512 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-only
+-
+-#include "netlink.h"
+-#include "common.h"
+-#include "bitset.h"
+-
+-struct linkmodes_req_info {
+-	struct ethnl_req_info		base;
+-};
+-
+-struct linkmodes_reply_data {
+-	struct ethnl_reply_data		base;
+-	struct ethtool_link_ksettings	ksettings;
+-	struct ethtool_link_settings	*lsettings;
+-	bool				peer_empty;
+-};
+-
+-#define LINKMODES_REPDATA(__reply_base) \
+-	container_of(__reply_base, struct linkmodes_reply_data, base)
+-
+-const struct nla_policy ethnl_linkmodes_get_policy[] = {
+-	[ETHTOOL_A_LINKMODES_HEADER]		=
+-		NLA_POLICY_NESTED(ethnl_header_policy),
+-};
+-
+-static int linkmodes_prepare_data(const struct ethnl_req_info *req_base,
+-				  struct ethnl_reply_data *reply_base,
+-				  struct genl_info *info)
+-{
+-	struct linkmodes_reply_data *data = LINKMODES_REPDATA(reply_base);
+-	struct net_device *dev = reply_base->dev;
+-	int ret;
+-
+-	data->lsettings = &data->ksettings.base;
+-
+-	ret = ethnl_ops_begin(dev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = __ethtool_get_link_ksettings(dev, &data->ksettings);
+-	if (ret < 0 && info) {
+-		GENL_SET_ERR_MSG(info, "failed to retrieve link settings");
+-		goto out;
+-	}
+-
+-	data->peer_empty =
+-		bitmap_empty(data->ksettings.link_modes.lp_advertising,
+-			     __ETHTOOL_LINK_MODE_MASK_NBITS);
+-
+-out:
+-	ethnl_ops_complete(dev);
+-	return ret;
+-}
+-
+-static int linkmodes_reply_size(const struct ethnl_req_info *req_base,
+-				const struct ethnl_reply_data *reply_base)
+-{
+-	const struct linkmodes_reply_data *data = LINKMODES_REPDATA(reply_base);
+-	const struct ethtool_link_ksettings *ksettings = &data->ksettings;
+-	const struct ethtool_link_settings *lsettings = &ksettings->base;
+-	bool compact = req_base->flags & ETHTOOL_FLAG_COMPACT_BITSETS;
+-	int len, ret;
+-
+-	len = nla_total_size(sizeof(u8)) /* LINKMODES_AUTONEG */
+-		+ nla_total_size(sizeof(u32)) /* LINKMODES_SPEED */
+-		+ nla_total_size(sizeof(u8)) /* LINKMODES_DUPLEX */
+-		+ 0;
+-	ret = ethnl_bitset_size(ksettings->link_modes.advertising,
+-				ksettings->link_modes.supported,
+-				__ETHTOOL_LINK_MODE_MASK_NBITS,
+-				link_mode_names, compact);
+-	if (ret < 0)
+-		return ret;
+-	len += ret;
+-	if (!data->peer_empty) {
+-		ret = ethnl_bitset_size(ksettings->link_modes.lp_advertising,
+-					NULL, __ETHTOOL_LINK_MODE_MASK_NBITS,
+-					link_mode_names, compact);
+-		if (ret < 0)
+-			return ret;
+-		len += ret;
+-	}
+-
+-	if (lsettings->master_slave_cfg != MASTER_SLAVE_CFG_UNSUPPORTED)
+-		len += nla_total_size(sizeof(u8));
+-
+-	if (lsettings->master_slave_state != MASTER_SLAVE_STATE_UNSUPPORTED)
+-		len += nla_total_size(sizeof(u8));
+-
+-	return len;
+-}
+-
+-static int linkmodes_fill_reply(struct sk_buff *skb,
+-				const struct ethnl_req_info *req_base,
+-				const struct ethnl_reply_data *reply_base)
+-{
+-	const struct linkmodes_reply_data *data = LINKMODES_REPDATA(reply_base);
+-	const struct ethtool_link_ksettings *ksettings = &data->ksettings;
+-	const struct ethtool_link_settings *lsettings = &ksettings->base;
+-	bool compact = req_base->flags & ETHTOOL_FLAG_COMPACT_BITSETS;
+-	int ret;
+-
+-	if (nla_put_u8(skb, ETHTOOL_A_LINKMODES_AUTONEG, lsettings->autoneg))
+-		return -EMSGSIZE;
+-
+-	ret = ethnl_put_bitset(skb, ETHTOOL_A_LINKMODES_OURS,
+-			       ksettings->link_modes.advertising,
+-			       ksettings->link_modes.supported,
+-			       __ETHTOOL_LINK_MODE_MASK_NBITS, link_mode_names,
+-			       compact);
+-	if (ret < 0)
+-		return -EMSGSIZE;
+-	if (!data->peer_empty) {
+-		ret = ethnl_put_bitset(skb, ETHTOOL_A_LINKMODES_PEER,
+-				       ksettings->link_modes.lp_advertising,
+-				       NULL, __ETHTOOL_LINK_MODE_MASK_NBITS,
+-				       link_mode_names, compact);
+-		if (ret < 0)
+-			return -EMSGSIZE;
+-	}
+-
+-	if (nla_put_u32(skb, ETHTOOL_A_LINKMODES_SPEED, lsettings->speed) ||
+-	    nla_put_u8(skb, ETHTOOL_A_LINKMODES_DUPLEX, lsettings->duplex))
+-		return -EMSGSIZE;
+-
+-	if (lsettings->master_slave_cfg != MASTER_SLAVE_CFG_UNSUPPORTED &&
+-	    nla_put_u8(skb, ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG,
+-		       lsettings->master_slave_cfg))
+-		return -EMSGSIZE;
+-
+-	if (lsettings->master_slave_state != MASTER_SLAVE_STATE_UNSUPPORTED &&
+-	    nla_put_u8(skb, ETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE,
+-		       lsettings->master_slave_state))
+-		return -EMSGSIZE;
+-
+-	return 0;
+-}
+-
+-const struct ethnl_request_ops ethnl_linkmodes_request_ops = {
+-	.request_cmd		= ETHTOOL_MSG_LINKMODES_GET,
+-	.reply_cmd		= ETHTOOL_MSG_LINKMODES_GET_REPLY,
+-	.hdr_attr		= ETHTOOL_A_LINKMODES_HEADER,
+-	.req_info_size		= sizeof(struct linkmodes_req_info),
+-	.reply_data_size	= sizeof(struct linkmodes_reply_data),
+-
+-	.prepare_data		= linkmodes_prepare_data,
+-	.reply_size		= linkmodes_reply_size,
+-	.fill_reply		= linkmodes_fill_reply,
+-};
+-
+-/* LINKMODES_SET */
+-
+-struct link_mode_info {
+-	int				speed;
+-	u8				lanes;
+-	u8				duplex;
+-};
+-
+-#define __LINK_MODE_LANES_CR		1
+-#define __LINK_MODE_LANES_CR2		2
+-#define __LINK_MODE_LANES_CR4		4
+-#define __LINK_MODE_LANES_CR8		8
+-#define __LINK_MODE_LANES_DR		1
+-#define __LINK_MODE_LANES_DR2		2
+-#define __LINK_MODE_LANES_DR4		4
+-#define __LINK_MODE_LANES_DR8		8
+-#define __LINK_MODE_LANES_KR		1
+-#define __LINK_MODE_LANES_KR2		2
+-#define __LINK_MODE_LANES_KR4		4
+-#define __LINK_MODE_LANES_KR8		8
+-#define __LINK_MODE_LANES_SR		1
+-#define __LINK_MODE_LANES_SR2		2
+-#define __LINK_MODE_LANES_SR4		4
+-#define __LINK_MODE_LANES_SR8		8
+-#define __LINK_MODE_LANES_ER		1
+-#define __LINK_MODE_LANES_KX		1
+-#define __LINK_MODE_LANES_KX4		4
+-#define __LINK_MODE_LANES_LR		1
+-#define __LINK_MODE_LANES_LR4		4
+-#define __LINK_MODE_LANES_LR4_ER4	4
+-#define __LINK_MODE_LANES_LR_ER_FR	1
+-#define __LINK_MODE_LANES_LR2_ER2_FR2	2
+-#define __LINK_MODE_LANES_LR4_ER4_FR4	4
+-#define __LINK_MODE_LANES_LR8_ER8_FR8	8
+-#define __LINK_MODE_LANES_LRM		1
+-#define __LINK_MODE_LANES_MLD2		2
+-#define __LINK_MODE_LANES_T		1
+-#define __LINK_MODE_LANES_T1		1
+-#define __LINK_MODE_LANES_X		1
+-#define __LINK_MODE_LANES_FX		1
+-
+-#define __DEFINE_LINK_MODE_PARAMS(_speed, _type, _duplex)	\
+-	[ETHTOOL_LINK_MODE(_speed, _type, _duplex)] = {		\
+-		.speed  = SPEED_ ## _speed, \
+-		.lanes  = __LINK_MODE_LANES_ ## _type, \
+-		.duplex	= __DUPLEX_ ## _duplex \
+-	}
+-#define __DUPLEX_Half DUPLEX_HALF
+-#define __DUPLEX_Full DUPLEX_FULL
+-#define __DEFINE_SPECIAL_MODE_PARAMS(_mode) \
+-	[ETHTOOL_LINK_MODE_ ## _mode ## _BIT] = { \
+-		.speed	= SPEED_UNKNOWN, \
+-		.lanes	= 0, \
+-		.duplex	= DUPLEX_UNKNOWN, \
+-	}
+-
+-static const struct link_mode_info link_mode_params[] = {
+-	__DEFINE_LINK_MODE_PARAMS(10, T, Half),
+-	__DEFINE_LINK_MODE_PARAMS(10, T, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100, T, Half),
+-	__DEFINE_LINK_MODE_PARAMS(100, T, Full),
+-	__DEFINE_LINK_MODE_PARAMS(1000, T, Half),
+-	__DEFINE_LINK_MODE_PARAMS(1000, T, Full),
+-	__DEFINE_SPECIAL_MODE_PARAMS(Autoneg),
+-	__DEFINE_SPECIAL_MODE_PARAMS(TP),
+-	__DEFINE_SPECIAL_MODE_PARAMS(AUI),
+-	__DEFINE_SPECIAL_MODE_PARAMS(MII),
+-	__DEFINE_SPECIAL_MODE_PARAMS(FIBRE),
+-	__DEFINE_SPECIAL_MODE_PARAMS(BNC),
+-	__DEFINE_LINK_MODE_PARAMS(10000, T, Full),
+-	__DEFINE_SPECIAL_MODE_PARAMS(Pause),
+-	__DEFINE_SPECIAL_MODE_PARAMS(Asym_Pause),
+-	__DEFINE_LINK_MODE_PARAMS(2500, X, Full),
+-	__DEFINE_SPECIAL_MODE_PARAMS(Backplane),
+-	__DEFINE_LINK_MODE_PARAMS(1000, KX, Full),
+-	__DEFINE_LINK_MODE_PARAMS(10000, KX4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(10000, KR, Full),
+-	[ETHTOOL_LINK_MODE_10000baseR_FEC_BIT] = {
+-		.speed	= SPEED_10000,
+-		.duplex = DUPLEX_FULL,
+-	},
+-	__DEFINE_LINK_MODE_PARAMS(20000, MLD2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(20000, KR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(40000, KR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(40000, CR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(40000, SR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(40000, LR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(56000, KR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(56000, CR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(56000, SR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(56000, LR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(25000, CR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(25000, KR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(25000, SR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(50000, CR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(50000, KR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, KR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, SR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, CR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, LR4_ER4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(50000, SR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(1000, X, Full),
+-	__DEFINE_LINK_MODE_PARAMS(10000, CR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(10000, SR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(10000, LR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(10000, LRM, Full),
+-	__DEFINE_LINK_MODE_PARAMS(10000, ER, Full),
+-	__DEFINE_LINK_MODE_PARAMS(2500, T, Full),
+-	__DEFINE_LINK_MODE_PARAMS(5000, T, Full),
+-	__DEFINE_SPECIAL_MODE_PARAMS(FEC_NONE),
+-	__DEFINE_SPECIAL_MODE_PARAMS(FEC_RS),
+-	__DEFINE_SPECIAL_MODE_PARAMS(FEC_BASER),
+-	__DEFINE_LINK_MODE_PARAMS(50000, KR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(50000, SR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(50000, CR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(50000, LR_ER_FR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(50000, DR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, KR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, SR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, CR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, LR2_ER2_FR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, DR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(200000, KR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(200000, SR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(200000, LR4_ER4_FR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(200000, DR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(200000, CR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100, T1, Full),
+-	__DEFINE_LINK_MODE_PARAMS(1000, T1, Full),
+-	__DEFINE_LINK_MODE_PARAMS(400000, KR8, Full),
+-	__DEFINE_LINK_MODE_PARAMS(400000, SR8, Full),
+-	__DEFINE_LINK_MODE_PARAMS(400000, LR8_ER8_FR8, Full),
+-	__DEFINE_LINK_MODE_PARAMS(400000, DR8, Full),
+-	__DEFINE_LINK_MODE_PARAMS(400000, CR8, Full),
+-	__DEFINE_SPECIAL_MODE_PARAMS(FEC_LLRS),
+-	__DEFINE_LINK_MODE_PARAMS(100000, KR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, SR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, LR_ER_FR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, DR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100000, CR, Full),
+-	__DEFINE_LINK_MODE_PARAMS(200000, KR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(200000, SR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(200000, LR2_ER2_FR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(200000, DR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(200000, CR2, Full),
+-	__DEFINE_LINK_MODE_PARAMS(400000, KR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(400000, SR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(400000, LR4_ER4_FR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(400000, DR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(400000, CR4, Full),
+-	__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
+-	__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
+-};
+-
+-const struct nla_policy ethnl_linkmodes_set_policy[] = {
+-	[ETHTOOL_A_LINKMODES_HEADER]		=
+-		NLA_POLICY_NESTED(ethnl_header_policy),
+-	[ETHTOOL_A_LINKMODES_AUTONEG]		= { .type = NLA_U8 },
+-	[ETHTOOL_A_LINKMODES_OURS]		= { .type = NLA_NESTED },
+-	[ETHTOOL_A_LINKMODES_SPEED]		= { .type = NLA_U32 },
+-	[ETHTOOL_A_LINKMODES_DUPLEX]		= { .type = NLA_U8 },
+-	[ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG]	= { .type = NLA_U8 },
+-	[ETHTOOL_A_LINKMODES_LANES]		=
+-		NLA_POLICY_RANGE(NLA_U32, 1, 8),
+-};
+-
+-/* Set advertised link modes to all supported modes matching requested speed,
+- * lanes and duplex values. Called when autonegotiation is on, speed, lanes or
+- * duplex is requested but no link mode change. This is done in userspace with
+- * ioctl() interface, move it into kernel for netlink.
+- * Returns true if advertised modes bitmap was modified.
+- */
+-static bool ethnl_auto_linkmodes(struct ethtool_link_ksettings *ksettings,
+-				 bool req_speed, bool req_lanes,
+-				 bool req_duplex)
+-{
+-	unsigned long *advertising = ksettings->link_modes.advertising;
+-	unsigned long *supported = ksettings->link_modes.supported;
+-	DECLARE_BITMAP(old_adv, __ETHTOOL_LINK_MODE_MASK_NBITS);
+-	unsigned int i;
+-
+-	BUILD_BUG_ON(ARRAY_SIZE(link_mode_params) !=
+-		     __ETHTOOL_LINK_MODE_MASK_NBITS);
+-
+-	bitmap_copy(old_adv, advertising, __ETHTOOL_LINK_MODE_MASK_NBITS);
+-
+-	for (i = 0; i < __ETHTOOL_LINK_MODE_MASK_NBITS; i++) {
+-		const struct link_mode_info *info = &link_mode_params[i];
+-
+-		if (info->speed == SPEED_UNKNOWN)
+-			continue;
+-		if (test_bit(i, supported) &&
+-		    (!req_speed || info->speed == ksettings->base.speed) &&
+-		    (!req_lanes || info->lanes == ksettings->lanes) &&
+-		    (!req_duplex || info->duplex == ksettings->base.duplex))
+-			set_bit(i, advertising);
+-		else
+-			clear_bit(i, advertising);
+-	}
+-
+-	return !bitmap_equal(old_adv, advertising,
+-			     __ETHTOOL_LINK_MODE_MASK_NBITS);
+-}
+-
+-static bool ethnl_validate_master_slave_cfg(u8 cfg)
+-{
+-	switch (cfg) {
+-	case MASTER_SLAVE_CFG_MASTER_PREFERRED:
+-	case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
+-	case MASTER_SLAVE_CFG_MASTER_FORCE:
+-	case MASTER_SLAVE_CFG_SLAVE_FORCE:
+-		return true;
+-	}
+-
+-	return false;
+-}
+-
+-static int ethnl_check_linkmodes(struct genl_info *info, struct nlattr **tb)
+-{
+-	const struct nlattr *master_slave_cfg, *lanes_cfg;
+-
+-	master_slave_cfg = tb[ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG];
+-	if (master_slave_cfg &&
+-	    !ethnl_validate_master_slave_cfg(nla_get_u8(master_slave_cfg))) {
+-		NL_SET_ERR_MSG_ATTR(info->extack, master_slave_cfg,
+-				    "master/slave value is invalid");
+-		return -EOPNOTSUPP;
+-	}
+-
+-	lanes_cfg = tb[ETHTOOL_A_LINKMODES_LANES];
+-	if (lanes_cfg && !is_power_of_2(nla_get_u32(lanes_cfg))) {
+-		NL_SET_ERR_MSG_ATTR(info->extack, lanes_cfg,
+-				    "lanes value is invalid");
+-		return -EINVAL;
+-	}
+-
+-	return 0;
+-}
+-
+-static int ethnl_update_linkmodes(struct genl_info *info, struct nlattr **tb,
+-				  struct ethtool_link_ksettings *ksettings,
+-				  bool *mod, const struct net_device *dev)
+-{
+-	struct ethtool_link_settings *lsettings = &ksettings->base;
+-	bool req_speed, req_lanes, req_duplex;
+-	const struct nlattr *master_slave_cfg, *lanes_cfg;
+-	int ret;
+-
+-	master_slave_cfg = tb[ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG];
+-	if (master_slave_cfg) {
+-		if (lsettings->master_slave_cfg == MASTER_SLAVE_CFG_UNSUPPORTED) {
+-			NL_SET_ERR_MSG_ATTR(info->extack, master_slave_cfg,
+-					    "master/slave configuration not supported by device");
+-			return -EOPNOTSUPP;
+-		}
+-	}
+-
+-	*mod = false;
+-	req_speed = tb[ETHTOOL_A_LINKMODES_SPEED];
+-	req_lanes = tb[ETHTOOL_A_LINKMODES_LANES];
+-	req_duplex = tb[ETHTOOL_A_LINKMODES_DUPLEX];
+-
+-	ethnl_update_u8(&lsettings->autoneg, tb[ETHTOOL_A_LINKMODES_AUTONEG],
+-			mod);
+-
+-	lanes_cfg = tb[ETHTOOL_A_LINKMODES_LANES];
+-	if (lanes_cfg) {
+-		/* If autoneg is off and lanes parameter is
+-		 * not supported by the driver,
+-		 * return an error.
+-		 */
+-		if (!lsettings->autoneg &&
+-		    !dev->ethtool_ops->cap_link_lanes_supported) {
+-			NL_SET_ERR_MSG_ATTR(info->extack, lanes_cfg,
+-					    "lanes configuration not supported by device");
+-			return -EOPNOTSUPP;
+-		}
+-	} else if (!lsettings->autoneg && ksettings->lanes) {
+-		/* If autoneg is off and lanes parameter is not passed from user but
+-		 * it was defined previously then set the lanes parameter to 0.
+-		 */
+-		ksettings->lanes = 0;
+-		*mod = true;
+-	}
+-
+-	ret = ethnl_update_bitset(ksettings->link_modes.advertising,
+-				  __ETHTOOL_LINK_MODE_MASK_NBITS,
+-				  tb[ETHTOOL_A_LINKMODES_OURS], link_mode_names,
+-				  info->extack, mod);
+-	if (ret < 0)
+-		return ret;
+-	ethnl_update_u32(&lsettings->speed, tb[ETHTOOL_A_LINKMODES_SPEED],
+-			 mod);
+-	ethnl_update_u32(&ksettings->lanes, lanes_cfg, mod);
+-	ethnl_update_u8(&lsettings->duplex, tb[ETHTOOL_A_LINKMODES_DUPLEX],
+-			mod);
+-	ethnl_update_u8(&lsettings->master_slave_cfg, master_slave_cfg, mod);
+-
+-	if (!tb[ETHTOOL_A_LINKMODES_OURS] && lsettings->autoneg &&
+-	    (req_speed || req_lanes || req_duplex) &&
+-	    ethnl_auto_linkmodes(ksettings, req_speed, req_lanes, req_duplex))
+-		*mod = true;
+-
+-	return 0;
+-}
+-
+-int ethnl_set_linkmodes(struct sk_buff *skb, struct genl_info *info)
+-{
+-	struct ethtool_link_ksettings ksettings = {};
+-	struct ethnl_req_info req_info = {};
+-	struct nlattr **tb = info->attrs;
+-	struct net_device *dev;
+-	bool mod = false;
+-	int ret;
+-
+-	ret = ethnl_check_linkmodes(info, tb);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = ethnl_parse_header_dev_get(&req_info,
+-					 tb[ETHTOOL_A_LINKMODES_HEADER],
+-					 genl_info_net(info), info->extack,
+-					 true);
+-	if (ret < 0)
+-		return ret;
+-	dev = req_info.dev;
+-	ret = -EOPNOTSUPP;
+-	if (!dev->ethtool_ops->get_link_ksettings ||
+-	    !dev->ethtool_ops->set_link_ksettings)
+-		goto out_dev;
+-
+-	rtnl_lock();
+-	ret = ethnl_ops_begin(dev);
+-	if (ret < 0)
+-		goto out_rtnl;
+-
+-	ret = __ethtool_get_link_ksettings(dev, &ksettings);
+-	if (ret < 0) {
+-		GENL_SET_ERR_MSG(info, "failed to retrieve link settings");
+-		goto out_ops;
+-	}
+-
+-	ret = ethnl_update_linkmodes(info, tb, &ksettings, &mod, dev);
+-	if (ret < 0)
+-		goto out_ops;
+-
+-	if (mod) {
+-		ret = dev->ethtool_ops->set_link_ksettings(dev, &ksettings);
+-		if (ret < 0)
+-			GENL_SET_ERR_MSG(info, "link settings update failed");
+-		else
+-			ethtool_notify(dev, ETHTOOL_MSG_LINKMODES_NTF, NULL);
+-	}
+-
+-out_ops:
+-	ethnl_ops_complete(dev);
+-out_rtnl:
+-	rtnl_unlock();
+-out_dev:
+-	dev_put(dev);
+-	return ret;
+-}
+diff --git a/net/ethtool/netlink.h b/net/ethtool/netlink.h
+index 17155d446f2d..ebecf06a5a6e 100644
+--- a/net/ethtool/netlink.h
++++ b/net/ethtool/netlink.h
+@@ -339,8 +339,6 @@ extern const struct nla_policy ethnl_strset_get_policy[ETHTOOL_A_STRSET_COUNTS_O
+ extern const struct nla_policy ethnl_linkinfo_get_policy[ETHTOOL_A_LINKINFO_HEADER + 1];
+ extern const struct nla_policy ethnl_linkinfo_set_policy[ETHTOOL_A_LINKINFO_TP_MDIX_CTRL + 1];
+ extern const struct nla_policy ethnl_linkmodes_get_policy[ETHTOOL_A_LINKMODES_HEADER + 1];
+-extern const struct nla_policy
+-		ethnl_linkmodes_set_policy[ETHTOOL_A_LINKMODES_LANES + 1];
+ extern const struct nla_policy ethnl_linkstate_get_policy[ETHTOOL_A_LINKSTATE_HEADER + 1];
+ extern const struct nla_policy ethnl_debug_get_policy[ETHTOOL_A_DEBUG_HEADER + 1];
+ extern const struct nla_policy ethnl_debug_set_policy[ETHTOOL_A_DEBUG_MSGMASK + 1];
+-- 
+2.34.1
+
diff --git a/patches/0640-net-hns3-Fallback-Ethtool-s-modifications-to-extack.patch b/patches/0640-net-hns3-Fallback-Ethtool-s-modifications-to-extack.patch
new file mode 100644
index 0000000..c3800b8
--- /dev/null
+++ b/patches/0640-net-hns3-Fallback-Ethtool-s-modifications-to-extack.patch
@@ -0,0 +1,61 @@
+From 506a7a706f7eb9a5af7ea96fcc3d8259a267b4d1 Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Wed, 15 Nov 2023 15:23:47 +0800
+Subject: [PATCH 279/283] net: hns3: Fallback Ethtool's modifications to extack
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+--------------------------------
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ include/linux/netlink.h  | 3 ---
+ net/ethtool/netlink.c    | 2 +-
+ net/netlink/af_netlink.c | 2 --
+ 3 files changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/include/linux/netlink.h b/include/linux/netlink.h
+index b25b2f427127..aff84a0067f1 100644
+--- a/include/linux/netlink.h
++++ b/include/linux/netlink.h
+@@ -176,9 +176,6 @@ struct netlink_callback {
+ 	void			*data;
+ 	/* the module that dump function belong to */
+ 	struct module		*module;
+-#ifndef __GENKSYMS__
+-	struct netlink_ext_ack  *extack;
+-#endif
+ 	u16			family;
+ 	u16			min_dump_alloc;
+ 	unsigned int		prev_seq, seq;
+diff --git a/net/ethtool/netlink.c b/net/ethtool/netlink.c
+index c5fa38fad466..f710cea37a96 100644
+--- a/net/ethtool/netlink.c
++++ b/net/ethtool/netlink.c
+@@ -570,7 +570,7 @@ static int ethnl_default_start(struct netlink_callback *cb)
+ 	}
+ 
+ 	ret = ethnl_default_parse(req_info, cb->nlh, sock_net(cb->skb->sk), ops,
+-				  cb->extack, false);
++				  NULL, false);
+ 	if (req_info->dev) {
+ 		/* We ignore device specification in dump requests but as the
+ 		 * same parser as for non-dump (doit) requests is used, it
+diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c
+index 135b658f060d..ab8efc593cb6 100644
+--- a/net/netlink/af_netlink.c
++++ b/net/netlink/af_netlink.c
+@@ -2258,9 +2258,7 @@ static int netlink_dump(struct sock *sk)
+ 	netlink_skb_set_owner_r(skb, sk);
+ 
+ 	if (nlk->dump_done_errno > 0) {
+-		cb->extack = &extack;
+ 		nlk->dump_done_errno = cb->dump(skb, cb);
+-		cb->extack = NULL;
+ 	}
+ 
+ 	if (nlk->dump_done_errno > 0 ||
+-- 
+2.34.1
+
diff --git a/patches/0641-Fallback-ethtool-about-nla_-Modification-of-kabi-cha.patch b/patches/0641-Fallback-ethtool-about-nla_-Modification-of-kabi-cha.patch
new file mode 100644
index 0000000..b94da6c
--- /dev/null
+++ b/patches/0641-Fallback-ethtool-about-nla_-Modification-of-kabi-cha.patch
@@ -0,0 +1,340 @@
+From 0a054d11626413adc327e60971edacc732ed5803 Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Wed, 15 Nov 2023 17:09:17 +0800
+Subject: [PATCH 280/283] Fallback ethtool about nla_ Modification of kabi
+ changes caused by the addition of new associations in the policy structure
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+--------------------------------
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ Documentation/networking/ethtool-netlink.rst |  2 -
+ include/linux/ethtool.h                      |  4 +-
+ include/net/netlink.h                        | 65 --------------------
+ include/uapi/linux/ethtool_netlink.h         |  2 +-
+ net/ethtool/bitset.c                         |  2 -
+ net/ethtool/fec.c                            |  6 --
+ net/ethtool/netlink.c                        | 14 +----
+ net/ethtool/netlink.h                        | 25 --------
+ net/ethtool/rings.c                          | 14 ++---
+ 9 files changed, 11 insertions(+), 123 deletions(-)
+
+diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst
+index c0c33704aa96..5855c92c68c3 100644
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -247,7 +247,6 @@ Kernel response contents:
+   ``ETHTOOL_A_RINGS_RX_MINI``           u32     size of RX mini ring
+   ``ETHTOOL_A_RINGS_RX_JUMBO``          u32     size of RX jumbo ring
+   ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
+-  ``ETHTOOL_A_RINGS_RX_BUF_LEN``        u32     size of buffers on the ring
+   ====================================  ======  ===========================
+ 
+ 
+@@ -264,7 +263,6 @@ Request contents:
+   ``ETHTOOL_A_RINGS_RX_MINI``           u32     size of RX mini ring
+   ``ETHTOOL_A_RINGS_RX_JUMBO``          u32     size of RX jumbo ring
+   ``ETHTOOL_A_RINGS_TX``                u32     size of TX ring
+-  ``ETHTOOL_A_RINGS_RX_BUF_LEN``        u32     size of buffers on the ring
+   ====================================  ======  ===========================
+ 
+ Kernel checks that requested ring sizes do not exceed limits reported by
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index bf14a439afc2..5b028a126d9a 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -76,7 +76,7 @@ enum {
+  * @rx_buf_len: Current length of buffers on the rx ring.
+  */
+ struct kernel_ethtool_ringparam {
+-	u32	rx_buf_len;
++	u32 rx_buf_len;
+ };
+ 
+ /**
+@@ -438,7 +438,7 @@ struct ethtool_fec_stats {
+ struct ethtool_ops {
+ #ifndef __GENKSYMS__
+ 	u32     supported_coalesce_params;
+-	u32     supported_ring_params;
++	u32	supported_ring_params;
+ #endif
+ 	int	(*get_settings)(struct net_device *, struct ethtool_cmd *);
+ 	int	(*set_settings)(struct net_device *, struct ethtool_cmd *);
+diff --git a/include/net/netlink.h b/include/net/netlink.h
+index d9c642558255..a87f11b9cf8d 100644
+--- a/include/net/netlink.h
++++ b/include/net/netlink.h
+@@ -191,17 +191,6 @@ enum {
+ 
+ #define NLA_TYPE_MAX (__NLA_TYPE_MAX - 1)
+ 
+-enum nla_policy_validation {
+-	NLA_VALIDATE_NONE,
+-	NLA_VALIDATE_RANGE,
+-	NLA_VALIDATE_RANGE_WARN_TOO_LONG,
+-	NLA_VALIDATE_MIN,
+-	NLA_VALIDATE_MAX,
+-	NLA_VALIDATE_MASK,
+-	NLA_VALIDATE_RANGE_PTR,
+-	NLA_VALIDATE_FUNCTION,
+-};
+-
+ /**
+  * struct nla_policy - attribute validation policy
+  * @type: Type of attribute or NLA_UNSPEC
+@@ -240,62 +229,8 @@ struct nla_policy {
+ 	u16		type;
+ 	u16		len;
+ 	void		*validation_data;
+-#ifndef __GENKSYMS__
+-	u8		validation_type;
+-	union {
+-		const u32 bitfield32_valid;
+-		const u32 mask;
+-		const char *reject_message;
+-		const struct nla_policy *nested_policy;
+-		struct netlink_range_validation *range;
+-		struct netlink_range_validation_signed *range_signed;
+-		struct {
+-			s16 min, max;
+-		};
+-		int (*validate)(const struct nlattr *attr,
+-				struct netlink_ext_ack *extack);
+-		u16 strict_start_type;
+-	};
+-#endif
+ };
+ 
+-#define _NLA_POLICY_NESTED(maxattr, policy) \
+-	{ .type = NLA_NESTED, .nested_policy = policy, .len = maxattr }
+-#define NLA_POLICY_NESTED(policy) \
+-	_NLA_POLICY_NESTED(ARRAY_SIZE(policy) - 1, policy)
+-
+-#define __NLA_IS_UINT_TYPE(tp)						\
+-	(tp == NLA_U8 || tp == NLA_U16 || tp == NLA_U32 || tp == NLA_U64)
+-#define __NLA_IS_SINT_TYPE(tp)						\
+-	(tp == NLA_S8 || tp == NLA_S16 || tp == NLA_S32 || tp == NLA_S64)
+-
+-#define __NLA_ENSURE(condition) BUILD_BUG_ON_ZERO(!(condition))
+-#define NLA_ENSURE_UINT_TYPE(tp)			\
+-	(__NLA_ENSURE(__NLA_IS_UINT_TYPE(tp)) + tp)
+-#define NLA_ENSURE_INT_OR_BINARY_TYPE(tp)		\
+-	(__NLA_ENSURE(__NLA_IS_UINT_TYPE(tp) ||		\
+-		      __NLA_IS_SINT_TYPE(tp) ||		\
+-		      tp == NLA_MSECS ||		\
+-		      tp == NLA_BINARY) + tp)
+-
+-#define NLA_POLICY_MIN(tp, _min) {			\
+-	.type = NLA_ENSURE_INT_OR_BINARY_TYPE(tp),	\
+-	.validation_type = NLA_VALIDATE_MIN,		\
+-	.min = _min,					\
+-}
+-
+-#define NLA_POLICY_MAX(tp, _max) {			\
+-	.type = NLA_ENSURE_INT_OR_BINARY_TYPE(tp),	\
+-	.validation_type = NLA_VALIDATE_MAX,		\
+-	.max = _max,					\
+-}
+-
+-#define NLA_POLICY_MASK(tp, _mask) {			\
+-	.type = NLA_ENSURE_UINT_TYPE(tp),		\
+-	.validation_type = NLA_VALIDATE_MASK,		\
+-	.mask = _mask,					\
+-}
+-
+ /**
+  * struct nl_info - netlink source information
+  * @nlh: Netlink message header of original request
+diff --git a/include/uapi/linux/ethtool_netlink.h b/include/uapi/linux/ethtool_netlink.h
+index a616a033c5be..088ca2aaa76c 100644
+--- a/include/uapi/linux/ethtool_netlink.h
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -286,7 +286,7 @@ enum {
+ 	ETHTOOL_A_RINGS_RX_MINI,			/* u32 */
+ 	ETHTOOL_A_RINGS_RX_JUMBO,			/* u32 */
+ 	ETHTOOL_A_RINGS_TX,				/* u32 */
+-	ETHTOOL_A_RINGS_RX_BUF_LEN,                     /* u32 */
++	ETHTOOL_A_RINGS_RX_BUF_LEN,			/* u32 */
+ 
+ 	/* add new constants above here */
+ 	__ETHTOOL_A_RINGS_CNT,
+diff --git a/net/ethtool/bitset.c b/net/ethtool/bitset.c
+index 674cbe6f421e..21426d080ada 100644
+--- a/net/ethtool/bitset.c
++++ b/net/ethtool/bitset.c
+@@ -306,8 +306,6 @@ int ethnl_put_bitset32(struct sk_buff *skb, int attrtype, const u32 *val,
+ static const struct nla_policy bitset_policy[ETHTOOL_A_BITSET_MAX + 1] = {
+ 	[ETHTOOL_A_BITSET_UNSPEC]	= { .type = NLA_REJECT },
+ 	[ETHTOOL_A_BITSET_NOMASK]	= { .type = NLA_FLAG },
+-	[ETHTOOL_A_BITSET_SIZE]		= NLA_POLICY_MAX(NLA_U32,
+-							 ETHNL_MAX_BITSET_SIZE),
+ 	[ETHTOOL_A_BITSET_BITS]		= { .type = NLA_NESTED },
+ 	[ETHTOOL_A_BITSET_VALUE]	= { .type = NLA_BINARY },
+ 	[ETHTOOL_A_BITSET_MASK]		= { .type = NLA_BINARY },
+diff --git a/net/ethtool/fec.c b/net/ethtool/fec.c
+index 8738dafd5417..61ee00ef7093 100644
+--- a/net/ethtool/fec.c
++++ b/net/ethtool/fec.c
+@@ -24,10 +24,6 @@ struct fec_reply_data {
+ 
+ #define ETHTOOL_FEC_MASK	((ETHTOOL_FEC_LLRS << 1) - 1)
+ 
+-const struct nla_policy ethnl_fec_get_policy[ETHTOOL_A_FEC_HEADER + 1] = {
+-	[ETHTOOL_A_FEC_HEADER]	= NLA_POLICY_NESTED(ethnl_header_policy_stats),
+-};
+-
+ static void
+ ethtool_fec_to_link_modes(u32 fec, unsigned long *link_modes, u8 *fec_auto)
+ {
+@@ -232,9 +228,7 @@ const struct ethnl_request_ops ethnl_fec_request_ops = {
+ /* FEC_SET */
+ 
+ const struct nla_policy ethnl_fec_set_policy[ETHTOOL_A_FEC_AUTO + 1] = {
+-	[ETHTOOL_A_FEC_HEADER]	= NLA_POLICY_NESTED(ethnl_header_policy),
+ 	[ETHTOOL_A_FEC_MODES]	= { .type = NLA_NESTED },
+-	[ETHTOOL_A_FEC_AUTO]	= NLA_POLICY_MAX(NLA_U8, 1),
+ };
+ 
+ int ethnl_set_fec(struct sk_buff *skb, struct genl_info *info)
+diff --git a/net/ethtool/netlink.c b/net/ethtool/netlink.c
+index f710cea37a96..8b0257ae21a1 100644
+--- a/net/ethtool/netlink.c
++++ b/net/ethtool/netlink.c
+@@ -13,7 +13,7 @@ static u32 ethnl_bcast_seq;
+ 			     ETHTOOL_FLAG_OMIT_REPLY)
+ #define ETHTOOL_FLAGS_STATS (ETHTOOL_FLAGS_BASIC | ETHTOOL_FLAG_STATS)
+ 
+-const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_MAX + 1] = {
++static const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_MAX + 1] = {
+ 	[ETHTOOL_A_HEADER_UNSPEC]	= { .type = NLA_REJECT },
+ 	[ETHTOOL_A_HEADER_DEV_INDEX]	= { .type = NLA_U32 },
+ 	[ETHTOOL_A_HEADER_DEV_NAME]	= { .type = NLA_NUL_STRING,
+@@ -21,14 +21,6 @@ const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_MAX + 1] = {
+ 	[ETHTOOL_A_HEADER_FLAGS]	= { .type = NLA_U32 },
+ };
+ 
+-const struct nla_policy ethnl_header_policy_stats[] = {
+-	[ETHTOOL_A_HEADER_DEV_INDEX]	= { .type = NLA_U32 },
+-	[ETHTOOL_A_HEADER_DEV_NAME]	= { .type = NLA_NUL_STRING,
+-					    .len = ALTIFNAMSIZ - 1 },
+-	[ETHTOOL_A_HEADER_FLAGS]	= NLA_POLICY_MASK(NLA_U32,
+-							  ETHTOOL_FLAGS_STATS),
+-};
+-
+ /**
+  * ethnl_parse_header_dev_get() - parse request header
+  * @req_info:    structure to put results into
+@@ -795,15 +787,11 @@ static const struct genl_ops ethtool_genl_ops[] = {
+ 		.start	= ethnl_default_start,
+ 		.dumpit	= ethnl_default_dumpit,
+ 		.done	= ethnl_default_done,
+-		.policy = ethnl_fec_get_policy,
+-		.maxattr = ARRAY_SIZE(ethnl_fec_get_policy) - 1,
+ 	},
+ 	{
+ 		.cmd	= ETHTOOL_MSG_FEC_SET,
+ 		.flags	= GENL_UNS_ADMIN_PERM,
+ 		.doit	= ethnl_set_fec,
+-		.policy = ethnl_fec_set_policy,
+-		.maxattr = ARRAY_SIZE(ethnl_fec_set_policy) - 1,
+ 	},
+ };
+ 
+diff --git a/net/ethtool/netlink.h b/net/ethtool/netlink.h
+index ebecf06a5a6e..a8be78e21218 100644
+--- a/net/ethtool/netlink.h
++++ b/net/ethtool/netlink.h
+@@ -326,33 +326,8 @@ extern const struct ethnl_request_ops ethnl_wol_request_ops;
+ extern const struct ethnl_request_ops ethnl_features_request_ops;
+ extern const struct ethnl_request_ops ethnl_privflags_request_ops;
+ extern const struct ethnl_request_ops ethnl_rings_request_ops;
+-extern const struct ethnl_request_ops ethnl_channels_request_ops;
+-extern const struct ethnl_request_ops ethnl_coalesce_request_ops;
+-extern const struct ethnl_request_ops ethnl_pause_request_ops;
+-extern const struct ethnl_request_ops ethnl_eee_request_ops;
+-extern const struct ethnl_request_ops ethnl_tsinfo_request_ops;
+ extern const struct ethnl_request_ops ethnl_fec_request_ops;
+ 
+-extern const struct nla_policy ethnl_header_policy[ETHTOOL_A_HEADER_FLAGS + 1];
+-extern const struct nla_policy ethnl_header_policy_stats[ETHTOOL_A_HEADER_FLAGS + 1];
+-extern const struct nla_policy ethnl_strset_get_policy[ETHTOOL_A_STRSET_COUNTS_ONLY + 1];
+-extern const struct nla_policy ethnl_linkinfo_get_policy[ETHTOOL_A_LINKINFO_HEADER + 1];
+-extern const struct nla_policy ethnl_linkinfo_set_policy[ETHTOOL_A_LINKINFO_TP_MDIX_CTRL + 1];
+-extern const struct nla_policy ethnl_linkmodes_get_policy[ETHTOOL_A_LINKMODES_HEADER + 1];
+-extern const struct nla_policy ethnl_linkstate_get_policy[ETHTOOL_A_LINKSTATE_HEADER + 1];
+-extern const struct nla_policy ethnl_debug_get_policy[ETHTOOL_A_DEBUG_HEADER + 1];
+-extern const struct nla_policy ethnl_debug_set_policy[ETHTOOL_A_DEBUG_MSGMASK + 1];
+-extern const struct nla_policy ethnl_wol_get_policy[ETHTOOL_A_WOL_HEADER + 1];
+-extern const struct nla_policy ethnl_wol_set_policy[ETHTOOL_A_WOL_SOPASS + 1];
+-extern const struct nla_policy ethnl_features_get_policy[ETHTOOL_A_FEATURES_HEADER + 1];
+-extern const struct nla_policy ethnl_features_set_policy[ETHTOOL_A_FEATURES_WANTED + 1];
+-extern const struct nla_policy ethnl_privflags_get_policy[ETHTOOL_A_PRIVFLAGS_HEADER + 1];
+-extern const struct nla_policy ethnl_privflags_set_policy[ETHTOOL_A_PRIVFLAGS_FLAGS + 1];
+-extern const struct nla_policy ethnl_rings_get_policy[ETHTOOL_A_RINGS_HEADER + 1];
+-extern const struct nla_policy ethnl_rings_set_policy[ETHTOOL_A_RINGS_RX_BUF_LEN + 1];
+-extern const struct nla_policy ethnl_fec_get_policy[ETHTOOL_A_FEC_HEADER + 1];
+-extern const struct nla_policy ethnl_fec_set_policy[ETHTOOL_A_FEC_AUTO + 1];
+-
+ int ethnl_set_linkinfo(struct sk_buff *skb, struct genl_info *info);
+ int ethnl_set_linkmodes(struct sk_buff *skb, struct genl_info *info);
+ int ethnl_set_debug(struct sk_buff *skb, struct genl_info *info);
+diff --git a/net/ethtool/rings.c b/net/ethtool/rings.c
+index 128e15b10883..8c9b39ce53f9 100644
+--- a/net/ethtool/rings.c
++++ b/net/ethtool/rings.c
+@@ -10,7 +10,7 @@ struct rings_req_info {
+ struct rings_reply_data {
+ 	struct ethnl_reply_data		base;
+ 	struct ethtool_ringparam	ringparam;
+-	struct kernel_ethtool_ringparam	kernel_ringparam;
++	struct kernel_ethtool_ringparam kernel_ringparam;
+ };
+ 
+ #define RINGS_REPDATA(__reply_base) \
+@@ -69,7 +69,7 @@ static int rings_fill_reply(struct sk_buff *skb,
+ {
+ 	const struct rings_reply_data *data = RINGS_REPDATA(reply_base);
+ 	const struct kernel_ethtool_ringparam *kernel_ringparam =
+-						&data->kernel_ringparam;
++					&data->kernel_ringparam;
+ 	const struct ethtool_ringparam *ringparam = &data->ringparam;
+ 
+ 	if ((ringparam->rx_max_pending &&
+@@ -91,10 +91,10 @@ static int rings_fill_reply(struct sk_buff *skb,
+ 	     (nla_put_u32(skb, ETHTOOL_A_RINGS_TX_MAX,
+ 			  ringparam->tx_max_pending) ||
+ 	      nla_put_u32(skb, ETHTOOL_A_RINGS_TX,
+-			  ringparam->tx_pending)))  ||
+-	    (kernel_ringparam->rx_buf_len &&
+-	     (nla_put_u32(skb, ETHTOOL_A_RINGS_RX_BUF_LEN,
+-			  kernel_ringparam->rx_buf_len))))
++			  ringparam->tx_pending))) ||
++		(kernel_ringparam->rx_buf_len &&
++		(nla_put_u32(skb, ETHTOOL_A_RINGS_RX_BUF_LEN,
++			     kernel_ringparam->rx_buf_len))))
+ 		return -EMSGSIZE;
+ 
+ 	return 0;
+@@ -128,7 +128,6 @@ rings_set_policy[ETHTOOL_A_RINGS_MAX + 1] = {
+ 	[ETHTOOL_A_RINGS_RX_MINI]		= { .type = NLA_U32 },
+ 	[ETHTOOL_A_RINGS_RX_JUMBO]		= { .type = NLA_U32 },
+ 	[ETHTOOL_A_RINGS_TX]			= { .type = NLA_U32 },
+-	[ETHTOOL_A_RINGS_RX_BUF_LEN]            = NLA_POLICY_MIN(NLA_U32, 1),
+ };
+ 
+ int ethnl_set_rings(struct sk_buff *skb, struct genl_info *info)
+@@ -174,6 +173,7 @@ int ethnl_set_rings(struct sk_buff *skb, struct genl_info *info)
+ 	ethnl_update_u32(&ringparam.tx_pending, tb[ETHTOOL_A_RINGS_TX], &mod);
+ 	ethnl_update_u32(&kernel_ringparam.rx_buf_len,
+ 			 tb[ETHTOOL_A_RINGS_RX_BUF_LEN], &mod);
++
+ 	ret = 0;
+ 	if (!mod)
+ 		goto out_ops;
+-- 
+2.34.1
+
diff --git a/patches/0642-net-hns3-Fix-Kabi-issue-caused-by-ptp-introducing-ge.patch b/patches/0642-net-hns3-Fix-Kabi-issue-caused-by-ptp-introducing-ge.patch
new file mode 100644
index 0000000..ed22ab7
--- /dev/null
+++ b/patches/0642-net-hns3-Fix-Kabi-issue-caused-by-ptp-introducing-ge.patch
@@ -0,0 +1,123 @@
+From ef24cbc7b7f598a1246f541899073c47e162efe7 Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Wed, 15 Nov 2023 17:22:29 +0800
+Subject: [PATCH 281/283] net: hns3: Fix Kabi issue caused by ptp introducing
+ gettimex64()
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+--------------------------------
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c | 7 +++----
+ drivers/ptp/ptp_chardev.c                              | 4 +---
+ drivers/ptp/ptp_clock.c                                | 4 +---
+ drivers/ptp/ptp_hisi.c                                 | 5 ++---
+ include/linux/ptp_clock_kernel.h                       | 4 ----
+ 5 files changed, 7 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+index a40b1583f114..41d47ab8b8aa 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.c
+@@ -137,8 +137,7 @@ void hclge_ptp_get_rx_hwts(struct hnae3_handle *handle, struct sk_buff *skb,
+ 	hdev->ptp->rx_cnt++;
+ }
+ 
+-static int hclge_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
+-			      struct ptp_system_timestamp *sts)
++static int hclge_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts)
+ {
+ 	struct hclge_dev *hdev = hclge_ptp_get_hdev(ptp);
+ 	unsigned long flags;
+@@ -194,7 +193,7 @@ static int hclge_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
+ 		struct timespec64 ts;
+ 		s64 ns;
+ 
+-		hclge_ptp_gettimex(ptp, &ts, NULL);
++		hclge_ptp_gettimex(ptp, &ts);
+ 		ns = timespec64_to_ns(&ts);
+ 		ns = is_neg ? ns - delta : ns + delta;
+ 		ts = ns_to_timespec64(ns);
+@@ -448,7 +447,7 @@ static int hclge_ptp_create_clock(struct hclge_dev *hdev)
+ 	ptp->info.pps = 0;
+ 	ptp->info.adjfreq = hclge_ptp_adjfreq;
+ 	ptp->info.adjtime = hclge_ptp_adjtime;
+-	ptp->info.gettimex64 = hclge_ptp_gettimex;
++	ptp->info.gettime64 = hclge_ptp_gettimex;
+ 	ptp->info.settime64 = hclge_ptp_settime;
+ 
+ 	ptp->info.n_alarm = 0;
+diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c
+index 28e589b794bb..d1e9684f8443 100644
+--- a/drivers/ptp/ptp_chardev.c
++++ b/drivers/ptp/ptp_chardev.c
+@@ -228,9 +228,7 @@ long ptp_ioctl(struct posix_clock *pc, unsigned int cmd, unsigned long arg)
+ 			pct->sec = ts.tv_sec;
+ 			pct->nsec = ts.tv_nsec;
+ 			pct++;
+-			if (ops->gettimex64)
+-				err = ops->gettimex64(ops, &ts, NULL);
+-			else
++			if (ops->gettime64)
+ 				err = ops->gettime64(ops, &ts);
+ 			if (err)
+ 				goto out;
+diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c
+index e865cfdef360..916e48109566 100644
+--- a/drivers/ptp/ptp_clock.c
++++ b/drivers/ptp/ptp_clock.c
+@@ -117,9 +117,7 @@ static int ptp_clock_gettime(struct posix_clock *pc, struct timespec64 *tp)
+ 	struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+ 	int err;
+ 
+-	if (ptp->info->gettimex64)
+-		err = ptp->info->gettimex64(ptp->info, tp, NULL);
+-	else
++	if (ptp->info->gettime64)
+ 		err = ptp->info->gettime64(ptp->info, tp);
+ 	return err;
+ }
+diff --git a/drivers/ptp/ptp_hisi.c b/drivers/ptp/ptp_hisi.c
+index 1fcff3c9a90b..60bf10a7a3d9 100644
+--- a/drivers/ptp/ptp_hisi.c
++++ b/drivers/ptp/ptp_hisi.c
+@@ -561,8 +561,7 @@ static int hisi_ptp_settime(struct ptp_clock_info *ptp_info,
+ }
+ 
+ static int hisi_ptp_gettime(struct ptp_clock_info *ptp_info,
+-			     struct timespec64 *ts,
+-			     struct ptp_system_timestamp *sts)
++			     struct timespec64 *ts)
+ {
+ 	struct hisi_ptp_pdev *ptp = hisi_ptp_get_pdev(ptp_info);
+ 	unsigned long flags;
+@@ -594,7 +593,7 @@ static int hisi_ptp_create_clock(struct hisi_ptp_pdev *ptp)
+ 	ptp->info.adjfine = hisi_ptp_adjfine;
+ 	ptp->info.adjtime = hisi_ptp_adjtime;
+ 	ptp->info.settime64 = hisi_ptp_settime;
+-	ptp->info.gettimex64 = hisi_ptp_gettime;
++	ptp->info.gettime64 = hisi_ptp_gettime;
+ 	ptp->clock = ptp_clock_register(&ptp->info, ptp->ptp_tx->dev);
+ 	if (IS_ERR(ptp->clock)) {
+ 		dev_err(ptp->ptp_tx->dev,
+diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h
+index 9d7afc71a2e7..91a47e2342f3 100644
+--- a/include/linux/ptp_clock_kernel.h
++++ b/include/linux/ptp_clock_kernel.h
+@@ -134,10 +134,6 @@ struct ptp_clock_info {
+ 	int (*adjfine)(struct ptp_clock_info *ptp, long scaled_ppm);
+ 	int (*adjfreq)(struct ptp_clock_info *ptp, s32 delta);
+ 	int (*adjtime)(struct ptp_clock_info *ptp, s64 delta);
+-#ifndef __GENKSYMS__
+-	int (*gettimex64)(struct ptp_clock_info *ptp, struct timespec64 *ts,
+-			  struct ptp_system_timestamp *sts);
+-#endif
+ 	int (*gettime64)(struct ptp_clock_info *ptp, struct timespec64 *ts);
+ 	int (*getcrosststamp)(struct ptp_clock_info *ptp,
+ 			      struct system_device_crosststamp *cts);
+-- 
+2.34.1
+
diff --git a/patches/0643-net-hns3-Fix-ethtool_-Ops-gen_-Improper-modification.patch b/patches/0643-net-hns3-Fix-ethtool_-Ops-gen_-Improper-modification.patch
new file mode 100644
index 0000000..2d8fb34
--- /dev/null
+++ b/patches/0643-net-hns3-Fix-ethtool_-Ops-gen_-Improper-modification.patch
@@ -0,0 +1,100 @@
+From 19c5d9f3c49c96f87ba7d5403af7539d0d220b8f Mon Sep 17 00:00:00 2001
+From: Algernon <lixiaodong67@huawei.com>
+Date: Wed, 15 Nov 2023 20:09:35 +0800
+Subject: [PATCH 282/283] net: hns3: Fix ethtool_ Ops&gen_ Improper
+ modification of kabi changes caused by adding members in the ops structure
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+--------------------------------
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ include/linux/ethtool.h | 21 +++++++++------------
+ include/net/genetlink.h |  8 +++++---
+ 2 files changed, 14 insertions(+), 15 deletions(-)
+
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index 5b028a126d9a..affef82ee8f3 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -436,10 +436,6 @@ struct ethtool_fec_stats {
+  * of the generic netdev features interface.
+  */
+ struct ethtool_ops {
+-#ifndef __GENKSYMS__
+-	u32     supported_coalesce_params;
+-	u32	supported_ring_params;
+-#endif
+ 	int	(*get_settings)(struct net_device *, struct ethtool_cmd *);
+ 	int	(*set_settings)(struct net_device *, struct ethtool_cmd *);
+ 	void	(*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);
+@@ -451,10 +447,6 @@ struct ethtool_ops {
+ 	void	(*set_msglevel)(struct net_device *, u32);
+ 	int	(*nway_reset)(struct net_device *);
+ 	u32	(*get_link)(struct net_device *);
+-#ifndef __GENKSYMS__
+-	int	(*get_link_ext_state)(struct net_device *,
+-				      struct ethtool_link_ext_state_info *);
+-#endif
+ 	int	(*get_eeprom_len)(struct net_device *);
+ 	int	(*get_eeprom)(struct net_device *,
+ 			      struct ethtool_eeprom *, u8 *);
+@@ -521,20 +513,25 @@ struct ethtool_ops {
+ 				      struct ethtool_link_ksettings *);
+ 	int	(*set_link_ksettings)(struct net_device *,
+ 				      const struct ethtool_link_ksettings *);
+-#ifndef __GENKSYMS__
+-	void	(*get_fec_stats)(struct net_device *dev,
+-				 struct ethtool_fec_stats *fec_stats);
+-#endif
+ 	int	(*get_fecparam)(struct net_device *,
+ 				      struct ethtool_fecparam *);
+ 	int	(*set_fecparam)(struct net_device *,
+ 				      struct ethtool_fecparam *);
+ 	void	(*get_ethtool_phy_stats)(struct net_device *,
+ 					 struct ethtool_stats *, u64 *);
++#ifndef __GENKSYMS__
++	u32     supported_coalesce_params;
++	u32     supported_ring_params;
+ 
++	int     (*get_link_ext_state)(struct net_device *,
++				      struct ethtool_link_ext_state_info *);
++	void    (*get_fec_stats)(struct net_device *dev,
++				 struct ethtool_fec_stats *fec_stats);
++#else
+ 	KABI_RESERVE(1)
+ 	KABI_RESERVE(2)
+ 	KABI_RESERVE(3)
++#endif
+ 	KABI_RESERVE(4)
+ 	KABI_RESERVE(5)
+ 	KABI_RESERVE(6)
+diff --git a/include/net/genetlink.h b/include/net/genetlink.h
+index 83554e1cc08e..cd57d2e1188b 100644
+--- a/include/net/genetlink.h
++++ b/include/net/genetlink.h
+@@ -148,14 +148,16 @@ struct genl_ops {
+ 	int		       (*dumpit)(struct sk_buff *skb,
+ 					 struct netlink_callback *cb);
+ 	int		       (*done)(struct netlink_callback *cb);
+-#ifndef __GENKSYMS__
+-	unsigned int		maxattr;
+-#endif
+ 	u8			cmd;
+ 	u8			internal_flags;
+ 	u8			flags;
+ 
++#ifndef __GENKSYMS__
++	unsigned int		maxattr;
++	unsigned int		reserve;
++#else
+ 	KABI_RESERVE(1)
++#endif
+ 	KABI_RESERVE(2)
+ 	KABI_RESERVE(3)
+ 	KABI_RESERVE(4)
+-- 
+2.34.1
+
diff --git a/patches/0644-net-hns3-Fix-unreasonable-modifications-caused-by-ro.patch b/patches/0644-net-hns3-Fix-unreasonable-modifications-caused-by-ro.patch
new file mode 100644
index 0000000..20c78f6
--- /dev/null
+++ b/patches/0644-net-hns3-Fix-unreasonable-modifications-caused-by-ro.patch
@@ -0,0 +1,278 @@
+From 275cb764c0a08c0ee0e9b484cbe29f9045055d6f Mon Sep 17 00:00:00 2001
+From: Xiaodong Li <lixiaodong67@huawei.com>
+Date: Thu, 16 Nov 2023 22:31:57 +0800
+Subject: [PATCH 283/283] net: hns3: Fix unreasonable modifications caused by
+ rollback extension ringparam parameters
+
+driver inclusion
+category: bugfix
+bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8EN49
+--------------------------------
+
+Fixed residual kernel introduced by subsequent patches in hns3 due to rollback
+of ringparam_ Param compilation reported an error and deleted unused enums and header files
+
+Signed-off-by: Xiaodong Li <lixiaodong67@huawei.com>
+---
+ .../ethernet/hisilicon/hns3/hns3_ethtool.c    | 21 ++++-------------
+ include/linux/ethtool.h                       | 23 +++++++++++++------
+ include/linux/phy.h                           |  1 +
+ include/net/genetlink.h                       |  2 +-
+ include/net/netlink.h                         |  3 +--
+ include/uapi/linux/ethtool.h                  |  9 +++-----
+ net/core/xdp.c                                |  3 ---
+ net/ethtool/ioctl.c                           |  4 ++--
+ 8 files changed, 29 insertions(+), 37 deletions(-)
+
+diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+index c951f7c4eea9..ea870fa15ce6 100644
+--- a/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
++++ b/drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
+@@ -726,7 +726,6 @@ static void hns3_get_ringparam(struct net_device *netdev,
+ 
+ 	param->tx_pending = priv->ring[0].desc_num;
+ 	param->rx_pending = priv->ring[rx_queue_index].desc_num;
+-	kernel_param->rx_buf_len = priv->ring[rx_queue_index].buf_size;
+ }
+ 
+ static void hns3_get_pauseparam(struct net_device *netdev,
+@@ -1129,8 +1128,7 @@ static struct hns3_enet_ring *hns3_backup_ringparam(struct hns3_nic_priv *priv)
+ }
+ 
+ static int hns3_check_ringparam(struct net_device *ndev,
+-				struct ethtool_ringparam *param,
+-				struct kernel_ethtool_ringparam *kernel_param)
++				struct ethtool_ringparam *param)
+ {
+ #define RX_BUF_LEN_2K 2048
+ #define RX_BUF_LEN_4K 4096
+@@ -1140,12 +1138,6 @@ static int hns3_check_ringparam(struct net_device *ndev,
+ 	if (param->rx_mini_pending || param->rx_jumbo_pending)
+ 		return -EINVAL;
+ 
+-	if (kernel_param->rx_buf_len != RX_BUF_LEN_2K &&
+-	    kernel_param->rx_buf_len != RX_BUF_LEN_4K) {
+-		netdev_err(ndev, "Rx buf len only support 2048 and 4096\n");
+-		return -EINVAL;
+-	}
+-
+ 	if (param->tx_pending > HNS3_RING_MAX_PENDING ||
+ 	    param->tx_pending < HNS3_RING_MIN_PENDING ||
+ 	    param->rx_pending > HNS3_RING_MAX_PENDING ||
+@@ -1187,7 +1179,7 @@ static int hns3_set_ringparam(struct net_device *ndev,
+ 	u32 old_rx_buf_len;
+ 	int ret, i;
+ 
+-	ret = hns3_check_ringparam(ndev, param, kernel_param);
++	ret = hns3_check_ringparam(ndev, param);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -1198,8 +1190,7 @@ static int hns3_set_ringparam(struct net_device *ndev,
+ 	old_rx_desc_num = priv->ring[queue_num].desc_num;
+ 	old_rx_buf_len = priv->ring[queue_num].buf_size;
+ 	if (old_tx_desc_num == new_tx_desc_num &&
+-	    old_rx_desc_num == new_rx_desc_num &&
+-	    kernel_param->rx_buf_len == old_rx_buf_len)
++	    old_rx_desc_num == new_rx_desc_num)
+ 		return 0;
+ 
+ 	tmp_rings = hns3_backup_ringparam(priv);
+@@ -1210,16 +1201,14 @@ static int hns3_set_ringparam(struct net_device *ndev,
+ 	}
+ 
+ 	netdev_info(ndev,
+-		    "Changing Tx/Rx ring depth from %u/%u to %u/%u, Changing rx buffer len from %d to %d\n",
++		    "Changing Tx/Rx ring depth from %u/%u to %u/%u\n",
+ 		    old_tx_desc_num, old_rx_desc_num,
+-		    new_tx_desc_num, new_rx_desc_num,
+-		    old_rx_buf_len, kernel_param->rx_buf_len);
++		    new_tx_desc_num, new_rx_desc_num);
+ 
+ 	if (if_running)
+ 		ndev->netdev_ops->ndo_stop(ndev);
+ 
+ 	hns3_change_all_ring_bd_num(priv, new_tx_desc_num, new_rx_desc_num);
+-	hns3_change_rx_buf_len(ndev, kernel_param->rx_buf_len);
+ 	ret = hns3_init_all_ring(priv);
+ 	if (ret) {
+ 		netdev_err(ndev, "set ringparam fail, revert to old value(%d)\n",
+diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
+index affef82ee8f3..8f321c874ce0 100644
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -130,10 +130,12 @@ static inline u32 ethtool_rxfh_indir_default(u32 index, u32 n_rx_rings)
+ 	return index % n_rx_rings;
+ }
+ 
+-#ifdef __GENKSYMS__
++/* number of link mode bits/ulongs handled internally by kernel */
+ #define __ETHTOOL_LINK_MODE_MASK_NBITS			\
+ 	(__ETHTOOL_LINK_MODE_LAST + 1)
+-#endif
++
++#define __ETHTOOL_LINK_MODE_MASK_ASSERT_NBITS			\
++	(ETHTOOL_LINK_MODE_100baseFX_Full_BIT + 1)
+ 
+ /* declare a link mode bitmap */
+ #define __ETHTOOL_DECLARE_LINK_MODE_MASK(name)		\
+@@ -292,6 +294,14 @@ struct ethtool_fec_stats {
+ 
+ /**
+  * struct ethtool_ops - optional netdev operations
++ * @get_settings: DEPRECATED, use %get_link_ksettings/%set_link_ksettings
++ *	API. Get various device settings including Ethernet link
++ *	settings. The @cmd parameter is expected to have been cleared
++ *	before get_settings is called. Returns a negative error code
++ *	or zero.
++ * @set_settings: DEPRECATED, use %get_link_ksettings/%set_link_ksettings
++ *	API. Set various device settings including Ethernet link
++ *	settings.  Returns a negative error code or zero.
+  * @supported_coalesce_params: supported types of interrupt coalescing.
+  * @supported_ring_params: supported ring params.
+  * @get_drvinfo: Report driver/device information.  Should only set the
+@@ -322,9 +332,8 @@ struct ethtool_fec_stats {
+  *	or zero.
+  * @get_coalesce: Get interrupt coalescing parameters.  Returns a negative
+  *	error code or zero.
+- * @set_coalesce: Set interrupt coalescing parameters.  Supported coalescing
+- *     types should be set in @supported_coalesce_params.
+- *     Returns a negative error code or zero.
++ * @set_coalesce: Set interrupt coalescing parameters.  Returns a negative
++ *	error code or zero.
+  * @get_ringparam: Report ring sizes
+  * @set_ringparam: Set ring sizes.  Returns a negative error code or zero.
+  * @get_pauseparam: Report pause parameters
+@@ -454,9 +463,9 @@ struct ethtool_ops {
+ 			      struct ethtool_eeprom *, u8 *);
+ 	int	(*get_coalesce)(struct net_device *, struct ethtool_coalesce *);
+ 	int	(*set_coalesce)(struct net_device *, struct ethtool_coalesce *);
+-	void    (*get_ringparam)(struct net_device *,
++	void	(*get_ringparam)(struct net_device *,
+ 				 struct ethtool_ringparam *);
+-	int     (*set_ringparam)(struct net_device *,
++	int	(*set_ringparam)(struct net_device *,
+ 				 struct ethtool_ringparam *);
+ 	void	(*get_pauseparam)(struct net_device *,
+ 				  struct ethtool_pauseparam*);
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index 03eb46c632da..655db68e99a8 100644
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -418,6 +418,7 @@ struct phy_device {
+ 	unsigned autoneg:1;
+ 	/* The most recently read link state */
+ 	unsigned link:1;
++
+ 	enum phy_state state;
+ 
+ 	u32 dev_flags;
+diff --git a/include/net/genetlink.h b/include/net/genetlink.h
+index cd57d2e1188b..61cee458f43b 100644
+--- a/include/net/genetlink.h
++++ b/include/net/genetlink.h
+@@ -141,7 +141,7 @@ static inline int genl_err_attr(struct genl_info *info, int err,
+  * @done: completion callback for dumps
+  */
+ struct genl_ops {
+-	const struct nla_policy *policy;
++	const struct nla_policy	*policy;
+ 	int		       (*doit)(struct sk_buff *skb,
+ 				       struct genl_info *info);
+ 	int		       (*start)(struct netlink_callback *cb);
+diff --git a/include/net/netlink.h b/include/net/netlink.h
+index a87f11b9cf8d..30b4dd1408b4 100644
+--- a/include/net/netlink.h
++++ b/include/net/netlink.h
+@@ -173,7 +173,6 @@ enum {
+ 	NLA_MSECS,
+ 	NLA_NESTED,
+ 	NLA_NESTED_COMPAT,
+-	NLA_NESTED_ARRAY,
+ 	NLA_NUL_STRING,
+ 	NLA_BINARY,
+ 	NLA_S8,
+@@ -228,7 +227,7 @@ enum {
+ struct nla_policy {
+ 	u16		type;
+ 	u16		len;
+-	void		*validation_data;
++	void            *validation_data;
+ };
+ 
+ /**
+diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
+index 0649b8295feb..6f46b6cbc84c 100644
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -228,7 +228,7 @@ enum tunable_id {
+ 	ETHTOOL_TX_COPYBREAK_BUF_SIZE,
+ 	/*
+ 	 * Add your fresh new tunable attribute above and remember to update
+-	 * tunable_strings[] in net/core/ethtool.c
++	 * tunable_strings[] in net/ethtool/common.c
+ 	 */
+ 	__ETHTOOL_TUNABLE_COUNT,
+ };
+@@ -264,7 +264,7 @@ enum phy_tunable_id {
+ 	ETHTOOL_PHY_EDPD,
+ 	/*
+ 	 * Add your fresh new phy tunable attribute above and remember to update
+-	 * phy_tunable_strings[] in net/core/ethtool.c
++	 * phy_tunable_strings[] in net/ethtool/common.c
+ 	 */
+ 	__ETHTOOL_PHY_TUNABLE_COUNT,
+ };
+@@ -1629,12 +1629,9 @@ enum ethtool_link_mode_bit_indices {
+ 	 * macro for bits > 31. The only way to use indices > 31 is to
+ 	 * use the new ETHTOOL_GLINKSETTINGS/ETHTOOL_SLINKSETTINGS API.
+ 	 */
+-#ifndef __GENKSYMS__
+-	__ETHTOOL_LINK_MODE_MASK_NBITS,
+-#else
++
+ 	__ETHTOOL_LINK_MODE_LAST
+ 	  = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
+-#endif
+ };
+ 
+ #define __ETHTOOL_LINK_MODE_LEGACY_MASK(base_name)	\
+diff --git a/net/core/xdp.c b/net/core/xdp.c
+index 978bd4432a73..89b6785cef2a 100644
+--- a/net/core/xdp.c
++++ b/net/core/xdp.c
+@@ -14,9 +14,6 @@
+ #include <net/page_pool.h>
+ 
+ #include <net/xdp.h>
+-#ifndef __GENKSYMS__
+-#include <trace/events/xdp.h>
+-#endif
+ 
+ #define REG_STATE_NEW		0x0
+ #define REG_STATE_REGISTERED	0x1
+diff --git a/net/ethtool/ioctl.c b/net/ethtool/ioctl.c
+index c7f67750ecc4..8069c49e21e1 100644
+--- a/net/ethtool/ioctl.c
++++ b/net/ethtool/ioctl.c
+@@ -156,7 +156,7 @@ static int __ethtool_get_sset_count(struct net_device *dev, int sset)
+ 		return phy_ethtool_get_sset_count(dev->phydev);
+ 
+ 	if (sset == ETH_SS_LINK_MODES)
+-		return __ETHTOOL_LINK_MODE_MASK_NBITS;
++		return __ETHTOOL_LINK_MODE_MASK_ASSERT_NBITS;
+ 
+ 	if (ops->get_sset_count && ops->get_strings)
+ 		return ops->get_sset_count(dev, sset);
+@@ -184,7 +184,7 @@ static void __ethtool_get_strings(struct net_device *dev,
+ 		phy_ethtool_get_strings(dev->phydev, data);
+ 	else if (stringset == ETH_SS_LINK_MODES)
+ 		memcpy(data, link_mode_names,
+-		       __ETHTOOL_LINK_MODE_MASK_NBITS * ETH_GSTRING_LEN);
++		       __ETHTOOL_LINK_MODE_MASK_ASSERT_NBITS * ETH_GSTRING_LEN);
+ 	else
+ 		/* ops->get_strings is valid because checked earlier */
+ 		ops->get_strings(dev, stringset, data);
+-- 
+2.34.1
+
diff --git a/series.conf b/series.conf
index d78c29d..27625bb 100644
--- a/series.conf
+++ b/series.conf
@@ -362,3 +362,286 @@ patches/0358-spi-hisi-sfc-v3xx-add-address-mode-check.patch
 patches/0359-spi-hisi-sfc-v3xx-fix-potential-irq-race-condition.patch
 patches/0360-spi-hisi-sfc-v3xx-drop-unnecessary-ACPI_PTR-and-rela.patch
 patches/0361-config-arm64-Build-HiSilicon-SPI-SFC-driver-as-modul.patch
+patches/0362-net-hns3-Fix-for-loopback-selftest-failed-problem.patch
+patches/0363-net-hns3-Only-update-mac-configuation-when-necessary.patch
+patches/0364-net-hns3-Add-default-irq-affinity.patch
+patches/0365-net-hns3-Add-unlikely-for-buf_num-check.patch
+patches/0366-net-phy-Move-linkmode-helpers-to-somewhere-public.patch
+patches/0367-net-hns3-make-function-hclge_set_all_vf_rst-static.patch
+patches/0368-net-hns3-return-0-and-print-warning-when-hit-duplica.patch
+patches/0369-net-hns3-Use-LLDP-ethertype-define-ETH_P_LLDP.patch
+patches/0370-net-hns3-fix-compile-warning-without-CONFIG_RFS_ACCE.patch
+patches/0371-net-hns3-adjust-hns3_uninit_phy-s-location-in-the-hn.patch
+patches/0372-net-hns3-remove-unused-macros.patch
+patches/0373-net-hns3-modify-an-unsuitable-log-in-hclge_map_ring_.patch
+patches/0374-net-hns3-reject-unsupported-coalescing-params.patch
+patches/0375-net-hns3-clear-port-base-VLAN-when-unload-PF.patch
+patches/0376-net-hns-Remove-custom-driver-version-in-favour-of-gl.patch
+patches/0377-net-hns3-remove-a-redundant-register-macro-definitio.patch
+patches/0378-net-hns3-modify-two-uncorrect-macro-names.patch
+patches/0379-net-hns3-remove-a-duplicated-printing-in-hclge_confi.patch
+patches/0380-net-hns3-refactor-hclge_config_tso.patch
+patches/0381-net-hns3-refactor-hclge_query_bd_num_cmd_send.patch
+patches/0382-net-hns3-modify-an-incorrect-type-in-struct-hclge_cf.patch
+patches/0383-net-hns3-modify-an-incorrect-type-in-struct-hclgevf_.patch
+patches/0384-net-hns3-remove-some-unused-fields-in-struct-hns3_ni.patch
+patches/0385-net-hns3-remove-unused-struct-hnae3_unic_private_inf.patch
+patches/0386-net-hns3-remove-two-duplicated-register-macros-in-hc.patch
+patches/0387-net-hns3-remove-some-unused-fields-in-struct-hclge_d.patch
+patches/0388-net-hns3-fix-a-print-format-issue-in-hclge_mac_mdio_.patch
+patches/0389-net-hns3-remove-an-unused-macro-hclge_is_csq.patch
+patches/0390-net-hns3-remove-two-unused-macros-in-hclgevf_cmd.c.patch
+patches/0391-net-hns3-fix-two-coding-style-issues-in-hclgevf_main.patch
+patches/0392-net-hns3-remove-some-unused-codes-in-hns3_nic_set_fe.patch
+patches/0393-net-hns3-remove-some-unused-macros.patch
+patches/0394-net-hns3-add-device-version-to-replace-pci-revision.patch
+patches/0395-net-hns3-add-support-to-query-device-capability.patch
+patches/0396-net-hns3-use-capabilities-queried-from-firmware.patch
+patches/0397-net-hns3-add-UDP-segmentation-offload-support.patch
+patches/0398-net-hns3-initialize-the-message-content-in-hclge_get.patch
+patches/0399-net-hns3-add-support-for-TX-hardware-checksum-offloa.patch
+patches/0400-net-hns3-add-a-structure-for-IR-shaper-s-parameter-i.patch
+patches/0401-net-hns3-remove-the-shaper-param-magic-number.patch
+patches/0402-net-hns3-clean-up-unnecessary-parentheses-in-macro-d.patch
+patches/0403-net-hns3-change-hclge_parse_speed-param-type.patch
+patches/0404-net-hns3-change-hclge_query_bd_num-param-type.patch
+patches/0405-net-hns3-remove-unused-macro-definition.patch
+patches/0406-net-hns3-refactor-out-hclge_cmd_convert_err_code.patch
+patches/0407-net-hns3-refactor-out-hclgevf_cmd_convert_err_code.patch
+patches/0408-net-hns3-use-ipv6_addr_any-helper.patch
+patches/0409-net-hns3-refactor-out-hclge_set_vf_vlan_common.patch
+patches/0410-net-hns3-refactor-out-hclge_get_rss_tuple.patch
+patches/0411-net-hns3-refactor-out-hclgevf_get_rss_tuple.patch
+patches/0412-net-hns3-split-out-hclge_cmd_send.patch
+patches/0413-net-hns3-split-out-hclgevf_cmd_send.patch
+patches/0414-net-hns3-Fix-KABI-for-ethtools-supported_coalesce_pa.patch
+patches/0415-net-hns3-Fix-KABI-for-deletion-of-hnae3_unic_private.patch
+patches/0416-net-hns3-Fix-KABI-for-The-dev_version-caps-element-i.patch
+patches/0417-net-hns3-add-support-for-imp-controlled-PHYs.patch
+patches/0418-net-hns3-add-get-set-pause-parameters-support-for-im.patch
+patches/0419-net-hns3-add-ioctl-support-for-imp-controlled-PHYs.patch
+patches/0420-net-hns3-add-phy-loopback-support-for-imp-controlled.patch
+patches/0421-net-hns3-add-support-to-query-device-specifications.patch
+patches/0422-net-hns3-remove-unused-code-of-vmdq.patch
+patches/0423-net-hns3-remove-redundant-blank-lines.patch
+patches/0424-net-hns3-remove-redundant-query-in-hclge_config_tm_h.patch
+patches/0425-net-hns3-split-function-hclge_reset_rebuild.patch
+patches/0426-net-hns3-split-out-hclge_tm_vport_tc_info_update.patch
+patches/0427-net-hns3-Trivial-spell-fix-in-hns3-driver.patch
+patches/0428-net-hns3-cleanup-inappropriate-spaces-in-struct-hlcg.patch
+patches/0429-net-hns3-clear-unnecessary-reset-request-in-hclge_re.patch
+patches/0430-net-hns3-add-support-for-configuring-interrupt-quant.patch
+patches/0431-net-hns3-fix-user-s-coalesce-configuration-lost-issu.patch
+patches/0432-net-hns3-use-HCLGE_VPORT_STATE_PROMISC_CHANGE-to-rep.patch
+patches/0433-net-hns3-add-a-separate-error-handling-task.patch
+patches/0434-net-hns3-add-scheduling-logic-for-error-handling-tas.patch
+patches/0435-net-hns3-add-log-for-workqueue-scheduled-late.patch
+patches/0436-net-hns3-remove-now-redundant-logic-related-to-HNAE3.patch
+patches/0437-net-hns3-add-support-for-handling-all-errors-through.patch
+patches/0438-net-hns3-add-the-RAS-compatibility-adaptation-soluti.patch
+patches/0439-net-hns3-add-support-for-imp-handle-ras-capability.patch
+patches/0440-net-hns3-update-error-recovery-module-and-type.patch
+patches/0441-net-hns3-add-error-handling-compatibility-during-ini.patch
+patches/0442-net-hns3-use-list_move_tail-instead-of-list_del-list.patch
+patches/0443-net-hns3-refactor-dev-capability-and-dev-spec-of-deb.patch
+patches/0444-net-hns3-add-support-for-PTP.patch
+patches/0445-net-hns3-fix-a-double-shift-bug.patch
+patches/0446-net-hns3-minor-refactor-related-to-desc_cb-handling.patch
+patches/0447-net-hns3-refactor-for-hns3_fill_desc-function.patch
+patches/0448-net-hns3-add-priv-flags-support-to-switch-limit-prom.patch
+patches/0449-net-hns3-use-tx-bounce-buffer-for-small-packets.patch
+patches/0450-net-hns3-add-support-to-query-tx-spare-buffer-size-f.patch
+patches/0451-net-hns3-support-dma_map_sg-for-multi-frags-skb.patch
+patches/0452-net-hns3-use-bounce-buffer-when-rx-page-can-not-be-r.patch
+patches/0453-net-hns3-fix-different-snprintf-limit.patch
+patches/0454-net-hns3-Fix-a-memory-leak-in-an-error-handling-path.patch
+patches/0455-net-hns3-add-support-for-FD-counter-in-debugfs.patch
+patches/0456-net-hns3-fix-rx-VLAN-offload-state-inconsistent-issu.patch
+patches/0457-net-hns3-change-the-method-of-obtaining-default-ptp-.patch
+patches/0458-net-hns3-add-support-for-triggering-reset-by-ethtool.patch
+patches/0459-docs-ethtool-Add-two-link-extended-substates-of-bad-.patch
+patches/0460-ethtool-add-two-link-extended-substates-of-bad-signa.patch
+patches/0461-net-hns3-add-header-file-hns3_ethtoo.h.patch
+patches/0462-net-hns3-add-support-ethtool-extended-link-state.patch
+patches/0463-net-hns3-fix-speed-unknown-issue-in-bond-4.patch
+patches/0464-net-hns3-fix-GRO-configuration-error-after-reset.patch
+patches/0465-net-hns3-add-macros-for-mac-speeds-of-firmware-comma.patch
+patches/0466-net-hns3-add-hns3_state_init-to-do-state-initializat.patch
+patches/0467-net-hns3-use-memcpy-to-simplify-code.patch
+patches/0468-net-hns3-remove-redundant-param-to-simplify-code.patch
+patches/0469-net-hns3-package-new-functions-to-simplify-hclgevf_m.patch
+patches/0470-net-hns3-merge-some-repetitive-macros.patch
+patches/0471-net-hns3-uniform-type-of-function-parameter-cmd.patch
+patches/0472-net-hns3-refactor-function-hclge_parse_capability.patch
+patches/0473-net-hns3-refactor-function-hclgevf_parse_capability.patch
+patches/0474-net-hns3-add-new-function-hclge_get_speed_bit.patch
+patches/0475-net-hns3-don-t-config-TM-DWRR-twice-when-set-ETS.patch
+patches/0476-net-hns3-remove-unnecessary-static-of-local-variable.patch
+patches/0477-net-hns3-add-required-space-in-comment.patch
+patches/0478-net-hns3-initialize-each-member-of-structure-array-o.patch
+patches/0479-net-hns3-reconstruct-function-hns3_self_test.patch
+patches/0480-net-hns3-reconstruct-function-hclge_ets_validate.patch
+patches/0481-net-hns3-refine-function-hclge_dbg_dump_tm_pri.patch
+patches/0482-net-hnss3-use-max-to-simplify-code.patch
+patches/0483-net-hns3-uniform-parameter-name-of-hclge_ptp_clean_t.patch
+patches/0484-net-hns3-refine-function-hns3_set_default_feature.patch
+patches/0485-net-hns3-clean-up-a-type-mismatch-warning.patch
+patches/0486-net-hns3-add-some-required-spaces.patch
+patches/0487-net-hns3-remove-unnecessary-spaces.patch
+patches/0488-net-hns3-make-hclgevf_cmd_caps_bit_map0-and-hclge_cm.patch
+patches/0489-net-hns3-fix-misuse-vf-id-and-vport-id-in-some-logs.patch
+patches/0490-net-hns3-optimize-the-rx-page-reuse-handling-process.patch
+patches/0491-net-hns3-do-not-allow-call-hns3_nic_net_open-repeate.patch
+patches/0492-net-hns3-fix-show-wrong-state-when-add-existing-uc-m.patch
+patches/0493-net-hns3-fix-always-enable-rx-vlan-filter-problem-af.patch
+patches/0494-net-hns3-add-limit-ets-dwrr-bandwidth-cannot-be-0.patch
+patches/0495-net-hns3-disable-sriov-before-unload-hclge-layer.patch
+patches/0496-net-hns3-fix-the-max-tx-size-according-to-user-manua.patch
+patches/0497-xdp-Fixed-an-issue-where-the-trace_mem_disconnect-fu.patch
+patches/0498-net-hns3-fix-hclge_dbg_dump_tm_pg-stack-usage.patch
+patches/0499-net-hns3-don-t-rollback-when-destroy-mqprio-fail.patch
+patches/0500-net-hns3-PF-enable-promisc-for-VF-when-mac-table-is-.patch
+patches/0501-net-hns3-fix-for-miscalculation-of-rx-unused-desc.patch
+patches/0502-net-hns3-schedule-the-polling-again-when-allocation-.patch
+patches/0503-net-hns3-modify-mac-statistics-update-process-for-co.patch
+patches/0504-net-hns3-device-specifications-add-number-of-mac-sta.patch
+patches/0505-net-hns3-add-support-pause-pfc-durations-for-mac-sta.patch
+patches/0506-net-hns3-modify-functions-of-converting-speed-abilit.patch
+patches/0507-net-hns3-add-update-ethtool-advertised-link-modes-fo.patch
+patches/0508-net-hns3-add-new-ras-error-type-for-roce.patch
+patches/0509-net-hns3-add-error-recovery-module-and-type-for-hima.patch
+patches/0510-net-hns3-fix-data-endian-problem-of-some-functions-o.patch
+patches/0511-net-hns3-add-more-string-spaces-for-dumping-packets-.patch
+patches/0512-net-hns3-adjust-string-spaces-of-some-parameters-of-.patch
+patches/0513-net-hisilicon-fix-hsn3_ethtool-kernel-doc-warnings.patch
+patches/0514-net-hns3-add-support-for-pf-querying-new-interrupt-r.patch
+patches/0515-net-hns3-fix-ROCE-base-interrupt-vector-initializati.patch
+patches/0516-net-hns3-sync-rx-ring-head-in-echo-common-pull.patch
+patches/0517-net-hns3-fix-some-mac-statistics-is-always-0-in-devi.patch
+patches/0518-net-hns3-allow-configure-ETS-bandwidth-of-all-TCs.patch
+patches/0519-ethtool-move-to-its-own-directory.patch
+patches/0520-ethtool-move-string-arrays-into-common-file.patch
+patches/0521-ethtool-provide-link-mode-names-as-a-string-set.patch
+patches/0522-ethtool-introduce-ethtool-netlink-interface.patch
+patches/0523-ethtool-helper-functions-for-netlink-interface.patch
+patches/0524-ethtool-provide-ring-sizes-with-RINGS_GET-request.patch
+patches/0525-ethtool-set-device-ring-sizes-with-RINGS_SET-request.patch
+patches/0526-ethtool-add-support-to-set-get-tx-copybreak-buf-size.patch
+patches/0527-net-hns3-add-support-to-set-get-tx-copybreak-buf-siz.patch
+patches/0528-ethtool-add-support-to-set-get-rx-buf-len-via-ethtoo.patch
+patches/0529-net-hns3-add-support-to-set-get-rx-buf-len-via-ethto.patch
+patches/0530-net-hns3-remove-the-way-to-set-tx-spare-buf-via-modu.patch
+patches/0531-net-hns3-debugfs-add-drop-packet-statistics-of-multi.patch
+patches/0532-net-hns3-add-dql-info-when-tx-timeout.patch
+patches/0533-net-hns3-fix-incorrect-components-info-of-ethtool-re.patch
+patches/0534-net-hns3-create-new-cmdq-hardware-description-struct.patch
+patches/0535-net-hns3-use-struct-hclge_desc-to-replace-hclgevf_de.patch
+patches/0536-net-hns3-create-new-set-of-unified-hclge_comm_cmd_se.patch
+patches/0537-net-hns3-add-support-for-TX-push-mode.patch
+patches/0538-net-hns3-handle-empty-unknown-interrupt-for-VF.patch
+patches/0539-net-hns3-fix-software-vlan-talbe-of-vlan-0-inconsist.patch
+patches/0540-net-hns3-add-querying-fec-ability-from-firmware.patch
+patches/0541-net-hns3-add-querying-and-setting-fec-llrs-mode-from.patch
+patches/0542-net-hns3-net-hns3-add-querying-and-setting-fec-off-m.patch
+patches/0543-net-hns3-add-support-for-external-loopback-test.patch
+patches/0544-net-hns3-fix-setting-incorrect-phy-link-ksettings-fo.patch
+patches/0545-net-hns3-refine-the-handling-for-VF-heartbeat.patch
+patches/0546-net-hns3-add-support-for-queue-bonding-mode-of-flow-.patch
+patches/0547-net-hns3-add-queue-bonding-mode-support-for-VF.patch
+patches/0548-net-hns3-allocate-fd-counter-for-queue-bonding.patch
+patches/0549-net-hns3-refactor-the-debugfs-for-dumping-FD-tcam.patch
+patches/0550-net-hns3-support-wake-on-lan-configuration-and-query.patch
+patches/0551-net-hns3-fix-miss-L3E-checking-for-rx-packet.patch
+patches/0552-net-hns3-add-support-customized-exception-handling-i.patch
+patches/0553-net-hns3-add-support-clear-mac-statistics.patch
+patches/0554-net-hns3-add-support-configuring-function-level-inte.patch
+patches/0555-net-hns3-add-supports-fast-reporting-of-faulty-nodes.patch
+patches/0556-net-hns3-add-support-to-get-set-1d-torus-param.patch
+patches/0557-net-hns3-add-support-query-port-ext-information.patch
+patches/0558-net-hns3-support-set-pfc-pause-trans-time.patch
+patches/0559-net-hns3-disbable-pfc-en-before-the-reset.patch
+patches/0560-net-hns3-add-support-query-the-presence-of-optical-m.patch
+patches/0561-net-hns3-add-supports-configure-optical-module-enabl.patch
+patches/0562-net-hns3-add-support-config-and-query-serdes-lane-st.patch
+patches/0563-net-hns3-add-support-disable-nic-clock.patch
+patches/0564-net-hns3-add-support-PF-provides-customized-interfac.patch
+patches/0565-net-hns3-add-support-detect-port-wire-type.patch
+patches/0566-net-hns3-add-support-set-mac-state.patch
+patches/0567-net-hns3-add-support-set-led.patch
+patches/0568-net-hns3-add-extend-interface-support-for-read-and-w.patch
+patches/0569-net-ethtool-add-VxLAN-to-the-NFC-API.patch
+patches/0570-net-hns3-PF-supports-to-set-and-query-lane_num-by-sy.patch
+patches/0571-net-hns3-refactor-for-function-hclge_fd_convert_tupl.patch
+patches/0572-net-hns3-support-set-get-VxLAN-rule-of-rx-flow-direc.patch
+patches/0573-net-hns3-Use-the-correct-style-for-SPDX-License-Iden.patch
+patches/0574-net-hns3-add-support-for-getting-GE-port-lanes.patch
+patches/0575-net-hns3-modify-reset-delay-time-to-avoid-configurat.patch
+patches/0576-net-hns3-fix-reset-timeout-when-enable-full-VF.patch
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