From 8061299b4e8c67438cacec2896d52d7440987798 Mon Sep 17 00:00:00 2001
From: Qi Liu <liuqi115@huawei.com>
Date: Wed, 30 Nov 2022 19:01:38 +0800
Subject: [PATCH 189/201] perf jevents: Add support for HiSilicon HHA PMU
 aliasing

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I63VF5

--------------------------------------------------------------------------

Add support for HiSilicon HHA PMU aliasing on Hip09 platform.

Signed-off-by: Qi Liu <liuqi115@huawei.com>
Signed-off-by: Junhao He <hejunhao3@huawei.com>
Signed-off-by: hongrongxuan <hongrongxuan@huawei.com>
---
 .../arm64/hisilicon/hip09/sys/uncore-hha.json | 102 ++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json
new file mode 100644
index 000000000000..e49dceeaa263
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json
@@ -0,0 +1,102 @@
+[
+   {
+	"EventCode": "0x00",
+	"EventName": "rx_ops_num",
+	"BriefDescription": "The number of all operations received by the HHA",
+	"Compat": "0x00000030",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"EventCode": "0x01",
+	"EventName": "rx_outer",
+	"BriefDescription": "The number of all operations received by the HHA from another socket",
+	"Compat": "0x00000030",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"EventCode": "0x02",
+	"EventName": "rx_sccl",
+	"BriefDescription": "The number of all operations received by the HHA from another SCCL in this socket",
+	"Compat": "0x00000030",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"EventCode": "0x1c",
+	"EventName": "rd_ddr_64b",
+	"BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes",
+	"Compat": "0x00000030",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"EventCode": "0x1d",
+	"EventName": "wr_ddr_64b",
+	"BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes",
+	"Compat": "0x00000030",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"EventCode": "0x1e",
+	"EventName": "rd_ddr_128b",
+	"BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes",
+	"Compat": "0x00000030",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"EventCode": "0x1f",
+	"EventName": "wr_ddr_128b",
+	"BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes",
+	"Compat": "0x00000030",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"EventCode": "0x2e",
+	"EventName": "hha_retry",
+	"BriefDescription": "Count of the HHA retry",
+	"Compat": "0x00000030",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"EventCode": "0x55",
+	"EventName": "hha_cycles",
+	"BriefDescription": "Count of the HHA cycles",
+	"Compat": "0x00000030",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"EventName": "cycles",
+	"Compat": "0x00000030",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"MetricExpr": "(rd_ddr_64b * 64 + rd_ddr_128b *128) / duration_time",
+	"BriefDescription": "Average bandwidth of reading DDRC(Byte/s)",
+	"Compat": "0x00000030",
+	"MetricGroup": "HHA",
+	"MetricName": "hha_read_ddrc_bw",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"MetricExpr": "(wr_ddr_64b * 64 + wr_ddr_128b *128) / duration_time",
+	"BriefDescription": "Average bandwidth of writing DDRC(Byte/s)",
+	"Compat": "0x00000030",
+	"MetricGroup": "HHA",
+	"MetricName": "hha_write_ddrc_bw",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"MetricExpr": "rx_outer / rx_ops_num",
+	"BriefDescription": "Rate of cross-chip operations received by HHA",
+	"Compat": "0x00000030",
+	"MetricGroup": "HHA",
+	"MetricName": "cross_chip_ops_rate",
+	"Unit": "hisi_sccl,hha"
+   },
+   {
+	"MetricExpr": "rx_sccl / rx_ops_num",
+	"BriefDescription": "Rate of cross-die operations received by HHA",
+	"Compat": "0x00000030",
+	"MetricGroup": "HHA",
+	"MetricName": "cross_die_ops_rate",
+	"Unit": "hisi_sccl,hha"
+   }
+]
\ No newline at end of file
-- 
2.27.0

